1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "utilities/powerOfTwo.hpp"
32
33 // MacroAssembler extends Assembler by frequently used macros.
34 //
35 // Instructions for which a 'better' code sequence exists depending
36 // on arguments should also go in here.
37
38 class MacroAssembler: public Assembler {
39 friend class LIR_Assembler;
40
41 public:
42 using Assembler::mov;
43 using Assembler::movi;
44
45 protected:
46
47 // Support for VM calls
48 //
49 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
50 // may customize this version by overriding it for its purposes (e.g., to save/restore
51 // additional registers when doing a VM call).
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments, // the number of arguments to pop after the call
55 Label *retaddr = NULL
56 );
57
58 virtual void call_VM_leaf_base(
59 address entry_point, // the entry point
60 int number_of_arguments, // the number of arguments to pop after the call
61 Label &retaddr) {
62 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
63 }
64
65 // This is the base routine called by the different versions of call_VM. The interpreter
66 // may customize this version by overriding it for its purposes (e.g., to save/restore
67 // additional registers when doing a VM call).
68 //
69 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
70 // returns the register which contains the thread upon return. If a thread register has been
71 // specified, the return value will correspond to that register. If no last_java_sp is specified
72 // (noreg) than rsp will be used instead.
73 virtual void call_VM_base( // returns the register containing the thread upon return
74 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
75 Register java_thread, // the thread if computed before ; use noreg otherwise
76 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
77 address entry_point, // the entry point
78 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
79 bool check_exceptions // whether to check for pending exceptions after return
80 );
81
82 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
83
84 enum KlassDecodeMode {
85 KlassDecodeNone,
86 KlassDecodeZero,
87 KlassDecodeXor,
88 KlassDecodeMovk
89 };
90
91 KlassDecodeMode klass_decode_mode();
92
93 private:
94 static KlassDecodeMode _klass_decode_mode;
95
96 public:
97 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
98
99 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
100 // The implementation is only non-empty for the InterpreterMacroAssembler,
101 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
102 virtual void check_and_handle_popframe(Register java_thread);
103 virtual void check_and_handle_earlyret(Register java_thread);
104
105 void safepoint_poll(Label& slow_path);
106 void safepoint_poll_acquire(Label& slow_path);
107
108 // Biased locking support
109 // lock_reg and obj_reg must be loaded up with the appropriate values.
110 // swap_reg is killed.
111 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
112 // Optional slow case is for implementations (interpreter and C1) which branch to
113 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
114 // Returns offset of first potentially-faulting instruction for null
115 // check info (currently consumed only by C1). If
116 // swap_reg_contains_mark is true then returns -1 as it is assumed
117 // the calling code has already passed any potential faults.
118 int biased_locking_enter(Register lock_reg, Register obj_reg,
119 Register swap_reg, Register tmp_reg,
120 bool swap_reg_contains_mark,
121 Label& done, Label* slow_case = NULL,
122 BiasedLockingCounters* counters = NULL);
123 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
124
125
126 // Helper functions for statistics gathering.
127 // Unconditional atomic increment.
128 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
129 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
130 lea(tmp1, counter_addr);
131 atomic_incw(tmp1, tmp2, tmp3);
132 }
133 // Load Effective Address
134 void lea(Register r, const Address &a) {
135 InstructionMark im(this);
136 code_section()->relocate(inst_mark(), a.rspec());
137 a.lea(this, r);
138 }
139
140 /* Sometimes we get misaligned loads and stores, usually from Unsafe
141 accesses, and these can exceed the offset range. */
142 Address legitimize_address(const Address &a, int size, Register scratch) {
143 if (a.getMode() == Address::base_plus_offset) {
144 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
145 block_comment("legitimize_address {");
146 lea(scratch, a);
147 block_comment("} legitimize_address");
148 return Address(scratch);
149 }
150 }
151 return a;
152 }
153
154 void addmw(Address a, Register incr, Register scratch) {
155 ldrw(scratch, a);
156 addw(scratch, scratch, incr);
157 strw(scratch, a);
158 }
159
160 // Add constant to memory word
161 void addmw(Address a, int imm, Register scratch) {
162 ldrw(scratch, a);
163 if (imm > 0)
164 addw(scratch, scratch, (unsigned)imm);
165 else
166 subw(scratch, scratch, (unsigned)-imm);
167 strw(scratch, a);
168 }
169
170 void bind(Label& L) {
171 Assembler::bind(L);
172 code()->clear_last_insn();
173 }
174
175 void membar(Membar_mask_bits order_constraint);
176
177 using Assembler::ldr;
178 using Assembler::str;
179 using Assembler::ldrw;
180 using Assembler::strw;
181
182 void ldr(Register Rx, const Address &adr);
183 void ldrw(Register Rw, const Address &adr);
184 void str(Register Rx, const Address &adr);
185 void strw(Register Rx, const Address &adr);
186
187 // Frame creation and destruction shared between JITs.
188 void build_frame(int framesize);
189 void remove_frame(int framesize);
190
191 virtual void _call_Unimplemented(address call_site) {
192 mov(rscratch2, call_site);
193 }
194
195 #ifdef _WIN64
196 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
197 #else
198 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
199 #endif
200
201 // aliases defined in AARCH64 spec
202
203 template<class T>
204 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
205
206 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
207 inline DEPRECATED void cmp(Register Rd, unsigned imm);
208
209 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
210 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
211
212 void cset(Register Rd, Assembler::Condition cond) {
213 csinc(Rd, zr, zr, ~cond);
214 }
215 void csetw(Register Rd, Assembler::Condition cond) {
216 csincw(Rd, zr, zr, ~cond);
217 }
218
219 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
220 csneg(Rd, Rn, Rn, ~cond);
221 }
222 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
223 csnegw(Rd, Rn, Rn, ~cond);
224 }
225
226 inline void movw(Register Rd, Register Rn) {
227 if (Rd == sp || Rn == sp) {
228 addw(Rd, Rn, 0U);
229 } else {
230 orrw(Rd, zr, Rn);
231 }
232 }
233 inline void mov(Register Rd, Register Rn) {
234 assert(Rd != r31_sp && Rn != r31_sp, "should be");
235 if (Rd == Rn) {
236 } else if (Rd == sp || Rn == sp) {
237 add(Rd, Rn, 0U);
238 } else {
239 orr(Rd, zr, Rn);
240 }
241 }
242
243 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
244 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
245
246 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
247 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
248
249 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
250 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
251
252 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
254 }
255 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
257 }
258
259 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 bfmw(Rd, Rn, lsb, (lsb + width - 1));
261 }
262 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 bfm(Rd, Rn, lsb , (lsb + width - 1));
264 }
265
266 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
268 }
269 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
271 }
272
273 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
274 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
275 }
276 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 sbfm(Rd, Rn, lsb , (lsb + width - 1));
278 }
279
280 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
281 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
282 }
283 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
284 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
285 }
286
287 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
288 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
289 }
290 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
291 ubfm(Rd, Rn, lsb , (lsb + width - 1));
292 }
293
294 inline void asrw(Register Rd, Register Rn, unsigned imm) {
295 sbfmw(Rd, Rn, imm, 31);
296 }
297
298 inline void asr(Register Rd, Register Rn, unsigned imm) {
299 sbfm(Rd, Rn, imm, 63);
300 }
301
302 inline void lslw(Register Rd, Register Rn, unsigned imm) {
303 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
304 }
305
306 inline void lsl(Register Rd, Register Rn, unsigned imm) {
307 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
308 }
309
310 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
311 ubfmw(Rd, Rn, imm, 31);
312 }
313
314 inline void lsr(Register Rd, Register Rn, unsigned imm) {
315 ubfm(Rd, Rn, imm, 63);
316 }
317
318 inline void rorw(Register Rd, Register Rn, unsigned imm) {
319 extrw(Rd, Rn, Rn, imm);
320 }
321
322 inline void ror(Register Rd, Register Rn, unsigned imm) {
323 extr(Rd, Rn, Rn, imm);
324 }
325
326 inline void sxtbw(Register Rd, Register Rn) {
327 sbfmw(Rd, Rn, 0, 7);
328 }
329 inline void sxthw(Register Rd, Register Rn) {
330 sbfmw(Rd, Rn, 0, 15);
331 }
332 inline void sxtb(Register Rd, Register Rn) {
333 sbfm(Rd, Rn, 0, 7);
334 }
335 inline void sxth(Register Rd, Register Rn) {
336 sbfm(Rd, Rn, 0, 15);
337 }
338 inline void sxtw(Register Rd, Register Rn) {
339 sbfm(Rd, Rn, 0, 31);
340 }
341
342 inline void uxtbw(Register Rd, Register Rn) {
343 ubfmw(Rd, Rn, 0, 7);
344 }
345 inline void uxthw(Register Rd, Register Rn) {
346 ubfmw(Rd, Rn, 0, 15);
347 }
348 inline void uxtb(Register Rd, Register Rn) {
349 ubfm(Rd, Rn, 0, 7);
350 }
351 inline void uxth(Register Rd, Register Rn) {
352 ubfm(Rd, Rn, 0, 15);
353 }
354 inline void uxtw(Register Rd, Register Rn) {
355 ubfm(Rd, Rn, 0, 31);
356 }
357
358 inline void cmnw(Register Rn, Register Rm) {
359 addsw(zr, Rn, Rm);
360 }
361 inline void cmn(Register Rn, Register Rm) {
362 adds(zr, Rn, Rm);
363 }
364
365 inline void cmpw(Register Rn, Register Rm) {
366 subsw(zr, Rn, Rm);
367 }
368 inline void cmp(Register Rn, Register Rm) {
369 subs(zr, Rn, Rm);
370 }
371
372 inline void negw(Register Rd, Register Rn) {
373 subw(Rd, zr, Rn);
374 }
375
376 inline void neg(Register Rd, Register Rn) {
377 sub(Rd, zr, Rn);
378 }
379
380 inline void negsw(Register Rd, Register Rn) {
381 subsw(Rd, zr, Rn);
382 }
383
384 inline void negs(Register Rd, Register Rn) {
385 subs(Rd, zr, Rn);
386 }
387
388 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
389 addsw(zr, Rn, Rm, kind, shift);
390 }
391 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
392 adds(zr, Rn, Rm, kind, shift);
393 }
394
395 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
396 subsw(zr, Rn, Rm, kind, shift);
397 }
398 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
399 subs(zr, Rn, Rm, kind, shift);
400 }
401
402 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
403 subw(Rd, zr, Rn, kind, shift);
404 }
405
406 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
407 sub(Rd, zr, Rn, kind, shift);
408 }
409
410 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
411 subsw(Rd, zr, Rn, kind, shift);
412 }
413
414 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
415 subs(Rd, zr, Rn, kind, shift);
416 }
417
418 inline void mnegw(Register Rd, Register Rn, Register Rm) {
419 msubw(Rd, Rn, Rm, zr);
420 }
421 inline void mneg(Register Rd, Register Rn, Register Rm) {
422 msub(Rd, Rn, Rm, zr);
423 }
424
425 inline void mulw(Register Rd, Register Rn, Register Rm) {
426 maddw(Rd, Rn, Rm, zr);
427 }
428 inline void mul(Register Rd, Register Rn, Register Rm) {
429 madd(Rd, Rn, Rm, zr);
430 }
431
432 inline void smnegl(Register Rd, Register Rn, Register Rm) {
433 smsubl(Rd, Rn, Rm, zr);
434 }
435 inline void smull(Register Rd, Register Rn, Register Rm) {
436 smaddl(Rd, Rn, Rm, zr);
437 }
438
439 inline void umnegl(Register Rd, Register Rn, Register Rm) {
440 umsubl(Rd, Rn, Rm, zr);
441 }
442 inline void umull(Register Rd, Register Rn, Register Rm) {
443 umaddl(Rd, Rn, Rm, zr);
444 }
445
446 #define WRAP(INSN) \
447 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
448 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
449 nop(); \
450 Assembler::INSN(Rd, Rn, Rm, Ra); \
451 }
452
453 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
454 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
455 #undef WRAP
456
457
458 // macro assembly operations needed for aarch64
459
460 // first two private routines for loading 32 bit or 64 bit constants
461 private:
462
463 void mov_immediate64(Register dst, uint64_t imm64);
464 void mov_immediate32(Register dst, uint32_t imm32);
465
466 int push(unsigned int bitset, Register stack);
467 int pop(unsigned int bitset, Register stack);
468
469 int push_fp(unsigned int bitset, Register stack);
470 int pop_fp(unsigned int bitset, Register stack);
471
472 void mov(Register dst, Address a);
473
474 public:
475 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
476 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
477
478 void push_fp(RegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
479 void pop_fp(RegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
480
481 // Push and pop everything that might be clobbered by a native
482 // runtime call except rscratch1 and rscratch2. (They are always
483 // scratch, so we don't have to protect them.) Only save the lower
484 // 64 bits of each vector register.
485 void push_call_clobbered_registers();
486 void pop_call_clobbered_registers();
487
488 // now mov instructions for loading absolute addresses and 32 or
489 // 64 bit integers
490
491 inline void mov(Register dst, address addr)
492 {
493 mov_immediate64(dst, (uint64_t)addr);
494 }
495
496 inline void mov(Register dst, uint64_t imm64)
497 {
498 mov_immediate64(dst, imm64);
499 }
500
501 inline void movw(Register dst, uint32_t imm32)
502 {
503 mov_immediate32(dst, imm32);
504 }
505
506 inline void mov(Register dst, int64_t l)
507 {
508 mov(dst, (uint64_t)l);
509 }
510
511 inline void mov(Register dst, int i)
512 {
513 mov(dst, (int64_t)i);
514 }
515
516 void mov(Register dst, RegisterOrConstant src) {
517 if (src.is_register())
518 mov(dst, src.as_register());
519 else
520 mov(dst, src.as_constant());
521 }
522
523 void movptr(Register r, uintptr_t imm64);
524
525 void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32);
526
527 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
528 orr(Vd, T, Vn, Vn);
529 }
530
531 public:
532
533 // Generalized Test Bit And Branch, including a "far" variety which
534 // spans more than 32KiB.
535 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
536 assert(cond == EQ || cond == NE, "must be");
537
538 if (isfar)
539 cond = ~cond;
540
541 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
542 if (cond == Assembler::EQ)
543 branch = &Assembler::tbz;
544 else
545 branch = &Assembler::tbnz;
546
547 if (isfar) {
548 Label L;
549 (this->*branch)(Rt, bitpos, L);
550 b(dest);
551 bind(L);
552 } else {
553 (this->*branch)(Rt, bitpos, dest);
554 }
555 }
556
557 // macro instructions for accessing and updating floating point
558 // status register
559 //
560 // FPSR : op1 == 011
561 // CRn == 0100
562 // CRm == 0100
563 // op2 == 001
564
565 inline void get_fpsr(Register reg)
566 {
567 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
568 }
569
570 inline void set_fpsr(Register reg)
571 {
572 msr(0b011, 0b0100, 0b0100, 0b001, reg);
573 }
574
575 inline void clear_fpsr()
576 {
577 msr(0b011, 0b0100, 0b0100, 0b001, zr);
578 }
579
580 // DCZID_EL0: op1 == 011
581 // CRn == 0000
582 // CRm == 0000
583 // op2 == 111
584 inline void get_dczid_el0(Register reg)
585 {
586 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
587 }
588
589 // CTR_EL0: op1 == 011
590 // CRn == 0000
591 // CRm == 0000
592 // op2 == 001
593 inline void get_ctr_el0(Register reg)
594 {
595 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
596 }
597
598 // idiv variant which deals with MINLONG as dividend and -1 as divisor
599 int corrected_idivl(Register result, Register ra, Register rb,
600 bool want_remainder, Register tmp = rscratch1);
601 int corrected_idivq(Register result, Register ra, Register rb,
602 bool want_remainder, Register tmp = rscratch1);
603
604 // Support for NULL-checks
605 //
606 // Generates code that causes a NULL OS exception if the content of reg is NULL.
607 // If the accessed location is M[reg + offset] and the offset is known, provide the
608 // offset. No explicit code generation is needed if the offset is within a certain
609 // range (0 <= offset <= page_size).
610
611 virtual void null_check(Register reg, int offset = -1);
612 static bool needs_explicit_null_check(intptr_t offset);
613 static bool uses_implicit_null_check(void* address);
614
615 static address target_addr_for_insn(address insn_addr, unsigned insn);
616 static address target_addr_for_insn(address insn_addr) {
617 unsigned insn = *(unsigned*)insn_addr;
618 return target_addr_for_insn(insn_addr, insn);
619 }
620
621 // Required platform-specific helpers for Label::patch_instructions.
622 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
623 static int pd_patch_instruction_size(address branch, address target);
624 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
625 pd_patch_instruction_size(branch, target);
626 }
627 static address pd_call_destination(address branch) {
628 return target_addr_for_insn(branch);
629 }
630 #ifndef PRODUCT
631 static void pd_print_patched_instruction(address branch);
632 #endif
633
634 static int patch_oop(address insn_addr, address o);
635 static int patch_narrow_klass(address insn_addr, narrowKlass n);
636
637 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
638 void emit_static_call_stub();
639
640 // The following 4 methods return the offset of the appropriate move instruction
641
642 // Support for fast byte/short loading with zero extension (depending on particular CPU)
643 int load_unsigned_byte(Register dst, Address src);
644 int load_unsigned_short(Register dst, Address src);
645
646 // Support for fast byte/short loading with sign extension (depending on particular CPU)
647 int load_signed_byte(Register dst, Address src);
648 int load_signed_short(Register dst, Address src);
649
650 int load_signed_byte32(Register dst, Address src);
651 int load_signed_short32(Register dst, Address src);
652
653 // Support for sign-extension (hi:lo = extend_sign(lo))
654 void extend_sign(Register hi, Register lo);
655
656 // Load and store values by size and signed-ness
657 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
658 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
659
660 // Support for inc/dec with optimal instruction selection depending on value
661
662 // x86_64 aliases an unqualified register/address increment and
663 // decrement to call incrementq and decrementq but also supports
664 // explicitly sized calls to incrementq/decrementq or
665 // incrementl/decrementl
666
667 // for aarch64 the proper convention would be to use
668 // increment/decrement for 64 bit operatons and
669 // incrementw/decrementw for 32 bit operations. so when porting
670 // x86_64 code we can leave calls to increment/decrement as is,
671 // replace incrementq/decrementq with increment/decrement and
672 // replace incrementl/decrementl with incrementw/decrementw.
673
674 // n.b. increment/decrement calls with an Address destination will
675 // need to use a scratch register to load the value to be
676 // incremented. increment/decrement calls which add or subtract a
677 // constant value greater than 2^12 will need to use a 2nd scratch
678 // register to hold the constant. so, a register increment/decrement
679 // may trash rscratch2 and an address increment/decrement trash
680 // rscratch and rscratch2
681
682 void decrementw(Address dst, int value = 1);
683 void decrementw(Register reg, int value = 1);
684
685 void decrement(Register reg, int value = 1);
686 void decrement(Address dst, int value = 1);
687
688 void incrementw(Address dst, int value = 1);
689 void incrementw(Register reg, int value = 1);
690
691 void increment(Register reg, int value = 1);
692 void increment(Address dst, int value = 1);
693
694
695 // Alignment
696 void align(int modulus);
697
698 // Stack frame creation/removal
699 void enter()
700 {
701 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
702 mov(rfp, sp);
703 }
704 void leave()
705 {
706 mov(sp, rfp);
707 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
708 }
709
710 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
711 // The pointer will be loaded into the thread register.
712 void get_thread(Register thread);
713
714
715 // Support for VM calls
716 //
717 // It is imperative that all calls into the VM are handled via the call_VM macros.
718 // They make sure that the stack linkage is setup correctly. call_VM's correspond
719 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
720
721
722 void call_VM(Register oop_result,
723 address entry_point,
724 bool check_exceptions = true);
725 void call_VM(Register oop_result,
726 address entry_point,
727 Register arg_1,
728 bool check_exceptions = true);
729 void call_VM(Register oop_result,
730 address entry_point,
731 Register arg_1, Register arg_2,
732 bool check_exceptions = true);
733 void call_VM(Register oop_result,
734 address entry_point,
735 Register arg_1, Register arg_2, Register arg_3,
736 bool check_exceptions = true);
737
738 // Overloadings with last_Java_sp
739 void call_VM(Register oop_result,
740 Register last_java_sp,
741 address entry_point,
742 int number_of_arguments = 0,
743 bool check_exceptions = true);
744 void call_VM(Register oop_result,
745 Register last_java_sp,
746 address entry_point,
747 Register arg_1, bool
748 check_exceptions = true);
749 void call_VM(Register oop_result,
750 Register last_java_sp,
751 address entry_point,
752 Register arg_1, Register arg_2,
753 bool check_exceptions = true);
754 void call_VM(Register oop_result,
755 Register last_java_sp,
756 address entry_point,
757 Register arg_1, Register arg_2, Register arg_3,
758 bool check_exceptions = true);
759
760 void get_vm_result (Register oop_result, Register thread);
761 void get_vm_result_2(Register metadata_result, Register thread);
762
763 // These always tightly bind to MacroAssembler::call_VM_base
764 // bypassing the virtual implementation
765 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
766 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
767 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
768 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
769 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
770
771 void call_VM_leaf(address entry_point,
772 int number_of_arguments = 0);
773 void call_VM_leaf(address entry_point,
774 Register arg_1);
775 void call_VM_leaf(address entry_point,
776 Register arg_1, Register arg_2);
777 void call_VM_leaf(address entry_point,
778 Register arg_1, Register arg_2, Register arg_3);
779
780 // These always tightly bind to MacroAssembler::call_VM_leaf_base
781 // bypassing the virtual implementation
782 void super_call_VM_leaf(address entry_point);
783 void super_call_VM_leaf(address entry_point, Register arg_1);
784 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
785 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
786 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
787
788 // last Java Frame (fills frame anchor)
789 void set_last_Java_frame(Register last_java_sp,
790 Register last_java_fp,
791 address last_java_pc,
792 Register scratch);
793
794 void set_last_Java_frame(Register last_java_sp,
795 Register last_java_fp,
796 Label &last_java_pc,
797 Register scratch);
798
799 void set_last_Java_frame(Register last_java_sp,
800 Register last_java_fp,
801 Register last_java_pc,
802 Register scratch);
803
804 void reset_last_Java_frame(Register thread);
805
806 // thread in the default location (rthread)
807 void reset_last_Java_frame(bool clear_fp);
808
809 // Stores
810 void store_check(Register obj); // store check for obj - register is destroyed afterwards
811 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
812
813 void resolve_jobject(Register value, Register thread, Register tmp);
814
815 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
816 void c2bool(Register x);
817
818 void load_method_holder_cld(Register rresult, Register rmethod);
819 void load_method_holder(Register holder, Register method);
820
821 // oop manipulations
822 void load_klass(Register dst, Register src);
823 void store_klass(Register dst, Register src);
824 void cmp_klass(Register oop, Register trial_klass, Register tmp);
825
826 void resolve_weak_handle(Register result, Register tmp);
827 void resolve_oop_handle(Register result, Register tmp = r5);
828 void load_mirror(Register dst, Register method, Register tmp = r5);
829
830 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
831 Register tmp1, Register tmp_thread);
832
833 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
834 Register tmp1, Register tmp_thread);
835
836 // Resolves obj for access. Result is placed in the same register.
837 // All other registers are preserved.
838 void resolve(DecoratorSet decorators, Register obj);
839
840 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
841 Register thread_tmp = noreg, DecoratorSet decorators = 0);
842
843 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
844 Register thread_tmp = noreg, DecoratorSet decorators = 0);
845 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
846 Register tmp_thread = noreg, DecoratorSet decorators = 0);
847
848 // currently unimplemented
849 // Used for storing NULL. All other oop constants should be
850 // stored using routines that take a jobject.
851 void store_heap_oop_null(Address dst);
852
853 void load_prototype_header(Register dst, Register src);
854
855 void store_klass_gap(Register dst, Register src);
856
857 // This dummy is to prevent a call to store_heap_oop from
858 // converting a zero (like NULL) into a Register by giving
859 // the compiler two choices it can't resolve
860
861 void store_heap_oop(Address dst, void* dummy);
862
863 void encode_heap_oop(Register d, Register s);
864 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
865 void decode_heap_oop(Register d, Register s);
866 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
867 void encode_heap_oop_not_null(Register r);
868 void decode_heap_oop_not_null(Register r);
869 void encode_heap_oop_not_null(Register dst, Register src);
870 void decode_heap_oop_not_null(Register dst, Register src);
871
872 void set_narrow_oop(Register dst, jobject obj);
873
874 void encode_klass_not_null(Register r);
875 void decode_klass_not_null(Register r);
876 void encode_klass_not_null(Register dst, Register src);
877 void decode_klass_not_null(Register dst, Register src);
878
879 void set_narrow_klass(Register dst, Klass* k);
880
881 // if heap base register is used - reinit it with the correct value
882 void reinit_heapbase();
883
884 DEBUG_ONLY(void verify_heapbase(const char* msg);)
885
886 void push_CPU_state(bool save_vectors = false);
887 void pop_CPU_state(bool restore_vectors = false) ;
888
889 // Round up to a power of two
890 void round_to(Register reg, int modulus);
891
892 // allocation
893 void eden_allocate(
894 Register obj, // result: pointer to object after successful allocation
895 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
896 int con_size_in_bytes, // object size in bytes if known at compile time
897 Register t1, // temp register
898 Label& slow_case // continuation point if fast allocation fails
899 );
900 void tlab_allocate(
901 Register obj, // result: pointer to object after successful allocation
902 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
903 int con_size_in_bytes, // object size in bytes if known at compile time
904 Register t1, // temp register
905 Register t2, // temp register
906 Label& slow_case // continuation point if fast allocation fails
907 );
908 void zero_memory(Register addr, Register len, Register t1);
909 void verify_tlab();
910
911 // interface method calling
912 void lookup_interface_method(Register recv_klass,
913 Register intf_klass,
914 RegisterOrConstant itable_index,
915 Register method_result,
916 Register scan_temp,
917 Label& no_such_interface,
918 bool return_method = true);
919
920 // virtual method calling
921 // n.b. x86 allows RegisterOrConstant for vtable_index
922 void lookup_virtual_method(Register recv_klass,
923 RegisterOrConstant vtable_index,
924 Register method_result);
925
926 // Test sub_klass against super_klass, with fast and slow paths.
927
928 // The fast path produces a tri-state answer: yes / no / maybe-slow.
929 // One of the three labels can be NULL, meaning take the fall-through.
930 // If super_check_offset is -1, the value is loaded up from super_klass.
931 // No registers are killed, except temp_reg.
932 void check_klass_subtype_fast_path(Register sub_klass,
933 Register super_klass,
934 Register temp_reg,
935 Label* L_success,
936 Label* L_failure,
937 Label* L_slow_path,
938 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
939
940 // The rest of the type check; must be wired to a corresponding fast path.
941 // It does not repeat the fast path logic, so don't use it standalone.
942 // The temp_reg and temp2_reg can be noreg, if no temps are available.
943 // Updates the sub's secondary super cache as necessary.
944 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
945 void check_klass_subtype_slow_path(Register sub_klass,
946 Register super_klass,
947 Register temp_reg,
948 Register temp2_reg,
949 Label* L_success,
950 Label* L_failure,
951 bool set_cond_codes = false);
952
953 // Simplified, combined version, good for typical uses.
954 // Falls through on failure.
955 void check_klass_subtype(Register sub_klass,
956 Register super_klass,
957 Register temp_reg,
958 Label& L_success);
959
960 void clinit_barrier(Register klass,
961 Register thread,
962 Label* L_fast_path = NULL,
963 Label* L_slow_path = NULL);
964
965 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
966
967
968 // Debugging
969
970 // only if +VerifyOops
971 void verify_oop(Register reg, const char* s = "broken oop");
972 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
973
974 // TODO: verify method and klass metadata (compare against vptr?)
975 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
976 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
977
978 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
979 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
980
981 // only if +VerifyFPU
982 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
983
984 // prints msg, dumps registers and stops execution
985 void stop(const char* msg);
986
987 static void debug64(char* msg, int64_t pc, int64_t regs[]);
988
989 void untested() { stop("untested"); }
990
991 void unimplemented(const char* what = "");
992
993 void should_not_reach_here() { stop("should not reach here"); }
994
995 // Stack overflow checking
996 void bang_stack_with_offset(int offset) {
997 // stack grows down, caller passes positive offset
998 assert(offset > 0, "must bang with negative offset");
999 sub(rscratch2, sp, offset);
1000 str(zr, Address(rscratch2));
1001 }
1002
1003 // Writes to stack successive pages until offset reached to check for
1004 // stack overflow + shadow pages. Also, clobbers tmp
1005 void bang_stack_size(Register size, Register tmp);
1006
1007 // Check for reserved stack access in method being exited (for JIT)
1008 void reserved_stack_check();
1009
1010 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1011 Register tmp,
1012 int offset);
1013
1014 // Arithmetics
1015
1016 void addptr(const Address &dst, int32_t src);
1017 void cmpptr(Register src1, Address src2);
1018
1019 void cmpoop(Register obj1, Register obj2);
1020
1021 // Various forms of CAS
1022
1023 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1024 Label &suceed, Label *fail);
1025 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1026 Label &suceed, Label *fail);
1027
1028 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1029 Label &suceed, Label *fail);
1030
1031 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1032 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1033 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1034 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1035
1036 void atomic_xchg(Register prev, Register newv, Register addr);
1037 void atomic_xchgw(Register prev, Register newv, Register addr);
1038 void atomic_xchgal(Register prev, Register newv, Register addr);
1039 void atomic_xchgalw(Register prev, Register newv, Register addr);
1040
1041 void orptr(Address adr, RegisterOrConstant src) {
1042 ldr(rscratch1, adr);
1043 if (src.is_register())
1044 orr(rscratch1, rscratch1, src.as_register());
1045 else
1046 orr(rscratch1, rscratch1, src.as_constant());
1047 str(rscratch1, adr);
1048 }
1049
1050 // A generic CAS; success or failure is in the EQ flag.
1051 // Clobbers rscratch1
1052 void cmpxchg(Register addr, Register expected, Register new_val,
1053 enum operand_size size,
1054 bool acquire, bool release, bool weak,
1055 Register result);
1056 private:
1057 void compare_eq(Register rn, Register rm, enum operand_size size);
1058
1059 public:
1060 // Calls
1061
1062 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1063
1064 static bool far_branches() {
1065 return ReservedCodeCacheSize > branch_range || UseAOT;
1066 }
1067
1068 // Jumps that can reach anywhere in the code cache.
1069 // Trashes tmp.
1070 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1071 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1072
1073 static int far_branch_size() {
1074 if (far_branches()) {
1075 return 3 * 4; // adrp, add, br
1076 } else {
1077 return 4;
1078 }
1079 }
1080
1081 // Emit the CompiledIC call idiom
1082 address ic_call(address entry, jint method_index = 0);
1083
1084 public:
1085
1086 // Data
1087
1088 void mov_metadata(Register dst, Metadata* obj);
1089 Address allocate_metadata_address(Metadata* obj);
1090 Address constant_oop_address(jobject obj);
1091
1092 void movoop(Register dst, jobject obj, bool immediate = false);
1093
1094 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1095 void kernel_crc32(Register crc, Register buf, Register len,
1096 Register table0, Register table1, Register table2, Register table3,
1097 Register tmp, Register tmp2, Register tmp3);
1098 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1099 void kernel_crc32c(Register crc, Register buf, Register len,
1100 Register table0, Register table1, Register table2, Register table3,
1101 Register tmp, Register tmp2, Register tmp3);
1102
1103 // Stack push and pop individual 64 bit registers
1104 void push(Register src);
1105 void pop(Register dst);
1106
1107 // push all registers onto the stack
1108 void pusha();
1109 void popa();
1110
1111 void repne_scan(Register addr, Register value, Register count,
1112 Register scratch);
1113 void repne_scanw(Register addr, Register value, Register count,
1114 Register scratch);
1115
1116 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1117 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1118
1119 // If a constant does not fit in an immediate field, generate some
1120 // number of MOV instructions and then perform the operation
1121 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1122 add_sub_imm_insn insn1,
1123 add_sub_reg_insn insn2);
1124 // Seperate vsn which sets the flags
1125 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1126 add_sub_imm_insn insn1,
1127 add_sub_reg_insn insn2);
1128
1129 #define WRAP(INSN) \
1130 void INSN(Register Rd, Register Rn, unsigned imm) { \
1131 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1132 } \
1133 \
1134 void INSN(Register Rd, Register Rn, Register Rm, \
1135 enum shift_kind kind, unsigned shift = 0) { \
1136 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1137 } \
1138 \
1139 void INSN(Register Rd, Register Rn, Register Rm) { \
1140 Assembler::INSN(Rd, Rn, Rm); \
1141 } \
1142 \
1143 void INSN(Register Rd, Register Rn, Register Rm, \
1144 ext::operation option, int amount = 0) { \
1145 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1146 }
1147
1148 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1149
1150 #undef WRAP
1151 #define WRAP(INSN) \
1152 void INSN(Register Rd, Register Rn, unsigned imm) { \
1153 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1154 } \
1155 \
1156 void INSN(Register Rd, Register Rn, Register Rm, \
1157 enum shift_kind kind, unsigned shift = 0) { \
1158 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1159 } \
1160 \
1161 void INSN(Register Rd, Register Rn, Register Rm) { \
1162 Assembler::INSN(Rd, Rn, Rm); \
1163 } \
1164 \
1165 void INSN(Register Rd, Register Rn, Register Rm, \
1166 ext::operation option, int amount = 0) { \
1167 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1168 }
1169
1170 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1171
1172 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1173 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1174 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1175 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1176
1177 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1178
1179 void tableswitch(Register index, jint lowbound, jint highbound,
1180 Label &jumptable, Label &jumptable_end, int stride = 1) {
1181 adr(rscratch1, jumptable);
1182 subsw(rscratch2, index, lowbound);
1183 subsw(zr, rscratch2, highbound - lowbound);
1184 br(Assembler::HS, jumptable_end);
1185 add(rscratch1, rscratch1, rscratch2,
1186 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1187 br(rscratch1);
1188 }
1189
1190 // Form an address from base + offset in Rd. Rd may or may not
1191 // actually be used: you must use the Address that is returned. It
1192 // is up to you to ensure that the shift provided matches the size
1193 // of your data.
1194 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1195
1196 // Return true iff an address is within the 48-bit AArch64 address
1197 // space.
1198 bool is_valid_AArch64_address(address a) {
1199 return ((uint64_t)a >> 48) == 0;
1200 }
1201
1202 // Load the base of the cardtable byte map into reg.
1203 void load_byte_map_base(Register reg);
1204
1205 // Prolog generator routines to support switch between x86 code and
1206 // generated ARM code
1207
1208 // routine to generate an x86 prolog for a stub function which
1209 // bootstraps into the generated ARM code which directly follows the
1210 // stub
1211 //
1212
1213 public:
1214
1215 void ldr_constant(Register dest, const Address &const_addr) {
1216 if (NearCpool) {
1217 ldr(dest, const_addr);
1218 } else {
1219 uint64_t offset;
1220 adrp(dest, InternalAddress(const_addr.target()), offset);
1221 ldr(dest, Address(dest, offset));
1222 }
1223 }
1224
1225 address read_polling_page(Register r, relocInfo::relocType rtype);
1226 void get_polling_page(Register dest, relocInfo::relocType rtype);
1227 address fetch_and_read_polling_page(Register r, relocInfo::relocType rtype);
1228
1229 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1230 void update_byte_crc32(Register crc, Register val, Register table);
1231 void update_word_crc32(Register crc, Register v, Register tmp,
1232 Register table0, Register table1, Register table2, Register table3,
1233 bool upper = false);
1234
1235 void has_negatives(Register ary1, Register len, Register result);
1236
1237 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1238 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1239
1240 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1241 int elem_size);
1242
1243 void fill_words(Register base, Register cnt, Register value);
1244 void zero_words(Register base, uint64_t cnt);
1245 void zero_words(Register ptr, Register cnt);
1246 void zero_dcache_blocks(Register base, Register cnt);
1247
1248 static const int zero_words_block_size;
1249
1250 void byte_array_inflate(Register src, Register dst, Register len,
1251 FloatRegister vtmp1, FloatRegister vtmp2,
1252 FloatRegister vtmp3, Register tmp4);
1253
1254 void char_array_compress(Register src, Register dst, Register len,
1255 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1256 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1257 Register result);
1258
1259 void encode_iso_array(Register src, Register dst,
1260 Register len, Register result,
1261 FloatRegister Vtmp1, FloatRegister Vtmp2,
1262 FloatRegister Vtmp3, FloatRegister Vtmp4);
1263 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1264 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1265 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1266 FloatRegister tmpC4, Register tmp1, Register tmp2,
1267 Register tmp3, Register tmp4, Register tmp5);
1268 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1269 address pio2, address dsin_coef, address dcos_coef);
1270 private:
1271 // begin trigonometric functions support block
1272 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1273 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1274 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1275 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1276 // end trigonometric functions support block
1277 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1278 Register src1, Register src2);
1279 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1280 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1281 }
1282 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1283 Register y, Register y_idx, Register z,
1284 Register carry, Register product,
1285 Register idx, Register kdx);
1286 void multiply_128_x_128_loop(Register y, Register z,
1287 Register carry, Register carry2,
1288 Register idx, Register jdx,
1289 Register yz_idx1, Register yz_idx2,
1290 Register tmp, Register tmp3, Register tmp4,
1291 Register tmp7, Register product_hi);
1292 void kernel_crc32_using_crc32(Register crc, Register buf,
1293 Register len, Register tmp0, Register tmp1, Register tmp2,
1294 Register tmp3);
1295 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1296 Register len, Register tmp0, Register tmp1, Register tmp2,
1297 Register tmp3);
1298 public:
1299 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1300 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1301 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1302 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1303 // ISB may be needed because of a safepoint
1304 void maybe_isb() { isb(); }
1305
1306 private:
1307 // Return the effective address r + (r1 << ext) + offset.
1308 // Uses rscratch2.
1309 Address offsetted_address(Register r, Register r1, Address::extend ext,
1310 int offset, int size);
1311
1312 private:
1313 // Returns an address on the stack which is reachable with a ldr/str of size
1314 // Uses rscratch2 if the address is not directly reachable
1315 Address spill_address(int size, int offset, Register tmp=rscratch2);
1316
1317 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1318
1319 // Check whether two loads/stores can be merged into ldp/stp.
1320 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1321
1322 // Merge current load/store with previous load/store into ldp/stp.
1323 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1324
1325 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1326 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1327
1328 public:
1329 void spill(Register Rx, bool is64, int offset) {
1330 if (is64) {
1331 str(Rx, spill_address(8, offset));
1332 } else {
1333 strw(Rx, spill_address(4, offset));
1334 }
1335 }
1336 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1337 str(Vx, T, spill_address(1 << (int)T, offset));
1338 }
1339 void unspill(Register Rx, bool is64, int offset) {
1340 if (is64) {
1341 ldr(Rx, spill_address(8, offset));
1342 } else {
1343 ldrw(Rx, spill_address(4, offset));
1344 }
1345 }
1346 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1347 ldr(Vx, T, spill_address(1 << (int)T, offset));
1348 }
1349 void spill_copy128(int src_offset, int dst_offset,
1350 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1351 if (src_offset < 512 && (src_offset & 7) == 0 &&
1352 dst_offset < 512 && (dst_offset & 7) == 0) {
1353 ldp(tmp1, tmp2, Address(sp, src_offset));
1354 stp(tmp1, tmp2, Address(sp, dst_offset));
1355 } else {
1356 unspill(tmp1, true, src_offset);
1357 spill(tmp1, true, dst_offset);
1358 unspill(tmp1, true, src_offset+8);
1359 spill(tmp1, true, dst_offset+8);
1360 }
1361 }
1362
1363 void cache_wb(Address line);
1364 void cache_wbsync(bool is_pre);
1365 };
1366
1367 #ifdef ASSERT
1368 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1369 #endif
1370
1371 /**
1372 * class SkipIfEqual:
1373 *
1374 * Instantiating this class will result in assembly code being output that will
1375 * jump around any code emitted between the creation of the instance and it's
1376 * automatic destruction at the end of a scope block, depending on the value of
1377 * the flag passed to the constructor, which will be checked at run-time.
1378 */
1379 class SkipIfEqual {
1380 private:
1381 MacroAssembler* _masm;
1382 Label _label;
1383
1384 public:
1385 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1386 ~SkipIfEqual();
1387 };
1388
1389 struct tableswitch {
1390 Register _reg;
1391 int _insn_index; jint _first_key; jint _last_key;
1392 Label _after;
1393 Label _branches;
1394 };
1395
1396 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP