src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp

8248238: Adding Windows support to OpenJDK on AArch64

Summary: LP64 vs LLP64 changes to add Windows support

Contributed-by: Monica Beckwith <monica.beckwith@microsoft.com>, Ludovic Henry <luhenry@microsoft.com>
Reviewed-by:
8248238: Adding Windows support to OpenJDK on AArch64

Summary: Adding Windows support for AArch64

Contributed-by: Ludovic Henry <luhenry@microsoft.com>, Monica Beckwith <monica.beckwith@microsoft.com>
Reviewed-by:

*** 199,211 ****
  //     2. Return n in r2, y[0] == y0 == v4, y[1] == y1 == v5
  // NOTE: general purpose register names match local variable names in C code
  // NOTE: fpu registers are actively reused. See comments in code about their usage
  void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
      address two_over_pi, address pio2) {
!   const long PIO2_1t = 0x3DD0B4611A626331UL;
!   const long PIO2_2  = 0x3DD0B4611A600000UL;
!   const long PIO2_2t = 0x3BA3198A2E037073UL;
    Label X_IS_NEGATIVE, X_IS_MEDIUM_OR_LARGE, X_IS_POSITIVE_LONG_PI, LARGE_ELSE,
        REDUCTION_DONE, X_IS_MEDIUM_BRANCH_DONE, X_IS_LARGE, NX_SET,
        X_IS_NEGATIVE_LONG_PI;
    Register X = r0, n = r2, ix = r3, jv = r4, tmp5 = r5, jx = r6,
        tmp3 = r7, iqBase = r10, ih = r11, i = r17;
--- 199,211 ----
  //     2. Return n in r2, y[0] == y0 == v4, y[1] == y1 == v5
  // NOTE: general purpose register names match local variable names in C code
  // NOTE: fpu registers are actively reused. See comments in code about their usage
  void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
      address two_over_pi, address pio2) {
!   const int64_t PIO2_1t = 0x3DD0B4611A626331UL;
!   const int64_t PIO2_2  = 0x3DD0B4611A600000UL;
!   const int64_t PIO2_2t = 0x3BA3198A2E037073UL;
    Label X_IS_NEGATIVE, X_IS_MEDIUM_OR_LARGE, X_IS_POSITIVE_LONG_PI, LARGE_ELSE,
        REDUCTION_DONE, X_IS_MEDIUM_BRANCH_DONE, X_IS_LARGE, NX_SET,
        X_IS_NEGATIVE_LONG_PI;
    Register X = r0, n = r2, ix = r3, jv = r4, tmp5 = r5, jx = r6,
        tmp3 = r7, iqBase = r10, ih = r11, i = r17;
*** 687,697 ****
        CONVERTION_FOR, FW_Y0_NO_NEGATION, FW_FOR1_DONE, FW_FOR2, FW_FOR2_DONE,
        IH_FOR, SKIP_F_LOAD, RECOMP_FOR1, RECOMP_FIRST_FOR, INIT_F_COPY,
        RECOMP_FOR1_CHECK;
    Register tmp2 = r1, n = r2, jv = r4, tmp5 = r5, jx = r6,
        tmp3 = r7, iqBase = r10, ih = r11, tmp4 = r12, tmp1 = r13,
!       jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r18;
      // jp = jk == init_jk[prec] = init_jk[2] == {2,3,4,6}[2] == 4
      // jx = nx - 1
      lea(twoOverPiBase, ExternalAddress(two_over_pi));
      cmpw(jv, zr);
      addw(tmp4, jx, 4); // tmp4 = m = jx + jk = jx + 4. jx is in {0,1,2} so m is in [4,5,6]
--- 687,697 ----
        CONVERTION_FOR, FW_Y0_NO_NEGATION, FW_FOR1_DONE, FW_FOR2, FW_FOR2_DONE,
        IH_FOR, SKIP_F_LOAD, RECOMP_FOR1, RECOMP_FIRST_FOR, INIT_F_COPY,
        RECOMP_FOR1_CHECK;
    Register tmp2 = r1, n = r2, jv = r4, tmp5 = r5, jx = r6,
        tmp3 = r7, iqBase = r10, ih = r11, tmp4 = r12, tmp1 = r13,
!       jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r19;
      // jp = jk == init_jk[prec] = init_jk[2] == {2,3,4,6}[2] == 4
      // jx = nx - 1
      lea(twoOverPiBase, ExternalAddress(two_over_pi));
      cmpw(jv, zr);
      addw(tmp4, jx, 4); // tmp4 = m = jx + jk = jx + 4. jx is in {0,1,2} so m is in [4,5,6]