1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/macros.hpp"
35 #include "vm_version_aarch64.hpp"
36
37 #include OS_HEADER_INLINE(os)
38
39 #ifndef _WIN64
40 #include <sys/auxv.h>
41 #include <asm/hwcap.h>
42 #endif
43
44 int VM_Version::_cpu;
45 int VM_Version::_model;
46 int VM_Version::_model2;
47 int VM_Version::_variant;
48 int VM_Version::_revision;
49 int VM_Version::_stepping;
50 bool VM_Version::_dcpop;
51 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
52
53 static BufferBlob* stub_blob;
54 static const int stub_size = 550;
55
56 extern "C" {
57 typedef void (*getPsrInfo_stub_t)(void*);
58 }
59 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
60
61
62 class VM_Version_StubGenerator: public StubCodeGenerator {
63 public:
64
65 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
66
67 address generate_getPsrInfo() {
68 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
69 # define __ _masm->
70 address start = __ pc();
71
72 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
73
74 address entry = __ pc();
75
76 __ enter();
77
78 __ get_dczid_el0(rscratch1);
79 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
80
81 #ifndef _WIN64
82 __ get_ctr_el0(rscratch1);
83 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
84 #endif
85
86 __ leave();
87 __ ret(lr);
88
89 # undef __
90
91 return start;
92 }
93 };
94
95
96 void VM_Version::get_processor_features() {
97 _supports_cx8 = true;
98 _supports_atomic_getset4 = true;
99 _supports_atomic_getadd4 = true;
100 _supports_atomic_getset8 = true;
101 _supports_atomic_getadd8 = true;
102
103 getPsrInfo_stub(&_psr_info);
104
105 int dcache_line = VM_Version::dcache_line_size();
106
107 // Limit AllocatePrefetchDistance so that it does not exceed the
108 // constraint in AllocatePrefetchDistanceConstraintFunc.
109 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
110 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
111
112 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
113 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
114 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
115 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
116 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
117 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
118 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
119 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
120
121 if (PrefetchCopyIntervalInBytes != -1 &&
122 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
123 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
124 PrefetchCopyIntervalInBytes &= ~7;
125 if (PrefetchCopyIntervalInBytes >= 32768)
126 PrefetchCopyIntervalInBytes = 32760;
127 }
128
129 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
130 warning("AllocatePrefetchDistance must be multiple of 8");
131 AllocatePrefetchDistance &= ~7;
132 }
133
134 if (AllocatePrefetchStepSize & 7) {
135 warning("AllocatePrefetchStepSize must be multiple of 8");
136 AllocatePrefetchStepSize &= ~7;
137 }
138
139 if (SoftwarePrefetchHintDistance != -1 &&
140 (SoftwarePrefetchHintDistance & 7)) {
141 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
142 SoftwarePrefetchHintDistance &= ~7;
143 }
144
145 #ifndef _WIN64
146 _features = getauxval(AT_HWCAP);
147 #else
148 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) _features |= CPU_CRC32;
149 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) _features |= CPU_AES | CPU_SHA1 | CPU_SHA2;
150 if (IsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE)) _features |= CPU_ASIMD;
151 // No check for CPU_PMULL
152 #endif // _WIN64
153
154 char buf[512];
155
156 int cpu_lines = 0;
157 #ifndef _WIN64
158 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
159 // need a large buffer as the flags line may include lots of text
160 char buf[1024], *p;
161 while (fgets(buf, sizeof (buf), f) != NULL) {
162 if ((p = strchr(buf, ':')) != NULL) {
163 int64_t v = strtol(p+1, NULL, 0);
164 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
165 _cpu = v;
166 cpu_lines++;
167 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
168 _variant = v;
169 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
170 if (_model != v) _model2 = _model;
171 _model = v;
172 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
173 _revision = v;
174 } else if (strncmp(buf, "flags", sizeof("flags") - 1) == 0) {
175 if (strstr(p+1, "dcpop")) {
176 _dcpop = true;
177 }
178 }
179 }
180 }
181 fclose(f);
182 }
183 #else
184 {
185 char* buf = ::getenv("PROCESSOR_IDENTIFIER");
186 if (buf && strstr(buf, "Ampere(TM)") != NULL) {
187 _cpu = CPU_AMCC;
188 cpu_lines++;
189 } else if (buf && strstr(buf, "Cavium Inc.") != NULL) {
190 _cpu = CPU_CAVIUM;
191 cpu_lines++;
192 } else {
193 log_info(os)("VM_Version: unknown CPU model");
194 }
195
196 if (_cpu) {
197 SYSTEM_INFO si;
198 GetSystemInfo(&si);
199 _model = si.wProcessorLevel;
200 _variant = si.wProcessorRevision / 0xFF;
201 _revision = si.wProcessorRevision & 0xFF;
202 }
203 }
204 #endif // _WIN64
205
206 if (os::supports_map_sync()) {
207 // if dcpop is available publish data cache line flush size via
208 // generic field, otherwise let if default to zero thereby
209 // disabling writeback
210 if (_dcpop) {
211 _data_cache_line_flush_size = dcache_line;
212 }
213 }
214
215 // Enable vendor specific features
216
217 // Ampere eMAG
218 if (_cpu == CPU_AMCC && (_model == 0) && (_variant == 0x3)) {
219 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
220 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
221 }
222 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
223 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
224 }
225 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
226 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
227 }
228 }
229
230 // ThunderX
231 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
232 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
233 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
234 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
235 }
236 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
237 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
238 }
239 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
240 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
241 }
242 }
243
244 // ThunderX2
245 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
246 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
247 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
248 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
249 }
250 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
251 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
252 }
253 }
254
255 // HiSilicon TSV110
256 if (_cpu == CPU_HISILICON && _model == 0xd01) {
257 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
258 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
259 }
260 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
261 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
262 }
263 }
264
265 // Cortex A53
266 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
267 _features |= CPU_A53MAC;
268 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
269 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
270 }
271 }
272
273 // Cortex A73
274 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
275 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
276 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
277 }
278 // A73 is faster with short-and-easy-for-speculative-execution-loop
279 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
280 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
281 }
282 }
283
284 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
285 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
286 // we assume the worst and assume we could be on a big little system and have
287 // undisclosed A53 cores which we could be swapped to at any stage
288 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
289
290 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
291 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
292 if (_features & CPU_ASIMD) strcat(buf, ", simd");
293 if (_features & CPU_CRC32) strcat(buf, ", crc");
294 if (_features & CPU_AES) strcat(buf, ", aes");
295 if (_features & CPU_SHA1) strcat(buf, ", sha1");
296 if (_features & CPU_SHA2) strcat(buf, ", sha256");
297 if (_features & CPU_LSE) strcat(buf, ", lse");
298
299 _features_string = os::strdup(buf);
300
301 if (FLAG_IS_DEFAULT(UseCRC32)) {
302 UseCRC32 = (_features & CPU_CRC32) != 0;
303 }
304
305 if (UseCRC32 && (_features & CPU_CRC32) == 0) {
306 warning("UseCRC32 specified, but not supported on this CPU");
307 FLAG_SET_DEFAULT(UseCRC32, false);
308 }
309
310 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
311 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
312 }
313
314 if (UseVectorizedMismatchIntrinsic) {
315 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
316 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
317 }
318
319 if (_features & CPU_LSE) {
320 if (FLAG_IS_DEFAULT(UseLSE))
321 FLAG_SET_DEFAULT(UseLSE, true);
322 } else {
323 if (UseLSE) {
324 warning("UseLSE specified, but not supported on this CPU");
325 FLAG_SET_DEFAULT(UseLSE, false);
326 }
327 }
328
329 if (_features & CPU_AES) {
330 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
331 UseAESIntrinsics =
332 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
333 if (UseAESIntrinsics && !UseAES) {
334 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
335 UseAES = true;
336 }
337 } else {
338 if (UseAES) {
339 warning("AES instructions are not available on this CPU");
340 FLAG_SET_DEFAULT(UseAES, false);
341 }
342 if (UseAESIntrinsics) {
343 warning("AES intrinsics are not available on this CPU");
344 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
345 }
346 }
347
348 if (UseAESCTRIntrinsics) {
349 warning("AES/CTR intrinsics are not available on this CPU");
350 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
351 }
352
353 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
354 UseCRC32Intrinsics = true;
355 }
356
357 if (_features & CPU_CRC32) {
358 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
359 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
360 }
361 } else if (UseCRC32CIntrinsics) {
362 warning("CRC32C is not available on the CPU");
363 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
364 }
365
366 if (FLAG_IS_DEFAULT(UseFMA)) {
367 FLAG_SET_DEFAULT(UseFMA, true);
368 }
369
370 if (_features & (CPU_SHA1 | CPU_SHA2)) {
371 if (FLAG_IS_DEFAULT(UseSHA)) {
372 FLAG_SET_DEFAULT(UseSHA, true);
373 }
374 } else if (UseSHA) {
375 warning("SHA instructions are not available on this CPU");
376 FLAG_SET_DEFAULT(UseSHA, false);
377 }
378
379 if (UseSHA && (_features & CPU_SHA1)) {
380 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
381 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
382 }
383 } else if (UseSHA1Intrinsics) {
384 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
385 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
386 }
387
388 if (UseSHA && (_features & CPU_SHA2)) {
389 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
390 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
391 }
392 } else if (UseSHA256Intrinsics) {
393 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
394 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
395 }
396
397 if (UseSHA512Intrinsics) {
398 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
399 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
400 }
401
402 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
403 FLAG_SET_DEFAULT(UseSHA, false);
404 }
405
406 if (_features & CPU_PMULL) {
407 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
408 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
409 }
410 } else if (UseGHASHIntrinsics) {
411 warning("GHASH intrinsics are not available on this CPU");
412 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
413 }
414
415 if (is_zva_enabled()) {
416 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
417 FLAG_SET_DEFAULT(UseBlockZeroing, true);
418 }
419 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
420 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
421 }
422 } else if (UseBlockZeroing) {
423 warning("DC ZVA is not available on this CPU");
424 FLAG_SET_DEFAULT(UseBlockZeroing, false);
425 }
426
427 // This machine allows unaligned memory accesses
428 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
429 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
430 }
431
432 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
433 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
434 }
435
436 if (!UsePopCountInstruction) {
437 warning("UsePopCountInstruction is always enabled on this CPU");
438 UsePopCountInstruction = true;
439 }
440
441 #ifdef COMPILER2
442 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
443 UseMultiplyToLenIntrinsic = true;
444 }
445
446 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
447 UseSquareToLenIntrinsic = true;
448 }
449
450 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
451 UseMulAddIntrinsic = true;
452 }
453
454 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
455 UseMontgomeryMultiplyIntrinsic = true;
456 }
457 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
458 UseMontgomerySquareIntrinsic = true;
459 }
460
461 if (FLAG_IS_DEFAULT(OptoScheduling)) {
462 OptoScheduling = true;
463 }
464
465 if (FLAG_IS_DEFAULT(AlignVector)) {
466 AlignVector = AvoidUnalignedAccesses;
467 }
468 #endif
469 }
470
471 void VM_Version::initialize() {
472 ResourceMark rm;
473
474 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
475 if (stub_blob == NULL) {
476 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
477 }
478
479 CodeBuffer c(stub_blob);
480 VM_Version_StubGenerator g(&c);
481 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
482 g.generate_getPsrInfo());
483
484 get_processor_features();
485
486 UNSUPPORTED_OPTION(CriticalJNINatives);
487 }