1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
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24 */
25
26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
28
29 #include "runtime/abstract_vm_version.hpp"
30 #include "runtime/globals_extension.hpp"
31 #include "utilities/sizes.hpp"
32 #include "runtime/java.hpp"
33
34 class VM_Version : public Abstract_VM_Version {
35 friend class JVMCIVMStructs;
36
37 protected:
38 static int _cpu;
39 static int _model;
40 static int _model2;
41 static int _variant;
42 static int _revision;
43 static int _stepping;
44 static bool _dcpop;
45 struct PsrInfo {
46 uint32_t dczid_el0;
47 #ifndef _WIN64
48 // On Windows-aarch64, this register is not accessible. We then need to
49 // access the cache line size in a different way. Instead, we get the cache
50 // line size in os::win32::get_cacheline_size.
51 uint32_t ctr_el0;
52 #endif
53 };
54 static PsrInfo _psr_info;
55 static void get_processor_features();
56
57 public:
58 // Initialization
59 static void initialize();
60
61 // Asserts
62 static void assert_is_initialized() {
63 }
64
65 static bool expensive_load(int ld_size, int scale) {
66 if (cpu_family() == CPU_ARM) {
67 // Half-word load with index shift by 1 (aka scale is 2) has
68 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
69 if (ld_size == 2 && scale == 2) {
70 return true;
71 }
72 }
73 return false;
74 }
75
76 // The CPU implementer codes can be found in
77 // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
78 // https://developer.arm.com/docs/ddi0487/latest
79 enum Family {
80 CPU_AMPERE = 0xC0,
81 CPU_ARM = 'A',
82 CPU_BROADCOM = 'B',
83 CPU_CAVIUM = 'C',
84 CPU_DEC = 'D',
85 CPU_HISILICON = 'H',
86 CPU_INFINEON = 'I',
87 CPU_MOTOROLA = 'M',
88 CPU_NVIDIA = 'N',
89 CPU_AMCC = 'P',
90 CPU_QUALCOM = 'Q',
91 CPU_MARVELL = 'V',
92 CPU_INTEL = 'i',
93 };
94
95 enum Feature_Flag {
96 CPU_FP = (1<<0),
97 CPU_ASIMD = (1<<1),
98 CPU_EVTSTRM = (1<<2),
99 CPU_AES = (1<<3),
100 CPU_PMULL = (1<<4),
101 CPU_SHA1 = (1<<5),
102 CPU_SHA2 = (1<<6),
103 CPU_CRC32 = (1<<7),
104 CPU_LSE = (1<<8),
105 CPU_STXR_PREFETCH= (1 << 29),
106 CPU_A53MAC = (1 << 30),
107 };
108
109 static int cpu_family() { return _cpu; }
110 static int cpu_model() { return _model; }
111 static int cpu_model2() { return _model2; }
112 static int cpu_variant() { return _variant; }
113 static int cpu_revision() { return _revision; }
114 static bool supports_dcpop() { return _dcpop; }
115
116 static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
117 #ifndef _WIN64
118 static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); }
119 #endif
120 static bool is_zva_enabled() {
121 // Check the DZP bit (bit 4) of dczid_el0 is zero
122 // and block size (bit 0~3) is not zero.
123 return ((_psr_info.dczid_el0 & 0x10) == 0 &&
124 (_psr_info.dczid_el0 & 0xf) != 0);
125 }
126 static int zva_length() {
127 assert(is_zva_enabled(), "ZVA not available");
128 return 4 << (_psr_info.dczid_el0 & 0xf);
129 }
130 static int icache_line_size() {
131 #ifndef _WIN64
132 return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
133 #else
134 return os::win32::get_cacheline_size();
135 #endif
136 }
137 static int dcache_line_size() {
138 #ifndef _WIN64
139 return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
140 #else
141 return os::win32::get_cacheline_size();
142 #endif
143 }
144 static bool supports_fast_class_init_checks() { return true; }
145 };
146
147 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP