1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 public:
40 using Assembler::mov;
41 using Assembler::movi;
42
43 protected:
44
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50 #ifdef CC_INTERP
51 // c++ interpreter never wants to use interp_masm version of call_VM
52 #define VIRTUAL
53 #else
54 #define VIRTUAL virtual
55 #endif
56
57 VIRTUAL void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label *retaddr = NULL
61 );
62
63 VIRTUAL void call_VM_leaf_base(
64 address entry_point, // the entry point
65 int number_of_arguments, // the number of arguments to pop after the call
66 Label &retaddr) {
67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
68 }
69
70 // This is the base routine called by the different versions of call_VM. The interpreter
71 // may customize this version by overriding it for its purposes (e.g., to save/restore
72 // additional registers when doing a VM call).
73 //
74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
75 // returns the register which contains the thread upon return. If a thread register has been
76 // specified, the return value will correspond to that register. If no last_java_sp is specified
77 // (noreg) than rsp will be used instead.
78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
80 Register java_thread, // the thread if computed before ; use noreg otherwise
81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
82 address entry_point, // the entry point
83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
84 bool check_exceptions // whether to check for pending exceptions after return
85 );
86
87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
88 // The implementation is only non-empty for the InterpreterMacroAssembler,
89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
90 virtual void check_and_handle_popframe(Register java_thread);
91 virtual void check_and_handle_earlyret(Register java_thread);
92
93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
94
95 // Maximum size of class area in Metaspace when compressed
96 uint64_t use_XOR_for_compressed_class_base;
97
98 public:
99 MacroAssembler(CodeBuffer* code) : Assembler(code) {
100 use_XOR_for_compressed_class_base
101 = (operand_valid_for_logical_immediate(false /*is32*/,
102 (uint64_t)Universe::narrow_klass_base())
103 && ((uint64_t)Universe::narrow_klass_base()
104 > (1u << log2_intptr(CompressedClassSpaceSize))));
105 }
106
107 // Biased locking support
108 // lock_reg and obj_reg must be loaded up with the appropriate values.
109 // swap_reg is killed.
110 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
111 // Optional slow case is for implementations (interpreter and C1) which branch to
112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
113 // Returns offset of first potentially-faulting instruction for null
114 // check info (currently consumed only by C1). If
115 // swap_reg_contains_mark is true then returns -1 as it is assumed
116 // the calling code has already passed any potential faults.
117 int biased_locking_enter(Register lock_reg, Register obj_reg,
118 Register swap_reg, Register tmp_reg,
119 bool swap_reg_contains_mark,
120 Label& done, Label* slow_case = NULL,
121 BiasedLockingCounters* counters = NULL);
122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
123
124
125 // Helper functions for statistics gathering.
126 // Unconditional atomic increment.
127 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
129 lea(tmp1, counter_addr);
130 atomic_incw(tmp1, tmp2, tmp3);
131 }
132 // Load Effective Address
133 void lea(Register r, const Address &a) {
134 InstructionMark im(this);
135 code_section()->relocate(inst_mark(), a.rspec());
136 a.lea(this, r);
137 }
138
139 void addmw(Address a, Register incr, Register scratch) {
140 ldrw(scratch, a);
141 addw(scratch, scratch, incr);
142 strw(scratch, a);
143 }
144
145 // Add constant to memory word
146 void addmw(Address a, int imm, Register scratch) {
147 ldrw(scratch, a);
148 if (imm > 0)
149 addw(scratch, scratch, (unsigned)imm);
150 else
151 subw(scratch, scratch, (unsigned)-imm);
152 strw(scratch, a);
153 }
154
155 void bind(Label& L) {
156 Assembler::bind(L);
157 code()->clear_last_membar();
158 }
159
160 void membar(Membar_mask_bits order_constraint);
161
162 // Frame creation and destruction shared between JITs.
163 void build_frame(int framesize);
164 void remove_frame(int framesize);
165
166 virtual void _call_Unimplemented(address call_site) {
167 mov(rscratch2, call_site);
168 haltsim();
169 }
170
171 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
172
173 virtual void notify(int type);
174
175 // aliases defined in AARCH64 spec
176
177 template<class T>
178 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
179 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
180
181 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
182 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
183
184 void cset(Register Rd, Assembler::Condition cond) {
185 csinc(Rd, zr, zr, ~cond);
186 }
187 void csetw(Register Rd, Assembler::Condition cond) {
188 csincw(Rd, zr, zr, ~cond);
189 }
190
191 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
192 csneg(Rd, Rn, Rn, ~cond);
193 }
194 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
195 csnegw(Rd, Rn, Rn, ~cond);
196 }
197
198 inline void movw(Register Rd, Register Rn) {
199 if (Rd == sp || Rn == sp) {
200 addw(Rd, Rn, 0U);
201 } else {
202 orrw(Rd, zr, Rn);
203 }
204 }
205 inline void mov(Register Rd, Register Rn) {
206 assert(Rd != r31_sp && Rn != r31_sp, "should be");
207 if (Rd == Rn) {
208 } else if (Rd == sp || Rn == sp) {
209 add(Rd, Rn, 0U);
210 } else {
211 orr(Rd, zr, Rn);
212 }
213 }
214
215 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
216 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
217
218 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
219 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
220
221 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
222 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
223
224 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
225 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
226 }
227 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
228 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
229 }
230
231 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 bfmw(Rd, Rn, lsb, (lsb + width - 1));
233 }
234 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
235 bfm(Rd, Rn, lsb , (lsb + width - 1));
236 }
237
238 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
240 }
241 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
242 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
243 }
244
245 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
247 }
248 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
249 sbfm(Rd, Rn, lsb , (lsb + width - 1));
250 }
251
252 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
254 }
255 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
257 }
258
259 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
261 }
262 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 ubfm(Rd, Rn, lsb , (lsb + width - 1));
264 }
265
266 inline void asrw(Register Rd, Register Rn, unsigned imm) {
267 sbfmw(Rd, Rn, imm, 31);
268 }
269
270 inline void asr(Register Rd, Register Rn, unsigned imm) {
271 sbfm(Rd, Rn, imm, 63);
272 }
273
274 inline void lslw(Register Rd, Register Rn, unsigned imm) {
275 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
276 }
277
278 inline void lsl(Register Rd, Register Rn, unsigned imm) {
279 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
280 }
281
282 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
283 ubfmw(Rd, Rn, imm, 31);
284 }
285
286 inline void lsr(Register Rd, Register Rn, unsigned imm) {
287 ubfm(Rd, Rn, imm, 63);
288 }
289
290 inline void rorw(Register Rd, Register Rn, unsigned imm) {
291 extrw(Rd, Rn, Rn, imm);
292 }
293
294 inline void ror(Register Rd, Register Rn, unsigned imm) {
295 extr(Rd, Rn, Rn, imm);
296 }
297
298 inline void sxtbw(Register Rd, Register Rn) {
299 sbfmw(Rd, Rn, 0, 7);
300 }
301 inline void sxthw(Register Rd, Register Rn) {
302 sbfmw(Rd, Rn, 0, 15);
303 }
304 inline void sxtb(Register Rd, Register Rn) {
305 sbfm(Rd, Rn, 0, 7);
306 }
307 inline void sxth(Register Rd, Register Rn) {
308 sbfm(Rd, Rn, 0, 15);
309 }
310 inline void sxtw(Register Rd, Register Rn) {
311 sbfm(Rd, Rn, 0, 31);
312 }
313
314 inline void uxtbw(Register Rd, Register Rn) {
315 ubfmw(Rd, Rn, 0, 7);
316 }
317 inline void uxthw(Register Rd, Register Rn) {
318 ubfmw(Rd, Rn, 0, 15);
319 }
320 inline void uxtb(Register Rd, Register Rn) {
321 ubfm(Rd, Rn, 0, 7);
322 }
323 inline void uxth(Register Rd, Register Rn) {
324 ubfm(Rd, Rn, 0, 15);
325 }
326 inline void uxtw(Register Rd, Register Rn) {
327 ubfm(Rd, Rn, 0, 31);
328 }
329
330 inline void cmnw(Register Rn, Register Rm) {
331 addsw(zr, Rn, Rm);
332 }
333 inline void cmn(Register Rn, Register Rm) {
334 adds(zr, Rn, Rm);
335 }
336
337 inline void cmpw(Register Rn, Register Rm) {
338 subsw(zr, Rn, Rm);
339 }
340 inline void cmp(Register Rn, Register Rm) {
341 subs(zr, Rn, Rm);
342 }
343
344 inline void negw(Register Rd, Register Rn) {
345 subw(Rd, zr, Rn);
346 }
347
348 inline void neg(Register Rd, Register Rn) {
349 sub(Rd, zr, Rn);
350 }
351
352 inline void negsw(Register Rd, Register Rn) {
353 subsw(Rd, zr, Rn);
354 }
355
356 inline void negs(Register Rd, Register Rn) {
357 subs(Rd, zr, Rn);
358 }
359
360 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
361 addsw(zr, Rn, Rm, kind, shift);
362 }
363 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
364 adds(zr, Rn, Rm, kind, shift);
365 }
366
367 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
368 subsw(zr, Rn, Rm, kind, shift);
369 }
370 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
371 subs(zr, Rn, Rm, kind, shift);
372 }
373
374 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
375 subw(Rd, zr, Rn, kind, shift);
376 }
377
378 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
379 sub(Rd, zr, Rn, kind, shift);
380 }
381
382 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
383 subsw(Rd, zr, Rn, kind, shift);
384 }
385
386 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
387 subs(Rd, zr, Rn, kind, shift);
388 }
389
390 inline void mnegw(Register Rd, Register Rn, Register Rm) {
391 msubw(Rd, Rn, Rm, zr);
392 }
393 inline void mneg(Register Rd, Register Rn, Register Rm) {
394 msub(Rd, Rn, Rm, zr);
395 }
396
397 inline void mulw(Register Rd, Register Rn, Register Rm) {
398 maddw(Rd, Rn, Rm, zr);
399 }
400 inline void mul(Register Rd, Register Rn, Register Rm) {
401 madd(Rd, Rn, Rm, zr);
402 }
403
404 inline void smnegl(Register Rd, Register Rn, Register Rm) {
405 smsubl(Rd, Rn, Rm, zr);
406 }
407 inline void smull(Register Rd, Register Rn, Register Rm) {
408 smaddl(Rd, Rn, Rm, zr);
409 }
410
411 inline void umnegl(Register Rd, Register Rn, Register Rm) {
412 umsubl(Rd, Rn, Rm, zr);
413 }
414 inline void umull(Register Rd, Register Rn, Register Rm) {
415 umaddl(Rd, Rn, Rm, zr);
416 }
417
418 #define WRAP(INSN) \
419 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
420 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
421 nop(); \
422 Assembler::INSN(Rd, Rn, Rm, Ra); \
423 }
424
425 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
426 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
427 #undef WRAP
428
429
430 // macro assembly operations needed for aarch64
431
432 // first two private routines for loading 32 bit or 64 bit constants
433 private:
434
435 void mov_immediate64(Register dst, u_int64_t imm64);
436 void mov_immediate32(Register dst, u_int32_t imm32);
437
438 int push(unsigned int bitset, Register stack);
439 int pop(unsigned int bitset, Register stack);
440
441 void mov(Register dst, Address a);
442
443 public:
444 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
445 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
446
447 // now mov instructions for loading absolute addresses and 32 or
448 // 64 bit integers
449
450 inline void mov(Register dst, address addr)
451 {
452 mov_immediate64(dst, (u_int64_t)addr);
453 }
454
455 inline void mov(Register dst, u_int64_t imm64)
456 {
457 mov_immediate64(dst, imm64);
458 }
459
460 inline void movw(Register dst, u_int32_t imm32)
461 {
462 mov_immediate32(dst, imm32);
463 }
464
465 inline void mov(Register dst, long l)
466 {
467 mov(dst, (u_int64_t)l);
468 }
469
470 inline void mov(Register dst, int i)
471 {
472 mov(dst, (long)i);
473 }
474
475 void mov(Register dst, RegisterOrConstant src) {
476 if (src.is_register())
477 mov(dst, src.as_register());
478 else
479 mov(dst, src.as_constant());
480 }
481
482 void movptr(Register r, uintptr_t imm64);
483
484 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
485
486 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
487 orr(Vd, T, Vn, Vn);
488 }
489
490 // macro instructions for accessing and updating floating point
491 // status register
492 //
493 // FPSR : op1 == 011
494 // CRn == 0100
495 // CRm == 0100
496 // op2 == 001
497
498 inline void get_fpsr(Register reg)
499 {
500 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
501 }
502
503 inline void set_fpsr(Register reg)
504 {
505 msr(0b011, 0b0100, 0b0100, 0b001, reg);
506 }
507
508 inline void clear_fpsr()
509 {
510 msr(0b011, 0b0100, 0b0100, 0b001, zr);
511 }
512
513 // idiv variant which deals with MINLONG as dividend and -1 as divisor
514 int corrected_idivl(Register result, Register ra, Register rb,
515 bool want_remainder, Register tmp = rscratch1);
516 int corrected_idivq(Register result, Register ra, Register rb,
517 bool want_remainder, Register tmp = rscratch1);
518
519 // Support for NULL-checks
520 //
521 // Generates code that causes a NULL OS exception if the content of reg is NULL.
522 // If the accessed location is M[reg + offset] and the offset is known, provide the
523 // offset. No explicit code generation is needed if the offset is within a certain
524 // range (0 <= offset <= page_size).
525
526 virtual void null_check(Register reg, int offset = -1);
527 static bool needs_explicit_null_check(intptr_t offset);
528
529 static address target_addr_for_insn(address insn_addr, unsigned insn);
530 static address target_addr_for_insn(address insn_addr) {
531 unsigned insn = *(unsigned*)insn_addr;
532 return target_addr_for_insn(insn_addr, insn);
533 }
534
535 // Required platform-specific helpers for Label::patch_instructions.
536 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
537 static int pd_patch_instruction_size(address branch, address target);
538 static void pd_patch_instruction(address branch, address target) {
539 pd_patch_instruction_size(branch, target);
540 }
541 static address pd_call_destination(address branch) {
542 return target_addr_for_insn(branch);
543 }
544 #ifndef PRODUCT
545 static void pd_print_patched_instruction(address branch);
546 #endif
547
548 static int patch_oop(address insn_addr, address o);
549
550 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
551
552 // The following 4 methods return the offset of the appropriate move instruction
553
554 // Support for fast byte/short loading with zero extension (depending on particular CPU)
555 int load_unsigned_byte(Register dst, Address src);
556 int load_unsigned_short(Register dst, Address src);
557
558 // Support for fast byte/short loading with sign extension (depending on particular CPU)
559 int load_signed_byte(Register dst, Address src);
560 int load_signed_short(Register dst, Address src);
561
562 int load_signed_byte32(Register dst, Address src);
563 int load_signed_short32(Register dst, Address src);
564
565 // Support for sign-extension (hi:lo = extend_sign(lo))
566 void extend_sign(Register hi, Register lo);
567
568 // Load and store values by size and signed-ness
569 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
570 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
571
572 // Support for inc/dec with optimal instruction selection depending on value
573
574 // x86_64 aliases an unqualified register/address increment and
575 // decrement to call incrementq and decrementq but also supports
576 // explicitly sized calls to incrementq/decrementq or
577 // incrementl/decrementl
578
579 // for aarch64 the proper convention would be to use
580 // increment/decrement for 64 bit operatons and
581 // incrementw/decrementw for 32 bit operations. so when porting
582 // x86_64 code we can leave calls to increment/decrement as is,
583 // replace incrementq/decrementq with increment/decrement and
584 // replace incrementl/decrementl with incrementw/decrementw.
585
586 // n.b. increment/decrement calls with an Address destination will
587 // need to use a scratch register to load the value to be
588 // incremented. increment/decrement calls which add or subtract a
589 // constant value greater than 2^12 will need to use a 2nd scratch
590 // register to hold the constant. so, a register increment/decrement
591 // may trash rscratch2 and an address increment/decrement trash
592 // rscratch and rscratch2
593
594 void decrementw(Address dst, int value = 1);
595 void decrementw(Register reg, int value = 1);
596
597 void decrement(Register reg, int value = 1);
598 void decrement(Address dst, int value = 1);
599
600 void incrementw(Address dst, int value = 1);
601 void incrementw(Register reg, int value = 1);
602
603 void increment(Register reg, int value = 1);
604 void increment(Address dst, int value = 1);
605
606
607 // Alignment
608 void align(int modulus);
609
610 // Stack frame creation/removal
611 void enter()
612 {
613 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
614 mov(rfp, sp);
615 }
616 void leave()
617 {
618 mov(sp, rfp);
619 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
620 }
621
622 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
623 // The pointer will be loaded into the thread register.
624 void get_thread(Register thread);
625
626
627 // Support for VM calls
628 //
629 // It is imperative that all calls into the VM are handled via the call_VM macros.
630 // They make sure that the stack linkage is setup correctly. call_VM's correspond
631 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
632
633
634 void call_VM(Register oop_result,
635 address entry_point,
636 bool check_exceptions = true);
637 void call_VM(Register oop_result,
638 address entry_point,
639 Register arg_1,
640 bool check_exceptions = true);
641 void call_VM(Register oop_result,
642 address entry_point,
643 Register arg_1, Register arg_2,
644 bool check_exceptions = true);
645 void call_VM(Register oop_result,
646 address entry_point,
647 Register arg_1, Register arg_2, Register arg_3,
648 bool check_exceptions = true);
649
650 // Overloadings with last_Java_sp
651 void call_VM(Register oop_result,
652 Register last_java_sp,
653 address entry_point,
654 int number_of_arguments = 0,
655 bool check_exceptions = true);
656 void call_VM(Register oop_result,
657 Register last_java_sp,
658 address entry_point,
659 Register arg_1, bool
660 check_exceptions = true);
661 void call_VM(Register oop_result,
662 Register last_java_sp,
663 address entry_point,
664 Register arg_1, Register arg_2,
665 bool check_exceptions = true);
666 void call_VM(Register oop_result,
667 Register last_java_sp,
668 address entry_point,
669 Register arg_1, Register arg_2, Register arg_3,
670 bool check_exceptions = true);
671
672 void get_vm_result (Register oop_result, Register thread);
673 void get_vm_result_2(Register metadata_result, Register thread);
674
675 // These always tightly bind to MacroAssembler::call_VM_base
676 // bypassing the virtual implementation
677 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
678 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
679 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
680 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
681 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
682
683 void call_VM_leaf(address entry_point,
684 int number_of_arguments = 0);
685 void call_VM_leaf(address entry_point,
686 Register arg_1);
687 void call_VM_leaf(address entry_point,
688 Register arg_1, Register arg_2);
689 void call_VM_leaf(address entry_point,
690 Register arg_1, Register arg_2, Register arg_3);
691
692 // These always tightly bind to MacroAssembler::call_VM_leaf_base
693 // bypassing the virtual implementation
694 void super_call_VM_leaf(address entry_point);
695 void super_call_VM_leaf(address entry_point, Register arg_1);
696 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
697 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
698 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
699
700 // last Java Frame (fills frame anchor)
701 void set_last_Java_frame(Register last_java_sp,
702 Register last_java_fp,
703 address last_java_pc,
704 Register scratch);
705
706 void set_last_Java_frame(Register last_java_sp,
707 Register last_java_fp,
708 Label &last_java_pc,
709 Register scratch);
710
711 void set_last_Java_frame(Register last_java_sp,
712 Register last_java_fp,
713 Register last_java_pc,
714 Register scratch);
715
716 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
717
718 // thread in the default location (r15_thread on 64bit)
719 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
720
721 // Stores
722 void store_check(Register obj); // store check for obj - register is destroyed afterwards
723 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
724
725 #if INCLUDE_ALL_GCS
726
727 void g1_write_barrier_pre(Register obj,
728 Register pre_val,
729 Register thread,
730 Register tmp,
731 bool tosca_live,
732 bool expand_call);
733
734 void g1_write_barrier_post(Register store_addr,
735 Register new_val,
736 Register thread,
737 Register tmp,
738 Register tmp2);
739
740 #endif // INCLUDE_ALL_GCS
741
742 // oop manipulations
743 void load_klass(Register dst, Register src);
744 void store_klass(Register dst, Register src);
745 void cmp_klass(Register oop, Register trial_klass, Register tmp);
746
747 void load_heap_oop(Register dst, Address src);
748
749 void load_heap_oop_not_null(Register dst, Address src);
750 void store_heap_oop(Address dst, Register src);
751
752 // currently unimplemented
753 // Used for storing NULL. All other oop constants should be
754 // stored using routines that take a jobject.
755 void store_heap_oop_null(Address dst);
756
757 void load_prototype_header(Register dst, Register src);
758
759 void store_klass_gap(Register dst, Register src);
760
761 // This dummy is to prevent a call to store_heap_oop from
762 // converting a zero (like NULL) into a Register by giving
763 // the compiler two choices it can't resolve
764
765 void store_heap_oop(Address dst, void* dummy);
766
767 void encode_heap_oop(Register d, Register s);
768 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
769 void decode_heap_oop(Register d, Register s);
770 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
771 void encode_heap_oop_not_null(Register r);
772 void decode_heap_oop_not_null(Register r);
773 void encode_heap_oop_not_null(Register dst, Register src);
774 void decode_heap_oop_not_null(Register dst, Register src);
775
776 void set_narrow_oop(Register dst, jobject obj);
777
778 void encode_klass_not_null(Register r);
779 void decode_klass_not_null(Register r);
780 void encode_klass_not_null(Register dst, Register src);
781 void decode_klass_not_null(Register dst, Register src);
782
783 void set_narrow_klass(Register dst, Klass* k);
784
785 // if heap base register is used - reinit it with the correct value
786 void reinit_heapbase();
787
788 DEBUG_ONLY(void verify_heapbase(const char* msg);)
789
790 void push_CPU_state(bool save_vectors = false);
791 void pop_CPU_state(bool restore_vectors = false) ;
792
793 // Round up to a power of two
794 void round_to(Register reg, int modulus);
795
796 // allocation
797 void eden_allocate(
798 Register obj, // result: pointer to object after successful allocation
799 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
800 int con_size_in_bytes, // object size in bytes if known at compile time
801 Register t1, // temp register
802 Label& slow_case // continuation point if fast allocation fails
803 );
804 void tlab_allocate(
805 Register obj, // result: pointer to object after successful allocation
806 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
807 int con_size_in_bytes, // object size in bytes if known at compile time
808 Register t1, // temp register
809 Register t2, // temp register
810 Label& slow_case // continuation point if fast allocation fails
811 );
812 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
813 void verify_tlab();
814
815 void incr_allocated_bytes(Register thread,
816 Register var_size_in_bytes, int con_size_in_bytes,
817 Register t1 = noreg);
818
819 // interface method calling
820 void lookup_interface_method(Register recv_klass,
821 Register intf_klass,
822 RegisterOrConstant itable_index,
823 Register method_result,
824 Register scan_temp,
825 Label& no_such_interface);
826
827 // virtual method calling
828 // n.b. x86 allows RegisterOrConstant for vtable_index
829 void lookup_virtual_method(Register recv_klass,
830 RegisterOrConstant vtable_index,
831 Register method_result);
832
833 // Test sub_klass against super_klass, with fast and slow paths.
834
835 // The fast path produces a tri-state answer: yes / no / maybe-slow.
836 // One of the three labels can be NULL, meaning take the fall-through.
837 // If super_check_offset is -1, the value is loaded up from super_klass.
838 // No registers are killed, except temp_reg.
839 void check_klass_subtype_fast_path(Register sub_klass,
840 Register super_klass,
841 Register temp_reg,
842 Label* L_success,
843 Label* L_failure,
844 Label* L_slow_path,
845 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
846
847 // The rest of the type check; must be wired to a corresponding fast path.
848 // It does not repeat the fast path logic, so don't use it standalone.
849 // The temp_reg and temp2_reg can be noreg, if no temps are available.
850 // Updates the sub's secondary super cache as necessary.
851 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
852 void check_klass_subtype_slow_path(Register sub_klass,
853 Register super_klass,
854 Register temp_reg,
855 Register temp2_reg,
856 Label* L_success,
857 Label* L_failure,
858 bool set_cond_codes = false);
859
860 // Simplified, combined version, good for typical uses.
861 // Falls through on failure.
862 void check_klass_subtype(Register sub_klass,
863 Register super_klass,
864 Register temp_reg,
865 Label& L_success);
866
867 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
868
869
870 // Debugging
871
872 // only if +VerifyOops
873 void verify_oop(Register reg, const char* s = "broken oop");
874 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
875
876 // TODO: verify method and klass metadata (compare against vptr?)
877 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
878 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
879
880 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
881 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
882
883 // only if +VerifyFPU
884 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
885
886 // prints msg, dumps registers and stops execution
887 void stop(const char* msg);
888
889 // prints msg and continues
890 void warn(const char* msg);
891
892 static void debug64(char* msg, int64_t pc, int64_t regs[]);
893
894 void untested() { stop("untested"); }
895
896 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
897
898 void should_not_reach_here() { stop("should not reach here"); }
899
900 // Stack overflow checking
901 void bang_stack_with_offset(int offset) {
902 // stack grows down, caller passes positive offset
903 assert(offset > 0, "must bang with negative offset");
904 mov(rscratch2, -offset);
905 str(zr, Address(sp, rscratch2));
906 }
907
908 // Writes to stack successive pages until offset reached to check for
909 // stack overflow + shadow pages. Also, clobbers tmp
910 void bang_stack_size(Register size, Register tmp);
911
912 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
913 Register tmp,
914 int offset);
915
916 // Support for serializing memory accesses between threads
917 void serialize_memory(Register thread, Register tmp);
918
919 // Arithmetics
920
921 void addptr(const Address &dst, int32_t src);
922 void cmpptr(Register src1, Address src2);
923
924 // Various forms of CAS
925
926 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
927 Label &suceed, Label *fail);
928
929 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
930 Label &suceed, Label *fail);
931
932 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
933 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
934
935 void atomic_xchg(Register prev, Register newv, Register addr);
936 void atomic_xchgw(Register prev, Register newv, Register addr);
937
938 void orptr(Address adr, RegisterOrConstant src) {
939 ldr(rscratch2, adr);
940 if (src.is_register())
941 orr(rscratch2, rscratch2, src.as_register());
942 else
943 orr(rscratch2, rscratch2, src.as_constant());
944 str(rscratch2, adr);
945 }
946
947 // A generic CAS; success or failure is in the EQ flag.
948 template <typename T1, typename T2>
949 void cmpxchg(Register addr, Register expected, Register new_val,
950 T1 load_insn,
951 void (MacroAssembler::*cmp_insn)(Register, Register),
952 T2 store_insn,
953 Register tmp = rscratch1) {
954 Label retry_load, done;
955 bind(retry_load);
956 (this->*load_insn)(tmp, addr);
957 (this->*cmp_insn)(tmp, expected);
958 br(Assembler::NE, done);
959 (this->*store_insn)(tmp, new_val, addr);
960 cbnzw(tmp, retry_load);
961 bind(done);
962 }
963
964 // Calls
965
966 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
967
968 static bool far_branches() {
969 return ReservedCodeCacheSize > branch_range;
970 }
971
972 // Jumps that can reach anywhere in the code cache.
973 // Trashes tmp.
974 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
975 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
976
977 static int far_branch_size() {
978 if (far_branches()) {
979 return 3 * 4; // adrp, add, br
980 } else {
981 return 4;
982 }
983 }
984
985 // Emit the CompiledIC call idiom
986 address ic_call(address entry);
987
988 public:
989
990 // Data
991
992 void mov_metadata(Register dst, Metadata* obj);
993 Address allocate_metadata_address(Metadata* obj);
994 Address constant_oop_address(jobject obj);
995
996 void movoop(Register dst, jobject obj, bool immediate = false);
997
998 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
999 void kernel_crc32(Register crc, Register buf, Register len,
1000 Register table0, Register table1, Register table2, Register table3,
1001 Register tmp, Register tmp2, Register tmp3);
1002 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1003 void kernel_crc32c(Register crc, Register buf, Register len,
1004 Register table0, Register table1, Register table2, Register table3,
1005 Register tmp, Register tmp2, Register tmp3);
1006
1007 #undef VIRTUAL
1008
1009 // Stack push and pop individual 64 bit registers
1010 void push(Register src);
1011 void pop(Register dst);
1012
1013 // push all registers onto the stack
1014 void pusha();
1015 void popa();
1016
1017 void repne_scan(Register addr, Register value, Register count,
1018 Register scratch);
1019 void repne_scanw(Register addr, Register value, Register count,
1020 Register scratch);
1021
1022 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1023 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1024
1025 // If a constant does not fit in an immediate field, generate some
1026 // number of MOV instructions and then perform the operation
1027 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1028 add_sub_imm_insn insn1,
1029 add_sub_reg_insn insn2);
1030 // Seperate vsn which sets the flags
1031 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1032 add_sub_imm_insn insn1,
1033 add_sub_reg_insn insn2);
1034
1035 #define WRAP(INSN) \
1036 void INSN(Register Rd, Register Rn, unsigned imm) { \
1037 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1038 } \
1039 \
1040 void INSN(Register Rd, Register Rn, Register Rm, \
1041 enum shift_kind kind, unsigned shift = 0) { \
1042 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1043 } \
1044 \
1045 void INSN(Register Rd, Register Rn, Register Rm) { \
1046 Assembler::INSN(Rd, Rn, Rm); \
1047 } \
1048 \
1049 void INSN(Register Rd, Register Rn, Register Rm, \
1050 ext::operation option, int amount = 0) { \
1051 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1052 }
1053
1054 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1055
1056 #undef WRAP
1057 #define WRAP(INSN) \
1058 void INSN(Register Rd, Register Rn, unsigned imm) { \
1059 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1060 } \
1061 \
1062 void INSN(Register Rd, Register Rn, Register Rm, \
1063 enum shift_kind kind, unsigned shift = 0) { \
1064 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1065 } \
1066 \
1067 void INSN(Register Rd, Register Rn, Register Rm) { \
1068 Assembler::INSN(Rd, Rn, Rm); \
1069 } \
1070 \
1071 void INSN(Register Rd, Register Rn, Register Rm, \
1072 ext::operation option, int amount = 0) { \
1073 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1074 }
1075
1076 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1077
1078 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1079 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1080 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1081 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1082
1083 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1084
1085 void tableswitch(Register index, jint lowbound, jint highbound,
1086 Label &jumptable, Label &jumptable_end, int stride = 1) {
1087 adr(rscratch1, jumptable);
1088 subsw(rscratch2, index, lowbound);
1089 subsw(zr, rscratch2, highbound - lowbound);
1090 br(Assembler::HS, jumptable_end);
1091 add(rscratch1, rscratch1, rscratch2,
1092 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1093 br(rscratch1);
1094 }
1095
1096 // Form an address from base + offset in Rd. Rd may or may not
1097 // actually be used: you must use the Address that is returned. It
1098 // is up to you to ensure that the shift provided matches the size
1099 // of your data.
1100 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1101
1102 // Prolog generator routines to support switch between x86 code and
1103 // generated ARM code
1104
1105 // routine to generate an x86 prolog for a stub function which
1106 // bootstraps into the generated ARM code which directly follows the
1107 // stub
1108 //
1109
1110 public:
1111 // enum used for aarch64--x86 linkage to define return type of x86 function
1112 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1113
1114 #ifdef BUILTIN_SIM
1115 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1116 #else
1117 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1118 #endif
1119
1120 // special version of call_VM_leaf_base needed for aarch64 simulator
1121 // where we need to specify both the gp and fp arg counts and the
1122 // return type so that the linkage routine from aarch64 to x86 and
1123 // back knows which aarch64 registers to copy to x86 registers and
1124 // which x86 result register to copy back to an aarch64 register
1125
1126 void call_VM_leaf_base1(
1127 address entry_point, // the entry point
1128 int number_of_gp_arguments, // the number of gp reg arguments to pass
1129 int number_of_fp_arguments, // the number of fp reg arguments to pass
1130 ret_type type, // the return type for the call
1131 Label* retaddr = NULL
1132 );
1133
1134 void ldr_constant(Register dest, const Address &const_addr) {
1135 if (NearCpool) {
1136 ldr(dest, const_addr);
1137 } else {
1138 unsigned long offset;
1139 adrp(dest, InternalAddress(const_addr.target()), offset);
1140 ldr(dest, Address(dest, offset));
1141 }
1142 }
1143
1144 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1145 address read_polling_page(Register r, relocInfo::relocType rtype);
1146
1147 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1148 void update_byte_crc32(Register crc, Register val, Register table);
1149 void update_word_crc32(Register crc, Register v, Register tmp,
1150 Register table0, Register table1, Register table2, Register table3,
1151 bool upper = false);
1152
1153 void string_compare(Register str1, Register str2,
1154 Register cnt1, Register cnt2, Register result,
1155 Register tmp1);
1156 void string_equals(Register str1, Register str2,
1157 Register cnt, Register result,
1158 Register tmp1);
1159 void char_arrays_equals(Register ary1, Register ary2,
1160 Register result, Register tmp1);
1161 void encode_iso_array(Register src, Register dst,
1162 Register len, Register result,
1163 FloatRegister Vtmp1, FloatRegister Vtmp2,
1164 FloatRegister Vtmp3, FloatRegister Vtmp4);
1165 void string_indexof(Register str1, Register str2,
1166 Register cnt1, Register cnt2,
1167 Register tmp1, Register tmp2,
1168 Register tmp3, Register tmp4,
1169 int int_cnt1, Register result);
1170 private:
1171 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1172 Register src1, Register src2);
1173 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1174 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1175 }
1176 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1177 Register y, Register y_idx, Register z,
1178 Register carry, Register product,
1179 Register idx, Register kdx);
1180 void multiply_128_x_128_loop(Register y, Register z,
1181 Register carry, Register carry2,
1182 Register idx, Register jdx,
1183 Register yz_idx1, Register yz_idx2,
1184 Register tmp, Register tmp3, Register tmp4,
1185 Register tmp7, Register product_hi);
1186 public:
1187 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1188 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1189 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1190 // ISB may be needed because of a safepoint
1191 void maybe_isb() { isb(); }
1192
1193 private:
1194 // Return the effective address r + (r1 << ext) + offset.
1195 // Uses rscratch2.
1196 Address offsetted_address(Register r, Register r1, Address::extend ext,
1197 int offset, int size);
1198
1199 private:
1200 // Returns an address on the stack which is reachable with a ldr/str of size
1201 // Uses rscratch2 if the address is not directly reachable
1202 Address spill_address(int size, int offset, Register tmp=rscratch2);
1203
1204 public:
1205 void spill(Register Rx, bool is64, int offset) {
1206 if (is64) {
1207 str(Rx, spill_address(8, offset));
1208 } else {
1209 strw(Rx, spill_address(4, offset));
1210 }
1211 }
1212 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1213 str(Vx, T, spill_address(1 << (int)T, offset));
1214 }
1215 void unspill(Register Rx, bool is64, int offset) {
1216 if (is64) {
1217 ldr(Rx, spill_address(8, offset));
1218 } else {
1219 ldrw(Rx, spill_address(4, offset));
1220 }
1221 }
1222 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1223 ldr(Vx, T, spill_address(1 << (int)T, offset));
1224 }
1225 void spill_copy128(int src_offset, int dst_offset,
1226 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1227 if (src_offset < 512 && (src_offset & 7) == 0 &&
1228 dst_offset < 512 && (dst_offset & 7) == 0) {
1229 ldp(tmp1, tmp2, Address(sp, src_offset));
1230 stp(tmp1, tmp2, Address(sp, dst_offset));
1231 } else {
1232 unspill(tmp1, true, src_offset);
1233 spill(tmp1, true, dst_offset);
1234 unspill(tmp1, true, src_offset+8);
1235 spill(tmp1, true, dst_offset+8);
1236 }
1237 }
1238 };
1239
1240 #ifdef ASSERT
1241 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1242 #endif
1243
1244 /**
1245 * class SkipIfEqual:
1246 *
1247 * Instantiating this class will result in assembly code being output that will
1248 * jump around any code emitted between the creation of the instance and it's
1249 * automatic destruction at the end of a scope block, depending on the value of
1250 * the flag passed to the constructor, which will be checked at run-time.
1251 */
1252 class SkipIfEqual {
1253 private:
1254 MacroAssembler* _masm;
1255 Label _label;
1256
1257 public:
1258 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1259 ~SkipIfEqual();
1260 };
1261
1262 struct tableswitch {
1263 Register _reg;
1264 int _insn_index; jint _first_key; jint _last_key;
1265 Label _after;
1266 Label _branches;
1267 };
1268
1269 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP