1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP 26 #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP 27 28 #include "asm/assembler.hpp" 29 #include "utilities/macros.hpp" 30 31 // <sys/trap.h> promises that the system will not use traps 16-31 32 #define ST_RESERVED_FOR_USER_0 0x10 33 34 class BiasedLockingCounters; 35 36 37 // Register aliases for parts of the system: 38 39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe 40 // across context switches in V8+ ABI. Of course, there are no 64 bit regs 41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. 42 43 // g2-g4 are scratch registers called "application globals". Their 44 // meaning is reserved to the "compilation system"--which means us! 45 // They are are not supposed to be touched by ordinary C code, although 46 // highly-optimized C code might steal them for temps. They are safe 47 // across thread switches, and the ABI requires that they be safe 48 // across function calls. 49 // 50 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered 51 // across func calls, and V8+ also allows g5 to be clobbered across 52 // func calls. Also, g1 and g5 can get touched while doing shared 53 // library loading. 54 // 55 // We must not touch g7 (it is the thread-self register) and g6 is 56 // reserved for certain tools. g0, of course, is always zero. 57 // 58 // (Sources: SunSoft Compilers Group, thread library engineers.) 59 60 // %%%% The interpreter should be revisited to reduce global scratch regs. 61 62 // This global always holds the current JavaThread pointer: 63 64 REGISTER_DECLARATION(Register, G2_thread , G2); 65 REGISTER_DECLARATION(Register, G6_heapbase , G6); 66 67 // The following globals are part of the Java calling convention: 68 69 REGISTER_DECLARATION(Register, G5_method , G5); 70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); 71 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); 72 73 // The following globals are used for the new C1 & interpreter calling convention: 74 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument 75 76 // This local is used to preserve G2_thread in the interpreter and in stubs: 77 REGISTER_DECLARATION(Register, L7_thread_cache , L7); 78 79 // These globals are used as scratch registers in the interpreter: 80 81 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch 82 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME 83 REGISTER_DECLARATION(Register, G3_scratch , G3); 84 REGISTER_DECLARATION(Register, G4_scratch , G4); 85 86 // These globals are used as short-lived scratch registers in the compiler: 87 88 REGISTER_DECLARATION(Register, Gtemp , G5); 89 90 // JSR 292 fixed register usages: 91 REGISTER_DECLARATION(Register, G5_method_type , G5); 92 REGISTER_DECLARATION(Register, G3_method_handle , G3); 93 REGISTER_DECLARATION(Register, L7_mh_SP_save , L7); 94 95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, 96 // because a single patchable "set" instruction (NativeMovConstReg, 97 // or NativeMovConstPatching for compiler1) instruction 98 // serves to set up either quantity, depending on whether the compiled 99 // call site is an inline cache or is megamorphic. See the function 100 // CompiledIC::set_to_megamorphic. 101 // 102 // If a inline cache targets an interpreted method, then the 103 // G5 register will be used twice during the call. First, 104 // the call site will be patched to load a compiledICHolder 105 // into G5. (This is an ordered pair of ic_klass, method.) 106 // The c2i adapter will first check the ic_klass, then load 107 // G5_method with the method part of the pair just before 108 // jumping into the interpreter. 109 // 110 // Note that G5_method is only the method-self for the interpreter, 111 // and is logically unrelated to G5_megamorphic_method. 112 // 113 // Invariants on G2_thread (the JavaThread pointer): 114 // - it should not be used for any other purpose anywhere 115 // - it must be re-initialized by StubRoutines::call_stub() 116 // - it must be preserved around every use of call_VM 117 118 // We can consider using g2/g3/g4 to cache more values than the 119 // JavaThread, such as the card-marking base or perhaps pointers into 120 // Eden. It's something of a waste to use them as scratch temporaries, 121 // since they are not supposed to be volatile. (Of course, if we find 122 // that Java doesn't benefit from application globals, then we can just 123 // use them as ordinary temporaries.) 124 // 125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, 126 // it makes sense to use them routinely for procedure linkage, 127 // whenever the On registers are not applicable. Examples: G5_method, 128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler 129 // stubs. This means that compiler stubs, etc., should be kept to a 130 // maximum of two or three G-register arguments. 131 132 133 // stub frames 134 135 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself 136 137 // Interpreter frames 138 139 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer 140 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode 141 REGISTER_DECLARATION(Register, Lmethod , L2); 142 REGISTER_DECLARATION(Register, Llocals , L3); 143 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler 144 // must match Llocals in asm interpreter 145 REGISTER_DECLARATION(Register, Lmonitors , L4); 146 REGISTER_DECLARATION(Register, Lbyte_code , L5); 147 // When calling out from the interpreter we record SP so that we can remove any extra stack 148 // space allocated during adapter transitions. This register is only live from the point 149 // of the call until we return. 150 REGISTER_DECLARATION(Register, Llast_SP , L5); 151 REGISTER_DECLARATION(Register, Lscratch , L5); 152 REGISTER_DECLARATION(Register, Lscratch2 , L6); 153 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache 154 155 REGISTER_DECLARATION(Register, O5_savedSP , O5); 156 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply 157 // a copy SP, so in 64-bit it's a biased value. The bias 158 // is added and removed as needed in the frame code. 159 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables 160 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode 161 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data 162 163 // NOTE: Lscratch2 and LcpoolCache point to the same registers in 164 // the interpreter code. If Lscratch2 needs to be used for some 165 // purpose than LcpoolCache should be restore after that for 166 // the interpreter to work right 167 // (These assignments must be compatible with L7_thread_cache; see above.) 168 169 // Lbcp points into the middle of the method object. 170 171 // Exception processing 172 // These registers are passed into exception handlers. 173 // All exception handlers require the exception object being thrown. 174 // In addition, an nmethod's exception handler must be passed 175 // the address of the call site within the nmethod, to allow 176 // proper selection of the applicable catch block. 177 // (Interpreter frames use their own bcp() for this purpose.) 178 // 179 // The Oissuing_pc value is not always needed. When jumping to a 180 // handler that is known to be interpreted, the Oissuing_pc value can be 181 // omitted. An actual catch block in compiled code receives (from its 182 // nmethod's exception handler) the thrown exception in the Oexception, 183 // but it doesn't need the Oissuing_pc. 184 // 185 // If an exception handler (either interpreted or compiled) 186 // discovers there is no applicable catch block, it updates 187 // the Oissuing_pc to the continuation PC of its own caller, 188 // pops back to that caller's stack frame, and executes that 189 // caller's exception handler. Obviously, this process will 190 // iterate until the control stack is popped back to a method 191 // containing an applicable catch block. A key invariant is 192 // that the Oissuing_pc value is always a value local to 193 // the method whose exception handler is currently executing. 194 // 195 // Note: The issuing PC value is __not__ a raw return address (I7 value). 196 // It is a "return pc", the address __following__ the call. 197 // Raw return addresses are converted to issuing PCs by frame::pc(), 198 // or by stubs. Issuing PCs can be used directly with PC range tables. 199 // 200 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown 201 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from 202 203 204 // These must occur after the declarations above 205 #ifndef DONT_USE_REGISTER_DEFINES 206 207 #define Gthread AS_REGISTER(Register, Gthread) 208 #define Gmethod AS_REGISTER(Register, Gmethod) 209 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) 210 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) 211 #define Gargs AS_REGISTER(Register, Gargs) 212 #define Lthread_cache AS_REGISTER(Register, Lthread_cache) 213 #define Gframe_size AS_REGISTER(Register, Gframe_size) 214 #define Gtemp AS_REGISTER(Register, Gtemp) 215 216 #define Lesp AS_REGISTER(Register, Lesp) 217 #define Lbcp AS_REGISTER(Register, Lbcp) 218 #define Lmethod AS_REGISTER(Register, Lmethod) 219 #define Llocals AS_REGISTER(Register, Llocals) 220 #define Lmonitors AS_REGISTER(Register, Lmonitors) 221 #define Lbyte_code AS_REGISTER(Register, Lbyte_code) 222 #define Lscratch AS_REGISTER(Register, Lscratch) 223 #define Lscratch2 AS_REGISTER(Register, Lscratch2) 224 #define LcpoolCache AS_REGISTER(Register, LcpoolCache) 225 226 #define Lentry_args AS_REGISTER(Register, Lentry_args) 227 #define I5_savedSP AS_REGISTER(Register, I5_savedSP) 228 #define O5_savedSP AS_REGISTER(Register, O5_savedSP) 229 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) 230 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) 231 #define IdispatchTables AS_REGISTER(Register, IdispatchTables) 232 233 #define Oexception AS_REGISTER(Register, Oexception) 234 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) 235 236 #endif 237 238 239 // Address is an abstraction used to represent a memory location. 240 // 241 // Note: A register location is represented via a Register, not 242 // via an address for efficiency & simplicity reasons. 243 244 class Address VALUE_OBJ_CLASS_SPEC { 245 private: 246 Register _base; // Base register. 247 RegisterOrConstant _index_or_disp; // Index register or constant displacement. 248 RelocationHolder _rspec; 249 250 public: 251 Address() : _base(noreg), _index_or_disp(noreg) {} 252 253 Address(Register base, RegisterOrConstant index_or_disp) 254 : _base(base), 255 _index_or_disp(index_or_disp) { 256 } 257 258 Address(Register base, Register index) 259 : _base(base), 260 _index_or_disp(index) { 261 } 262 263 Address(Register base, int disp) 264 : _base(base), 265 _index_or_disp(disp) { 266 } 267 268 #ifdef ASSERT 269 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 270 Address(Register base, ByteSize disp) 271 : _base(base), 272 _index_or_disp(in_bytes(disp)) { 273 } 274 #endif 275 276 // accessors 277 Register base() const { return _base; } 278 Register index() const { return _index_or_disp.as_register(); } 279 int disp() const { return _index_or_disp.as_constant(); } 280 281 bool has_index() const { return _index_or_disp.is_register(); } 282 bool has_disp() const { return _index_or_disp.is_constant(); } 283 284 bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); } 285 286 const relocInfo::relocType rtype() { return _rspec.type(); } 287 const RelocationHolder& rspec() { return _rspec; } 288 289 RelocationHolder rspec(int offset) const { 290 return offset == 0 ? _rspec : _rspec.plus(offset); 291 } 292 293 inline bool is_simm13(int offset = 0); // check disp+offset for overflow 294 295 Address plus_disp(int plusdisp) const { // bump disp by a small amount 296 assert(_index_or_disp.is_constant(), "must have a displacement"); 297 Address a(base(), disp() + plusdisp); 298 return a; 299 } 300 bool is_same_address(Address a) const { 301 // disregard _rspec 302 return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp()); 303 } 304 305 Address after_save() const { 306 Address a = (*this); 307 a._base = a._base->after_save(); 308 return a; 309 } 310 311 Address after_restore() const { 312 Address a = (*this); 313 a._base = a._base->after_restore(); 314 return a; 315 } 316 317 // Convert the raw encoding form into the form expected by the 318 // constructor for Address. 319 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 320 321 friend class Assembler; 322 }; 323 324 325 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 326 private: 327 address _address; 328 RelocationHolder _rspec; 329 330 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 331 switch (rtype) { 332 case relocInfo::external_word_type: 333 return external_word_Relocation::spec(addr); 334 case relocInfo::internal_word_type: 335 return internal_word_Relocation::spec(addr); 336 #ifdef _LP64 337 case relocInfo::opt_virtual_call_type: 338 return opt_virtual_call_Relocation::spec(); 339 case relocInfo::static_call_type: 340 return static_call_Relocation::spec(); 341 case relocInfo::runtime_call_type: 342 return runtime_call_Relocation::spec(); 343 #endif 344 case relocInfo::none: 345 return RelocationHolder(); 346 default: 347 ShouldNotReachHere(); 348 return RelocationHolder(); 349 } 350 } 351 352 protected: 353 // creation 354 AddressLiteral() : _address(NULL), _rspec(NULL) {} 355 356 public: 357 AddressLiteral(address addr, RelocationHolder const& rspec) 358 : _address(addr), 359 _rspec(rspec) {} 360 361 // Some constructors to avoid casting at the call site. 362 AddressLiteral(jobject obj, RelocationHolder const& rspec) 363 : _address((address) obj), 364 _rspec(rspec) {} 365 366 AddressLiteral(intptr_t value, RelocationHolder const& rspec) 367 : _address((address) value), 368 _rspec(rspec) {} 369 370 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 371 : _address((address) addr), 372 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 373 374 // Some constructors to avoid casting at the call site. 375 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) 376 : _address((address) addr), 377 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 378 379 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) 380 : _address((address) addr), 381 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 382 383 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) 384 : _address((address) addr), 385 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 386 387 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) 388 : _address((address) addr), 389 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 390 391 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) 392 : _address((address) addr), 393 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 394 395 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) 396 : _address((address) addr), 397 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 398 399 #ifdef _LP64 400 // 32-bit complains about a multiple declaration for int*. 401 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) 402 : _address((address) addr), 403 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 404 #endif 405 406 AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none) 407 : _address((address) addr), 408 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 409 410 AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none) 411 : _address((address) addr), 412 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 413 414 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) 415 : _address((address) addr), 416 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 417 418 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) 419 : _address((address) addr), 420 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 421 422 intptr_t value() const { return (intptr_t) _address; } 423 int low10() const; 424 425 const relocInfo::relocType rtype() const { return _rspec.type(); } 426 const RelocationHolder& rspec() const { return _rspec; } 427 428 RelocationHolder rspec(int offset) const { 429 return offset == 0 ? _rspec : _rspec.plus(offset); 430 } 431 }; 432 433 // Convenience classes 434 class ExternalAddress: public AddressLiteral { 435 private: 436 static relocInfo::relocType reloc_for_target(address target) { 437 // Sometimes ExternalAddress is used for values which aren't 438 // exactly addresses, like the card table base. 439 // external_word_type can't be used for values in the first page 440 // so just skip the reloc in that case. 441 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 442 } 443 444 public: 445 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} 446 ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {} 447 }; 448 449 inline Address RegisterImpl::address_in_saved_window() const { 450 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); 451 } 452 453 454 455 // Argument is an abstraction used to represent an outgoing 456 // actual argument or an incoming formal parameter, whether 457 // it resides in memory or in a register, in a manner consistent 458 // with the SPARC Application Binary Interface, or ABI. This is 459 // often referred to as the native or C calling convention. 460 461 class Argument VALUE_OBJ_CLASS_SPEC { 462 private: 463 int _number; 464 bool _is_in; 465 466 public: 467 #ifdef _LP64 468 enum { 469 n_register_parameters = 6, // only 6 registers may contain integer parameters 470 n_float_register_parameters = 16 // Can have up to 16 floating registers 471 }; 472 #else 473 enum { 474 n_register_parameters = 6 // only 6 registers may contain integer parameters 475 }; 476 #endif 477 478 // creation 479 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} 480 481 int number() const { return _number; } 482 bool is_in() const { return _is_in; } 483 bool is_out() const { return !is_in(); } 484 485 Argument successor() const { return Argument(number() + 1, is_in()); } 486 Argument as_in() const { return Argument(number(), true ); } 487 Argument as_out() const { return Argument(number(), false); } 488 489 // locating register-based arguments: 490 bool is_register() const { return _number < n_register_parameters; } 491 492 #ifdef _LP64 493 // locating Floating Point register-based arguments: 494 bool is_float_register() const { return _number < n_float_register_parameters; } 495 496 FloatRegister as_float_register() const { 497 assert(is_float_register(), "must be a register argument"); 498 return as_FloatRegister(( number() *2 ) + 1); 499 } 500 FloatRegister as_double_register() const { 501 assert(is_float_register(), "must be a register argument"); 502 return as_FloatRegister(( number() *2 )); 503 } 504 #endif 505 506 Register as_register() const { 507 assert(is_register(), "must be a register argument"); 508 return is_in() ? as_iRegister(number()) : as_oRegister(number()); 509 } 510 511 // locating memory-based arguments 512 Address as_address() const { 513 assert(!is_register(), "must be a memory argument"); 514 return address_in_frame(); 515 } 516 517 // When applied to a register-based argument, give the corresponding address 518 // into the 6-word area "into which callee may store register arguments" 519 // (This is a different place than the corresponding register-save area location.) 520 Address address_in_frame() const; 521 522 // debugging 523 const char* name() const; 524 525 friend class Assembler; 526 }; 527 528 529 class RegistersForDebugging : public StackObj { 530 public: 531 intptr_t i[8], l[8], o[8], g[8]; 532 float f[32]; 533 double d[32]; 534 535 void print(outputStream* s); 536 537 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } 538 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } 539 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } 540 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } 541 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } 542 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } 543 544 // gen asm code to save regs 545 static void save_registers(MacroAssembler* a); 546 547 // restore global registers in case C code disturbed them 548 static void restore_registers(MacroAssembler* a, Register r); 549 }; 550 551 552 // MacroAssembler extends Assembler by a few frequently used macros. 553 // 554 // Most of the standard SPARC synthetic ops are defined here. 555 // Instructions for which a 'better' code sequence exists depending 556 // on arguments should also go in here. 557 558 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) 559 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) 560 #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__) 561 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__) 562 563 564 class MacroAssembler : public Assembler { 565 // code patchers need various routines like inv_wdisp() 566 friend class NativeInstruction; 567 friend class NativeGeneralJump; 568 friend class Relocation; 569 friend class Label; 570 571 protected: 572 static int patched_branch(int dest_pos, int inst, int inst_pos); 573 static int branch_destination(int inst, int pos); 574 575 // Support for VM calls 576 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 577 // may customize this version by overriding it for its purposes (e.g., to save/restore 578 // additional registers when doing a VM call). 579 virtual void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); 580 581 // 582 // It is imperative that all calls into the VM are handled via the call_VM macros. 583 // They make sure that the stack linkage is setup correctly. call_VM's correspond 584 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 585 // 586 // This is the base routine called by the different versions of call_VM. The interpreter 587 // may customize this version by overriding it for its purposes (e.g., to save/restore 588 // additional registers when doing a VM call). 589 // 590 // A non-volatile java_thread_cache register should be specified so 591 // that the G2_thread value can be preserved across the call. 592 // (If java_thread_cache is noreg, then a slow get_thread call 593 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the 594 // thread. 595 // 596 // If no last_java_sp is specified (noreg) than SP will be used instead. 597 598 virtual void call_VM_base( 599 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 600 Register java_thread_cache, // the thread if computed before ; use noreg otherwise 601 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 602 address entry_point, // the entry point 603 int number_of_arguments, // the number of arguments (w/o thread) to pop after call 604 bool check_exception=true // flag which indicates if exception should be checked 605 ); 606 607 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. 608 // The implementation is only non-empty for the InterpreterMacroAssembler, 609 // as only the interpreter handles and ForceEarlyReturn PopFrame requests. 610 virtual void check_and_handle_popframe(Register scratch_reg); 611 virtual void check_and_handle_earlyret(Register scratch_reg); 612 613 public: 614 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 615 616 // Support for NULL-checks 617 // 618 // Generates code that causes a NULL OS exception if the content of reg is NULL. 619 // If the accessed location is M[reg + offset] and the offset is known, provide the 620 // offset. No explicit code generation is needed if the offset is within a certain 621 // range (0 <= offset <= page_size). 622 // 623 // %%%%%% Currently not done for SPARC 624 625 void null_check(Register reg, int offset = -1); 626 static bool needs_explicit_null_check(intptr_t offset); 627 628 // support for delayed instructions 629 MacroAssembler* delayed() { Assembler::delayed(); return this; } 630 631 // branches that use right instruction for v8 vs. v9 632 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 633 inline void br( Condition c, bool a, Predict p, Label& L ); 634 635 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 636 inline void fb( Condition c, bool a, Predict p, Label& L ); 637 638 // compares register with zero (32 bit) and branches (V9 and V8 instructions) 639 void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn ); 640 // Compares a pointer register with zero and branches on (not)null. 641 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. 642 void br_null ( Register s1, bool a, Predict p, Label& L ); 643 void br_notnull( Register s1, bool a, Predict p, Label& L ); 644 645 // 646 // Compare registers and branch with nop in delay slot or cbcond without delay slot. 647 // 648 // ATTENTION: use these instructions with caution because cbcond instruction 649 // has very short distance: 512 instructions (2Kbyte). 650 651 // Compare integer (32 bit) values (icc only). 652 void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L); 653 void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L); 654 // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64). 655 void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L); 656 void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L); 657 658 // Short branch version for compares a pointer pwith zero. 659 void br_null_short ( Register s1, Predict p, Label& L ); 660 void br_notnull_short( Register s1, Predict p, Label& L ); 661 662 // unconditional short branch 663 void ba_short(Label& L); 664 665 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 666 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); 667 668 // Branch that tests xcc in LP64 and icc in !LP64 669 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 670 inline void brx( Condition c, bool a, Predict p, Label& L ); 671 672 // unconditional branch 673 inline void ba( Label& L ); 674 675 // Branch that tests fp condition codes 676 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 677 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); 678 679 // get PC the best way 680 inline int get_pc( Register d ); 681 682 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) 683 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } 684 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } 685 686 inline void jmp( Register s1, Register s2 ); 687 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); 688 689 // Check if the call target is out of wdisp30 range (relative to the code cache) 690 static inline bool is_far_target(address d); 691 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); 692 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); 693 inline void callr( Register s1, Register s2 ); 694 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); 695 696 // Emits nothing on V8 697 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); 698 inline void iprefetch( Label& L); 699 700 inline void tst( Register s ) { orcc( G0, s, G0 ); } 701 702 #ifdef PRODUCT 703 inline void ret( bool trace = TraceJumps ) { if (trace) { 704 mov(I7, O7); // traceable register 705 JMP(O7, 2 * BytesPerInstWord); 706 } else { 707 jmpl( I7, 2 * BytesPerInstWord, G0 ); 708 } 709 } 710 711 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); 712 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } 713 #else 714 void ret( bool trace = TraceJumps ); 715 void retl( bool trace = TraceJumps ); 716 #endif /* PRODUCT */ 717 718 // Required platform-specific helpers for Label::patch_instructions. 719 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 720 void pd_patch_instruction(address branch, address target); 721 722 // sethi Macro handles optimizations and relocations 723 private: 724 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable); 725 public: 726 void sethi(const AddressLiteral& addrlit, Register d); 727 void patchable_sethi(const AddressLiteral& addrlit, Register d); 728 729 // compute the number of instructions for a sethi/set 730 static int insts_for_sethi( address a, bool worst_case = false ); 731 static int worst_case_insts_for_set(); 732 733 // set may be either setsw or setuw (high 32 bits may be zero or sign) 734 private: 735 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable); 736 static int insts_for_internal_set(intptr_t value); 737 public: 738 void set(const AddressLiteral& addrlit, Register d); 739 void set(intptr_t value, Register d); 740 void set(address addr, Register d, RelocationHolder const& rspec); 741 static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); } 742 743 void patchable_set(const AddressLiteral& addrlit, Register d); 744 void patchable_set(intptr_t value, Register d); 745 void set64(jlong value, Register d, Register tmp); 746 static int insts_for_set64(jlong value); 747 748 // sign-extend 32 to 64 749 inline void signx( Register s, Register d ) { sra( s, G0, d); } 750 inline void signx( Register d ) { sra( d, G0, d); } 751 752 inline void not1( Register s, Register d ) { xnor( s, G0, d ); } 753 inline void not1( Register d ) { xnor( d, G0, d ); } 754 755 inline void neg( Register s, Register d ) { sub( G0, s, d ); } 756 inline void neg( Register d ) { sub( G0, d, d ); } 757 758 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } 759 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } 760 // Functions for isolating 64 bit atomic swaps for LP64 761 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's 762 inline void cas_ptr( Register s1, Register s2, Register d) { 763 #ifdef _LP64 764 casx( s1, s2, d ); 765 #else 766 cas( s1, s2, d ); 767 #endif 768 } 769 770 // Functions for isolating 64 bit shifts for LP64 771 inline void sll_ptr( Register s1, Register s2, Register d ); 772 inline void sll_ptr( Register s1, int imm6a, Register d ); 773 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); 774 inline void srl_ptr( Register s1, Register s2, Register d ); 775 inline void srl_ptr( Register s1, int imm6a, Register d ); 776 777 // little-endian 778 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } 779 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } 780 781 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } 782 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } 783 784 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } 785 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } 786 787 using Assembler::add; 788 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype); 789 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec); 790 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0); 791 inline void add(const Address& a, Register d, int offset = 0); 792 793 using Assembler::andn; 794 inline void andn( Register s1, RegisterOrConstant s2, Register d); 795 796 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } 797 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } 798 799 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } 800 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } 801 802 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } 803 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } 804 805 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } 806 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } 807 808 inline void clr( Register d ) { or3( G0, G0, d ); } 809 810 inline void clrb( Register s1, Register s2); 811 inline void clrh( Register s1, Register s2); 812 inline void clr( Register s1, Register s2); 813 inline void clrx( Register s1, Register s2); 814 815 inline void clrb( Register s1, int simm13a); 816 inline void clrh( Register s1, int simm13a); 817 inline void clr( Register s1, int simm13a); 818 inline void clrx( Register s1, int simm13a); 819 820 // copy & clear upper word 821 inline void clruw( Register s, Register d ) { srl( s, G0, d); } 822 // clear upper word 823 inline void clruwu( Register d ) { srl( d, G0, d); } 824 825 using Assembler::ldsb; 826 using Assembler::ldsh; 827 using Assembler::ldsw; 828 using Assembler::ldub; 829 using Assembler::lduh; 830 using Assembler::lduw; 831 using Assembler::ldx; 832 using Assembler::ldd; 833 834 #ifdef ASSERT 835 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 836 inline void ld(Register s1, ByteSize simm13a, Register d); 837 #endif 838 839 inline void ld(Register s1, Register s2, Register d); 840 inline void ld(Register s1, int simm13a, Register d); 841 842 inline void ldsb(const Address& a, Register d, int offset = 0); 843 inline void ldsh(const Address& a, Register d, int offset = 0); 844 inline void ldsw(const Address& a, Register d, int offset = 0); 845 inline void ldub(const Address& a, Register d, int offset = 0); 846 inline void lduh(const Address& a, Register d, int offset = 0); 847 inline void lduw(const Address& a, Register d, int offset = 0); 848 inline void ldx( const Address& a, Register d, int offset = 0); 849 inline void ld( const Address& a, Register d, int offset = 0); 850 inline void ldd( const Address& a, Register d, int offset = 0); 851 852 inline void ldub(Register s1, RegisterOrConstant s2, Register d ); 853 inline void ldsb(Register s1, RegisterOrConstant s2, Register d ); 854 inline void lduh(Register s1, RegisterOrConstant s2, Register d ); 855 inline void ldsh(Register s1, RegisterOrConstant s2, Register d ); 856 inline void lduw(Register s1, RegisterOrConstant s2, Register d ); 857 inline void ldsw(Register s1, RegisterOrConstant s2, Register d ); 858 inline void ldx( Register s1, RegisterOrConstant s2, Register d ); 859 inline void ld( Register s1, RegisterOrConstant s2, Register d ); 860 inline void ldd( Register s1, RegisterOrConstant s2, Register d ); 861 862 using Assembler::ldf; 863 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d); 864 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); 865 866 // little-endian 867 inline void lduwl(Register s1, Register s2, Register d) { lduwa(s1, s2, ASI_PRIMARY_LITTLE, d); } 868 inline void ldswl(Register s1, Register s2, Register d) { ldswa(s1, s2, ASI_PRIMARY_LITTLE, d);} 869 inline void ldxl( Register s1, Register s2, Register d) { ldxa(s1, s2, ASI_PRIMARY_LITTLE, d); } 870 inline void ldfl(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { ldfa(w, s1, s2, ASI_PRIMARY_LITTLE, d); } 871 872 // membar psuedo instruction. takes into account target memory model. 873 inline void membar( Assembler::Membar_mask_bits const7a ); 874 875 // returns if membar generates anything. 876 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); 877 878 // mov pseudo instructions 879 inline void mov( Register s, Register d) { 880 if ( s != d ) or3( G0, s, d); 881 else assert_not_delayed(); // Put something useful in the delay slot! 882 } 883 884 inline void mov_or_nop( Register s, Register d) { 885 if ( s != d ) or3( G0, s, d); 886 else nop(); 887 } 888 889 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } 890 891 using Assembler::prefetch; 892 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); 893 894 using Assembler::stb; 895 using Assembler::sth; 896 using Assembler::stw; 897 using Assembler::stx; 898 using Assembler::std; 899 900 #ifdef ASSERT 901 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 902 inline void st(Register d, Register s1, ByteSize simm13a); 903 #endif 904 905 inline void st(Register d, Register s1, Register s2); 906 inline void st(Register d, Register s1, int simm13a); 907 908 inline void stb(Register d, const Address& a, int offset = 0 ); 909 inline void sth(Register d, const Address& a, int offset = 0 ); 910 inline void stw(Register d, const Address& a, int offset = 0 ); 911 inline void stx(Register d, const Address& a, int offset = 0 ); 912 inline void st( Register d, const Address& a, int offset = 0 ); 913 inline void std(Register d, const Address& a, int offset = 0 ); 914 915 inline void stb(Register d, Register s1, RegisterOrConstant s2 ); 916 inline void sth(Register d, Register s1, RegisterOrConstant s2 ); 917 inline void stw(Register d, Register s1, RegisterOrConstant s2 ); 918 inline void stx(Register d, Register s1, RegisterOrConstant s2 ); 919 inline void std(Register d, Register s1, RegisterOrConstant s2 ); 920 inline void st( Register d, Register s1, RegisterOrConstant s2 ); 921 922 using Assembler::stf; 923 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2); 924 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); 925 926 // Note: offset is added to s2. 927 using Assembler::sub; 928 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0); 929 930 using Assembler::swap; 931 inline void swap(const Address& a, Register d, int offset = 0); 932 933 // address pseudos: make these names unlike instruction names to avoid confusion 934 inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); 935 inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0); 936 inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0); 937 inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0); 938 inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); 939 inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); 940 inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0); 941 inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0); 942 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0); 943 944 // ring buffer traceable jumps 945 946 void jmp2( Register r1, Register r2, const char* file, int line ); 947 void jmp ( Register r1, int offset, const char* file, int line ); 948 949 void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line); 950 void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line); 951 952 953 // argument pseudos: 954 955 inline void load_argument( Argument& a, Register d ); 956 inline void store_argument( Register s, Argument& a ); 957 inline void store_ptr_argument( Register s, Argument& a ); 958 inline void store_float_argument( FloatRegister s, Argument& a ); 959 inline void store_double_argument( FloatRegister s, Argument& a ); 960 inline void store_long_argument( Register s, Argument& a ); 961 962 // handy macros: 963 964 inline void round_to( Register r, int modulus ) { 965 assert_not_delayed(); 966 inc( r, modulus - 1 ); 967 and3( r, -modulus, r ); 968 } 969 970 // -------------------------------------------------- 971 972 // Functions for isolating 64 bit loads for LP64 973 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's 974 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's 975 inline void ld_ptr(Register s1, Register s2, Register d); 976 inline void ld_ptr(Register s1, int simm13a, Register d); 977 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d); 978 inline void ld_ptr(const Address& a, Register d, int offset = 0); 979 inline void st_ptr(Register d, Register s1, Register s2); 980 inline void st_ptr(Register d, Register s1, int simm13a); 981 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2); 982 inline void st_ptr(Register d, const Address& a, int offset = 0); 983 984 #ifdef ASSERT 985 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 986 inline void ld_ptr(Register s1, ByteSize simm13a, Register d); 987 inline void st_ptr(Register d, Register s1, ByteSize simm13a); 988 #endif 989 990 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's 991 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's 992 inline void ld_long(Register s1, Register s2, Register d); 993 inline void ld_long(Register s1, int simm13a, Register d); 994 inline void ld_long(Register s1, RegisterOrConstant s2, Register d); 995 inline void ld_long(const Address& a, Register d, int offset = 0); 996 inline void st_long(Register d, Register s1, Register s2); 997 inline void st_long(Register d, Register s1, int simm13a); 998 inline void st_long(Register d, Register s1, RegisterOrConstant s2); 999 inline void st_long(Register d, const Address& a, int offset = 0); 1000 1001 // Helpers for address formation. 1002 // - They emit only a move if s2 is a constant zero. 1003 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result. 1004 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant. 1005 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); 1006 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); 1007 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); 1008 1009 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) { 1010 if (is_simm13(src.constant_or_zero())) 1011 return src; // register or short constant 1012 guarantee(temp != noreg, "constant offset overflow"); 1013 set(src.as_constant(), temp); 1014 return temp; 1015 } 1016 1017 // -------------------------------------------------- 1018 1019 public: 1020 // traps as per trap.h (SPARC ABI?) 1021 1022 void breakpoint_trap(); 1023 void breakpoint_trap(Condition c, CC cc); 1024 1025 // Support for serializing memory accesses between threads 1026 void serialize_memory(Register thread, Register tmp1, Register tmp2); 1027 1028 // Stack frame creation/removal 1029 void enter(); 1030 void leave(); 1031 1032 // Manipulation of C++ bools 1033 // These are idioms to flag the need for care with accessing bools but on 1034 // this platform we assume byte size 1035 1036 inline void stbool(Register d, const Address& a) { stb(d, a); } 1037 inline void ldbool(const Address& a, Register d) { ldub(a, d); } 1038 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } 1039 1040 // klass oop manipulations if compressed 1041 void load_klass(Register src_oop, Register klass); 1042 void store_klass(Register klass, Register dst_oop); 1043 void store_klass_gap(Register s, Register dst_oop); 1044 1045 // oop manipulations 1046 void load_heap_oop(const Address& s, Register d); 1047 void load_heap_oop(Register s1, Register s2, Register d); 1048 void load_heap_oop(Register s1, int simm13a, Register d); 1049 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d); 1050 void store_heap_oop(Register d, Register s1, Register s2); 1051 void store_heap_oop(Register d, Register s1, int simm13a); 1052 void store_heap_oop(Register d, const Address& a, int offset = 0); 1053 1054 void encode_heap_oop(Register src, Register dst); 1055 void encode_heap_oop(Register r) { 1056 encode_heap_oop(r, r); 1057 } 1058 void decode_heap_oop(Register src, Register dst); 1059 void decode_heap_oop(Register r) { 1060 decode_heap_oop(r, r); 1061 } 1062 void encode_heap_oop_not_null(Register r); 1063 void decode_heap_oop_not_null(Register r); 1064 void encode_heap_oop_not_null(Register src, Register dst); 1065 void decode_heap_oop_not_null(Register src, Register dst); 1066 1067 void encode_klass_not_null(Register r); 1068 void decode_klass_not_null(Register r); 1069 void encode_klass_not_null(Register src, Register dst); 1070 void decode_klass_not_null(Register src, Register dst); 1071 1072 // Support for managing the JavaThread pointer (i.e.; the reference to 1073 // thread-local information). 1074 void get_thread(); // load G2_thread 1075 void verify_thread(); // verify G2_thread contents 1076 void save_thread (const Register threache); // save to cache 1077 void restore_thread(const Register thread_cache); // restore from cache 1078 1079 // Support for last Java frame (but use call_VM instead where possible) 1080 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); 1081 void reset_last_Java_frame(void); 1082 1083 // Call into the VM. 1084 // Passes the thread pointer (in O0) as a prepended argument. 1085 // Makes sure oop return values are visible to the GC. 1086 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 1087 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); 1088 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 1089 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 1090 1091 // these overloadings are not presently used on SPARC: 1092 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 1093 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 1094 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 1095 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 1096 1097 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); 1098 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); 1099 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); 1100 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); 1101 1102 void get_vm_result (Register oop_result); 1103 void get_vm_result_2(Register metadata_result); 1104 1105 // vm result is currently getting hijacked to for oop preservation 1106 void set_vm_result(Register oop_result); 1107 1108 // Emit the CompiledIC call idiom 1109 void ic_call(address entry, bool emit_delay = true); 1110 1111 // if call_VM_base was called with check_exceptions=false, then call 1112 // check_and_forward_exception to handle exceptions when it is safe 1113 void check_and_forward_exception(Register scratch_reg); 1114 1115 // Write to card table for - register is destroyed afterwards. 1116 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); 1117 1118 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); 1119 1120 #if INCLUDE_ALL_GCS 1121 // General G1 pre-barrier generator. 1122 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs); 1123 1124 // General G1 post-barrier generator 1125 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); 1126 #endif // INCLUDE_ALL_GCS 1127 1128 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 1129 void push_fTOS(); 1130 1131 // pops double TOS element from CPU stack and pushes on FPU stack 1132 void pop_fTOS(); 1133 1134 void empty_FPU_stack(); 1135 1136 void push_IU_state(); 1137 void pop_IU_state(); 1138 1139 void push_FPU_state(); 1140 void pop_FPU_state(); 1141 1142 void push_CPU_state(); 1143 void pop_CPU_state(); 1144 1145 // Returns the byte size of the instructions generated by decode_klass_not_null(). 1146 static int instr_size_for_decode_klass_not_null(); 1147 1148 // if heap base register is used - reinit it with the correct value 1149 void reinit_heapbase(); 1150 1151 // Debugging 1152 void _verify_oop(Register reg, const char * msg, const char * file, int line); 1153 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); 1154 1155 // TODO: verify_method and klass metadata (compare against vptr?) 1156 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 1157 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 1158 1159 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) 1160 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) 1161 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 1162 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 1163 1164 // only if +VerifyOops 1165 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 1166 // only if +VerifyFPU 1167 void stop(const char* msg); // prints msg, dumps registers and stops execution 1168 void warn(const char* msg); // prints msg, but don't stop 1169 void untested(const char* what = ""); 1170 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 1171 void should_not_reach_here() { stop("should not reach here"); } 1172 void print_CPU_state(); 1173 1174 // oops in code 1175 AddressLiteral allocate_oop_address(jobject obj); // allocate_index 1176 AddressLiteral constant_oop_address(jobject obj); // find_index 1177 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address 1178 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address 1179 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address 1180 1181 // metadata in code that we have to keep track of 1182 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index 1183 AddressLiteral constant_metadata_address(Metadata* obj); // find_index 1184 inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address 1185 inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address 1186 inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address 1187 1188 void set_narrow_oop( jobject obj, Register d ); 1189 void set_narrow_klass( Klass* k, Register d ); 1190 1191 // nop padding 1192 void align(int modulus); 1193 1194 // declare a safepoint 1195 void safepoint(); 1196 1197 // factor out part of stop into subroutine to save space 1198 void stop_subroutine(); 1199 // factor out part of verify_oop into subroutine to save space 1200 void verify_oop_subroutine(); 1201 1202 // side-door communication with signalHandler in os_solaris.cpp 1203 static address _verify_oop_implicit_branch[3]; 1204 1205 int total_frame_size_in_bytes(int extraWords); 1206 1207 // used when extraWords known statically 1208 void save_frame(int extraWords = 0); 1209 void save_frame_c1(int size_in_bytes); 1210 // make a frame, and simultaneously pass up one or two register value 1211 // into the new register window 1212 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); 1213 1214 // give no. (outgoing) params, calc # of words will need on frame 1215 void calc_mem_param_words(Register Rparam_words, Register Rresult); 1216 1217 // used to calculate frame size dynamically 1218 // result is in bytes and must be negated for save inst 1219 void calc_frame_size(Register extraWords, Register resultReg); 1220 1221 // calc and also save 1222 void calc_frame_size_and_save(Register extraWords, Register resultReg); 1223 1224 static void debug(char* msg, RegistersForDebugging* outWindow); 1225 1226 // implementations of bytecodes used by both interpreter and compiler 1227 1228 void lcmp( Register Ra_hi, Register Ra_low, 1229 Register Rb_hi, Register Rb_low, 1230 Register Rresult); 1231 1232 void lneg( Register Rhi, Register Rlow ); 1233 1234 void lshl( Register Rin_high, Register Rin_low, Register Rcount, 1235 Register Rout_high, Register Rout_low, Register Rtemp ); 1236 1237 void lshr( Register Rin_high, Register Rin_low, Register Rcount, 1238 Register Rout_high, Register Rout_low, Register Rtemp ); 1239 1240 void lushr( Register Rin_high, Register Rin_low, Register Rcount, 1241 Register Rout_high, Register Rout_low, Register Rtemp ); 1242 1243 #ifdef _LP64 1244 void lcmp( Register Ra, Register Rb, Register Rresult); 1245 #endif 1246 1247 // Load and store values by size and signed-ness 1248 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed); 1249 void store_sized_value(Register src, Address dst, size_t size_in_bytes); 1250 1251 void float_cmp( bool is_float, int unordered_result, 1252 FloatRegister Fa, FloatRegister Fb, 1253 Register Rresult); 1254 1255 void save_all_globals_into_locals(); 1256 void restore_globals_from_locals(); 1257 1258 // These set the icc condition code to equal if the lock succeeded 1259 // and notEqual if it failed and requires a slow case 1260 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, 1261 Register Rscratch, 1262 BiasedLockingCounters* counters = NULL, 1263 bool try_bias = UseBiasedLocking); 1264 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, 1265 Register Rscratch, 1266 bool try_bias = UseBiasedLocking); 1267 1268 // Biased locking support 1269 // Upon entry, lock_reg must point to the lock record on the stack, 1270 // obj_reg must contain the target object, and mark_reg must contain 1271 // the target object's header. 1272 // Destroys mark_reg if an attempt is made to bias an anonymously 1273 // biased lock. In this case a failure will go either to the slow 1274 // case or fall through with the notEqual condition code set with 1275 // the expectation that the slow case in the runtime will be called. 1276 // In the fall-through case where the CAS-based lock is done, 1277 // mark_reg is not destroyed. 1278 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, 1279 Label& done, Label* slow_case = NULL, 1280 BiasedLockingCounters* counters = NULL); 1281 // Upon entry, the base register of mark_addr must contain the oop. 1282 // Destroys temp_reg. 1283 1284 // If allow_delay_slot_filling is set to true, the next instruction 1285 // emitted after this one will go in an annulled delay slot if the 1286 // biased locking exit case failed. 1287 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); 1288 1289 // allocation 1290 void eden_allocate( 1291 Register obj, // result: pointer to object after successful allocation 1292 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1293 int con_size_in_bytes, // object size in bytes if known at compile time 1294 Register t1, // temp register 1295 Register t2, // temp register 1296 Label& slow_case // continuation point if fast allocation fails 1297 ); 1298 void tlab_allocate( 1299 Register obj, // result: pointer to object after successful allocation 1300 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1301 int con_size_in_bytes, // object size in bytes if known at compile time 1302 Register t1, // temp register 1303 Label& slow_case // continuation point if fast allocation fails 1304 ); 1305 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); 1306 void incr_allocated_bytes(RegisterOrConstant size_in_bytes, 1307 Register t1, Register t2); 1308 1309 // interface method calling 1310 void lookup_interface_method(Register recv_klass, 1311 Register intf_klass, 1312 RegisterOrConstant itable_index, 1313 Register method_result, 1314 Register temp_reg, Register temp2_reg, 1315 Label& no_such_interface); 1316 1317 // virtual method calling 1318 void lookup_virtual_method(Register recv_klass, 1319 RegisterOrConstant vtable_index, 1320 Register method_result); 1321 1322 // Test sub_klass against super_klass, with fast and slow paths. 1323 1324 // The fast path produces a tri-state answer: yes / no / maybe-slow. 1325 // One of the three labels can be NULL, meaning take the fall-through. 1326 // If super_check_offset is -1, the value is loaded up from super_klass. 1327 // No registers are killed, except temp_reg and temp2_reg. 1328 // If super_check_offset is not -1, temp2_reg is not used and can be noreg. 1329 void check_klass_subtype_fast_path(Register sub_klass, 1330 Register super_klass, 1331 Register temp_reg, 1332 Register temp2_reg, 1333 Label* L_success, 1334 Label* L_failure, 1335 Label* L_slow_path, 1336 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 1337 1338 // The rest of the type check; must be wired to a corresponding fast path. 1339 // It does not repeat the fast path logic, so don't use it standalone. 1340 // The temp_reg can be noreg, if no temps are available. 1341 // It can also be sub_klass or super_klass, meaning it's OK to kill that one. 1342 // Updates the sub's secondary super cache as necessary. 1343 void check_klass_subtype_slow_path(Register sub_klass, 1344 Register super_klass, 1345 Register temp_reg, 1346 Register temp2_reg, 1347 Register temp3_reg, 1348 Register temp4_reg, 1349 Label* L_success, 1350 Label* L_failure); 1351 1352 // Simplified, combined version, good for typical uses. 1353 // Falls through on failure. 1354 void check_klass_subtype(Register sub_klass, 1355 Register super_klass, 1356 Register temp_reg, 1357 Register temp2_reg, 1358 Label& L_success); 1359 1360 // method handles (JSR 292) 1361 // offset relative to Gargs of argument at tos[arg_slot]. 1362 // (arg_slot == 0 means the last argument, not the first). 1363 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, 1364 Register temp_reg, 1365 int extra_slot_offset = 0); 1366 // Address of Gargs and argument_offset. 1367 Address argument_address(RegisterOrConstant arg_slot, 1368 Register temp_reg = noreg, 1369 int extra_slot_offset = 0); 1370 1371 // Stack overflow checking 1372 1373 // Note: this clobbers G3_scratch 1374 void bang_stack_with_offset(int offset) { 1375 // stack grows down, caller passes positive offset 1376 assert(offset > 0, "must bang with negative offset"); 1377 set((-offset)+STACK_BIAS, G3_scratch); 1378 st(G0, SP, G3_scratch); 1379 } 1380 1381 // Writes to stack successive pages until offset reached to check for 1382 // stack overflow + shadow pages. Clobbers tsp and scratch registers. 1383 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); 1384 1385 // Check for reserved stack access in method being exited (for JIT) 1386 void reserved_stack_check(); 1387 1388 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); 1389 1390 void verify_tlab(); 1391 1392 Condition negate_condition(Condition cond); 1393 1394 // Helper functions for statistics gathering. 1395 // Conditionally (non-atomically) increments passed counter address, preserving condition codes. 1396 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); 1397 // Unconditional increment. 1398 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2); 1399 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2); 1400 1401 #ifdef COMPILER2 1402 // Compress char[] to byte[] by compressing 16 bytes at once. Return 0 on failure. 1403 void string_compress_16(Register src, Register dst, Register cnt, Register result, 1404 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 1405 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, Label& Ldone); 1406 1407 // Compress char[] to byte[]. Return 0 on failure. 1408 void string_compress(Register src, Register dst, Register cnt, Register tmp, Register result, Label& Ldone); 1409 1410 // Inflate byte[] to char[] by inflating 16 bytes at once. 1411 void string_inflate_16(Register src, Register dst, Register cnt, Register tmp, 1412 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, FloatRegister ftmp4, Label& Ldone); 1413 1414 // Inflate byte[] to char[]. 1415 void string_inflate(Register src, Register dst, Register cnt, Register tmp, Label& Ldone); 1416 1417 void string_compare(Register str1, Register str2, 1418 Register cnt1, Register cnt2, 1419 Register tmp1, Register tmp2, 1420 Register result, int ae); 1421 1422 void array_equals(bool is_array_equ, Register ary1, Register ary2, 1423 Register limit, Register tmp, Register result, bool is_byte); 1424 #endif 1425 1426 // Use BIS for zeroing 1427 void bis_zeroing(Register to, Register count, Register temp, Label& Ldone); 1428 1429 // Update CRC-32[C] with a byte value according to constants in table 1430 void update_byte_crc32(Register crc, Register val, Register table); 1431 1432 // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros 1433 void reverse_bytes_32(Register src, Register dst, Register tmp); 1434 void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2); 1435 void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2); 1436 1437 // CRC32 code for java.util.zip.CRC32::updateBytes0() instrinsic. 1438 void kernel_crc32(Register crc, Register buf, Register len, Register table); 1439 // Fold 128-bit data chunk 1440 void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset); 1441 void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo); 1442 // Fold 8-bit data 1443 void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp); 1444 void fold_8bit_crc32(Register crc, Register table, Register tmp); 1445 1446 }; 1447 1448 /** 1449 * class SkipIfEqual: 1450 * 1451 * Instantiating this class will result in assembly code being output that will 1452 * jump around any code emitted between the creation of the instance and it's 1453 * automatic destruction at the end of a scope block, depending on the value of 1454 * the flag passed to the constructor, which will be checked at run-time. 1455 */ 1456 class SkipIfEqual : public StackObj { 1457 private: 1458 MacroAssembler* _masm; 1459 Label _label; 1460 1461 public: 1462 // 'temp' is a temp register that this object can use (and trash) 1463 SkipIfEqual(MacroAssembler*, Register temp, 1464 const bool* flag_addr, Assembler::Condition condition); 1465 ~SkipIfEqual(); 1466 }; 1467 1468 #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP