src/cpu/sparc/vm/macroAssembler_sparc.hpp
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src/cpu/sparc/vm/macroAssembler_sparc.hpp

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 119 // JavaThread, such as the card-marking base or perhaps pointers into
 120 // Eden.  It's something of a waste to use them as scratch temporaries,
 121 // since they are not supposed to be volatile.  (Of course, if we find
 122 // that Java doesn't benefit from application globals, then we can just
 123 // use them as ordinary temporaries.)
 124 //
 125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
 126 // it makes sense to use them routinely for procedure linkage,
 127 // whenever the On registers are not applicable.  Examples:  G5_method,
 128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
 129 // stubs.  This means that compiler stubs, etc., should be kept to a
 130 // maximum of two or three G-register arguments.
 131 
 132 
 133 // stub frames
 134 
 135 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
 136 
 137 // Interpreter frames
 138 
 139 #ifdef CC_INTERP
 140 REGISTER_DECLARATION(Register, Lstate           , L0); // interpreter state object pointer
 141 REGISTER_DECLARATION(Register, L1_scratch       , L1); // scratch
 142 REGISTER_DECLARATION(Register, Lmirror          , L1); // mirror (for native methods only)
 143 REGISTER_DECLARATION(Register, L2_scratch       , L2);
 144 REGISTER_DECLARATION(Register, L3_scratch       , L3);
 145 REGISTER_DECLARATION(Register, L4_scratch       , L4);
 146 REGISTER_DECLARATION(Register, Lscratch         , L5); // C1 uses
 147 REGISTER_DECLARATION(Register, Lscratch2        , L6); // C1 uses
 148 REGISTER_DECLARATION(Register, L7_scratch       , L7); // constant pool cache
 149 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 150 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 151                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 152                                                        // is added and removed as needed in the frame code.
 153 // Interface to signature handler
 154 REGISTER_DECLARATION(Register, Llocals          , L7); // pointer to locals for signature handler
 155 REGISTER_DECLARATION(Register, Lmethod          , L6); // Method* when calling signature handler
 156 
 157 #else
 158 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
 159 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
 160 REGISTER_DECLARATION(Register, Lmethod          , L2);
 161 REGISTER_DECLARATION(Register, Llocals          , L3);
 162 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
 163                                                        // must match Llocals in asm interpreter
 164 REGISTER_DECLARATION(Register, Lmonitors        , L4);
 165 REGISTER_DECLARATION(Register, Lbyte_code       , L5);
 166 // When calling out from the interpreter we record SP so that we can remove any extra stack
 167 // space allocated during adapter transitions. This register is only live from the point
 168 // of the call until we return.
 169 REGISTER_DECLARATION(Register, Llast_SP         , L5);
 170 REGISTER_DECLARATION(Register, Lscratch         , L5);
 171 REGISTER_DECLARATION(Register, Lscratch2        , L6);
 172 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
 173 
 174 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 175 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 176                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 177                                                        // is added and removed as needed in the frame code.
 178 REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables
 179 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
 180 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data
 181 #endif /* CC_INTERP */
 182 
 183 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
 184 //       the interpreter code. If Lscratch2 needs to be used for some
 185 //       purpose than LcpoolCache should be restore after that for
 186 //       the interpreter to work right
 187 // (These assignments must be compatible with L7_thread_cache; see above.)
 188 
 189 // Lbcp points into the middle of the method object.
 190 
 191 // Exception processing
 192 // These registers are passed into exception handlers.
 193 // All exception handlers require the exception object being thrown.
 194 // In addition, an nmethod's exception handler must be passed
 195 // the address of the call site within the nmethod, to allow
 196 // proper selection of the applicable catch block.
 197 // (Interpreter frames use their own bcp() for this purpose.)
 198 //
 199 // The Oissuing_pc value is not always needed.  When jumping to a
 200 // handler that is known to be interpreted, the Oissuing_pc value can be
 201 // omitted.  An actual catch block in compiled code receives (from its


 216 // It is a "return pc", the address __following__ the call.
 217 // Raw return addresses are converted to issuing PCs by frame::pc(),
 218 // or by stubs.  Issuing PCs can be used directly with PC range tables.
 219 //
 220 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
 221 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
 222 
 223 
 224 // These must occur after the declarations above
 225 #ifndef DONT_USE_REGISTER_DEFINES
 226 
 227 #define Gthread             AS_REGISTER(Register, Gthread)
 228 #define Gmethod             AS_REGISTER(Register, Gmethod)
 229 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
 230 #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)
 231 #define Gargs               AS_REGISTER(Register, Gargs)
 232 #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)
 233 #define Gframe_size         AS_REGISTER(Register, Gframe_size)
 234 #define Gtemp               AS_REGISTER(Register, Gtemp)
 235 
 236 #ifdef CC_INTERP
 237 #define Lstate              AS_REGISTER(Register, Lstate)
 238 #define Lesp                AS_REGISTER(Register, Lesp)
 239 #define L1_scratch          AS_REGISTER(Register, L1_scratch)
 240 #define Lmirror             AS_REGISTER(Register, Lmirror)
 241 #define L2_scratch          AS_REGISTER(Register, L2_scratch)
 242 #define L3_scratch          AS_REGISTER(Register, L3_scratch)
 243 #define L4_scratch          AS_REGISTER(Register, L4_scratch)
 244 #define Lscratch            AS_REGISTER(Register, Lscratch)
 245 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 246 #define L7_scratch          AS_REGISTER(Register, L7_scratch)
 247 #define Ostate              AS_REGISTER(Register, Ostate)
 248 #else
 249 #define Lesp                AS_REGISTER(Register, Lesp)
 250 #define Lbcp                AS_REGISTER(Register, Lbcp)
 251 #define Lmethod             AS_REGISTER(Register, Lmethod)
 252 #define Llocals             AS_REGISTER(Register, Llocals)
 253 #define Lmonitors           AS_REGISTER(Register, Lmonitors)
 254 #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)
 255 #define Lscratch            AS_REGISTER(Register, Lscratch)
 256 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 257 #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)
 258 #endif /* ! CC_INTERP */
 259 
 260 #define Lentry_args         AS_REGISTER(Register, Lentry_args)
 261 #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)
 262 #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)
 263 #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)
 264 #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)
 265 #define IdispatchTables     AS_REGISTER(Register, IdispatchTables)
 266 
 267 #define Oexception          AS_REGISTER(Register, Oexception)
 268 #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)
 269 
 270 #endif
 271 
 272 
 273 // Address is an abstraction used to represent a memory location.
 274 //
 275 // Note: A register location is represented via a Register, not
 276 //       via an address for efficiency & simplicity reasons.
 277 
 278 class Address VALUE_OBJ_CLASS_SPEC {


 593 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
 594 #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
 595 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
 596 
 597 
 598 class MacroAssembler : public Assembler {
 599   // code patchers need various routines like inv_wdisp()
 600   friend class NativeInstruction;
 601   friend class NativeGeneralJump;
 602   friend class Relocation;
 603   friend class Label;
 604 
 605  protected:
 606   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 607   static int  branch_destination(int inst, int pos);
 608 
 609   // Support for VM calls
 610   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
 611   // may customize this version by overriding it for its purposes (e.g., to save/restore
 612   // additional registers when doing a VM call).
 613 #ifdef CC_INTERP
 614   #define VIRTUAL
 615 #else
 616   #define VIRTUAL virtual
 617 #endif
 618 
 619   VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
 620 
 621   //
 622   // It is imperative that all calls into the VM are handled via the call_VM macros.
 623   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 624   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 625   //
 626   // This is the base routine called by the different versions of call_VM. The interpreter
 627   // may customize this version by overriding it for its purposes (e.g., to save/restore
 628   // additional registers when doing a VM call).
 629   //
 630   // A non-volatile java_thread_cache register should be specified so
 631   // that the G2_thread value can be preserved across the call.
 632   // (If java_thread_cache is noreg, then a slow get_thread call
 633   // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
 634   // thread.
 635   //
 636   // If no last_java_sp is specified (noreg) than SP will be used instead.
 637 
 638   virtual void call_VM_base(
 639     Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise


1466   // Use BIS for zeroing
1467   void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1468 
1469   // Update CRC-32[C] with a byte value according to constants in table
1470   void update_byte_crc32(Register crc, Register val, Register table);
1471 
1472   // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
1473   void reverse_bytes_32(Register src, Register dst, Register tmp);
1474   void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
1475   void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
1476 
1477   // CRC32 code for java.util.zip.CRC32::updateBytes0() instrinsic.
1478   void kernel_crc32(Register crc, Register buf, Register len, Register table);
1479   // Fold 128-bit data chunk
1480   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
1481   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo);
1482   // Fold 8-bit data
1483   void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
1484   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1485 
1486 #undef VIRTUAL
1487 };
1488 
1489 /**
1490  * class SkipIfEqual:
1491  *
1492  * Instantiating this class will result in assembly code being output that will
1493  * jump around any code emitted between the creation of the instance and it's
1494  * automatic destruction at the end of a scope block, depending on the value of
1495  * the flag passed to the constructor, which will be checked at run-time.
1496  */
1497 class SkipIfEqual : public StackObj {
1498  private:
1499   MacroAssembler* _masm;
1500   Label _label;
1501 
1502  public:
1503    // 'temp' is a temp register that this object can use (and trash)
1504    SkipIfEqual(MacroAssembler*, Register temp,
1505                const bool* flag_addr, Assembler::Condition condition);
1506    ~SkipIfEqual();


 119 // JavaThread, such as the card-marking base or perhaps pointers into
 120 // Eden.  It's something of a waste to use them as scratch temporaries,
 121 // since they are not supposed to be volatile.  (Of course, if we find
 122 // that Java doesn't benefit from application globals, then we can just
 123 // use them as ordinary temporaries.)
 124 //
 125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
 126 // it makes sense to use them routinely for procedure linkage,
 127 // whenever the On registers are not applicable.  Examples:  G5_method,
 128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
 129 // stubs.  This means that compiler stubs, etc., should be kept to a
 130 // maximum of two or three G-register arguments.
 131 
 132 
 133 // stub frames
 134 
 135 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
 136 
 137 // Interpreter frames
 138 



















 139 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
 140 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
 141 REGISTER_DECLARATION(Register, Lmethod          , L2);
 142 REGISTER_DECLARATION(Register, Llocals          , L3);
 143 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
 144                                                        // must match Llocals in asm interpreter
 145 REGISTER_DECLARATION(Register, Lmonitors        , L4);
 146 REGISTER_DECLARATION(Register, Lbyte_code       , L5);
 147 // When calling out from the interpreter we record SP so that we can remove any extra stack
 148 // space allocated during adapter transitions. This register is only live from the point
 149 // of the call until we return.
 150 REGISTER_DECLARATION(Register, Llast_SP         , L5);
 151 REGISTER_DECLARATION(Register, Lscratch         , L5);
 152 REGISTER_DECLARATION(Register, Lscratch2        , L6);
 153 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
 154 
 155 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 156 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 157                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 158                                                        // is added and removed as needed in the frame code.
 159 REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables
 160 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
 161 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data

 162 
 163 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
 164 //       the interpreter code. If Lscratch2 needs to be used for some
 165 //       purpose than LcpoolCache should be restore after that for
 166 //       the interpreter to work right
 167 // (These assignments must be compatible with L7_thread_cache; see above.)
 168 
 169 // Lbcp points into the middle of the method object.
 170 
 171 // Exception processing
 172 // These registers are passed into exception handlers.
 173 // All exception handlers require the exception object being thrown.
 174 // In addition, an nmethod's exception handler must be passed
 175 // the address of the call site within the nmethod, to allow
 176 // proper selection of the applicable catch block.
 177 // (Interpreter frames use their own bcp() for this purpose.)
 178 //
 179 // The Oissuing_pc value is not always needed.  When jumping to a
 180 // handler that is known to be interpreted, the Oissuing_pc value can be
 181 // omitted.  An actual catch block in compiled code receives (from its


 196 // It is a "return pc", the address __following__ the call.
 197 // Raw return addresses are converted to issuing PCs by frame::pc(),
 198 // or by stubs.  Issuing PCs can be used directly with PC range tables.
 199 //
 200 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
 201 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
 202 
 203 
 204 // These must occur after the declarations above
 205 #ifndef DONT_USE_REGISTER_DEFINES
 206 
 207 #define Gthread             AS_REGISTER(Register, Gthread)
 208 #define Gmethod             AS_REGISTER(Register, Gmethod)
 209 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
 210 #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)
 211 #define Gargs               AS_REGISTER(Register, Gargs)
 212 #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)
 213 #define Gframe_size         AS_REGISTER(Register, Gframe_size)
 214 #define Gtemp               AS_REGISTER(Register, Gtemp)
 215 













 216 #define Lesp                AS_REGISTER(Register, Lesp)
 217 #define Lbcp                AS_REGISTER(Register, Lbcp)
 218 #define Lmethod             AS_REGISTER(Register, Lmethod)
 219 #define Llocals             AS_REGISTER(Register, Llocals)
 220 #define Lmonitors           AS_REGISTER(Register, Lmonitors)
 221 #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)
 222 #define Lscratch            AS_REGISTER(Register, Lscratch)
 223 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 224 #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)

 225 
 226 #define Lentry_args         AS_REGISTER(Register, Lentry_args)
 227 #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)
 228 #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)
 229 #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)
 230 #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)
 231 #define IdispatchTables     AS_REGISTER(Register, IdispatchTables)
 232 
 233 #define Oexception          AS_REGISTER(Register, Oexception)
 234 #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)
 235 
 236 #endif
 237 
 238 
 239 // Address is an abstraction used to represent a memory location.
 240 //
 241 // Note: A register location is represented via a Register, not
 242 //       via an address for efficiency & simplicity reasons.
 243 
 244 class Address VALUE_OBJ_CLASS_SPEC {


 559 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
 560 #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
 561 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
 562 
 563 
 564 class MacroAssembler : public Assembler {
 565   // code patchers need various routines like inv_wdisp()
 566   friend class NativeInstruction;
 567   friend class NativeGeneralJump;
 568   friend class Relocation;
 569   friend class Label;
 570 
 571  protected:
 572   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 573   static int  branch_destination(int inst, int pos);
 574 
 575   // Support for VM calls
 576   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
 577   // may customize this version by overriding it for its purposes (e.g., to save/restore
 578   // additional registers when doing a VM call).
 579   virtual void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);






 580 
 581   //
 582   // It is imperative that all calls into the VM are handled via the call_VM macros.
 583   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 584   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 585   //
 586   // This is the base routine called by the different versions of call_VM. The interpreter
 587   // may customize this version by overriding it for its purposes (e.g., to save/restore
 588   // additional registers when doing a VM call).
 589   //
 590   // A non-volatile java_thread_cache register should be specified so
 591   // that the G2_thread value can be preserved across the call.
 592   // (If java_thread_cache is noreg, then a slow get_thread call
 593   // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
 594   // thread.
 595   //
 596   // If no last_java_sp is specified (noreg) than SP will be used instead.
 597 
 598   virtual void call_VM_base(
 599     Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise


1426   // Use BIS for zeroing
1427   void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1428 
1429   // Update CRC-32[C] with a byte value according to constants in table
1430   void update_byte_crc32(Register crc, Register val, Register table);
1431 
1432   // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
1433   void reverse_bytes_32(Register src, Register dst, Register tmp);
1434   void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
1435   void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
1436 
1437   // CRC32 code for java.util.zip.CRC32::updateBytes0() instrinsic.
1438   void kernel_crc32(Register crc, Register buf, Register len, Register table);
1439   // Fold 128-bit data chunk
1440   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
1441   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo);
1442   // Fold 8-bit data
1443   void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
1444   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1445 

1446 };
1447 
1448 /**
1449  * class SkipIfEqual:
1450  *
1451  * Instantiating this class will result in assembly code being output that will
1452  * jump around any code emitted between the creation of the instance and it's
1453  * automatic destruction at the end of a scope block, depending on the value of
1454  * the flag passed to the constructor, which will be checked at run-time.
1455  */
1456 class SkipIfEqual : public StackObj {
1457  private:
1458   MacroAssembler* _masm;
1459   Label _label;
1460 
1461  public:
1462    // 'temp' is a temp register that this object can use (and trash)
1463    SkipIfEqual(MacroAssembler*, Register temp,
1464                const bool* flag_addr, Assembler::Condition condition);
1465    ~SkipIfEqual();
src/cpu/sparc/vm/macroAssembler_sparc.hpp
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