1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 #ifdef CC_INTERP
52 // c++ interpreter never wants to use interp_masm version of call_VM
53 #define VIRTUAL
54 #else
55 #define VIRTUAL virtual
56 #endif
57
58 #define COMMA ,
59
60 VIRTUAL void call_VM_leaf_base(
61 address entry_point, // the entry point
62 int number_of_arguments // the number of arguments to pop after the call
63 );
64
65 // This is the base routine called by the different versions of call_VM. The interpreter
66 // may customize this version by overriding it for its purposes (e.g., to save/restore
67 // additional registers when doing a VM call).
68 //
69 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
70 // returns the register which contains the thread upon return. If a thread register has been
71 // specified, the return value will correspond to that register. If no last_java_sp is specified
72 // (noreg) than rsp will be used instead.
73 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
74 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
75 Register java_thread, // the thread if computed before ; use noreg otherwise
76 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
77 address entry_point, // the entry point
78 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
79 bool check_exceptions // whether to check for pending exceptions after return
80 );
81
82 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
83 // The implementation is only non-empty for the InterpreterMacroAssembler,
84 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
85 virtual void check_and_handle_popframe(Register java_thread);
86 virtual void check_and_handle_earlyret(Register java_thread);
87
88 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
89
90 // helpers for FPU flag access
91 // tmp is a temporary register, if none is available use noreg
92 void save_rax (Register tmp);
93 void restore_rax(Register tmp);
94
95 public:
96 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
97
98 // Support for NULL-checks
99 //
100 // Generates code that causes a NULL OS exception if the content of reg is NULL.
101 // If the accessed location is M[reg + offset] and the offset is known, provide the
102 // offset. No explicit code generation is needed if the offset is within a certain
103 // range (0 <= offset <= page_size).
104
105 void null_check(Register reg, int offset = -1);
106 static bool needs_explicit_null_check(intptr_t offset);
107
108 // Required platform-specific helpers for Label::patch_instructions.
109 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
110 void pd_patch_instruction(address branch, address target) {
111 unsigned char op = branch[0];
112 assert(op == 0xE8 /* call */ ||
113 op == 0xE9 /* jmp */ ||
114 op == 0xEB /* short jmp */ ||
115 (op & 0xF0) == 0x70 /* short jcc */ ||
116 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
117 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
118 "Invalid opcode at patch point");
119
120 if (op == 0xEB || (op & 0xF0) == 0x70) {
121 // short offset operators (jmp and jcc)
122 char* disp = (char*) &branch[1];
123 int imm8 = target - (address) &disp[1];
124 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
125 *disp = imm8;
126 } else {
127 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
128 int imm32 = target - (address) &disp[1];
129 *disp = imm32;
130 }
131 }
132
133 // The following 4 methods return the offset of the appropriate move instruction
134
135 // Support for fast byte/short loading with zero extension (depending on particular CPU)
136 int load_unsigned_byte(Register dst, Address src);
137 int load_unsigned_short(Register dst, Address src);
138
139 // Support for fast byte/short loading with sign extension (depending on particular CPU)
140 int load_signed_byte(Register dst, Address src);
141 int load_signed_short(Register dst, Address src);
142
143 // Support for sign-extension (hi:lo = extend_sign(lo))
144 void extend_sign(Register hi, Register lo);
145
146 // Load and store values by size and signed-ness
147 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
148 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
149
150 // Support for inc/dec with optimal instruction selection depending on value
151
152 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
153 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
154
155 void decrementl(Address dst, int value = 1);
156 void decrementl(Register reg, int value = 1);
157
158 void decrementq(Register reg, int value = 1);
159 void decrementq(Address dst, int value = 1);
160
161 void incrementl(Address dst, int value = 1);
162 void incrementl(Register reg, int value = 1);
163
164 void incrementq(Register reg, int value = 1);
165 void incrementq(Address dst, int value = 1);
166
167 // Support optimal SSE move instructions.
168 void movflt(XMMRegister dst, XMMRegister src) {
169 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
170 else { movss (dst, src); return; }
171 }
172 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
173 void movflt(XMMRegister dst, AddressLiteral src);
174 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
175
176 void movdbl(XMMRegister dst, XMMRegister src) {
177 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
178 else { movsd (dst, src); return; }
179 }
180
181 void movdbl(XMMRegister dst, AddressLiteral src);
182
183 void movdbl(XMMRegister dst, Address src) {
184 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
185 else { movlpd(dst, src); return; }
186 }
187 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
188
189 void incrementl(AddressLiteral dst);
190 void incrementl(ArrayAddress dst);
191
192 void incrementq(AddressLiteral dst);
193
194 // Alignment
195 void align(int modulus);
196 void align(int modulus, int target);
197
198 // A 5 byte nop that is safe for patching (see patch_verified_entry)
199 void fat_nop();
200
201 // Stack frame creation/removal
202 void enter();
203 void leave();
204
205 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
206 // The pointer will be loaded into the thread register.
207 void get_thread(Register thread);
208
209
210 // Support for VM calls
211 //
212 // It is imperative that all calls into the VM are handled via the call_VM macros.
213 // They make sure that the stack linkage is setup correctly. call_VM's correspond
214 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
215
216
217 void call_VM(Register oop_result,
218 address entry_point,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2,
227 bool check_exceptions = true);
228 void call_VM(Register oop_result,
229 address entry_point,
230 Register arg_1, Register arg_2, Register arg_3,
231 bool check_exceptions = true);
232
233 // Overloadings with last_Java_sp
234 void call_VM(Register oop_result,
235 Register last_java_sp,
236 address entry_point,
237 int number_of_arguments = 0,
238 bool check_exceptions = true);
239 void call_VM(Register oop_result,
240 Register last_java_sp,
241 address entry_point,
242 Register arg_1, bool
243 check_exceptions = true);
244 void call_VM(Register oop_result,
245 Register last_java_sp,
246 address entry_point,
247 Register arg_1, Register arg_2,
248 bool check_exceptions = true);
249 void call_VM(Register oop_result,
250 Register last_java_sp,
251 address entry_point,
252 Register arg_1, Register arg_2, Register arg_3,
253 bool check_exceptions = true);
254
255 void get_vm_result (Register oop_result, Register thread);
256 void get_vm_result_2(Register metadata_result, Register thread);
257
258 // These always tightly bind to MacroAssembler::call_VM_base
259 // bypassing the virtual implementation
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
261 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
262 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
263 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
264 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
265
266 void call_VM_leaf(address entry_point,
267 int number_of_arguments = 0);
268 void call_VM_leaf(address entry_point,
269 Register arg_1);
270 void call_VM_leaf(address entry_point,
271 Register arg_1, Register arg_2);
272 void call_VM_leaf(address entry_point,
273 Register arg_1, Register arg_2, Register arg_3);
274
275 // These always tightly bind to MacroAssembler::call_VM_leaf_base
276 // bypassing the virtual implementation
277 void super_call_VM_leaf(address entry_point);
278 void super_call_VM_leaf(address entry_point, Register arg_1);
279 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
280 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
281 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
282
283 // last Java Frame (fills frame anchor)
284 void set_last_Java_frame(Register thread,
285 Register last_java_sp,
286 Register last_java_fp,
287 address last_java_pc);
288
289 // thread in the default location (r15_thread on 64bit)
290 void set_last_Java_frame(Register last_java_sp,
291 Register last_java_fp,
292 address last_java_pc);
293
294 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
295
296 // thread in the default location (r15_thread on 64bit)
297 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
298
299 // Stores
300 void store_check(Register obj); // store check for obj - register is destroyed afterwards
301 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
302
303 #if INCLUDE_ALL_GCS
304
305 void g1_write_barrier_pre(Register obj,
306 Register pre_val,
307 Register thread,
308 Register tmp,
309 bool tosca_live,
310 bool expand_call);
311
312 void g1_write_barrier_post(Register store_addr,
313 Register new_val,
314 Register thread,
315 Register tmp,
316 Register tmp2);
317
318 #endif // INCLUDE_ALL_GCS
319
320 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
321 void c2bool(Register x);
322
323 // C++ bool manipulation
324
325 void movbool(Register dst, Address src);
326 void movbool(Address dst, bool boolconst);
327 void movbool(Address dst, Register src);
328 void testbool(Register dst);
329
330 // oop manipulations
331 void load_klass(Register dst, Register src);
332 void store_klass(Register dst, Register src);
333
334 void load_heap_oop(Register dst, Address src);
335 void load_heap_oop_not_null(Register dst, Address src);
336 void store_heap_oop(Address dst, Register src);
337 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
338
339 // Used for storing NULL. All other oop constants should be
340 // stored using routines that take a jobject.
341 void store_heap_oop_null(Address dst);
342
343 void load_prototype_header(Register dst, Register src);
344
345 #ifdef _LP64
346 void store_klass_gap(Register dst, Register src);
347
348 // This dummy is to prevent a call to store_heap_oop from
349 // converting a zero (like NULL) into a Register by giving
350 // the compiler two choices it can't resolve
351
352 void store_heap_oop(Address dst, void* dummy);
353
354 void encode_heap_oop(Register r);
355 void decode_heap_oop(Register r);
356 void encode_heap_oop_not_null(Register r);
357 void decode_heap_oop_not_null(Register r);
358 void encode_heap_oop_not_null(Register dst, Register src);
359 void decode_heap_oop_not_null(Register dst, Register src);
360
361 void set_narrow_oop(Register dst, jobject obj);
362 void set_narrow_oop(Address dst, jobject obj);
363 void cmp_narrow_oop(Register dst, jobject obj);
364 void cmp_narrow_oop(Address dst, jobject obj);
365
366 void encode_klass_not_null(Register r);
367 void decode_klass_not_null(Register r);
368 void encode_klass_not_null(Register dst, Register src);
369 void decode_klass_not_null(Register dst, Register src);
370 void set_narrow_klass(Register dst, Klass* k);
371 void set_narrow_klass(Address dst, Klass* k);
372 void cmp_narrow_klass(Register dst, Klass* k);
373 void cmp_narrow_klass(Address dst, Klass* k);
374
375 // Returns the byte size of the instructions generated by decode_klass_not_null()
376 // when compressed klass pointers are being used.
377 static int instr_size_for_decode_klass_not_null();
378
379 // if heap base register is used - reinit it with the correct value
380 void reinit_heapbase();
381
382 DEBUG_ONLY(void verify_heapbase(const char* msg);)
383
384 #endif // _LP64
385
386 // Int division/remainder for Java
387 // (as idivl, but checks for special case as described in JVM spec.)
388 // returns idivl instruction offset for implicit exception handling
389 int corrected_idivl(Register reg);
390
391 // Long division/remainder for Java
392 // (as idivq, but checks for special case as described in JVM spec.)
393 // returns idivq instruction offset for implicit exception handling
394 int corrected_idivq(Register reg);
395
396 void int3();
397
398 // Long operation macros for a 32bit cpu
399 // Long negation for Java
400 void lneg(Register hi, Register lo);
401
402 // Long multiplication for Java
403 // (destroys contents of eax, ebx, ecx and edx)
404 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
405
406 // Long shifts for Java
407 // (semantics as described in JVM spec.)
408 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
409 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
410
411 // Long compare for Java
412 // (semantics as described in JVM spec.)
413 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
414
415
416 // misc
417
418 // Sign extension
419 void sign_extend_short(Register reg);
420 void sign_extend_byte(Register reg);
421
422 // Division by power of 2, rounding towards 0
423 void division_with_shift(Register reg, int shift_value);
424
425 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
426 //
427 // CF (corresponds to C0) if x < y
428 // PF (corresponds to C2) if unordered
429 // ZF (corresponds to C3) if x = y
430 //
431 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
432 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
433 void fcmp(Register tmp);
434 // Variant of the above which allows y to be further down the stack
435 // and which only pops x and y if specified. If pop_right is
436 // specified then pop_left must also be specified.
437 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
438
439 // Floating-point comparison for Java
440 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
441 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
442 // (semantics as described in JVM spec.)
443 void fcmp2int(Register dst, bool unordered_is_less);
444 // Variant of the above which allows y to be further down the stack
445 // and which only pops x and y if specified. If pop_right is
446 // specified then pop_left must also be specified.
447 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
448
449 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
450 // tmp is a temporary register, if none is available use noreg
451 void fremr(Register tmp);
452
453
454 // same as fcmp2int, but using SSE2
455 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
456 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
457
458 // Inlined sin/cos generator for Java; must not use CPU instruction
459 // directly on Intel as it does not have high enough precision
460 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
461 // number of FPU stack slots in use; all but the topmost will
462 // require saving if a slow case is necessary. Assumes argument is
463 // on FP TOS; result is on FP TOS. No cpu registers are changed by
464 // this code.
465 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
466
467 // branch to L if FPU flag C2 is set/not set
468 // tmp is a temporary register, if none is available use noreg
469 void jC2 (Register tmp, Label& L);
470 void jnC2(Register tmp, Label& L);
471
472 // Pop ST (ffree & fincstp combined)
473 void fpop();
474
475 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
476 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
477 void load_float(Address src);
478
479 // Store float value to 'address'. If UseSSE >= 1, the value is stored
480 // from register xmm0. Otherwise, the value is stored from the FPU stack.
481 void store_float(Address dst);
482
483 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
484 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
485 void load_double(Address src);
486
487 // Store double value to 'address'. If UseSSE >= 2, the value is stored
488 // from register xmm0. Otherwise, the value is stored from the FPU stack.
489 void store_double(Address dst);
490
491 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
492 void push_fTOS();
493
494 // pops double TOS element from CPU stack and pushes on FPU stack
495 void pop_fTOS();
496
497 void empty_FPU_stack();
498
499 void push_IU_state();
500 void pop_IU_state();
501
502 void push_FPU_state();
503 void pop_FPU_state();
504
505 void push_CPU_state();
506 void pop_CPU_state();
507
508 // Round up to a power of two
509 void round_to(Register reg, int modulus);
510
511 // Callee saved registers handling
512 void push_callee_saved_registers();
513 void pop_callee_saved_registers();
514
515 // allocation
516 void eden_allocate(
517 Register obj, // result: pointer to object after successful allocation
518 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
519 int con_size_in_bytes, // object size in bytes if known at compile time
520 Register t1, // temp register
521 Label& slow_case // continuation point if fast allocation fails
522 );
523 void tlab_allocate(
524 Register obj, // result: pointer to object after successful allocation
525 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
526 int con_size_in_bytes, // object size in bytes if known at compile time
527 Register t1, // temp register
528 Register t2, // temp register
529 Label& slow_case // continuation point if fast allocation fails
530 );
531 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
532 void incr_allocated_bytes(Register thread,
533 Register var_size_in_bytes, int con_size_in_bytes,
534 Register t1 = noreg);
535
536 // interface method calling
537 void lookup_interface_method(Register recv_klass,
538 Register intf_klass,
539 RegisterOrConstant itable_index,
540 Register method_result,
541 Register scan_temp,
542 Label& no_such_interface);
543
544 // virtual method calling
545 void lookup_virtual_method(Register recv_klass,
546 RegisterOrConstant vtable_index,
547 Register method_result);
548
549 // Test sub_klass against super_klass, with fast and slow paths.
550
551 // The fast path produces a tri-state answer: yes / no / maybe-slow.
552 // One of the three labels can be NULL, meaning take the fall-through.
553 // If super_check_offset is -1, the value is loaded up from super_klass.
554 // No registers are killed, except temp_reg.
555 void check_klass_subtype_fast_path(Register sub_klass,
556 Register super_klass,
557 Register temp_reg,
558 Label* L_success,
559 Label* L_failure,
560 Label* L_slow_path,
561 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
562
563 // The rest of the type check; must be wired to a corresponding fast path.
564 // It does not repeat the fast path logic, so don't use it standalone.
565 // The temp_reg and temp2_reg can be noreg, if no temps are available.
566 // Updates the sub's secondary super cache as necessary.
567 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
568 void check_klass_subtype_slow_path(Register sub_klass,
569 Register super_klass,
570 Register temp_reg,
571 Register temp2_reg,
572 Label* L_success,
573 Label* L_failure,
574 bool set_cond_codes = false);
575
576 // Simplified, combined version, good for typical uses.
577 // Falls through on failure.
578 void check_klass_subtype(Register sub_klass,
579 Register super_klass,
580 Register temp_reg,
581 Label& L_success);
582
583 // method handles (JSR 292)
584 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
585
586 //----
587 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
588
589 // Debugging
590
591 // only if +VerifyOops
592 // TODO: Make these macros with file and line like sparc version!
593 void verify_oop(Register reg, const char* s = "broken oop");
594 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
595
596 // TODO: verify method and klass metadata (compare against vptr?)
597 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
598 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
599
600 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
601 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
602
603 // only if +VerifyFPU
604 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
605
606 // Verify or restore cpu control state after JNI call
607 void restore_cpu_control_state_after_jni();
608
609 // prints msg, dumps registers and stops execution
610 void stop(const char* msg);
611
612 // prints msg and continues
613 void warn(const char* msg);
614
615 // dumps registers and other state
616 void print_state();
617
618 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
619 static void debug64(char* msg, int64_t pc, int64_t regs[]);
620 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
621 static void print_state64(int64_t pc, int64_t regs[]);
622
623 void os_breakpoint();
624
625 void untested() { stop("untested"); }
626
627 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
628
629 void should_not_reach_here() { stop("should not reach here"); }
630
631 void print_CPU_state();
632
633 // Stack overflow checking
634 void bang_stack_with_offset(int offset) {
635 // stack grows down, caller passes positive offset
636 assert(offset > 0, "must bang with negative offset");
637 movl(Address(rsp, (-offset)), rax);
638 }
639
640 // Writes to stack successive pages until offset reached to check for
641 // stack overflow + shadow pages. Also, clobbers tmp
642 void bang_stack_size(Register size, Register tmp);
643
644 // Check for reserved stack access in method being exited (for JIT)
645 void reserved_stack_check();
646
647 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
648 Register tmp,
649 int offset);
650
651 // Support for serializing memory accesses between threads
652 void serialize_memory(Register thread, Register tmp);
653
654 void verify_tlab();
655
656 // Biased locking support
657 // lock_reg and obj_reg must be loaded up with the appropriate values.
658 // swap_reg must be rax, and is killed.
659 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
660 // be killed; if not supplied, push/pop will be used internally to
661 // allocate a temporary (inefficient, avoid if possible).
662 // Optional slow case is for implementations (interpreter and C1) which branch to
663 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
664 // Returns offset of first potentially-faulting instruction for null
665 // check info (currently consumed only by C1). If
666 // swap_reg_contains_mark is true then returns -1 as it is assumed
667 // the calling code has already passed any potential faults.
668 int biased_locking_enter(Register lock_reg, Register obj_reg,
669 Register swap_reg, Register tmp_reg,
670 bool swap_reg_contains_mark,
671 Label& done, Label* slow_case = NULL,
672 BiasedLockingCounters* counters = NULL);
673 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
674 #ifdef COMPILER2
675 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
676 // See full desription in macroAssembler_x86.cpp.
677 void fast_lock(Register obj, Register box, Register tmp,
678 Register scr, Register cx1, Register cx2,
679 BiasedLockingCounters* counters,
680 RTMLockingCounters* rtm_counters,
681 RTMLockingCounters* stack_rtm_counters,
682 Metadata* method_data,
683 bool use_rtm, bool profile_rtm);
684 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
685 #if INCLUDE_RTM_OPT
686 void rtm_counters_update(Register abort_status, Register rtm_counters);
687 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
688 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
689 RTMLockingCounters* rtm_counters,
690 Metadata* method_data);
691 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
692 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
693 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
694 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
695 void rtm_stack_locking(Register obj, Register tmp, Register scr,
696 Register retry_on_abort_count,
697 RTMLockingCounters* stack_rtm_counters,
698 Metadata* method_data, bool profile_rtm,
699 Label& DONE_LABEL, Label& IsInflated);
700 void rtm_inflated_locking(Register obj, Register box, Register tmp,
701 Register scr, Register retry_on_busy_count,
702 Register retry_on_abort_count,
703 RTMLockingCounters* rtm_counters,
704 Metadata* method_data, bool profile_rtm,
705 Label& DONE_LABEL);
706 #endif
707 #endif
708
709 Condition negate_condition(Condition cond);
710
711 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
712 // operands. In general the names are modified to avoid hiding the instruction in Assembler
713 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
714 // here in MacroAssembler. The major exception to this rule is call
715
716 // Arithmetics
717
718
719 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
720 void addptr(Address dst, Register src);
721
722 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
723 void addptr(Register dst, int32_t src);
724 void addptr(Register dst, Register src);
725 void addptr(Register dst, RegisterOrConstant src) {
726 if (src.is_constant()) addptr(dst, (int) src.as_constant());
727 else addptr(dst, src.as_register());
728 }
729
730 void andptr(Register dst, int32_t src);
731 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
732
733 void cmp8(AddressLiteral src1, int imm);
734
735 // renamed to drag out the casting of address to int32_t/intptr_t
736 void cmp32(Register src1, int32_t imm);
737
738 void cmp32(AddressLiteral src1, int32_t imm);
739 // compare reg - mem, or reg - &mem
740 void cmp32(Register src1, AddressLiteral src2);
741
742 void cmp32(Register src1, Address src2);
743
744 #ifndef _LP64
745 void cmpklass(Address dst, Metadata* obj);
746 void cmpklass(Register dst, Metadata* obj);
747 void cmpoop(Address dst, jobject obj);
748 void cmpoop(Register dst, jobject obj);
749 #endif // _LP64
750
751 // NOTE src2 must be the lval. This is NOT an mem-mem compare
752 void cmpptr(Address src1, AddressLiteral src2);
753
754 void cmpptr(Register src1, AddressLiteral src2);
755
756 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
757 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
758 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
759
760 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
761 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
762
763 // cmp64 to avoild hiding cmpq
764 void cmp64(Register src1, AddressLiteral src);
765
766 void cmpxchgptr(Register reg, Address adr);
767
768 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
769
770
771 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
772 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
773
774
775 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
776
777 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
778
779 void shlptr(Register dst, int32_t shift);
780 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
781
782 void shrptr(Register dst, int32_t shift);
783 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
784
785 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
786 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
787
788 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
789
790 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
791 void subptr(Register dst, int32_t src);
792 // Force generation of a 4 byte immediate value even if it fits into 8bit
793 void subptr_imm32(Register dst, int32_t src);
794 void subptr(Register dst, Register src);
795 void subptr(Register dst, RegisterOrConstant src) {
796 if (src.is_constant()) subptr(dst, (int) src.as_constant());
797 else subptr(dst, src.as_register());
798 }
799
800 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
801 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
802
803 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
804 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
805
806 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
807
808
809
810 // Helper functions for statistics gathering.
811 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
812 void cond_inc32(Condition cond, AddressLiteral counter_addr);
813 // Unconditional atomic increment.
814 void atomic_incl(Address counter_addr);
815 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
816 #ifdef _LP64
817 void atomic_incq(Address counter_addr);
818 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
819 #endif
820 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
821 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
822
823 void lea(Register dst, AddressLiteral adr);
824 void lea(Address dst, AddressLiteral adr);
825 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
826
827 void leal32(Register dst, Address src) { leal(dst, src); }
828
829 // Import other testl() methods from the parent class or else
830 // they will be hidden by the following overriding declaration.
831 using Assembler::testl;
832 void testl(Register dst, AddressLiteral src);
833
834 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
835 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
836 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
837 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
838
839 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
840 void testptr(Register src1, Register src2);
841
842 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
843 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
844
845 // Calls
846
847 void call(Label& L, relocInfo::relocType rtype);
848 void call(Register entry);
849
850 // NOTE: this call tranfers to the effective address of entry NOT
851 // the address contained by entry. This is because this is more natural
852 // for jumps/calls.
853 void call(AddressLiteral entry);
854
855 // Emit the CompiledIC call idiom
856 void ic_call(address entry);
857
858 // Jumps
859
860 // NOTE: these jumps tranfer to the effective address of dst NOT
861 // the address contained by dst. This is because this is more natural
862 // for jumps/calls.
863 void jump(AddressLiteral dst);
864 void jump_cc(Condition cc, AddressLiteral dst);
865
866 // 32bit can do a case table jump in one instruction but we no longer allow the base
867 // to be installed in the Address class. This jump will tranfers to the address
868 // contained in the location described by entry (not the address of entry)
869 void jump(ArrayAddress entry);
870
871 // Floating
872
873 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
874 void andpd(XMMRegister dst, AddressLiteral src);
875
876 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
877 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
878 void andps(XMMRegister dst, AddressLiteral src);
879
880 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
881 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
882 void comiss(XMMRegister dst, AddressLiteral src);
883
884 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
885 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
886 void comisd(XMMRegister dst, AddressLiteral src);
887
888 void fadd_s(Address src) { Assembler::fadd_s(src); }
889 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
890
891 void fldcw(Address src) { Assembler::fldcw(src); }
892 void fldcw(AddressLiteral src);
893
894 void fld_s(int index) { Assembler::fld_s(index); }
895 void fld_s(Address src) { Assembler::fld_s(src); }
896 void fld_s(AddressLiteral src);
897
898 void fld_d(Address src) { Assembler::fld_d(src); }
899 void fld_d(AddressLiteral src);
900
901 void fld_x(Address src) { Assembler::fld_x(src); }
902 void fld_x(AddressLiteral src);
903
904 void fmul_s(Address src) { Assembler::fmul_s(src); }
905 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
906
907 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
908 void ldmxcsr(AddressLiteral src);
909
910 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
911 // all corner cases and may result in NaN and require fallback to a
912 // runtime call.
913 void fast_pow();
914 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
915 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
916 Register rax, Register rcx, Register rdx, Register tmp);
917
918 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
919 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
920 Register rax, Register rcx, Register rdx, Register tmp1 LP64_ONLY(COMMA Register tmp2));
921
922 void increase_precision();
923 void restore_precision();
924
925 // computes pow(x,y). Fallback to runtime call included.
926 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(num_fpu_regs_in_use); }
927
928 private:
929
930 // call runtime as a fallback for trig functions and pow/exp.
931 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
932
933 // computes 2^(Ylog2X); Ylog2X in ST(0)
934 void pow_exp_core_encoding();
935
936 // computes pow(x,y) or exp(x). Fallback to runtime call included.
937 void pow_or_exp(int num_fpu_regs_in_use);
938
939 // these are private because users should be doing movflt/movdbl
940
941 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
942 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
943 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
944 void movss(XMMRegister dst, AddressLiteral src);
945
946 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
947 void movlpd(XMMRegister dst, AddressLiteral src);
948
949 public:
950
951 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
952 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
953 void addsd(XMMRegister dst, AddressLiteral src);
954
955 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
956 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
957 void addss(XMMRegister dst, AddressLiteral src);
958
959 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
960 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
961 void divsd(XMMRegister dst, AddressLiteral src);
962
963 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
964 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
965 void divss(XMMRegister dst, AddressLiteral src);
966
967 // Move Unaligned Double Quadword
968 void movdqu(Address dst, XMMRegister src);
969 void movdqu(XMMRegister dst, Address src);
970 void movdqu(XMMRegister dst, XMMRegister src);
971 void movdqu(XMMRegister dst, AddressLiteral src);
972 // AVX Unaligned forms
973 void vmovdqu(Address dst, XMMRegister src);
974 void vmovdqu(XMMRegister dst, Address src);
975 void vmovdqu(XMMRegister dst, XMMRegister src);
976 void vmovdqu(XMMRegister dst, AddressLiteral src);
977
978 // Move Aligned Double Quadword
979 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
980 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
981 void movdqa(XMMRegister dst, AddressLiteral src);
982
983 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
984 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
985 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
986 void movsd(XMMRegister dst, AddressLiteral src);
987
988 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
989 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
990 void mulpd(XMMRegister dst, AddressLiteral src);
991
992 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
993 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
994 void mulsd(XMMRegister dst, AddressLiteral src);
995
996 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
997 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
998 void mulss(XMMRegister dst, AddressLiteral src);
999
1000 // Carry-Less Multiplication Quadword
1001 void pclmulldq(XMMRegister dst, XMMRegister src) {
1002 // 0x00 - multiply lower 64 bits [0:63]
1003 Assembler::pclmulqdq(dst, src, 0x00);
1004 }
1005 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1006 // 0x11 - multiply upper 64 bits [64:127]
1007 Assembler::pclmulqdq(dst, src, 0x11);
1008 }
1009
1010 void pcmpeqb(XMMRegister dst, XMMRegister src);
1011 void pcmpeqw(XMMRegister dst, XMMRegister src);
1012
1013 void pcmpestri(XMMRegister dst, Address src, int imm8);
1014 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1015
1016 void pmovzxbw(XMMRegister dst, XMMRegister src);
1017 void pmovzxbw(XMMRegister dst, Address src);
1018
1019 void pmovmskb(Register dst, XMMRegister src);
1020
1021 void ptest(XMMRegister dst, XMMRegister src);
1022
1023 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1024 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1025 void sqrtsd(XMMRegister dst, AddressLiteral src);
1026
1027 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1028 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1029 void sqrtss(XMMRegister dst, AddressLiteral src);
1030
1031 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1032 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1033 void subsd(XMMRegister dst, AddressLiteral src);
1034
1035 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1036 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1037 void subss(XMMRegister dst, AddressLiteral src);
1038
1039 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1040 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1041 void ucomiss(XMMRegister dst, AddressLiteral src);
1042
1043 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1044 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1045 void ucomisd(XMMRegister dst, AddressLiteral src);
1046
1047 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1048 void xorpd(XMMRegister dst, XMMRegister src);
1049 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1050 void xorpd(XMMRegister dst, AddressLiteral src);
1051
1052 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1053 void xorps(XMMRegister dst, XMMRegister src);
1054 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1055 void xorps(XMMRegister dst, AddressLiteral src);
1056
1057 // Shuffle Bytes
1058 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1059 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1060 void pshufb(XMMRegister dst, AddressLiteral src);
1061 // AVX 3-operands instructions
1062
1063 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1064 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1065 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1066
1067 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1068 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1069 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1070
1071 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1072 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1073
1074 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1075 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1076
1077 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1078 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1079
1080 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1081
1082 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1083 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1084
1085 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1086 void vpmovmskb(Register dst, XMMRegister src);
1087
1088 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1089 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1090
1091 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1092 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1093
1094 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1095 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1096
1097 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1098 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1099
1100 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1101 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1102
1103 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1104 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1105
1106 void vptest(XMMRegister dst, XMMRegister src);
1107
1108 void punpcklbw(XMMRegister dst, XMMRegister src);
1109 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1110
1111 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1112 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1113
1114 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1115 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1116 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1117
1118 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1119 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1120 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1121
1122 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1123 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1124 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1125
1126 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1127 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1128 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1129
1130 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1131 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1132 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1133
1134 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1135 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1136 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1137
1138 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1139 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1140 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1141
1142 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1143 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1144 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1145
1146 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1147 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1148
1149 // AVX Vector instructions
1150
1151 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1152 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1153 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1154
1155 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1156 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1157 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1158
1159 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1160 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1161 Assembler::vpxor(dst, nds, src, vector_len);
1162 else
1163 Assembler::vxorpd(dst, nds, src, vector_len);
1164 }
1165 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1166 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1167 Assembler::vpxor(dst, nds, src, vector_len);
1168 else
1169 Assembler::vxorpd(dst, nds, src, vector_len);
1170 }
1171
1172 // Simple version for AVX2 256bit vectors
1173 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1174 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1175
1176 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
1177 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1178 if (UseAVX > 1) // vinserti128h is available only in AVX2
1179 Assembler::vinserti128h(dst, nds, src);
1180 else
1181 Assembler::vinsertf128h(dst, nds, src);
1182 }
1183
1184 // Carry-Less Multiplication Quadword
1185 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1186 // 0x00 - multiply lower 64 bits [0:63]
1187 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1188 }
1189 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1190 // 0x11 - multiply upper 64 bits [64:127]
1191 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1192 }
1193
1194 // Data
1195
1196 void cmov32( Condition cc, Register dst, Address src);
1197 void cmov32( Condition cc, Register dst, Register src);
1198
1199 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1200
1201 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1202 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1203
1204 void movoop(Register dst, jobject obj);
1205 void movoop(Address dst, jobject obj);
1206
1207 void mov_metadata(Register dst, Metadata* obj);
1208 void mov_metadata(Address dst, Metadata* obj);
1209
1210 void movptr(ArrayAddress dst, Register src);
1211 // can this do an lea?
1212 void movptr(Register dst, ArrayAddress src);
1213
1214 void movptr(Register dst, Address src);
1215
1216 #ifdef _LP64
1217 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1218 #else
1219 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1220 #endif
1221
1222 void movptr(Register dst, intptr_t src);
1223 void movptr(Register dst, Register src);
1224 void movptr(Address dst, intptr_t src);
1225
1226 void movptr(Address dst, Register src);
1227
1228 void movptr(Register dst, RegisterOrConstant src) {
1229 if (src.is_constant()) movptr(dst, src.as_constant());
1230 else movptr(dst, src.as_register());
1231 }
1232
1233 #ifdef _LP64
1234 // Generally the next two are only used for moving NULL
1235 // Although there are situations in initializing the mark word where
1236 // they could be used. They are dangerous.
1237
1238 // They only exist on LP64 so that int32_t and intptr_t are not the same
1239 // and we have ambiguous declarations.
1240
1241 void movptr(Address dst, int32_t imm32);
1242 void movptr(Register dst, int32_t imm32);
1243 #endif // _LP64
1244
1245 // to avoid hiding movl
1246 void mov32(AddressLiteral dst, Register src);
1247 void mov32(Register dst, AddressLiteral src);
1248
1249 // to avoid hiding movb
1250 void movbyte(ArrayAddress dst, int src);
1251
1252 // Import other mov() methods from the parent class or else
1253 // they will be hidden by the following overriding declaration.
1254 using Assembler::movdl;
1255 using Assembler::movq;
1256 void movdl(XMMRegister dst, AddressLiteral src);
1257 void movq(XMMRegister dst, AddressLiteral src);
1258
1259 // Can push value or effective address
1260 void pushptr(AddressLiteral src);
1261
1262 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1263 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1264
1265 void pushoop(jobject obj);
1266 void pushklass(Metadata* obj);
1267
1268 // sign extend as need a l to ptr sized element
1269 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1270 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1271
1272 // C2 compiled method's prolog code.
1273 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1274
1275 // clear memory of size 'cnt' qwords, starting at 'base'.
1276 void clear_mem(Register base, Register cnt, Register rtmp);
1277
1278 #ifdef COMPILER2
1279 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1280 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1281
1282 // IndexOf strings.
1283 // Small strings are loaded through stack if they cross page boundary.
1284 void string_indexof(Register str1, Register str2,
1285 Register cnt1, Register cnt2,
1286 int int_cnt2, Register result,
1287 XMMRegister vec, Register tmp,
1288 int ae);
1289
1290 // IndexOf for constant substrings with size >= 8 elements
1291 // which don't need to be loaded through stack.
1292 void string_indexofC8(Register str1, Register str2,
1293 Register cnt1, Register cnt2,
1294 int int_cnt2, Register result,
1295 XMMRegister vec, Register tmp,
1296 int ae);
1297
1298 // Smallest code: we don't need to load through stack,
1299 // check string tail.
1300
1301 // helper function for string_compare
1302 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1303 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1304 Address::ScaleFactor scale2, Register index, int ae);
1305 // Compare strings.
1306 void string_compare(Register str1, Register str2,
1307 Register cnt1, Register cnt2, Register result,
1308 XMMRegister vec1, int ae);
1309
1310 // Search for Non-ASCII character (Negative byte value) in a byte array,
1311 // return true if it has any and false otherwise.
1312 void has_negatives(Register ary1, Register len,
1313 Register result, Register tmp1,
1314 XMMRegister vec1, XMMRegister vec2);
1315
1316 // Compare char[] or byte[] arrays.
1317 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1318 Register limit, Register result, Register chr,
1319 XMMRegister vec1, XMMRegister vec2, bool is_char);
1320
1321 #endif
1322
1323 // Fill primitive arrays
1324 void generate_fill(BasicType t, bool aligned,
1325 Register to, Register value, Register count,
1326 Register rtmp, XMMRegister xtmp);
1327
1328 void encode_iso_array(Register src, Register dst, Register len,
1329 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1330 XMMRegister tmp4, Register tmp5, Register result);
1331
1332 #ifdef _LP64
1333 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1334 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1335 Register y, Register y_idx, Register z,
1336 Register carry, Register product,
1337 Register idx, Register kdx);
1338 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1339 Register yz_idx, Register idx,
1340 Register carry, Register product, int offset);
1341 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1342 Register carry, Register carry2,
1343 Register idx, Register jdx,
1344 Register yz_idx1, Register yz_idx2,
1345 Register tmp, Register tmp3, Register tmp4);
1346 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1347 Register yz_idx, Register idx, Register jdx,
1348 Register carry, Register product,
1349 Register carry2);
1350 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1351 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1352
1353 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1354 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1355 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1356 Register tmp2);
1357 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1358 Register rdxReg, Register raxReg);
1359 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1360 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1361 Register tmp3, Register tmp4);
1362 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1363 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1364
1365 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1366 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1367 Register raxReg);
1368 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1369 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1370 Register raxReg);
1371 #endif
1372
1373 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1374 void update_byte_crc32(Register crc, Register val, Register table);
1375 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1376 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1377 // Note on a naming convention:
1378 // Prefix w = register only used on a Westmere+ architecture
1379 // Prefix n = register only used on a Nehalem architecture
1380 #ifdef _LP64
1381 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1382 Register tmp1, Register tmp2, Register tmp3);
1383 #else
1384 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1385 Register tmp1, Register tmp2, Register tmp3,
1386 XMMRegister xtmp1, XMMRegister xtmp2);
1387 #endif
1388 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1389 Register in_out,
1390 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1391 XMMRegister w_xtmp2,
1392 Register tmp1,
1393 Register n_tmp2, Register n_tmp3);
1394 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1395 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1396 Register tmp1, Register tmp2,
1397 Register n_tmp3);
1398 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1399 Register in_out1, Register in_out2, Register in_out3,
1400 Register tmp1, Register tmp2, Register tmp3,
1401 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1402 Register tmp4, Register tmp5,
1403 Register n_tmp6);
1404 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1405 Register tmp1, Register tmp2, Register tmp3,
1406 Register tmp4, Register tmp5, Register tmp6,
1407 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1408 bool is_pclmulqdq_supported);
1409 // Fold 128-bit data chunk
1410 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1411 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1412 // Fold 8-bit data
1413 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1414 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1415
1416 // Compress char[] array to byte[].
1417 void char_array_compress(Register src, Register dst, Register len,
1418 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1419 XMMRegister tmp4, Register tmp5, Register result);
1420
1421 // Inflate byte[] array to char[].
1422 void byte_array_inflate(Register src, Register dst, Register len,
1423 XMMRegister tmp1, Register tmp2);
1424
1425 #undef VIRTUAL
1426
1427 };
1428
1429 /**
1430 * class SkipIfEqual:
1431 *
1432 * Instantiating this class will result in assembly code being output that will
1433 * jump around any code emitted between the creation of the instance and it's
1434 * automatic destruction at the end of a scope block, depending on the value of
1435 * the flag passed to the constructor, which will be checked at run-time.
1436 */
1437 class SkipIfEqual {
1438 private:
1439 MacroAssembler* _masm;
1440 Label _label;
1441
1442 public:
1443 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1444 ~SkipIfEqual();
1445 };
1446
1447 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP