1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 #define COMMA ,
52
53 virtual void call_VM_leaf_base(
54 address entry_point, // the entry point
55 int number_of_arguments // the number of arguments to pop after the call
56 );
57
58 // This is the base routine called by the different versions of call_VM. The interpreter
59 // may customize this version by overriding it for its purposes (e.g., to save/restore
60 // additional registers when doing a VM call).
61 //
62 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
63 // returns the register which contains the thread upon return. If a thread register has been
64 // specified, the return value will correspond to that register. If no last_java_sp is specified
65 // (noreg) than rsp will be used instead.
66 virtual void call_VM_base( // returns the register containing the thread upon return
67 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
68 Register java_thread, // the thread if computed before ; use noreg otherwise
69 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
70 address entry_point, // the entry point
71 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
72 bool check_exceptions // whether to check for pending exceptions after return
73 );
74
75 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
76 // The implementation is only non-empty for the InterpreterMacroAssembler,
77 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
78 virtual void check_and_handle_popframe(Register java_thread);
79 virtual void check_and_handle_earlyret(Register java_thread);
80
81 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
82
83 // helpers for FPU flag access
84 // tmp is a temporary register, if none is available use noreg
85 void save_rax (Register tmp);
86 void restore_rax(Register tmp);
87
88 public:
89 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
90
91 // Support for NULL-checks
92 //
93 // Generates code that causes a NULL OS exception if the content of reg is NULL.
94 // If the accessed location is M[reg + offset] and the offset is known, provide the
95 // offset. No explicit code generation is needed if the offset is within a certain
96 // range (0 <= offset <= page_size).
97
98 void null_check(Register reg, int offset = -1);
99 static bool needs_explicit_null_check(intptr_t offset);
100
101 // Required platform-specific helpers for Label::patch_instructions.
102 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
103 void pd_patch_instruction(address branch, address target) {
104 unsigned char op = branch[0];
105 assert(op == 0xE8 /* call */ ||
106 op == 0xE9 /* jmp */ ||
107 op == 0xEB /* short jmp */ ||
108 (op & 0xF0) == 0x70 /* short jcc */ ||
109 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
110 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
111 "Invalid opcode at patch point");
112
113 if (op == 0xEB || (op & 0xF0) == 0x70) {
114 // short offset operators (jmp and jcc)
115 char* disp = (char*) &branch[1];
116 int imm8 = target - (address) &disp[1];
117 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
118 *disp = imm8;
119 } else {
120 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
121 int imm32 = target - (address) &disp[1];
122 *disp = imm32;
123 }
124 }
125
126 // The following 4 methods return the offset of the appropriate move instruction
127
128 // Support for fast byte/short loading with zero extension (depending on particular CPU)
129 int load_unsigned_byte(Register dst, Address src);
130 int load_unsigned_short(Register dst, Address src);
131
132 // Support for fast byte/short loading with sign extension (depending on particular CPU)
133 int load_signed_byte(Register dst, Address src);
134 int load_signed_short(Register dst, Address src);
135
136 // Support for sign-extension (hi:lo = extend_sign(lo))
137 void extend_sign(Register hi, Register lo);
138
139 // Load and store values by size and signed-ness
140 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
141 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
142
143 // Support for inc/dec with optimal instruction selection depending on value
144
145 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
146 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
147
148 void decrementl(Address dst, int value = 1);
149 void decrementl(Register reg, int value = 1);
150
151 void decrementq(Register reg, int value = 1);
152 void decrementq(Address dst, int value = 1);
153
154 void incrementl(Address dst, int value = 1);
155 void incrementl(Register reg, int value = 1);
156
157 void incrementq(Register reg, int value = 1);
158 void incrementq(Address dst, int value = 1);
159
160 // Support optimal SSE move instructions.
161 void movflt(XMMRegister dst, XMMRegister src) {
162 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
163 else { movss (dst, src); return; }
164 }
165 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
166 void movflt(XMMRegister dst, AddressLiteral src);
167 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
168
169 void movdbl(XMMRegister dst, XMMRegister src) {
170 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
171 else { movsd (dst, src); return; }
172 }
173
174 void movdbl(XMMRegister dst, AddressLiteral src);
175
176 void movdbl(XMMRegister dst, Address src) {
177 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
178 else { movlpd(dst, src); return; }
179 }
180 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
181
182 void incrementl(AddressLiteral dst);
183 void incrementl(ArrayAddress dst);
184
185 void incrementq(AddressLiteral dst);
186
187 // Alignment
188 void align(int modulus);
189 void align(int modulus, int target);
190
191 // A 5 byte nop that is safe for patching (see patch_verified_entry)
192 void fat_nop();
193
194 // Stack frame creation/removal
195 void enter();
196 void leave();
197
198 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
199 // The pointer will be loaded into the thread register.
200 void get_thread(Register thread);
201
202
203 // Support for VM calls
204 //
205 // It is imperative that all calls into the VM are handled via the call_VM macros.
206 // They make sure that the stack linkage is setup correctly. call_VM's correspond
207 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
208
209
210 void call_VM(Register oop_result,
211 address entry_point,
212 bool check_exceptions = true);
213 void call_VM(Register oop_result,
214 address entry_point,
215 Register arg_1,
216 bool check_exceptions = true);
217 void call_VM(Register oop_result,
218 address entry_point,
219 Register arg_1, Register arg_2,
220 bool check_exceptions = true);
221 void call_VM(Register oop_result,
222 address entry_point,
223 Register arg_1, Register arg_2, Register arg_3,
224 bool check_exceptions = true);
225
226 // Overloadings with last_Java_sp
227 void call_VM(Register oop_result,
228 Register last_java_sp,
229 address entry_point,
230 int number_of_arguments = 0,
231 bool check_exceptions = true);
232 void call_VM(Register oop_result,
233 Register last_java_sp,
234 address entry_point,
235 Register arg_1, bool
236 check_exceptions = true);
237 void call_VM(Register oop_result,
238 Register last_java_sp,
239 address entry_point,
240 Register arg_1, Register arg_2,
241 bool check_exceptions = true);
242 void call_VM(Register oop_result,
243 Register last_java_sp,
244 address entry_point,
245 Register arg_1, Register arg_2, Register arg_3,
246 bool check_exceptions = true);
247
248 void get_vm_result (Register oop_result, Register thread);
249 void get_vm_result_2(Register metadata_result, Register thread);
250
251 // These always tightly bind to MacroAssembler::call_VM_base
252 // bypassing the virtual implementation
253 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
254 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
255 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
258
259 void call_VM_leaf(address entry_point,
260 int number_of_arguments = 0);
261 void call_VM_leaf(address entry_point,
262 Register arg_1);
263 void call_VM_leaf(address entry_point,
264 Register arg_1, Register arg_2);
265 void call_VM_leaf(address entry_point,
266 Register arg_1, Register arg_2, Register arg_3);
267
268 // These always tightly bind to MacroAssembler::call_VM_leaf_base
269 // bypassing the virtual implementation
270 void super_call_VM_leaf(address entry_point);
271 void super_call_VM_leaf(address entry_point, Register arg_1);
272 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
273 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
274 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
275
276 // last Java Frame (fills frame anchor)
277 void set_last_Java_frame(Register thread,
278 Register last_java_sp,
279 Register last_java_fp,
280 address last_java_pc);
281
282 // thread in the default location (r15_thread on 64bit)
283 void set_last_Java_frame(Register last_java_sp,
284 Register last_java_fp,
285 address last_java_pc);
286
287 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
288
289 // thread in the default location (r15_thread on 64bit)
290 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
291
292 // Stores
293 void store_check(Register obj); // store check for obj - register is destroyed afterwards
294 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
295
296 #if INCLUDE_ALL_GCS
297
298 void g1_write_barrier_pre(Register obj,
299 Register pre_val,
300 Register thread,
301 Register tmp,
302 bool tosca_live,
303 bool expand_call);
304
305 void g1_write_barrier_post(Register store_addr,
306 Register new_val,
307 Register thread,
308 Register tmp,
309 Register tmp2);
310
311 #endif // INCLUDE_ALL_GCS
312
313 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
314 void c2bool(Register x);
315
316 // C++ bool manipulation
317
318 void movbool(Register dst, Address src);
319 void movbool(Address dst, bool boolconst);
320 void movbool(Address dst, Register src);
321 void testbool(Register dst);
322
323 // oop manipulations
324 void load_klass(Register dst, Register src);
325 void store_klass(Register dst, Register src);
326
327 void load_heap_oop(Register dst, Address src);
328 void load_heap_oop_not_null(Register dst, Address src);
329 void store_heap_oop(Address dst, Register src);
330 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
331
332 // Used for storing NULL. All other oop constants should be
333 // stored using routines that take a jobject.
334 void store_heap_oop_null(Address dst);
335
336 void load_prototype_header(Register dst, Register src);
337
338 #ifdef _LP64
339 void store_klass_gap(Register dst, Register src);
340
341 // This dummy is to prevent a call to store_heap_oop from
342 // converting a zero (like NULL) into a Register by giving
343 // the compiler two choices it can't resolve
344
345 void store_heap_oop(Address dst, void* dummy);
346
347 void encode_heap_oop(Register r);
348 void decode_heap_oop(Register r);
349 void encode_heap_oop_not_null(Register r);
350 void decode_heap_oop_not_null(Register r);
351 void encode_heap_oop_not_null(Register dst, Register src);
352 void decode_heap_oop_not_null(Register dst, Register src);
353
354 void set_narrow_oop(Register dst, jobject obj);
355 void set_narrow_oop(Address dst, jobject obj);
356 void cmp_narrow_oop(Register dst, jobject obj);
357 void cmp_narrow_oop(Address dst, jobject obj);
358
359 void encode_klass_not_null(Register r);
360 void decode_klass_not_null(Register r);
361 void encode_klass_not_null(Register dst, Register src);
362 void decode_klass_not_null(Register dst, Register src);
363 void set_narrow_klass(Register dst, Klass* k);
364 void set_narrow_klass(Address dst, Klass* k);
365 void cmp_narrow_klass(Register dst, Klass* k);
366 void cmp_narrow_klass(Address dst, Klass* k);
367
368 // Returns the byte size of the instructions generated by decode_klass_not_null()
369 // when compressed klass pointers are being used.
370 static int instr_size_for_decode_klass_not_null();
371
372 // if heap base register is used - reinit it with the correct value
373 void reinit_heapbase();
374
375 DEBUG_ONLY(void verify_heapbase(const char* msg);)
376
377 #endif // _LP64
378
379 // Int division/remainder for Java
380 // (as idivl, but checks for special case as described in JVM spec.)
381 // returns idivl instruction offset for implicit exception handling
382 int corrected_idivl(Register reg);
383
384 // Long division/remainder for Java
385 // (as idivq, but checks for special case as described in JVM spec.)
386 // returns idivq instruction offset for implicit exception handling
387 int corrected_idivq(Register reg);
388
389 void int3();
390
391 // Long operation macros for a 32bit cpu
392 // Long negation for Java
393 void lneg(Register hi, Register lo);
394
395 // Long multiplication for Java
396 // (destroys contents of eax, ebx, ecx and edx)
397 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
398
399 // Long shifts for Java
400 // (semantics as described in JVM spec.)
401 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
402 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
403
404 // Long compare for Java
405 // (semantics as described in JVM spec.)
406 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
407
408
409 // misc
410
411 // Sign extension
412 void sign_extend_short(Register reg);
413 void sign_extend_byte(Register reg);
414
415 // Division by power of 2, rounding towards 0
416 void division_with_shift(Register reg, int shift_value);
417
418 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
419 //
420 // CF (corresponds to C0) if x < y
421 // PF (corresponds to C2) if unordered
422 // ZF (corresponds to C3) if x = y
423 //
424 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
425 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
426 void fcmp(Register tmp);
427 // Variant of the above which allows y to be further down the stack
428 // and which only pops x and y if specified. If pop_right is
429 // specified then pop_left must also be specified.
430 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
431
432 // Floating-point comparison for Java
433 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
434 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
435 // (semantics as described in JVM spec.)
436 void fcmp2int(Register dst, bool unordered_is_less);
437 // Variant of the above which allows y to be further down the stack
438 // and which only pops x and y if specified. If pop_right is
439 // specified then pop_left must also be specified.
440 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
441
442 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
443 // tmp is a temporary register, if none is available use noreg
444 void fremr(Register tmp);
445
446
447 // same as fcmp2int, but using SSE2
448 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
449 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
450
451 // Inlined sin/cos generator for Java; must not use CPU instruction
452 // directly on Intel as it does not have high enough precision
453 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
454 // number of FPU stack slots in use; all but the topmost will
455 // require saving if a slow case is necessary. Assumes argument is
456 // on FP TOS; result is on FP TOS. No cpu registers are changed by
457 // this code.
458 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
459
460 // branch to L if FPU flag C2 is set/not set
461 // tmp is a temporary register, if none is available use noreg
462 void jC2 (Register tmp, Label& L);
463 void jnC2(Register tmp, Label& L);
464
465 // Pop ST (ffree & fincstp combined)
466 void fpop();
467
468 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
469 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
470 void load_float(Address src);
471
472 // Store float value to 'address'. If UseSSE >= 1, the value is stored
473 // from register xmm0. Otherwise, the value is stored from the FPU stack.
474 void store_float(Address dst);
475
476 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
477 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
478 void load_double(Address src);
479
480 // Store double value to 'address'. If UseSSE >= 2, the value is stored
481 // from register xmm0. Otherwise, the value is stored from the FPU stack.
482 void store_double(Address dst);
483
484 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
485 void push_fTOS();
486
487 // pops double TOS element from CPU stack and pushes on FPU stack
488 void pop_fTOS();
489
490 void empty_FPU_stack();
491
492 void push_IU_state();
493 void pop_IU_state();
494
495 void push_FPU_state();
496 void pop_FPU_state();
497
498 void push_CPU_state();
499 void pop_CPU_state();
500
501 // Round up to a power of two
502 void round_to(Register reg, int modulus);
503
504 // Callee saved registers handling
505 void push_callee_saved_registers();
506 void pop_callee_saved_registers();
507
508 // allocation
509 void eden_allocate(
510 Register obj, // result: pointer to object after successful allocation
511 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
512 int con_size_in_bytes, // object size in bytes if known at compile time
513 Register t1, // temp register
514 Label& slow_case // continuation point if fast allocation fails
515 );
516 void tlab_allocate(
517 Register obj, // result: pointer to object after successful allocation
518 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
519 int con_size_in_bytes, // object size in bytes if known at compile time
520 Register t1, // temp register
521 Register t2, // temp register
522 Label& slow_case // continuation point if fast allocation fails
523 );
524 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
525 void incr_allocated_bytes(Register thread,
526 Register var_size_in_bytes, int con_size_in_bytes,
527 Register t1 = noreg);
528
529 // interface method calling
530 void lookup_interface_method(Register recv_klass,
531 Register intf_klass,
532 RegisterOrConstant itable_index,
533 Register method_result,
534 Register scan_temp,
535 Label& no_such_interface);
536
537 // virtual method calling
538 void lookup_virtual_method(Register recv_klass,
539 RegisterOrConstant vtable_index,
540 Register method_result);
541
542 // Test sub_klass against super_klass, with fast and slow paths.
543
544 // The fast path produces a tri-state answer: yes / no / maybe-slow.
545 // One of the three labels can be NULL, meaning take the fall-through.
546 // If super_check_offset is -1, the value is loaded up from super_klass.
547 // No registers are killed, except temp_reg.
548 void check_klass_subtype_fast_path(Register sub_klass,
549 Register super_klass,
550 Register temp_reg,
551 Label* L_success,
552 Label* L_failure,
553 Label* L_slow_path,
554 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
555
556 // The rest of the type check; must be wired to a corresponding fast path.
557 // It does not repeat the fast path logic, so don't use it standalone.
558 // The temp_reg and temp2_reg can be noreg, if no temps are available.
559 // Updates the sub's secondary super cache as necessary.
560 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
561 void check_klass_subtype_slow_path(Register sub_klass,
562 Register super_klass,
563 Register temp_reg,
564 Register temp2_reg,
565 Label* L_success,
566 Label* L_failure,
567 bool set_cond_codes = false);
568
569 // Simplified, combined version, good for typical uses.
570 // Falls through on failure.
571 void check_klass_subtype(Register sub_klass,
572 Register super_klass,
573 Register temp_reg,
574 Label& L_success);
575
576 // method handles (JSR 292)
577 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
578
579 //----
580 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
581
582 // Debugging
583
584 // only if +VerifyOops
585 // TODO: Make these macros with file and line like sparc version!
586 void verify_oop(Register reg, const char* s = "broken oop");
587 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
588
589 // TODO: verify method and klass metadata (compare against vptr?)
590 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
591 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
592
593 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
594 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
595
596 // only if +VerifyFPU
597 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
598
599 // Verify or restore cpu control state after JNI call
600 void restore_cpu_control_state_after_jni();
601
602 // prints msg, dumps registers and stops execution
603 void stop(const char* msg);
604
605 // prints msg and continues
606 void warn(const char* msg);
607
608 // dumps registers and other state
609 void print_state();
610
611 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
612 static void debug64(char* msg, int64_t pc, int64_t regs[]);
613 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
614 static void print_state64(int64_t pc, int64_t regs[]);
615
616 void os_breakpoint();
617
618 void untested() { stop("untested"); }
619
620 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
621
622 void should_not_reach_here() { stop("should not reach here"); }
623
624 void print_CPU_state();
625
626 // Stack overflow checking
627 void bang_stack_with_offset(int offset) {
628 // stack grows down, caller passes positive offset
629 assert(offset > 0, "must bang with negative offset");
630 movl(Address(rsp, (-offset)), rax);
631 }
632
633 // Writes to stack successive pages until offset reached to check for
634 // stack overflow + shadow pages. Also, clobbers tmp
635 void bang_stack_size(Register size, Register tmp);
636
637 // Check for reserved stack access in method being exited (for JIT)
638 void reserved_stack_check();
639
640 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
641 Register tmp,
642 int offset);
643
644 // Support for serializing memory accesses between threads
645 void serialize_memory(Register thread, Register tmp);
646
647 void verify_tlab();
648
649 // Biased locking support
650 // lock_reg and obj_reg must be loaded up with the appropriate values.
651 // swap_reg must be rax, and is killed.
652 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
653 // be killed; if not supplied, push/pop will be used internally to
654 // allocate a temporary (inefficient, avoid if possible).
655 // Optional slow case is for implementations (interpreter and C1) which branch to
656 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
657 // Returns offset of first potentially-faulting instruction for null
658 // check info (currently consumed only by C1). If
659 // swap_reg_contains_mark is true then returns -1 as it is assumed
660 // the calling code has already passed any potential faults.
661 int biased_locking_enter(Register lock_reg, Register obj_reg,
662 Register swap_reg, Register tmp_reg,
663 bool swap_reg_contains_mark,
664 Label& done, Label* slow_case = NULL,
665 BiasedLockingCounters* counters = NULL);
666 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
667 #ifdef COMPILER2
668 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
669 // See full desription in macroAssembler_x86.cpp.
670 void fast_lock(Register obj, Register box, Register tmp,
671 Register scr, Register cx1, Register cx2,
672 BiasedLockingCounters* counters,
673 RTMLockingCounters* rtm_counters,
674 RTMLockingCounters* stack_rtm_counters,
675 Metadata* method_data,
676 bool use_rtm, bool profile_rtm);
677 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
678 #if INCLUDE_RTM_OPT
679 void rtm_counters_update(Register abort_status, Register rtm_counters);
680 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
681 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
682 RTMLockingCounters* rtm_counters,
683 Metadata* method_data);
684 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
685 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
686 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
687 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
688 void rtm_stack_locking(Register obj, Register tmp, Register scr,
689 Register retry_on_abort_count,
690 RTMLockingCounters* stack_rtm_counters,
691 Metadata* method_data, bool profile_rtm,
692 Label& DONE_LABEL, Label& IsInflated);
693 void rtm_inflated_locking(Register obj, Register box, Register tmp,
694 Register scr, Register retry_on_busy_count,
695 Register retry_on_abort_count,
696 RTMLockingCounters* rtm_counters,
697 Metadata* method_data, bool profile_rtm,
698 Label& DONE_LABEL);
699 #endif
700 #endif
701
702 Condition negate_condition(Condition cond);
703
704 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
705 // operands. In general the names are modified to avoid hiding the instruction in Assembler
706 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
707 // here in MacroAssembler. The major exception to this rule is call
708
709 // Arithmetics
710
711
712 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
713 void addptr(Address dst, Register src);
714
715 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
716 void addptr(Register dst, int32_t src);
717 void addptr(Register dst, Register src);
718 void addptr(Register dst, RegisterOrConstant src) {
719 if (src.is_constant()) addptr(dst, (int) src.as_constant());
720 else addptr(dst, src.as_register());
721 }
722
723 void andptr(Register dst, int32_t src);
724 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
725
726 void cmp8(AddressLiteral src1, int imm);
727
728 // renamed to drag out the casting of address to int32_t/intptr_t
729 void cmp32(Register src1, int32_t imm);
730
731 void cmp32(AddressLiteral src1, int32_t imm);
732 // compare reg - mem, or reg - &mem
733 void cmp32(Register src1, AddressLiteral src2);
734
735 void cmp32(Register src1, Address src2);
736
737 #ifndef _LP64
738 void cmpklass(Address dst, Metadata* obj);
739 void cmpklass(Register dst, Metadata* obj);
740 void cmpoop(Address dst, jobject obj);
741 void cmpoop(Register dst, jobject obj);
742 #endif // _LP64
743
744 // NOTE src2 must be the lval. This is NOT an mem-mem compare
745 void cmpptr(Address src1, AddressLiteral src2);
746
747 void cmpptr(Register src1, AddressLiteral src2);
748
749 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
750 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
751 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
752
753 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
754 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
755
756 // cmp64 to avoild hiding cmpq
757 void cmp64(Register src1, AddressLiteral src);
758
759 void cmpxchgptr(Register reg, Address adr);
760
761 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
762
763
764 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
765 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
766
767
768 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
769
770 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
771
772 void shlptr(Register dst, int32_t shift);
773 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
774
775 void shrptr(Register dst, int32_t shift);
776 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
777
778 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
779 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
780
781 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
782
783 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
784 void subptr(Register dst, int32_t src);
785 // Force generation of a 4 byte immediate value even if it fits into 8bit
786 void subptr_imm32(Register dst, int32_t src);
787 void subptr(Register dst, Register src);
788 void subptr(Register dst, RegisterOrConstant src) {
789 if (src.is_constant()) subptr(dst, (int) src.as_constant());
790 else subptr(dst, src.as_register());
791 }
792
793 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
794 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
795
796 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
797 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
798
799 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
800
801
802
803 // Helper functions for statistics gathering.
804 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
805 void cond_inc32(Condition cond, AddressLiteral counter_addr);
806 // Unconditional atomic increment.
807 void atomic_incl(Address counter_addr);
808 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
809 #ifdef _LP64
810 void atomic_incq(Address counter_addr);
811 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
812 #endif
813 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
814 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
815
816 void lea(Register dst, AddressLiteral adr);
817 void lea(Address dst, AddressLiteral adr);
818 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
819
820 void leal32(Register dst, Address src) { leal(dst, src); }
821
822 // Import other testl() methods from the parent class or else
823 // they will be hidden by the following overriding declaration.
824 using Assembler::testl;
825 void testl(Register dst, AddressLiteral src);
826
827 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
828 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
829 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
830 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
831
832 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
833 void testptr(Register src1, Register src2);
834
835 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
836 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
837
838 // Calls
839
840 void call(Label& L, relocInfo::relocType rtype);
841 void call(Register entry);
842
843 // NOTE: this call tranfers to the effective address of entry NOT
844 // the address contained by entry. This is because this is more natural
845 // for jumps/calls.
846 void call(AddressLiteral entry);
847
848 // Emit the CompiledIC call idiom
849 void ic_call(address entry);
850
851 // Jumps
852
853 // NOTE: these jumps tranfer to the effective address of dst NOT
854 // the address contained by dst. This is because this is more natural
855 // for jumps/calls.
856 void jump(AddressLiteral dst);
857 void jump_cc(Condition cc, AddressLiteral dst);
858
859 // 32bit can do a case table jump in one instruction but we no longer allow the base
860 // to be installed in the Address class. This jump will tranfers to the address
861 // contained in the location described by entry (not the address of entry)
862 void jump(ArrayAddress entry);
863
864 // Floating
865
866 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
867 void andpd(XMMRegister dst, AddressLiteral src);
868
869 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
870 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
871 void andps(XMMRegister dst, AddressLiteral src);
872
873 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
874 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
875 void comiss(XMMRegister dst, AddressLiteral src);
876
877 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
878 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
879 void comisd(XMMRegister dst, AddressLiteral src);
880
881 void fadd_s(Address src) { Assembler::fadd_s(src); }
882 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
883
884 void fldcw(Address src) { Assembler::fldcw(src); }
885 void fldcw(AddressLiteral src);
886
887 void fld_s(int index) { Assembler::fld_s(index); }
888 void fld_s(Address src) { Assembler::fld_s(src); }
889 void fld_s(AddressLiteral src);
890
891 void fld_d(Address src) { Assembler::fld_d(src); }
892 void fld_d(AddressLiteral src);
893
894 void fld_x(Address src) { Assembler::fld_x(src); }
895 void fld_x(AddressLiteral src);
896
897 void fmul_s(Address src) { Assembler::fmul_s(src); }
898 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
899
900 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
901 void ldmxcsr(AddressLiteral src);
902
903 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
904 // all corner cases and may result in NaN and require fallback to a
905 // runtime call.
906 void fast_pow();
907 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
908 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
909 Register rax, Register rcx, Register rdx, Register tmp);
910
911 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
912 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
913 Register rax, Register rcx, Register rdx, Register tmp1 LP64_ONLY(COMMA Register tmp2));
914
915 void increase_precision();
916 void restore_precision();
917
918 // computes pow(x,y). Fallback to runtime call included.
919 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(num_fpu_regs_in_use); }
920
921 private:
922
923 // call runtime as a fallback for trig functions and pow/exp.
924 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
925
926 // computes 2^(Ylog2X); Ylog2X in ST(0)
927 void pow_exp_core_encoding();
928
929 // computes pow(x,y) or exp(x). Fallback to runtime call included.
930 void pow_or_exp(int num_fpu_regs_in_use);
931
932 // these are private because users should be doing movflt/movdbl
933
934 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
935 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
936 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
937 void movss(XMMRegister dst, AddressLiteral src);
938
939 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
940 void movlpd(XMMRegister dst, AddressLiteral src);
941
942 public:
943
944 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
945 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
946 void addsd(XMMRegister dst, AddressLiteral src);
947
948 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
949 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
950 void addss(XMMRegister dst, AddressLiteral src);
951
952 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
953 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
954 void divsd(XMMRegister dst, AddressLiteral src);
955
956 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
957 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
958 void divss(XMMRegister dst, AddressLiteral src);
959
960 // Move Unaligned Double Quadword
961 void movdqu(Address dst, XMMRegister src);
962 void movdqu(XMMRegister dst, Address src);
963 void movdqu(XMMRegister dst, XMMRegister src);
964 void movdqu(XMMRegister dst, AddressLiteral src);
965 // AVX Unaligned forms
966 void vmovdqu(Address dst, XMMRegister src);
967 void vmovdqu(XMMRegister dst, Address src);
968 void vmovdqu(XMMRegister dst, XMMRegister src);
969 void vmovdqu(XMMRegister dst, AddressLiteral src);
970
971 // Move Aligned Double Quadword
972 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
973 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
974 void movdqa(XMMRegister dst, AddressLiteral src);
975
976 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
977 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
978 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
979 void movsd(XMMRegister dst, AddressLiteral src);
980
981 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
982 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
983 void mulpd(XMMRegister dst, AddressLiteral src);
984
985 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
986 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
987 void mulsd(XMMRegister dst, AddressLiteral src);
988
989 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
990 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
991 void mulss(XMMRegister dst, AddressLiteral src);
992
993 // Carry-Less Multiplication Quadword
994 void pclmulldq(XMMRegister dst, XMMRegister src) {
995 // 0x00 - multiply lower 64 bits [0:63]
996 Assembler::pclmulqdq(dst, src, 0x00);
997 }
998 void pclmulhdq(XMMRegister dst, XMMRegister src) {
999 // 0x11 - multiply upper 64 bits [64:127]
1000 Assembler::pclmulqdq(dst, src, 0x11);
1001 }
1002
1003 void pcmpeqb(XMMRegister dst, XMMRegister src);
1004 void pcmpeqw(XMMRegister dst, XMMRegister src);
1005
1006 void pcmpestri(XMMRegister dst, Address src, int imm8);
1007 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1008
1009 void pmovzxbw(XMMRegister dst, XMMRegister src);
1010 void pmovzxbw(XMMRegister dst, Address src);
1011
1012 void pmovmskb(Register dst, XMMRegister src);
1013
1014 void ptest(XMMRegister dst, XMMRegister src);
1015
1016 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1017 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1018 void sqrtsd(XMMRegister dst, AddressLiteral src);
1019
1020 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1021 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1022 void sqrtss(XMMRegister dst, AddressLiteral src);
1023
1024 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1025 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1026 void subsd(XMMRegister dst, AddressLiteral src);
1027
1028 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1029 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1030 void subss(XMMRegister dst, AddressLiteral src);
1031
1032 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1033 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1034 void ucomiss(XMMRegister dst, AddressLiteral src);
1035
1036 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1037 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1038 void ucomisd(XMMRegister dst, AddressLiteral src);
1039
1040 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1041 void xorpd(XMMRegister dst, XMMRegister src);
1042 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1043 void xorpd(XMMRegister dst, AddressLiteral src);
1044
1045 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1046 void xorps(XMMRegister dst, XMMRegister src);
1047 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1048 void xorps(XMMRegister dst, AddressLiteral src);
1049
1050 // Shuffle Bytes
1051 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1052 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1053 void pshufb(XMMRegister dst, AddressLiteral src);
1054 // AVX 3-operands instructions
1055
1056 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1057 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1058 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1059
1060 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1061 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1062 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1063
1064 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1065 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1066
1067 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1068 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1069
1070 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1071 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1072
1073 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1074
1075 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1076 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1077
1078 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1079 void vpmovmskb(Register dst, XMMRegister src);
1080
1081 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1082 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1083
1084 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1085 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1086
1087 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1088 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1089
1090 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1091 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1092
1093 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1094 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1095
1096 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1097 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1098
1099 void vptest(XMMRegister dst, XMMRegister src);
1100
1101 void punpcklbw(XMMRegister dst, XMMRegister src);
1102 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1103
1104 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1105 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1106
1107 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1108 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1109 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1110
1111 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1112 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1113 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1114
1115 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1116 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1117 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1118
1119 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1120 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1121 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1122
1123 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1124 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1125 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1126
1127 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1128 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1129 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1130
1131 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1132 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1133 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1134
1135 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1136 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1137 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1138
1139 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1140 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1141
1142 // AVX Vector instructions
1143
1144 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1145 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1146 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1147
1148 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1149 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1150 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1151
1152 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1153 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1154 Assembler::vpxor(dst, nds, src, vector_len);
1155 else
1156 Assembler::vxorpd(dst, nds, src, vector_len);
1157 }
1158 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1159 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1160 Assembler::vpxor(dst, nds, src, vector_len);
1161 else
1162 Assembler::vxorpd(dst, nds, src, vector_len);
1163 }
1164
1165 // Simple version for AVX2 256bit vectors
1166 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1167 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1168
1169 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
1170 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1171 if (UseAVX > 1) // vinserti128h is available only in AVX2
1172 Assembler::vinserti128h(dst, nds, src);
1173 else
1174 Assembler::vinsertf128h(dst, nds, src);
1175 }
1176
1177 // Carry-Less Multiplication Quadword
1178 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1179 // 0x00 - multiply lower 64 bits [0:63]
1180 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1181 }
1182 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1183 // 0x11 - multiply upper 64 bits [64:127]
1184 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1185 }
1186
1187 // Data
1188
1189 void cmov32( Condition cc, Register dst, Address src);
1190 void cmov32( Condition cc, Register dst, Register src);
1191
1192 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1193
1194 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1195 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1196
1197 void movoop(Register dst, jobject obj);
1198 void movoop(Address dst, jobject obj);
1199
1200 void mov_metadata(Register dst, Metadata* obj);
1201 void mov_metadata(Address dst, Metadata* obj);
1202
1203 void movptr(ArrayAddress dst, Register src);
1204 // can this do an lea?
1205 void movptr(Register dst, ArrayAddress src);
1206
1207 void movptr(Register dst, Address src);
1208
1209 #ifdef _LP64
1210 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1211 #else
1212 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1213 #endif
1214
1215 void movptr(Register dst, intptr_t src);
1216 void movptr(Register dst, Register src);
1217 void movptr(Address dst, intptr_t src);
1218
1219 void movptr(Address dst, Register src);
1220
1221 void movptr(Register dst, RegisterOrConstant src) {
1222 if (src.is_constant()) movptr(dst, src.as_constant());
1223 else movptr(dst, src.as_register());
1224 }
1225
1226 #ifdef _LP64
1227 // Generally the next two are only used for moving NULL
1228 // Although there are situations in initializing the mark word where
1229 // they could be used. They are dangerous.
1230
1231 // They only exist on LP64 so that int32_t and intptr_t are not the same
1232 // and we have ambiguous declarations.
1233
1234 void movptr(Address dst, int32_t imm32);
1235 void movptr(Register dst, int32_t imm32);
1236 #endif // _LP64
1237
1238 // to avoid hiding movl
1239 void mov32(AddressLiteral dst, Register src);
1240 void mov32(Register dst, AddressLiteral src);
1241
1242 // to avoid hiding movb
1243 void movbyte(ArrayAddress dst, int src);
1244
1245 // Import other mov() methods from the parent class or else
1246 // they will be hidden by the following overriding declaration.
1247 using Assembler::movdl;
1248 using Assembler::movq;
1249 void movdl(XMMRegister dst, AddressLiteral src);
1250 void movq(XMMRegister dst, AddressLiteral src);
1251
1252 // Can push value or effective address
1253 void pushptr(AddressLiteral src);
1254
1255 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1256 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1257
1258 void pushoop(jobject obj);
1259 void pushklass(Metadata* obj);
1260
1261 // sign extend as need a l to ptr sized element
1262 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1263 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1264
1265 // C2 compiled method's prolog code.
1266 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1267
1268 // clear memory of size 'cnt' qwords, starting at 'base'.
1269 void clear_mem(Register base, Register cnt, Register rtmp);
1270
1271 #ifdef COMPILER2
1272 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1273 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1274
1275 // IndexOf strings.
1276 // Small strings are loaded through stack if they cross page boundary.
1277 void string_indexof(Register str1, Register str2,
1278 Register cnt1, Register cnt2,
1279 int int_cnt2, Register result,
1280 XMMRegister vec, Register tmp,
1281 int ae);
1282
1283 // IndexOf for constant substrings with size >= 8 elements
1284 // which don't need to be loaded through stack.
1285 void string_indexofC8(Register str1, Register str2,
1286 Register cnt1, Register cnt2,
1287 int int_cnt2, Register result,
1288 XMMRegister vec, Register tmp,
1289 int ae);
1290
1291 // Smallest code: we don't need to load through stack,
1292 // check string tail.
1293
1294 // helper function for string_compare
1295 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1296 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1297 Address::ScaleFactor scale2, Register index, int ae);
1298 // Compare strings.
1299 void string_compare(Register str1, Register str2,
1300 Register cnt1, Register cnt2, Register result,
1301 XMMRegister vec1, int ae);
1302
1303 // Search for Non-ASCII character (Negative byte value) in a byte array,
1304 // return true if it has any and false otherwise.
1305 void has_negatives(Register ary1, Register len,
1306 Register result, Register tmp1,
1307 XMMRegister vec1, XMMRegister vec2);
1308
1309 // Compare char[] or byte[] arrays.
1310 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1311 Register limit, Register result, Register chr,
1312 XMMRegister vec1, XMMRegister vec2, bool is_char);
1313
1314 #endif
1315
1316 // Fill primitive arrays
1317 void generate_fill(BasicType t, bool aligned,
1318 Register to, Register value, Register count,
1319 Register rtmp, XMMRegister xtmp);
1320
1321 void encode_iso_array(Register src, Register dst, Register len,
1322 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1323 XMMRegister tmp4, Register tmp5, Register result);
1324
1325 #ifdef _LP64
1326 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1327 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1328 Register y, Register y_idx, Register z,
1329 Register carry, Register product,
1330 Register idx, Register kdx);
1331 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1332 Register yz_idx, Register idx,
1333 Register carry, Register product, int offset);
1334 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1335 Register carry, Register carry2,
1336 Register idx, Register jdx,
1337 Register yz_idx1, Register yz_idx2,
1338 Register tmp, Register tmp3, Register tmp4);
1339 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1340 Register yz_idx, Register idx, Register jdx,
1341 Register carry, Register product,
1342 Register carry2);
1343 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1344 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1345
1346 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1347 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1348 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1349 Register tmp2);
1350 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1351 Register rdxReg, Register raxReg);
1352 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1353 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1354 Register tmp3, Register tmp4);
1355 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1356 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1357
1358 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1359 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1360 Register raxReg);
1361 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1362 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1363 Register raxReg);
1364 #endif
1365
1366 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1367 void update_byte_crc32(Register crc, Register val, Register table);
1368 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1369 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1370 // Note on a naming convention:
1371 // Prefix w = register only used on a Westmere+ architecture
1372 // Prefix n = register only used on a Nehalem architecture
1373 #ifdef _LP64
1374 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1375 Register tmp1, Register tmp2, Register tmp3);
1376 #else
1377 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1378 Register tmp1, Register tmp2, Register tmp3,
1379 XMMRegister xtmp1, XMMRegister xtmp2);
1380 #endif
1381 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1382 Register in_out,
1383 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1384 XMMRegister w_xtmp2,
1385 Register tmp1,
1386 Register n_tmp2, Register n_tmp3);
1387 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1388 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1389 Register tmp1, Register tmp2,
1390 Register n_tmp3);
1391 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1392 Register in_out1, Register in_out2, Register in_out3,
1393 Register tmp1, Register tmp2, Register tmp3,
1394 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1395 Register tmp4, Register tmp5,
1396 Register n_tmp6);
1397 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1398 Register tmp1, Register tmp2, Register tmp3,
1399 Register tmp4, Register tmp5, Register tmp6,
1400 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1401 bool is_pclmulqdq_supported);
1402 // Fold 128-bit data chunk
1403 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1404 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1405 // Fold 8-bit data
1406 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1407 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1408
1409 // Compress char[] array to byte[].
1410 void char_array_compress(Register src, Register dst, Register len,
1411 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1412 XMMRegister tmp4, Register tmp5, Register result);
1413
1414 // Inflate byte[] array to char[].
1415 void byte_array_inflate(Register src, Register dst, Register len,
1416 XMMRegister tmp1, Register tmp2);
1417
1418 };
1419
1420 /**
1421 * class SkipIfEqual:
1422 *
1423 * Instantiating this class will result in assembly code being output that will
1424 * jump around any code emitted between the creation of the instance and it's
1425 * automatic destruction at the end of a scope block, depending on the value of
1426 * the flag passed to the constructor, which will be checked at run-time.
1427 */
1428 class SkipIfEqual {
1429 private:
1430 MacroAssembler* _masm;
1431 Label _label;
1432
1433 public:
1434 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1435 ~SkipIfEqual();
1436 };
1437
1438 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP