1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 
  31 // <sys/trap.h> promises that the system will not use traps 16-31
  32 #define ST_RESERVED_FOR_USER_0 0x10
  33 
  34 class BiasedLockingCounters;
  35 
  36 
  37 // Register aliases for parts of the system:
  38 
  39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
  40 // across context switches in V8+ ABI.  Of course, there are no 64 bit regs
  41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
  42 
  43 // g2-g4 are scratch registers called "application globals".  Their
  44 // meaning is reserved to the "compilation system"--which means us!
  45 // They are are not supposed to be touched by ordinary C code, although
  46 // highly-optimized C code might steal them for temps.  They are safe
  47 // across thread switches, and the ABI requires that they be safe
  48 // across function calls.
  49 //
  50 // g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered
  51 // across func calls, and V8+ also allows g5 to be clobbered across
  52 // func calls.  Also, g1 and g5 can get touched while doing shared
  53 // library loading.
  54 //
  55 // We must not touch g7 (it is the thread-self register) and g6 is
  56 // reserved for certain tools.  g0, of course, is always zero.
  57 //
  58 // (Sources:  SunSoft Compilers Group, thread library engineers.)
  59 
  60 // %%%% The interpreter should be revisited to reduce global scratch regs.
  61 
  62 // This global always holds the current JavaThread pointer:
  63 
  64 REGISTER_DECLARATION(Register, G2_thread , G2);
  65 REGISTER_DECLARATION(Register, G6_heapbase , G6);
  66 
  67 // The following globals are part of the Java calling convention:
  68 
  69 REGISTER_DECLARATION(Register, G5_method             , G5);
  70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
  71 REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);
  72 
  73 // The following globals are used for the new C1 & interpreter calling convention:
  74 REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument
  75 
  76 // This local is used to preserve G2_thread in the interpreter and in stubs:
  77 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
  78 
  79 // These globals are used as scratch registers in the interpreter:
  80 
  81 REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch
  82 REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME
  83 REGISTER_DECLARATION(Register, G3_scratch    , G3);
  84 REGISTER_DECLARATION(Register, G4_scratch    , G4);
  85 
  86 // These globals are used as short-lived scratch registers in the compiler:
  87 
  88 REGISTER_DECLARATION(Register, Gtemp  , G5);
  89 
  90 // JSR 292 fixed register usages:
  91 REGISTER_DECLARATION(Register, G5_method_type        , G5);
  92 REGISTER_DECLARATION(Register, G3_method_handle      , G3);
  93 REGISTER_DECLARATION(Register, L7_mh_SP_save         , L7);
  94 
  95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
  96 // because a single patchable "set" instruction (NativeMovConstReg,
  97 // or NativeMovConstPatching for compiler1) instruction
  98 // serves to set up either quantity, depending on whether the compiled
  99 // call site is an inline cache or is megamorphic.  See the function
 100 // CompiledIC::set_to_megamorphic.
 101 //
 102 // If a inline cache targets an interpreted method, then the
 103 // G5 register will be used twice during the call.  First,
 104 // the call site will be patched to load a compiledICHolder
 105 // into G5. (This is an ordered pair of ic_klass, method.)
 106 // The c2i adapter will first check the ic_klass, then load
 107 // G5_method with the method part of the pair just before
 108 // jumping into the interpreter.
 109 //
 110 // Note that G5_method is only the method-self for the interpreter,
 111 // and is logically unrelated to G5_megamorphic_method.
 112 //
 113 // Invariants on G2_thread (the JavaThread pointer):
 114 //  - it should not be used for any other purpose anywhere
 115 //  - it must be re-initialized by StubRoutines::call_stub()
 116 //  - it must be preserved around every use of call_VM
 117 
 118 // We can consider using g2/g3/g4 to cache more values than the
 119 // JavaThread, such as the card-marking base or perhaps pointers into
 120 // Eden.  It's something of a waste to use them as scratch temporaries,
 121 // since they are not supposed to be volatile.  (Of course, if we find
 122 // that Java doesn't benefit from application globals, then we can just
 123 // use them as ordinary temporaries.)
 124 //
 125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
 126 // it makes sense to use them routinely for procedure linkage,
 127 // whenever the On registers are not applicable.  Examples:  G5_method,
 128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
 129 // stubs.  This means that compiler stubs, etc., should be kept to a
 130 // maximum of two or three G-register arguments.
 131 
 132 
 133 // stub frames
 134 
 135 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
 136 
 137 // Interpreter frames
 138 
 139 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
 140 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
 141 REGISTER_DECLARATION(Register, Lmethod          , L2);
 142 REGISTER_DECLARATION(Register, Llocals          , L3);
 143 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
 144                                                        // must match Llocals in asm interpreter
 145 REGISTER_DECLARATION(Register, Lmonitors        , L4);
 146 REGISTER_DECLARATION(Register, Lbyte_code       , L5);
 147 // When calling out from the interpreter we record SP so that we can remove any extra stack
 148 // space allocated during adapter transitions. This register is only live from the point
 149 // of the call until we return.
 150 REGISTER_DECLARATION(Register, Llast_SP         , L5);
 151 REGISTER_DECLARATION(Register, Lscratch         , L5);
 152 REGISTER_DECLARATION(Register, Lscratch2        , L6);
 153 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
 154 
 155 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 156 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 157                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 158                                                        // is added and removed as needed in the frame code.
 159 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
 160 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data
 161 
 162 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
 163 //       the interpreter code. If Lscratch2 needs to be used for some
 164 //       purpose than LcpoolCache should be restore after that for
 165 //       the interpreter to work right
 166 // (These assignments must be compatible with L7_thread_cache; see above.)
 167 
 168 // Lbcp points into the middle of the method object.
 169 
 170 // Exception processing
 171 // These registers are passed into exception handlers.
 172 // All exception handlers require the exception object being thrown.
 173 // In addition, an nmethod's exception handler must be passed
 174 // the address of the call site within the nmethod, to allow
 175 // proper selection of the applicable catch block.
 176 // (Interpreter frames use their own bcp() for this purpose.)
 177 //
 178 // The Oissuing_pc value is not always needed.  When jumping to a
 179 // handler that is known to be interpreted, the Oissuing_pc value can be
 180 // omitted.  An actual catch block in compiled code receives (from its
 181 // nmethod's exception handler) the thrown exception in the Oexception,
 182 // but it doesn't need the Oissuing_pc.
 183 //
 184 // If an exception handler (either interpreted or compiled)
 185 // discovers there is no applicable catch block, it updates
 186 // the Oissuing_pc to the continuation PC of its own caller,
 187 // pops back to that caller's stack frame, and executes that
 188 // caller's exception handler.  Obviously, this process will
 189 // iterate until the control stack is popped back to a method
 190 // containing an applicable catch block.  A key invariant is
 191 // that the Oissuing_pc value is always a value local to
 192 // the method whose exception handler is currently executing.
 193 //
 194 // Note:  The issuing PC value is __not__ a raw return address (I7 value).
 195 // It is a "return pc", the address __following__ the call.
 196 // Raw return addresses are converted to issuing PCs by frame::pc(),
 197 // or by stubs.  Issuing PCs can be used directly with PC range tables.
 198 //
 199 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
 200 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
 201 
 202 
 203 // These must occur after the declarations above
 204 #ifndef DONT_USE_REGISTER_DEFINES
 205 
 206 #define Gthread             AS_REGISTER(Register, Gthread)
 207 #define Gmethod             AS_REGISTER(Register, Gmethod)
 208 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
 209 #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)
 210 #define Gargs               AS_REGISTER(Register, Gargs)
 211 #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)
 212 #define Gframe_size         AS_REGISTER(Register, Gframe_size)
 213 #define Gtemp               AS_REGISTER(Register, Gtemp)
 214 
 215 #define Lesp                AS_REGISTER(Register, Lesp)
 216 #define Lbcp                AS_REGISTER(Register, Lbcp)
 217 #define Lmethod             AS_REGISTER(Register, Lmethod)
 218 #define Llocals             AS_REGISTER(Register, Llocals)
 219 #define Lmonitors           AS_REGISTER(Register, Lmonitors)
 220 #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)
 221 #define Lscratch            AS_REGISTER(Register, Lscratch)
 222 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
 223 #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)
 224 
 225 #define Lentry_args         AS_REGISTER(Register, Lentry_args)
 226 #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)
 227 #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)
 228 #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)
 229 #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)
 230 
 231 #define Oexception          AS_REGISTER(Register, Oexception)
 232 #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)
 233 
 234 #endif
 235 
 236 
 237 // Address is an abstraction used to represent a memory location.
 238 //
 239 // Note: A register location is represented via a Register, not
 240 //       via an address for efficiency & simplicity reasons.
 241 
 242 class Address {
 243  private:
 244   Register           _base;           // Base register.
 245   RegisterOrConstant _index_or_disp;  // Index register or constant displacement.
 246   RelocationHolder   _rspec;
 247 
 248  public:
 249   Address() : _base(noreg), _index_or_disp(noreg) {}
 250 
 251   Address(Register base, RegisterOrConstant index_or_disp)
 252     : _base(base),
 253       _index_or_disp(index_or_disp) {
 254   }
 255 
 256   Address(Register base, Register index)
 257     : _base(base),
 258       _index_or_disp(index) {
 259   }
 260 
 261   Address(Register base, int disp)
 262     : _base(base),
 263       _index_or_disp(disp) {
 264   }
 265 
 266 #ifdef ASSERT
 267   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 268   Address(Register base, ByteSize disp)
 269     : _base(base),
 270       _index_or_disp(in_bytes(disp)) {
 271   }
 272 #endif
 273 
 274   // accessors
 275   Register base()             const { return _base; }
 276   Register index()            const { return _index_or_disp.as_register(); }
 277   int      disp()             const { return _index_or_disp.as_constant(); }
 278 
 279   bool     has_index()        const { return _index_or_disp.is_register(); }
 280   bool     has_disp()         const { return _index_or_disp.is_constant(); }
 281 
 282   bool     uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
 283 
 284   const relocInfo::relocType rtype() { return _rspec.type(); }
 285   const RelocationHolder&    rspec() { return _rspec; }
 286 
 287   RelocationHolder rspec(int offset) const {
 288     return offset == 0 ? _rspec : _rspec.plus(offset);
 289   }
 290 
 291   inline bool is_simm13(int offset = 0);  // check disp+offset for overflow
 292 
 293   Address plus_disp(int plusdisp) const {     // bump disp by a small amount
 294     assert(_index_or_disp.is_constant(), "must have a displacement");
 295     Address a(base(), disp() + plusdisp);
 296     return a;
 297   }
 298   bool is_same_address(Address a) const {
 299     // disregard _rspec
 300     return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
 301   }
 302 
 303   Address after_save() const {
 304     Address a = (*this);
 305     a._base = a._base->after_save();
 306     return a;
 307   }
 308 
 309   Address after_restore() const {
 310     Address a = (*this);
 311     a._base = a._base->after_restore();
 312     return a;
 313   }
 314 
 315   // Convert the raw encoding form into the form expected by the
 316   // constructor for Address.
 317   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 318 
 319   friend class Assembler;
 320 };
 321 
 322 
 323 class AddressLiteral {
 324  private:
 325   address          _address;
 326   RelocationHolder _rspec;
 327 
 328   RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
 329     switch (rtype) {
 330     case relocInfo::external_word_type:
 331       return external_word_Relocation::spec(addr);
 332     case relocInfo::internal_word_type:
 333       return internal_word_Relocation::spec(addr);
 334     case relocInfo::opt_virtual_call_type:
 335       return opt_virtual_call_Relocation::spec();
 336     case relocInfo::static_call_type:
 337       return static_call_Relocation::spec();
 338     case relocInfo::runtime_call_type:
 339       return runtime_call_Relocation::spec();
 340     case relocInfo::none:
 341       return RelocationHolder();
 342     default:
 343       ShouldNotReachHere();
 344       return RelocationHolder();
 345     }
 346   }
 347 
 348  protected:
 349   // creation
 350   AddressLiteral() : _address(NULL), _rspec(NULL) {}
 351 
 352  public:
 353   AddressLiteral(address addr, RelocationHolder const& rspec)
 354     : _address(addr),
 355       _rspec(rspec) {}
 356 
 357   // Some constructors to avoid casting at the call site.
 358   AddressLiteral(jobject obj, RelocationHolder const& rspec)
 359     : _address((address) obj),
 360       _rspec(rspec) {}
 361 
 362   AddressLiteral(intptr_t value, RelocationHolder const& rspec)
 363     : _address((address) value),
 364       _rspec(rspec) {}
 365 
 366   AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
 367     : _address((address) addr),
 368     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 369 
 370   // Some constructors to avoid casting at the call site.
 371   AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
 372     : _address((address) addr),
 373     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 374 
 375   AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
 376     : _address((address) addr),
 377       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 378 
 379   AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
 380     : _address((address) addr),
 381       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 382 
 383   AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
 384     : _address((address) addr),
 385       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 386 
 387   AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
 388     : _address((address) addr),
 389       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 390 
 391   AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
 392     : _address((address) addr),
 393       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 394 
 395   // 32-bit complains about a multiple declaration for int*.
 396   AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
 397     : _address((address) addr),
 398       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 399 
 400   AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none)
 401     : _address((address) addr),
 402       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 403 
 404   AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none)
 405     : _address((address) addr),
 406       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 407 
 408   AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
 409     : _address((address) addr),
 410       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 411 
 412   AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
 413     : _address((address) addr),
 414       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 415 
 416   intptr_t value() const { return (intptr_t) _address; }
 417   int      low10() const;
 418 
 419   const relocInfo::relocType rtype() const { return _rspec.type(); }
 420   const RelocationHolder&    rspec() const { return _rspec; }
 421 
 422   RelocationHolder rspec(int offset) const {
 423     return offset == 0 ? _rspec : _rspec.plus(offset);
 424   }
 425 };
 426 
 427 // Convenience classes
 428 class ExternalAddress: public AddressLiteral {
 429  private:
 430   static relocInfo::relocType reloc_for_target(address target) {
 431     // Sometimes ExternalAddress is used for values which aren't
 432     // exactly addresses, like the card table base.
 433     // external_word_type can't be used for values in the first page
 434     // so just skip the reloc in that case.
 435     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 436   }
 437 
 438  public:
 439   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(          target)) {}
 440   ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {}
 441 };
 442 
 443 inline Address RegisterImpl::address_in_saved_window() const {
 444    return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
 445 }
 446 
 447 
 448 
 449 // Argument is an abstraction used to represent an outgoing
 450 // actual argument or an incoming formal parameter, whether
 451 // it resides in memory or in a register, in a manner consistent
 452 // with the SPARC Application Binary Interface, or ABI.  This is
 453 // often referred to as the native or C calling convention.
 454 
 455 class Argument {
 456  private:
 457   int _number;
 458   bool _is_in;
 459 
 460  public:
 461   enum {
 462     n_register_parameters = 6,          // only 6 registers may contain integer parameters
 463     n_float_register_parameters = 16    // Can have up to 16 floating registers
 464   };
 465 
 466   // creation
 467   Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
 468 
 469   int  number() const  { return _number;  }
 470   bool is_in()  const  { return _is_in;   }
 471   bool is_out() const  { return !is_in(); }
 472 
 473   Argument successor() const  { return Argument(number() + 1, is_in()); }
 474   Argument as_in()     const  { return Argument(number(), true ); }
 475   Argument as_out()    const  { return Argument(number(), false); }
 476 
 477   // locating register-based arguments:
 478   bool is_register() const { return _number < n_register_parameters; }
 479 
 480   // locating Floating Point register-based arguments:
 481   bool is_float_register() const { return _number < n_float_register_parameters; }
 482 
 483   FloatRegister as_float_register() const {
 484     assert(is_float_register(), "must be a register argument");
 485     return as_FloatRegister(( number() *2 ) + 1);
 486   }
 487   FloatRegister as_double_register() const {
 488     assert(is_float_register(), "must be a register argument");
 489     return as_FloatRegister(( number() *2 ));
 490   }
 491 
 492   Register as_register() const {
 493     assert(is_register(), "must be a register argument");
 494     return is_in() ? as_iRegister(number()) : as_oRegister(number());
 495   }
 496 
 497   // locating memory-based arguments
 498   Address as_address() const {
 499     assert(!is_register(), "must be a memory argument");
 500     return address_in_frame();
 501   }
 502 
 503   // When applied to a register-based argument, give the corresponding address
 504   // into the 6-word area "into which callee may store register arguments"
 505   // (This is a different place than the corresponding register-save area location.)
 506   Address address_in_frame() const;
 507 
 508   // debugging
 509   const char* name() const;
 510 
 511   friend class Assembler;
 512 };
 513 
 514 
 515 class RegistersForDebugging : public StackObj {
 516  public:
 517   intptr_t i[8], l[8], o[8], g[8];
 518   float    f[32];
 519   double   d[32];
 520 
 521   void print(outputStream* s);
 522 
 523   static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
 524   static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
 525   static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
 526   static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
 527   static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
 528   static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
 529 
 530   // gen asm code to save regs
 531   static void save_registers(MacroAssembler* a);
 532 
 533   // restore global registers in case C code disturbed them
 534   static void restore_registers(MacroAssembler* a, Register r);
 535 };
 536 
 537 
 538 // MacroAssembler extends Assembler by a few frequently used macros.
 539 //
 540 // Most of the standard SPARC synthetic ops are defined here.
 541 // Instructions for which a 'better' code sequence exists depending
 542 // on arguments should also go in here.
 543 
 544 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
 545 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
 546 #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
 547 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
 548 
 549 
 550 class MacroAssembler : public Assembler {
 551   // code patchers need various routines like inv_wdisp()
 552   friend class NativeInstruction;
 553   friend class NativeGeneralJump;
 554   friend class Relocation;
 555   friend class Label;
 556 
 557  protected:
 558   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 559   static int  branch_destination(int inst, int pos);
 560 
 561   // Support for VM calls
 562   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
 563   // may customize this version by overriding it for its purposes (e.g., to save/restore
 564   // additional registers when doing a VM call).
 565   virtual void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
 566 
 567   //
 568   // It is imperative that all calls into the VM are handled via the call_VM macros.
 569   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 570   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 571   //
 572   // This is the base routine called by the different versions of call_VM. The interpreter
 573   // may customize this version by overriding it for its purposes (e.g., to save/restore
 574   // additional registers when doing a VM call).
 575   //
 576   // A non-volatile java_thread_cache register should be specified so
 577   // that the G2_thread value can be preserved across the call.
 578   // (If java_thread_cache is noreg, then a slow get_thread call
 579   // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
 580   // thread.
 581   //
 582   // If no last_java_sp is specified (noreg) than SP will be used instead.
 583 
 584   virtual void call_VM_base(
 585     Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise
 586     Register        java_thread_cache,      // the thread if computed before     ; use noreg otherwise
 587     Register        last_java_sp,           // to set up last_Java_frame in stubs; use noreg otherwise
 588     address         entry_point,            // the entry point
 589     int             number_of_arguments,    // the number of arguments (w/o thread) to pop after call
 590     bool            check_exception=true    // flag which indicates if exception should be checked
 591   );
 592 
 593  public:
 594   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 595 
 596   // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 597   // The implementation is only non-empty for the InterpreterMacroAssembler,
 598   // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
 599   virtual void check_and_handle_popframe(Register scratch_reg);
 600   virtual void check_and_handle_earlyret(Register scratch_reg);
 601 
 602   // Support for NULL-checks
 603   //
 604   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 605   // If the accessed location is M[reg + offset] and the offset is known, provide the
 606   // offset.  No explicit code generation is needed if the offset is within a certain
 607   // range (0 <= offset <= page_size).
 608   //
 609   // FIXME: Currently not done for SPARC
 610 
 611   void null_check(Register reg, int offset = -1);
 612   static bool needs_explicit_null_check(intptr_t offset);
 613 
 614   // support for delayed instructions
 615   MacroAssembler* delayed() { Assembler::delayed();  return this; }
 616 
 617   // branches that use right instruction for v8 vs. v9
 618   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 619   inline void br( Condition c, bool a, Predict p, Label& L );
 620 
 621   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 622   inline void fb( Condition c, bool a, Predict p, Label& L );
 623 
 624   // compares register with zero (32 bit) and branches (V9 and V8 instructions)
 625   void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
 626   // Compares a pointer register with zero and branches on (not)null.
 627   // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
 628   void br_null   ( Register s1, bool a, Predict p, Label& L );
 629   void br_notnull( Register s1, bool a, Predict p, Label& L );
 630 
 631   //
 632   // Compare registers and branch with nop in delay slot or cbcond without delay slot.
 633   //
 634   // ATTENTION: use these instructions with caution because cbcond instruction
 635   //            has very short distance: 512 instructions (2Kbyte).
 636 
 637   // Compare integer (32 bit) values (icc only).
 638   void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
 639   void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
 640   // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
 641   void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
 642   void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
 643 
 644   // Short branch version for compares a pointer pwith zero.
 645   void br_null_short   ( Register s1, Predict p, Label& L );
 646   void br_notnull_short( Register s1, Predict p, Label& L );
 647 
 648   // unconditional short branch
 649   void ba_short(Label& L);
 650 
 651   // Branch on icc.z (true or not).
 652   void br_icc_zero(bool iszero, Predict p, Label &L);
 653 
 654   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 655   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
 656 
 657   // Branch that tests xcc in LP64 and icc in !LP64
 658   inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 659   inline void brx( Condition c, bool a, Predict p, Label& L );
 660 
 661   // unconditional branch
 662   inline void ba( Label& L );
 663 
 664   // Branch that tests fp condition codes
 665   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 666   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
 667 
 668   // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
 669   inline void cmp( Register s1, Register s2 );
 670   inline void cmp( Register s1, int simm13a );
 671 
 672   inline void jmp( Register s1, Register s2 );
 673   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
 674 
 675   // Check if the call target is out of wdisp30 range (relative to the code cache)
 676   static inline bool is_far_target(address d);
 677   inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
 678   inline void call( address d, RelocationHolder const& rspec);
 679 
 680   inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
 681   inline void call( Label& L, RelocationHolder const& rspec);
 682 
 683   inline void callr( Register s1, Register s2 );
 684   inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
 685 
 686   // Emits nothing on V8
 687   inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
 688   inline void iprefetch( Label& L);
 689 
 690   inline void tst( Register s );
 691 
 692   inline void ret(  bool trace = false );
 693   inline void retl( bool trace = false );
 694 
 695   // Required platform-specific helpers for Label::patch_instructions.
 696   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 697   void pd_patch_instruction(address branch, address target);
 698 
 699   // sethi Macro handles optimizations and relocations
 700 private:
 701   void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
 702 public:
 703   void sethi(const AddressLiteral& addrlit, Register d);
 704   void patchable_sethi(const AddressLiteral& addrlit, Register d);
 705 
 706   // compute the number of instructions for a sethi/set
 707   static int  insts_for_sethi( address a, bool worst_case = false );
 708   static int  worst_case_insts_for_set();
 709 
 710   // set may be either setsw or setuw (high 32 bits may be zero or sign)
 711 private:
 712   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
 713   static int insts_for_internal_set(intptr_t value);
 714 public:
 715   void set(const AddressLiteral& addrlit, Register d);
 716   void set(intptr_t value, Register d);
 717   void set(address addr, Register d, RelocationHolder const& rspec);
 718   static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
 719 
 720   void patchable_set(const AddressLiteral& addrlit, Register d);
 721   void patchable_set(intptr_t value, Register d);
 722   void set64(jlong value, Register d, Register tmp);
 723   static int insts_for_set64(jlong value);
 724 
 725   // sign-extend 32 to 64
 726   inline void signx( Register s, Register d );
 727   inline void signx( Register d );
 728 
 729   inline void not1( Register s, Register d );
 730   inline void not1( Register d );
 731 
 732   inline void neg( Register s, Register d );
 733   inline void neg( Register d );
 734 
 735   inline void cas(  Register s1, Register s2, Register d);
 736   inline void casx( Register s1, Register s2, Register d);
 737   // Functions for isolating 64 bit atomic swaps for LP64
 738   // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
 739   inline void cas_ptr(  Register s1, Register s2, Register d);
 740 
 741   // Functions for isolating 64 bit shifts for LP64
 742   inline void sll_ptr( Register s1, Register s2, Register d );
 743   inline void sll_ptr( Register s1, int imm6a,   Register d );
 744   inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
 745   inline void srl_ptr( Register s1, Register s2, Register d );
 746   inline void srl_ptr( Register s1, int imm6a,   Register d );
 747 
 748   // little-endian
 749   inline void casl(  Register s1, Register s2, Register d);
 750   inline void casxl( Register s1, Register s2, Register d);
 751 
 752   inline void inc(   Register d,  int const13 = 1 );
 753   inline void inccc( Register d,  int const13 = 1 );
 754 
 755   inline void dec(   Register d,  int const13 = 1 );
 756   inline void deccc( Register d,  int const13 = 1 );
 757 
 758   using Assembler::add;
 759   inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype);
 760   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
 761   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
 762   inline void add(const Address& a, Register d, int offset = 0);
 763 
 764   using Assembler::andn;
 765   inline void andn(  Register s1, RegisterOrConstant s2, Register d);
 766 
 767   inline void btst( Register s1,  Register s2 );
 768   inline void btst( int simm13a,  Register s );
 769 
 770   inline void bset( Register s1,  Register s2 );
 771   inline void bset( int simm13a,  Register s );
 772 
 773   inline void bclr( Register s1,  Register s2 );
 774   inline void bclr( int simm13a,  Register s );
 775 
 776   inline void btog( Register s1,  Register s2 );
 777   inline void btog( int simm13a,  Register s );
 778 
 779   inline void clr( Register d );
 780 
 781   inline void clrb( Register s1, Register s2);
 782   inline void clrh( Register s1, Register s2);
 783   inline void clr(  Register s1, Register s2);
 784   inline void clrx( Register s1, Register s2);
 785 
 786   inline void clrb( Register s1, int simm13a);
 787   inline void clrh( Register s1, int simm13a);
 788   inline void clr(  Register s1, int simm13a);
 789   inline void clrx( Register s1, int simm13a);
 790 
 791   // copy & clear upper word
 792   inline void clruw( Register s, Register d );
 793   // clear upper word
 794   inline void clruwu( Register d );
 795 
 796   using Assembler::ldsb;
 797   using Assembler::ldsh;
 798   using Assembler::ldsw;
 799   using Assembler::ldub;
 800   using Assembler::lduh;
 801   using Assembler::lduw;
 802   using Assembler::ldx;
 803   using Assembler::ldd;
 804 
 805 #ifdef ASSERT
 806   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 807   inline void ld(Register s1, ByteSize simm13a, Register d);
 808 #endif
 809 
 810   inline void ld(Register s1, Register s2, Register d);
 811   inline void ld(Register s1, int simm13a, Register d);
 812 
 813   inline void ldsb(const Address& a, Register d, int offset = 0);
 814   inline void ldsh(const Address& a, Register d, int offset = 0);
 815   inline void ldsw(const Address& a, Register d, int offset = 0);
 816   inline void ldub(const Address& a, Register d, int offset = 0);
 817   inline void lduh(const Address& a, Register d, int offset = 0);
 818   inline void lduw(const Address& a, Register d, int offset = 0);
 819   inline void ldx( const Address& a, Register d, int offset = 0);
 820   inline void ld(  const Address& a, Register d, int offset = 0);
 821   inline void ldd( const Address& a, Register d, int offset = 0);
 822 
 823   inline void ldub(Register s1, RegisterOrConstant s2, Register d );
 824   inline void ldsb(Register s1, RegisterOrConstant s2, Register d );
 825   inline void lduh(Register s1, RegisterOrConstant s2, Register d );
 826   inline void ldsh(Register s1, RegisterOrConstant s2, Register d );
 827   inline void lduw(Register s1, RegisterOrConstant s2, Register d );
 828   inline void ldsw(Register s1, RegisterOrConstant s2, Register d );
 829   inline void ldx( Register s1, RegisterOrConstant s2, Register d );
 830   inline void ld(  Register s1, RegisterOrConstant s2, Register d );
 831   inline void ldd( Register s1, RegisterOrConstant s2, Register d );
 832 
 833   using Assembler::ldf;
 834   inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
 835   inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
 836 
 837   // little-endian
 838   inline void lduwl(Register s1, Register s2, Register d);
 839   inline void ldswl(Register s1, Register s2, Register d);
 840   inline void ldxl( Register s1, Register s2, Register d);
 841   inline void ldfl(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 842 
 843   // membar psuedo instruction.  takes into account target memory model.
 844   inline void membar( Assembler::Membar_mask_bits const7a );
 845 
 846   // returns if membar generates anything.
 847   inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
 848 
 849   // mov pseudo instructions
 850   inline void mov( Register s,  Register d);
 851 
 852   inline void mov_or_nop( Register s,  Register d);
 853 
 854   inline void mov( int simm13a, Register d);
 855 
 856   using Assembler::prefetch;
 857   inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
 858 
 859   using Assembler::stb;
 860   using Assembler::sth;
 861   using Assembler::stw;
 862   using Assembler::stx;
 863   using Assembler::std;
 864 
 865 #ifdef ASSERT
 866   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 867   inline void st(Register d, Register s1, ByteSize simm13a);
 868 #endif
 869 
 870   inline void st(Register d, Register s1, Register s2);
 871   inline void st(Register d, Register s1, int simm13a);
 872 
 873   inline void stb(Register d, const Address& a, int offset = 0 );
 874   inline void sth(Register d, const Address& a, int offset = 0 );
 875   inline void stw(Register d, const Address& a, int offset = 0 );
 876   inline void stx(Register d, const Address& a, int offset = 0 );
 877   inline void st( Register d, const Address& a, int offset = 0 );
 878   inline void std(Register d, const Address& a, int offset = 0 );
 879 
 880   inline void stb(Register d, Register s1, RegisterOrConstant s2 );
 881   inline void sth(Register d, Register s1, RegisterOrConstant s2 );
 882   inline void stw(Register d, Register s1, RegisterOrConstant s2 );
 883   inline void stx(Register d, Register s1, RegisterOrConstant s2 );
 884   inline void std(Register d, Register s1, RegisterOrConstant s2 );
 885   inline void st( Register d, Register s1, RegisterOrConstant s2 );
 886 
 887   using Assembler::stf;
 888   inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
 889   inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
 890 
 891   // Note: offset is added to s2.
 892   using Assembler::sub;
 893   inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
 894 
 895   using Assembler::swap;
 896   inline void swap(const Address& a, Register d, int offset = 0);
 897 
 898   // address pseudos: make these names unlike instruction names to avoid confusion
 899   inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
 900   inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
 901   inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
 902   inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
 903   inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
 904   inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
 905   inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
 906   inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
 907   inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
 908 
 909   // ring buffer traceable jumps
 910 
 911   void jmp2( Register r1, Register r2, const char* file, int line );
 912   void jmp ( Register r1, int offset,  const char* file, int line );
 913 
 914   void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
 915   void jump (const AddressLiteral& addrlit, Register temp,             int offset, const char* file, int line);
 916 
 917 
 918   // argument pseudos:
 919 
 920   inline void load_argument( Argument& a, Register  d );
 921   inline void store_argument( Register s, Argument& a );
 922   inline void store_ptr_argument( Register s, Argument& a );
 923   inline void store_float_argument( FloatRegister s, Argument& a );
 924   inline void store_double_argument( FloatRegister s, Argument& a );
 925   inline void store_long_argument( Register s, Argument& a );
 926 
 927   // handy macros:
 928 
 929   inline void round_to( Register r, int modulus );
 930 
 931   // --------------------------------------------------
 932 
 933   // Functions for isolating 64 bit loads for LP64
 934   // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
 935   // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
 936   inline void ld_ptr(Register s1, Register s2, Register d);
 937   inline void ld_ptr(Register s1, int simm13a, Register d);
 938   inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
 939   inline void ld_ptr(const Address& a, Register d, int offset = 0);
 940   inline void st_ptr(Register d, Register s1, Register s2);
 941   inline void st_ptr(Register d, Register s1, int simm13a);
 942   inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
 943   inline void st_ptr(Register d, const Address& a, int offset = 0);
 944 
 945 #ifdef ASSERT
 946   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 947   inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
 948   inline void st_ptr(Register d, Register s1, ByteSize simm13a);
 949 #endif
 950 
 951   // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
 952   // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
 953   inline void ld_long(Register s1, Register s2, Register d);
 954   inline void ld_long(Register s1, int simm13a, Register d);
 955   inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
 956   inline void ld_long(const Address& a, Register d, int offset = 0);
 957   inline void st_long(Register d, Register s1, Register s2);
 958   inline void st_long(Register d, Register s1, int simm13a);
 959   inline void st_long(Register d, Register s1, RegisterOrConstant s2);
 960   inline void st_long(Register d, const Address& a, int offset = 0);
 961 
 962   // Helpers for address formation.
 963   // - They emit only a move if s2 is a constant zero.
 964   // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
 965   // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
 966   RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
 967   RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
 968   RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
 969 
 970   RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
 971     if (is_simm13(src.constant_or_zero()))
 972       return src;               // register or short constant
 973     guarantee(temp != noreg, "constant offset overflow");
 974     set(src.as_constant(), temp);
 975     return temp;
 976   }
 977 
 978   // --------------------------------------------------
 979 
 980  public:
 981   // traps as per trap.h (SPARC ABI?)
 982 
 983   void breakpoint_trap();
 984   void breakpoint_trap(Condition c, CC cc);
 985 
 986   // Support for serializing memory accesses between threads
 987   void serialize_memory(Register thread, Register tmp1, Register tmp2);
 988 
 989   void safepoint_poll(Label& slow_path, bool a, Register thread_reg, Register temp_reg);
 990 
 991   // Stack frame creation/removal
 992   void enter();
 993   void leave();
 994 
 995   // Manipulation of C++ bools
 996   // These are idioms to flag the need for care with accessing bools but on
 997   // this platform we assume byte size
 998 
 999   inline void stbool(Register d, const Address& a);
1000   inline void ldbool(const Address& a, Register d);
1001   inline void movbool( bool boolconst, Register d);
1002 
1003   void resolve_oop_handle(Register result);
1004   void load_mirror(Register mirror, Register method);
1005 
1006   // klass oop manipulations if compressed
1007   void load_klass(Register src_oop, Register klass);
1008   void store_klass(Register klass, Register dst_oop);
1009   void store_klass_gap(Register s, Register dst_oop);
1010 
1011    // oop manipulations
1012   void load_heap_oop(const Address& s, Register d);
1013   void load_heap_oop(Register s1, Register s2, Register d);
1014   void load_heap_oop(Register s1, int simm13a, Register d);
1015   void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
1016   void store_heap_oop(Register d, Register s1, Register s2);
1017   void store_heap_oop(Register d, Register s1, int simm13a);
1018   void store_heap_oop(Register d, const Address& a, int offset = 0);
1019 
1020   void encode_heap_oop(Register src, Register dst);
1021   void encode_heap_oop(Register r) {
1022     encode_heap_oop(r, r);
1023   }
1024   void decode_heap_oop(Register src, Register dst);
1025   void decode_heap_oop(Register r) {
1026     decode_heap_oop(r, r);
1027   }
1028   void encode_heap_oop_not_null(Register r);
1029   void decode_heap_oop_not_null(Register r);
1030   void encode_heap_oop_not_null(Register src, Register dst);
1031   void decode_heap_oop_not_null(Register src, Register dst);
1032 
1033   void encode_klass_not_null(Register r);
1034   void decode_klass_not_null(Register r);
1035   void encode_klass_not_null(Register src, Register dst);
1036   void decode_klass_not_null(Register src, Register dst);
1037 
1038   // Support for managing the JavaThread pointer (i.e.; the reference to
1039   // thread-local information).
1040   void get_thread();                                // load G2_thread
1041   void verify_thread();                             // verify G2_thread contents
1042   void save_thread   (const Register threache); // save to cache
1043   void restore_thread(const Register thread_cache); // restore from cache
1044 
1045   // Support for last Java frame (but use call_VM instead where possible)
1046   void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
1047   void reset_last_Java_frame(void);
1048 
1049   // Call into the VM.
1050   // Passes the thread pointer (in O0) as a prepended argument.
1051   // Makes sure oop return values are visible to the GC.
1052   void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1053   void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1054   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1055   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1056 
1057   // these overloadings are not presently used on SPARC:
1058   void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1059   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1060   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1061   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1062 
1063   void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1064   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1065   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1066   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1067 
1068   void get_vm_result  (Register oop_result);
1069   void get_vm_result_2(Register metadata_result);
1070 
1071   // vm result is currently getting hijacked to for oop preservation
1072   void set_vm_result(Register oop_result);
1073 
1074   // Emit the CompiledIC call idiom
1075   void ic_call(address entry, bool emit_delay = true, jint method_index = 0);
1076 
1077   // if call_VM_base was called with check_exceptions=false, then call
1078   // check_and_forward_exception to handle exceptions when it is safe
1079   void check_and_forward_exception(Register scratch_reg);
1080 
1081   // Write to card table for - register is destroyed afterwards.
1082   void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
1083 
1084   void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1085 
1086 #if INCLUDE_ALL_GCS
1087   // General G1 pre-barrier generator.
1088   void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
1089 
1090   // General G1 post-barrier generator
1091   void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1092 #endif // INCLUDE_ALL_GCS
1093 
1094   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1095   void push_fTOS();
1096 
1097   // pops double TOS element from CPU stack and pushes on FPU stack
1098   void pop_fTOS();
1099 
1100   void empty_FPU_stack();
1101 
1102   void push_IU_state();
1103   void pop_IU_state();
1104 
1105   void push_FPU_state();
1106   void pop_FPU_state();
1107 
1108   void push_CPU_state();
1109   void pop_CPU_state();
1110 
1111   // Returns the byte size of the instructions generated by decode_klass_not_null().
1112   static int instr_size_for_decode_klass_not_null();
1113 
1114   // if heap base register is used - reinit it with the correct value
1115   void reinit_heapbase();
1116 
1117   // Debugging
1118   void _verify_oop(Register reg, const char * msg, const char * file, int line);
1119   void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
1120 
1121   // TODO: verify_method and klass metadata (compare against vptr?)
1122   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1123   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1124 
1125 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
1126 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
1127 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1128 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1129 
1130         // only if +VerifyOops
1131   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1132         // only if +VerifyFPU
1133   void stop(const char* msg);                          // prints msg, dumps registers and stops execution
1134   void warn(const char* msg);                          // prints msg, but don't stop
1135   void untested(const char* what = "");
1136   void unimplemented(const char* what = "");
1137   void should_not_reach_here()                   { stop("should not reach here"); }
1138   void print_CPU_state();
1139 
1140   // oops in code
1141   AddressLiteral allocate_oop_address(jobject obj);                          // allocate_index
1142   AddressLiteral constant_oop_address(jobject obj);                          // find_index
1143   inline void    set_oop             (jobject obj, Register d);              // uses allocate_oop_address
1144   inline void    set_oop_constant    (jobject obj, Register d);              // uses constant_oop_address
1145   inline void    set_oop             (const AddressLiteral& obj_addr, Register d); // same as load_address
1146 
1147   // metadata in code that we have to keep track of
1148   AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
1149   AddressLiteral constant_metadata_address(Metadata* obj); // find_index
1150   inline void    set_metadata             (Metadata* obj, Register d);              // uses allocate_metadata_address
1151   inline void    set_metadata_constant    (Metadata* obj, Register d);              // uses constant_metadata_address
1152   inline void    set_metadata             (const AddressLiteral& obj_addr, Register d); // same as load_address
1153 
1154   void set_narrow_oop( jobject obj, Register d );
1155   void set_narrow_klass( Klass* k, Register d );
1156 
1157   // nop padding
1158   void align(int modulus);
1159 
1160   // declare a safepoint
1161   void safepoint();
1162 
1163   // factor out part of stop into subroutine to save space
1164   void stop_subroutine();
1165   // factor out part of verify_oop into subroutine to save space
1166   void verify_oop_subroutine();
1167 
1168   // side-door communication with signalHandler in os_solaris.cpp
1169   static address _verify_oop_implicit_branch[3];
1170 
1171   int total_frame_size_in_bytes(int extraWords);
1172 
1173   // used when extraWords known statically
1174   void save_frame(int extraWords = 0);
1175   void save_frame_c1(int size_in_bytes);
1176   // make a frame, and simultaneously pass up one or two register value
1177   // into the new register window
1178   void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
1179 
1180   // give no. (outgoing) params, calc # of words will need on frame
1181   void calc_mem_param_words(Register Rparam_words, Register Rresult);
1182 
1183   // used to calculate frame size dynamically
1184   // result is in bytes and must be negated for save inst
1185   void calc_frame_size(Register extraWords, Register resultReg);
1186 
1187   // calc and also save
1188   void calc_frame_size_and_save(Register extraWords, Register resultReg);
1189 
1190   static void debug(char* msg, RegistersForDebugging* outWindow);
1191 
1192   // implementations of bytecodes used by both interpreter and compiler
1193 
1194   void lcmp( Register Ra_hi, Register Ra_low,
1195              Register Rb_hi, Register Rb_low,
1196              Register Rresult);
1197 
1198   void lneg( Register Rhi, Register Rlow );
1199 
1200   void lshl(  Register Rin_high,  Register Rin_low,  Register Rcount,
1201               Register Rout_high, Register Rout_low, Register Rtemp );
1202 
1203   void lshr(  Register Rin_high,  Register Rin_low,  Register Rcount,
1204               Register Rout_high, Register Rout_low, Register Rtemp );
1205 
1206   void lushr( Register Rin_high,  Register Rin_low,  Register Rcount,
1207               Register Rout_high, Register Rout_low, Register Rtemp );
1208 
1209   void lcmp( Register Ra, Register Rb, Register Rresult);
1210 
1211   // Load and store values by size and signed-ness
1212   void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1213   void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1214 
1215   void float_cmp( bool is_float, int unordered_result,
1216                   FloatRegister Fa, FloatRegister Fb,
1217                   Register Rresult);
1218 
1219   void save_all_globals_into_locals();
1220   void restore_globals_from_locals();
1221 
1222   // These set the icc condition code to equal if the lock succeeded
1223   // and notEqual if it failed and requires a slow case
1224   void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1225                             Register Rscratch,
1226                             BiasedLockingCounters* counters = NULL,
1227                             bool try_bias = UseBiasedLocking);
1228   void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1229                               Register Rscratch,
1230                               bool try_bias = UseBiasedLocking);
1231 
1232   // Biased locking support
1233   // Upon entry, lock_reg must point to the lock record on the stack,
1234   // obj_reg must contain the target object, and mark_reg must contain
1235   // the target object's header.
1236   // Destroys mark_reg if an attempt is made to bias an anonymously
1237   // biased lock. In this case a failure will go either to the slow
1238   // case or fall through with the notEqual condition code set with
1239   // the expectation that the slow case in the runtime will be called.
1240   // In the fall-through case where the CAS-based lock is done,
1241   // mark_reg is not destroyed.
1242   void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
1243                             Label& done, Label* slow_case = NULL,
1244                             BiasedLockingCounters* counters = NULL);
1245   // Upon entry, the base register of mark_addr must contain the oop.
1246   // Destroys temp_reg.
1247 
1248   // If allow_delay_slot_filling is set to true, the next instruction
1249   // emitted after this one will go in an annulled delay slot if the
1250   // biased locking exit case failed.
1251   void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
1252 
1253   // allocation
1254   void eden_allocate(
1255     Register obj,                      // result: pointer to object after successful allocation
1256     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
1257     int      con_size_in_bytes,        // object size in bytes if   known at compile time
1258     Register t1,                       // temp register
1259     Register t2,                       // temp register
1260     Label&   slow_case                 // continuation point if fast allocation fails
1261   );
1262   void tlab_allocate(
1263     Register obj,                      // result: pointer to object after successful allocation
1264     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
1265     int      con_size_in_bytes,        // object size in bytes if   known at compile time
1266     Register t1,                       // temp register
1267     Label&   slow_case                 // continuation point if fast allocation fails
1268   );
1269   void zero_memory(Register base, Register index);
1270   void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
1271                             Register t1, Register t2);
1272 
1273   // interface method calling
1274   void lookup_interface_method(Register recv_klass,
1275                                Register intf_klass,
1276                                RegisterOrConstant itable_index,
1277                                Register method_result,
1278                                Register temp_reg, Register temp2_reg,
1279                                Label& no_such_interface,
1280                                bool return_method = true);
1281 
1282   // virtual method calling
1283   void lookup_virtual_method(Register recv_klass,
1284                              RegisterOrConstant vtable_index,
1285                              Register method_result);
1286 
1287   // Test sub_klass against super_klass, with fast and slow paths.
1288 
1289   // The fast path produces a tri-state answer: yes / no / maybe-slow.
1290   // One of the three labels can be NULL, meaning take the fall-through.
1291   // If super_check_offset is -1, the value is loaded up from super_klass.
1292   // No registers are killed, except temp_reg and temp2_reg.
1293   // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
1294   void check_klass_subtype_fast_path(Register sub_klass,
1295                                      Register super_klass,
1296                                      Register temp_reg,
1297                                      Register temp2_reg,
1298                                      Label* L_success,
1299                                      Label* L_failure,
1300                                      Label* L_slow_path,
1301                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1302 
1303   // The rest of the type check; must be wired to a corresponding fast path.
1304   // It does not repeat the fast path logic, so don't use it standalone.
1305   // The temp_reg can be noreg, if no temps are available.
1306   // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
1307   // Updates the sub's secondary super cache as necessary.
1308   void check_klass_subtype_slow_path(Register sub_klass,
1309                                      Register super_klass,
1310                                      Register temp_reg,
1311                                      Register temp2_reg,
1312                                      Register temp3_reg,
1313                                      Register temp4_reg,
1314                                      Label* L_success,
1315                                      Label* L_failure);
1316 
1317   // Simplified, combined version, good for typical uses.
1318   // Falls through on failure.
1319   void check_klass_subtype(Register sub_klass,
1320                            Register super_klass,
1321                            Register temp_reg,
1322                            Register temp2_reg,
1323                            Label& L_success);
1324 
1325   // method handles (JSR 292)
1326   // offset relative to Gargs of argument at tos[arg_slot].
1327   // (arg_slot == 0 means the last argument, not the first).
1328   RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
1329                                      Register temp_reg,
1330                                      int extra_slot_offset = 0);
1331   // Address of Gargs and argument_offset.
1332   Address            argument_address(RegisterOrConstant arg_slot,
1333                                       Register temp_reg = noreg,
1334                                       int extra_slot_offset = 0);
1335 
1336   // Stack overflow checking
1337 
1338   // Note: this clobbers G3_scratch
1339   inline void bang_stack_with_offset(int offset);
1340 
1341   // Writes to stack successive pages until offset reached to check for
1342   // stack overflow + shadow pages.  Clobbers tsp and scratch registers.
1343   void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
1344 
1345   // Check for reserved stack access in method being exited (for JIT)
1346   void reserved_stack_check();
1347 
1348   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
1349 
1350   void verify_tlab();
1351 
1352   Condition negate_condition(Condition cond);
1353 
1354   // Helper functions for statistics gathering.
1355   // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
1356   void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
1357   // Unconditional increment.
1358   void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
1359   void inc_counter(int*    counter_addr, Register Rtmp1, Register Rtmp2);
1360 
1361 #ifdef COMPILER2
1362   // Compress char[] to byte[] by compressing 16 bytes at once. Return 0 on failure.
1363   void string_compress_16(Register src, Register dst, Register cnt, Register result,
1364                           Register tmp1, Register tmp2, Register tmp3, Register tmp4,
1365                           FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, Label& Ldone);
1366 
1367   // Compress char[] to byte[]. Return 0 on failure.
1368   void string_compress(Register src, Register dst, Register cnt, Register tmp, Register result, Label& Ldone);
1369 
1370   // Inflate byte[] to char[] by inflating 16 bytes at once.
1371   void string_inflate_16(Register src, Register dst, Register cnt, Register tmp,
1372                          FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, FloatRegister ftmp4, Label& Ldone);
1373 
1374   // Inflate byte[] to char[].
1375   void string_inflate(Register src, Register dst, Register cnt, Register tmp, Label& Ldone);
1376 
1377   void string_compare(Register str1, Register str2,
1378                       Register cnt1, Register cnt2,
1379                       Register tmp1, Register tmp2,
1380                       Register result, int ae);
1381 
1382   void array_equals(bool is_array_equ, Register ary1, Register ary2,
1383                     Register limit, Register tmp, Register result, bool is_byte);
1384   // test for negative bytes in input string of a given size, result 0 if none
1385   void has_negatives(Register inp, Register size, Register result,
1386                      Register t2, Register t3, Register t4,
1387                      Register t5);
1388 
1389 #endif
1390 
1391   // Use BIS for zeroing
1392   void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1393 
1394   // Update CRC-32[C] with a byte value according to constants in table
1395   void update_byte_crc32(Register crc, Register val, Register table);
1396 
1397   // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
1398   void reverse_bytes_32(Register src, Register dst, Register tmp);
1399   void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
1400   void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
1401 
1402   // CRC32 code for java.util.zip.CRC32::updateBytes0() intrinsic.
1403   void kernel_crc32(Register crc, Register buf, Register len, Register table);
1404   // Fold 128-bit data chunk
1405   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
1406   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo);
1407   // Fold 8-bit data
1408   void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
1409   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1410   // CRC32C code for java.util.zip.CRC32C::updateBytes/updateDirectByteBuffer intrinsic.
1411   void kernel_crc32c(Register crc, Register buf, Register len, Register table);
1412 
1413 };
1414 
1415 /**
1416  * class SkipIfEqual:
1417  *
1418  * Instantiating this class will result in assembly code being output that will
1419  * jump around any code emitted between the creation of the instance and it's
1420  * automatic destruction at the end of a scope block, depending on the value of
1421  * the flag passed to the constructor, which will be checked at run-time.
1422  */
1423 class SkipIfEqual : public StackObj {
1424  private:
1425   MacroAssembler* _masm;
1426   Label _label;
1427 
1428  public:
1429    // 'temp' is a temp register that this object can use (and trash)
1430    SkipIfEqual(MacroAssembler*, Register temp,
1431                const bool* flag_addr, Assembler::Condition condition);
1432    ~SkipIfEqual();
1433 };
1434 
1435 #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP