1 /* 2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP 26 #define OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP 27 28 #include "runtime/atomic.hpp" 29 #include "runtime/orderAccess.hpp" 30 #include "runtime/os.hpp" 31 32 // Compiler version last used for testing: clang 5.1 33 // Please update this information when this file changes 34 35 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions 36 static inline void compiler_barrier() { 37 __asm__ volatile ("" : : : "memory"); 38 } 39 40 // x86 is TSO and hence only needs a fence for storeload 41 // However, a compiler barrier is still needed to prevent reordering 42 // between volatile and non-volatile memory accesses. 43 44 // Implementation of class OrderAccess. 45 46 inline void OrderAccess::loadload() { compiler_barrier(); } 47 inline void OrderAccess::storestore() { compiler_barrier(); } 48 inline void OrderAccess::loadstore() { compiler_barrier(); } 49 inline void OrderAccess::storeload() { fence(); } 50 51 inline void OrderAccess::acquire() { compiler_barrier(); } 52 inline void OrderAccess::release() { compiler_barrier(); } 53 54 inline void OrderAccess::fence() { 55 if (os::is_MP()) { 56 // always use locked addl since mfence is sometimes expensive 57 #ifdef AMD64 58 __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory"); 59 #else 60 __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory"); 61 #endif 62 } 63 compiler_barrier(); 64 } 65 66 template<> 67 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE> 68 VALUE_OBJ_CLASS_SPEC 69 { 70 template <typename T> 71 void operator()(T v, volatile T* p) const { 72 __asm__ volatile ( "xchgb (%2),%0" 73 : "=q" (v) 74 : "0" (v), "r" (p) 75 : "memory"); 76 } 77 }; 78 79 template<> 80 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE> 81 VALUE_OBJ_CLASS_SPEC 82 { 83 template <typename T> 84 void operator()(T v, volatile T* p) const { 85 __asm__ volatile ( "xchgw (%2),%0" 86 : "=r" (v) 87 : "0" (v), "r" (p) 88 : "memory"); 89 } 90 }; 91 92 template<> 93 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE> 94 VALUE_OBJ_CLASS_SPEC 95 { 96 template <typename T> 97 void operator()(T v, volatile T* p) const { 98 __asm__ volatile ( "xchgl (%2),%0" 99 : "=r" (v) 100 : "0" (v), "r" (p) 101 : "memory"); 102 } 103 }; 104 105 #ifdef AMD64 106 template<> 107 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE> 108 VALUE_OBJ_CLASS_SPEC 109 { 110 template <typename T> 111 void operator()(T v, volatile T* p) const { 112 __asm__ volatile ( "xchgq (%2), %0" 113 : "=r" (v) 114 : "0" (v), "r" (p) 115 : "memory"); 116 } 117 }; 118 #endif // AMD64 119 120 #endif // OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP