58
59 inline void OrderAccess::acquire() { compiler_barrier(); }
60 inline void OrderAccess::release() { compiler_barrier(); }
61
62 inline void OrderAccess::fence() {
63 #ifdef AMD64
64 StubRoutines_fence();
65 #else
66 if (os::is_MP()) {
67 __asm {
68 lock add dword ptr [esp], 0;
69 }
70 }
71 #endif // AMD64
72 compiler_barrier();
73 }
74
75 #ifndef AMD64
76 template<>
77 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE>
78 VALUE_OBJ_CLASS_SPEC
79 {
80 template <typename T>
81 void operator()(T v, volatile T* p) const {
82 __asm {
83 mov edx, p;
84 mov al, v;
85 xchg al, byte ptr [edx];
86 }
87 }
88 };
89
90 template<>
91 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE>
92 VALUE_OBJ_CLASS_SPEC
93 {
94 template <typename T>
95 void operator()(T v, volatile T* p) const {
96 __asm {
97 mov edx, p;
98 mov ax, v;
99 xchg ax, word ptr [edx];
100 }
101 }
102 };
103
104 template<>
105 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE>
106 VALUE_OBJ_CLASS_SPEC
107 {
108 template <typename T>
109 void operator()(T v, volatile T* p) const {
110 __asm {
111 mov edx, p;
112 mov eax, v;
113 xchg eax, dword ptr [edx];
114 }
115 }
116 };
117 #endif // AMD64
118
119 #endif // OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP
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58
59 inline void OrderAccess::acquire() { compiler_barrier(); }
60 inline void OrderAccess::release() { compiler_barrier(); }
61
62 inline void OrderAccess::fence() {
63 #ifdef AMD64
64 StubRoutines_fence();
65 #else
66 if (os::is_MP()) {
67 __asm {
68 lock add dword ptr [esp], 0;
69 }
70 }
71 #endif // AMD64
72 compiler_barrier();
73 }
74
75 #ifndef AMD64
76 template<>
77 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE>
78 {
79 template <typename T>
80 void operator()(T v, volatile T* p) const {
81 __asm {
82 mov edx, p;
83 mov al, v;
84 xchg al, byte ptr [edx];
85 }
86 }
87 };
88
89 template<>
90 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE>
91 {
92 template <typename T>
93 void operator()(T v, volatile T* p) const {
94 __asm {
95 mov edx, p;
96 mov ax, v;
97 xchg ax, word ptr [edx];
98 }
99 }
100 };
101
102 template<>
103 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE>
104 {
105 template <typename T>
106 void operator()(T v, volatile T* p) const {
107 __asm {
108 mov edx, p;
109 mov eax, v;
110 xchg eax, dword ptr [edx];
111 }
112 }
113 };
114 #endif // AMD64
115
116 #endif // OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP
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