1 /*
2 * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
26 #define CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
27
28 #include "code/relocInfo.hpp"
29 #include "code/relocInfo_ext.hpp"
30
31 class BiasedLockingCounters;
32
33 // Introduced AddressLiteral and its subclasses to ease portability from
34 // x86 and avoid relocation issues
35 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
36 RelocationHolder _rspec;
37 // Typically we use AddressLiterals we want to use their rval
38 // However in some situations we want the lval (effect address) of the item.
39 // We provide a special factory for making those lvals.
40 bool _is_lval;
41
42 address _target;
43
44 private:
45 static relocInfo::relocType reloc_for_target(address target) {
46 // Used for ExternalAddress or when the type is not specified
47 // Sometimes ExternalAddress is used for values which aren't
48 // exactly addresses, like the card table base.
49 // external_word_type can't be used for values in the first page
50 // so just skip the reloc in that case.
51 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
52 }
53
54 void set_rspec(relocInfo::relocType rtype);
55
56 protected:
57 // creation
58 AddressLiteral()
59 : _is_lval(false),
60 _target(NULL)
61 {}
62
63 public:
64
65 AddressLiteral(address target, relocInfo::relocType rtype) {
66 _is_lval = false;
67 _target = target;
68 set_rspec(rtype);
69 }
70
71 AddressLiteral(address target, RelocationHolder const& rspec)
72 : _rspec(rspec),
73 _is_lval(false),
74 _target(target)
75 {}
76
77 AddressLiteral(address target) {
78 _is_lval = false;
79 _target = target;
80 set_rspec(reloc_for_target(target));
81 }
82
83 AddressLiteral addr() {
84 AddressLiteral ret = *this;
85 ret._is_lval = true;
86 return ret;
87 }
88
89 private:
90
91 address target() { return _target; }
92 bool is_lval() { return _is_lval; }
93
94 relocInfo::relocType reloc() const { return _rspec.type(); }
95 const RelocationHolder& rspec() const { return _rspec; }
96
97 friend class Assembler;
98 friend class MacroAssembler;
99 friend class Address;
100 friend class LIR_Assembler;
101 friend class InlinedAddress;
102 };
103
104 class ExternalAddress: public AddressLiteral {
105
106 public:
107
108 ExternalAddress(address target) : AddressLiteral(target) {}
109
110 };
111
112 class InternalAddress: public AddressLiteral {
113
114 public:
115
116 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
117
118 };
119
120 // Inlined constants, for use with ldr_literal / bind_literal
121 // Note: InlinedInteger not supported (use move_slow(Register,int[,cond]))
122 class InlinedLiteral: StackObj {
123 public:
124 Label label; // need to be public for direct access with &
125 InlinedLiteral() {
126 }
127 };
128
129 class InlinedMetadata: public InlinedLiteral {
130 private:
131 Metadata *_data;
132
133 public:
134 InlinedMetadata(Metadata *data): InlinedLiteral() {
135 _data = data;
136 }
137 Metadata *data() { return _data; }
138 };
139
140 // Currently unused
141 // class InlinedOop: public InlinedLiteral {
142 // private:
143 // jobject _jobject;
144 //
145 // public:
146 // InlinedOop(jobject target): InlinedLiteral() {
147 // _jobject = target;
148 // }
149 // jobject jobject() { return _jobject; }
150 // };
151
152 class InlinedAddress: public InlinedLiteral {
153 private:
154 AddressLiteral _literal;
155
156 public:
157
158 InlinedAddress(jobject object): InlinedLiteral(), _literal((address)object, relocInfo::oop_type) {
159 ShouldNotReachHere(); // use mov_oop (or implement InlinedOop)
160 }
161
162 InlinedAddress(Metadata *data): InlinedLiteral(), _literal((address)data, relocInfo::metadata_type) {
163 ShouldNotReachHere(); // use InlinedMetadata or mov_metadata
164 }
165
166 InlinedAddress(address target, const RelocationHolder &rspec): InlinedLiteral(), _literal(target, rspec) {
167 assert(rspec.type() != relocInfo::oop_type, "Do not use InlinedAddress for oops");
168 assert(rspec.type() != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");
169 }
170
171 InlinedAddress(address target, relocInfo::relocType rtype): InlinedLiteral(), _literal(target, rtype) {
172 assert(rtype != relocInfo::oop_type, "Do not use InlinedAddress for oops");
173 assert(rtype != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");
174 }
175
176 // Note: default is relocInfo::none for InlinedAddress
177 InlinedAddress(address target): InlinedLiteral(), _literal(target, relocInfo::none) {
178 }
179
180 address target() { return _literal.target(); }
181
182 const RelocationHolder& rspec() const { return _literal.rspec(); }
183 };
184
185 class InlinedString: public InlinedLiteral {
186 private:
187 const char* _msg;
188
189 public:
190 InlinedString(const char* msg): InlinedLiteral() {
191 _msg = msg;
192 }
193 const char* msg() { return _msg; }
194 };
195
196 class MacroAssembler: public Assembler {
197 protected:
198
199 // Support for VM calls
200 //
201
202 // This is the base routine called by the different versions of call_VM_leaf.
203 void call_VM_leaf_helper(address entry_point, int number_of_arguments);
204
205 // This is the base routine called by the different versions of call_VM. The interpreter
206 // may customize this version by overriding it for its purposes (e.g., to save/restore
207 // additional registers when doing a VM call).
208 virtual void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions);
209 public:
210
211 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
212
213 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
214 // The implementation is only non-empty for the InterpreterMacroAssembler,
215 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
216 virtual void check_and_handle_popframe() {}
217 virtual void check_and_handle_earlyret() {}
218
219 // By default, we do not need relocation information for non
220 // patchable absolute addresses. However, when needed by some
221 // extensions, ignore_non_patchable_relocations can be modified,
222 // returning false to preserve all relocation information.
223 inline bool ignore_non_patchable_relocations() { return true; }
224
225 // Initially added to the Assembler interface as a pure virtual:
226 // RegisterConstant delayed_value(..)
227 // for:
228 // 6812678 macro assembler needs delayed binding of a few constants (for 6655638)
229 // this was subsequently modified to its present name and return type
230 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
231
232 #ifdef AARCH64
233 # define NOT_IMPLEMENTED() unimplemented("NYI at " __FILE__ ":" XSTR(__LINE__))
234 # define NOT_TESTED() warn("Not tested at " __FILE__ ":" XSTR(__LINE__))
235 #endif
236
237 void align(int modulus);
238
239 // Support for VM calls
240 //
241 // It is imperative that all calls into the VM are handled via the call_VM methods.
242 // They make sure that the stack linkage is setup correctly. call_VM's correspond
243 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
244
245 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
246 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
247 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
248 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
249
250 // The following methods are required by templateTable.cpp,
251 // but not used on ARM.
252 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
253 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
254 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
255 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
256
257 // Note: The super_call_VM calls are not used on ARM
258
259 // Raw call, without saving/restoring registers, exception handling, etc.
260 // Mainly used from various stubs.
261 // Note: if 'save_R9_if_scratched' is true, call_VM may on some
262 // platforms save values on the stack. Set it to false (and handle
263 // R9 in the callers) if the top of the stack must not be modified
264 // by call_VM.
265 void call_VM(address entry_point, bool save_R9_if_scratched);
266
267 void call_VM_leaf(address entry_point);
268 void call_VM_leaf(address entry_point, Register arg_1);
269 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
270 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
271 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
272
273 void get_vm_result(Register oop_result, Register tmp);
274 void get_vm_result_2(Register metadata_result, Register tmp);
275
276 // Always sets/resets sp, which default to SP if (last_sp == noreg)
277 // Optionally sets/resets fp (use noreg to avoid setting it)
278 // Always sets/resets pc on AArch64; optionally sets/resets pc on 32-bit ARM depending on save_last_java_pc flag
279 // Note: when saving PC, set_last_Java_frame returns PC's offset in the code section
280 // (for oop_maps offset computation)
281 int set_last_Java_frame(Register last_sp, Register last_fp, bool save_last_java_pc, Register tmp);
282 void reset_last_Java_frame(Register tmp);
283 // status set in set_last_Java_frame for reset_last_Java_frame
284 bool _fp_saved;
285 bool _pc_saved;
286
287 #ifdef PRODUCT
288 #define BLOCK_COMMENT(str) /* nothing */
289 #define STOP(error) __ stop(error)
290 #else
291 #define BLOCK_COMMENT(str) __ block_comment(str)
292 #define STOP(error) __ block_comment(error); __ stop(error)
293 #endif
294
295 void lookup_virtual_method(Register recv_klass,
296 Register vtable_index,
297 Register method_result);
298
299 // Test sub_klass against super_klass, with fast and slow paths.
300
301 // The fast path produces a tri-state answer: yes / no / maybe-slow.
302 // One of the three labels can be NULL, meaning take the fall-through.
303 // No registers are killed, except temp_regs.
304 void check_klass_subtype_fast_path(Register sub_klass,
305 Register super_klass,
306 Register temp_reg,
307 Register temp_reg2,
308 Label* L_success,
309 Label* L_failure,
310 Label* L_slow_path);
311
312 // The rest of the type check; must be wired to a corresponding fast path.
313 // It does not repeat the fast path logic, so don't use it standalone.
314 // temp_reg3 can be noreg, if no temps are available.
315 // Updates the sub's secondary super cache as necessary.
316 // If set_cond_codes:
317 // - condition codes will be Z on success, NZ on failure.
318 // - temp_reg will be 0 on success, non-0 on failure
319 void check_klass_subtype_slow_path(Register sub_klass,
320 Register super_klass,
321 Register temp_reg,
322 Register temp_reg2,
323 Register temp_reg3, // auto assigned if noreg
324 Label* L_success,
325 Label* L_failure,
326 bool set_cond_codes = false);
327
328 // Simplified, combined version, good for typical uses.
329 // temp_reg3 can be noreg, if no temps are available. It is used only on slow path.
330 // Falls through on failure.
331 void check_klass_subtype(Register sub_klass,
332 Register super_klass,
333 Register temp_reg,
334 Register temp_reg2,
335 Register temp_reg3, // auto assigned on slow path if noreg
336 Label& L_success);
337
338 // Returns address of receiver parameter, using tmp as base register. tmp and params_count can be the same.
339 Address receiver_argument_address(Register params_base, Register params_count, Register tmp);
340
341 void _verify_oop(Register reg, const char* s, const char* file, int line);
342 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
343
344 // TODO: verify method and klass metadata (compare against vptr?)
345 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
346 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
347
348 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
349 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop ", __FILE__, __LINE__)
350 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
351 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
352
353 void null_check(Register reg, Register tmp, int offset = -1);
354 inline void null_check(Register reg) { null_check(reg, noreg, -1); } // for C1 lir_null_check
355
356 // Puts address of allocated object into register `obj` and end of allocated object into register `obj_end`.
357 void eden_allocate(Register obj, Register obj_end, Register tmp1, Register tmp2,
358 RegisterOrConstant size_expression, Label& slow_case);
359 void tlab_allocate(Register obj, Register obj_end, Register tmp1,
360 RegisterOrConstant size_expression, Label& slow_case);
361
362 void tlab_refill(Register top, Register tmp1, Register tmp2, Register tmp3, Register tmp4,
363 Label& try_eden, Label& slow_case);
364 void zero_memory(Register start, Register end, Register tmp);
365
366 void incr_allocated_bytes(RegisterOrConstant size_in_bytes, Register tmp);
367
368 static bool needs_explicit_null_check(intptr_t offset);
369
370 void arm_stack_overflow_check(int frame_size_in_bytes, Register tmp);
371 void arm_stack_overflow_check(Register Rsize, Register tmp);
372
373 void bang_stack_with_offset(int offset) {
374 ShouldNotReachHere();
375 }
376
377 // Biased locking support
378 // lock_reg and obj_reg must be loaded up with the appropriate values.
379 // swap_reg must be supplied.
380 // tmp_reg must be supplied.
381 // Optional slow case is for implementations (interpreter and C1) which branch to
382 // slow case directly. If slow_case is NULL, then leaves condition
383 // codes set (for C2's Fast_Lock node) and jumps to done label.
384 // Falls through for the fast locking attempt.
385 // Returns offset of first potentially-faulting instruction for null
386 // check info (currently consumed only by C1). If
387 // swap_reg_contains_mark is true then returns -1 as it is assumed
388 // the calling code has already passed any potential faults.
389 // Notes:
390 // - swap_reg and tmp_reg are scratched
391 // - Rtemp was (implicitly) scratched and can now be specified as the tmp2
392 int biased_locking_enter(Register obj_reg, Register swap_reg, Register tmp_reg,
393 bool swap_reg_contains_mark,
394 Register tmp2,
395 Label& done, Label& slow_case,
396 BiasedLockingCounters* counters = NULL);
397 void biased_locking_exit(Register obj_reg, Register temp_reg, Label& done);
398
399 // Building block for CAS cases of biased locking: makes CAS and records statistics.
400 // Optional slow_case label is used to transfer control if CAS fails. Otherwise leaves condition codes set.
401 void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
402 Register tmp, Label& slow_case, int* counter_addr);
403
404 void resolve_jobject(Register value, Register tmp1, Register tmp2);
405
406 #if INCLUDE_ALL_GCS
407 // G1 pre-barrier.
408 // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
409 // If store_addr != noreg, then previous value is loaded from [store_addr];
410 // in such case store_addr and new_val registers are preserved;
411 // otherwise pre_val register is preserved.
412 void g1_write_barrier_pre(Register store_addr,
413 Register new_val,
414 Register pre_val,
415 Register tmp1,
416 Register tmp2);
417
418 // G1 post-barrier.
419 // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
420 void g1_write_barrier_post(Register store_addr,
421 Register new_val,
422 Register tmp1,
423 Register tmp2,
424 Register tmp3);
425 #endif // INCLUDE_ALL_GCS
426
427 #ifndef AARCH64
428 void nop() {
429 mov(R0, R0);
430 }
431
432 void push(Register rd, AsmCondition cond = al) {
433 assert(rd != SP, "unpredictable instruction");
434 str(rd, Address(SP, -wordSize, pre_indexed), cond);
435 }
436
437 void push(RegisterSet reg_set, AsmCondition cond = al) {
438 assert(!reg_set.contains(SP), "unpredictable instruction");
439 stmdb(SP, reg_set, writeback, cond);
440 }
441
442 void pop(Register rd, AsmCondition cond = al) {
443 assert(rd != SP, "unpredictable instruction");
444 ldr(rd, Address(SP, wordSize, post_indexed), cond);
445 }
446
447 void pop(RegisterSet reg_set, AsmCondition cond = al) {
448 assert(!reg_set.contains(SP), "unpredictable instruction");
449 ldmia(SP, reg_set, writeback, cond);
450 }
451
452 void fpushd(FloatRegister fd, AsmCondition cond = al) {
453 fstmdbd(SP, FloatRegisterSet(fd), writeback, cond);
454 }
455
456 void fpushs(FloatRegister fd, AsmCondition cond = al) {
457 fstmdbs(SP, FloatRegisterSet(fd), writeback, cond);
458 }
459
460 void fpopd(FloatRegister fd, AsmCondition cond = al) {
461 fldmiad(SP, FloatRegisterSet(fd), writeback, cond);
462 }
463
464 void fpops(FloatRegister fd, AsmCondition cond = al) {
465 fldmias(SP, FloatRegisterSet(fd), writeback, cond);
466 }
467 #endif // !AARCH64
468
469 // Order access primitives
470 enum Membar_mask_bits {
471 StoreStore = 1 << 3,
472 LoadStore = 1 << 2,
473 StoreLoad = 1 << 1,
474 LoadLoad = 1 << 0
475 };
476
477 #ifdef AARCH64
478 // tmp register is not used on AArch64, this parameter is provided solely for better compatibility with 32-bit ARM
479 void membar(Membar_mask_bits order_constraint, Register tmp = noreg);
480 #else
481 void membar(Membar_mask_bits mask,
482 Register tmp,
483 bool preserve_flags = true,
484 Register load_tgt = noreg);
485 #endif
486
487 void breakpoint(AsmCondition cond = al);
488 void stop(const char* msg);
489 // prints msg and continues
490 void warn(const char* msg);
491 void unimplemented(const char* what = "");
492 void should_not_reach_here() { stop("should not reach here"); }
493 static void debug(const char* msg, const intx* registers);
494
495 // Create a walkable frame to help tracking down who called this code.
496 // Returns the frame size in words.
497 int should_not_call_this() {
498 raw_push(FP, LR);
499 should_not_reach_here();
500 flush();
501 return 2; // frame_size_in_words (FP+LR)
502 }
503
504 int save_all_registers();
505 void restore_all_registers();
506 int save_caller_save_registers();
507 void restore_caller_save_registers();
508
509 void add_rc(Register dst, Register arg1, RegisterOrConstant arg2);
510
511 // add_slow and mov_slow are used to manipulate offsets larger than 1024,
512 // these functions are not expected to handle all possible constants,
513 // only those that can really occur during compilation
514 void add_slow(Register rd, Register rn, int c);
515 void sub_slow(Register rd, Register rn, int c);
516
517 #ifdef AARCH64
518 static int mov_slow_helper(Register rd, intptr_t c, MacroAssembler* masm /* optional */);
519 #endif
520
521 void mov_slow(Register rd, intptr_t c NOT_AARCH64_ARG(AsmCondition cond = al));
522 void mov_slow(Register rd, const char *string);
523 void mov_slow(Register rd, address addr);
524
525 void patchable_mov_oop(Register rd, jobject o, int oop_index) {
526 mov_oop(rd, o, oop_index AARCH64_ONLY_ARG(true));
527 }
528 void mov_oop(Register rd, jobject o, int index = 0
529 AARCH64_ONLY_ARG(bool patchable = false)
530 NOT_AARCH64_ARG(AsmCondition cond = al));
531
532
533 void patchable_mov_metadata(Register rd, Metadata* o, int index) {
534 mov_metadata(rd, o, index AARCH64_ONLY_ARG(true));
535 }
536 void mov_metadata(Register rd, Metadata* o, int index = 0 AARCH64_ONLY_ARG(bool patchable = false));
537
538 void mov_float(FloatRegister fd, jfloat c NOT_AARCH64_ARG(AsmCondition cond = al));
539 void mov_double(FloatRegister fd, jdouble c NOT_AARCH64_ARG(AsmCondition cond = al));
540
541 #ifdef AARCH64
542 int mov_pc_to(Register rd) {
543 Label L;
544 adr(rd, L);
545 bind(L);
546 return offset();
547 }
548 #endif
549
550 // Note: this variant of mov_address assumes the address moves with
551 // the code. Do *not* implement it with non-relocated instructions,
552 // unless PC-relative.
553 #ifdef AARCH64
554 void mov_relative_address(Register rd, address addr) {
555 adr(rd, addr);
556 }
557 #else
558 void mov_relative_address(Register rd, address addr, AsmCondition cond = al) {
559 int offset = addr - pc() - 8;
560 assert((offset & 3) == 0, "bad alignment");
561 if (offset >= 0) {
562 assert(AsmOperand::is_rotated_imm(offset), "addr too far");
563 add(rd, PC, offset, cond);
564 } else {
565 assert(AsmOperand::is_rotated_imm(-offset), "addr too far");
566 sub(rd, PC, -offset, cond);
567 }
568 }
569 #endif // AARCH64
570
571 // Runtime address that may vary from one execution to another. The
572 // symbolic_reference describes what the address is, allowing
573 // the address to be resolved in a different execution context.
574 // Warning: do not implement as a PC relative address.
575 void mov_address(Register rd, address addr, symbolic_Relocation::symbolic_reference t) {
576 mov_address(rd, addr, RelocationHolder::none);
577 }
578
579 // rspec can be RelocationHolder::none (for ignored symbolic_Relocation).
580 // In that case, the address is absolute and the generated code need
581 // not be relocable.
582 void mov_address(Register rd, address addr, RelocationHolder const& rspec) {
583 assert(rspec.type() != relocInfo::runtime_call_type, "do not use mov_address for runtime calls");
584 assert(rspec.type() != relocInfo::static_call_type, "do not use mov_address for relocable calls");
585 if (rspec.type() == relocInfo::none) {
586 // absolute address, relocation not needed
587 mov_slow(rd, (intptr_t)addr);
588 return;
589 }
590 #ifndef AARCH64
591 if (VM_Version::supports_movw()) {
592 relocate(rspec);
593 int c = (int)addr;
594 movw(rd, c & 0xffff);
595 if ((unsigned int)c >> 16) {
596 movt(rd, (unsigned int)c >> 16);
597 }
598 return;
599 }
600 #endif
601 Label skip_literal;
602 InlinedAddress addr_literal(addr, rspec);
603 ldr_literal(rd, addr_literal);
604 b(skip_literal);
605 bind_literal(addr_literal);
606 // AARCH64 WARNING: because of alignment padding, extra padding
607 // may be required to get a consistent size for C2, or rules must
608 // overestimate size see MachEpilogNode::size
609 bind(skip_literal);
610 }
611
612 // Note: Do not define mov_address for a Label
613 //
614 // Load from addresses potentially within the code are now handled
615 // InlinedLiteral subclasses (to allow more flexibility on how the
616 // ldr_literal is performed).
617
618 void ldr_literal(Register rd, InlinedAddress& L) {
619 assert(L.rspec().type() != relocInfo::runtime_call_type, "avoid ldr_literal for calls");
620 assert(L.rspec().type() != relocInfo::static_call_type, "avoid ldr_literal for calls");
621 relocate(L.rspec());
622 #ifdef AARCH64
623 ldr(rd, target(L.label));
624 #else
625 ldr(rd, Address(PC, target(L.label) - pc() - 8));
626 #endif
627 }
628
629 void ldr_literal(Register rd, InlinedString& L) {
630 const char* msg = L.msg();
631 if (code()->consts()->contains((address)msg)) {
632 // string address moves with the code
633 #ifdef AARCH64
634 ldr(rd, (address)msg);
635 #else
636 ldr(rd, Address(PC, ((address)msg) - pc() - 8));
637 #endif
638 return;
639 }
640 // Warning: use external strings with care. They are not relocated
641 // if the code moves. If needed, use code_string to move them
642 // to the consts section.
643 #ifdef AARCH64
644 ldr(rd, target(L.label));
645 #else
646 ldr(rd, Address(PC, target(L.label) - pc() - 8));
647 #endif
648 }
649
650 void ldr_literal(Register rd, InlinedMetadata& L) {
651 // relocation done in the bind_literal for metadatas
652 #ifdef AARCH64
653 ldr(rd, target(L.label));
654 #else
655 ldr(rd, Address(PC, target(L.label) - pc() - 8));
656 #endif
657 }
658
659 void bind_literal(InlinedAddress& L) {
660 AARCH64_ONLY(align(wordSize));
661 bind(L.label);
662 assert(L.rspec().type() != relocInfo::metadata_type, "Must use InlinedMetadata");
663 // We currently do not use oop 'bound' literals.
664 // If the code evolves and the following assert is triggered,
665 // we need to implement InlinedOop (see InlinedMetadata).
666 assert(L.rspec().type() != relocInfo::oop_type, "Inlined oops not supported");
667 // Note: relocation is handled by relocate calls in ldr_literal
668 AbstractAssembler::emit_address((address)L.target());
669 }
670
671 void bind_literal(InlinedString& L) {
672 const char* msg = L.msg();
673 if (code()->consts()->contains((address)msg)) {
674 // The Label should not be used; avoid binding it
675 // to detect errors.
676 return;
677 }
678 AARCH64_ONLY(align(wordSize));
679 bind(L.label);
680 AbstractAssembler::emit_address((address)L.msg());
681 }
682
683 void bind_literal(InlinedMetadata& L) {
684 AARCH64_ONLY(align(wordSize));
685 bind(L.label);
686 relocate(metadata_Relocation::spec_for_immediate());
687 AbstractAssembler::emit_address((address)L.data());
688 }
689
690 void resolve_oop_handle(Register result);
691 void load_mirror(Register mirror, Register method, Register tmp);
692
693 // Porting layer between 32-bit ARM and AArch64
694
695 #define COMMON_INSTR_1(common_mnemonic, aarch64_mnemonic, arm32_mnemonic, arg_type) \
696 void common_mnemonic(arg_type arg) { \
697 AARCH64_ONLY(aarch64_mnemonic) NOT_AARCH64(arm32_mnemonic) (arg); \
698 }
699
700 #define COMMON_INSTR_2(common_mnemonic, aarch64_mnemonic, arm32_mnemonic, arg1_type, arg2_type) \
701 void common_mnemonic(arg1_type arg1, arg2_type arg2) { \
702 AARCH64_ONLY(aarch64_mnemonic) NOT_AARCH64(arm32_mnemonic) (arg1, arg2); \
703 }
704
705 #define COMMON_INSTR_3(common_mnemonic, aarch64_mnemonic, arm32_mnemonic, arg1_type, arg2_type, arg3_type) \
706 void common_mnemonic(arg1_type arg1, arg2_type arg2, arg3_type arg3) { \
707 AARCH64_ONLY(aarch64_mnemonic) NOT_AARCH64(arm32_mnemonic) (arg1, arg2, arg3); \
708 }
709
710 COMMON_INSTR_1(jump, br, bx, Register)
711 COMMON_INSTR_1(call, blr, blx, Register)
712
713 COMMON_INSTR_2(cbz_32, cbz_w, cbz, Register, Label&)
714 COMMON_INSTR_2(cbnz_32, cbnz_w, cbnz, Register, Label&)
715
716 COMMON_INSTR_2(ldr_u32, ldr_w, ldr, Register, Address)
717 COMMON_INSTR_2(ldr_s32, ldrsw, ldr, Register, Address)
718 COMMON_INSTR_2(str_32, str_w, str, Register, Address)
719
720 COMMON_INSTR_2(mvn_32, mvn_w, mvn, Register, Register)
721 COMMON_INSTR_2(cmp_32, cmp_w, cmp, Register, Register)
722 COMMON_INSTR_2(neg_32, neg_w, neg, Register, Register)
723 COMMON_INSTR_2(clz_32, clz_w, clz, Register, Register)
724 COMMON_INSTR_2(rbit_32, rbit_w, rbit, Register, Register)
725
726 COMMON_INSTR_2(cmp_32, cmp_w, cmp, Register, int)
727 COMMON_INSTR_2(cmn_32, cmn_w, cmn, Register, int)
728
729 COMMON_INSTR_3(add_32, add_w, add, Register, Register, Register)
730 COMMON_INSTR_3(sub_32, sub_w, sub, Register, Register, Register)
731 COMMON_INSTR_3(subs_32, subs_w, subs, Register, Register, Register)
732 COMMON_INSTR_3(mul_32, mul_w, mul, Register, Register, Register)
733 COMMON_INSTR_3(and_32, andr_w, andr, Register, Register, Register)
734 COMMON_INSTR_3(orr_32, orr_w, orr, Register, Register, Register)
735 COMMON_INSTR_3(eor_32, eor_w, eor, Register, Register, Register)
736
737 COMMON_INSTR_3(add_32, add_w, add, Register, Register, AsmOperand)
738 COMMON_INSTR_3(sub_32, sub_w, sub, Register, Register, AsmOperand)
739 COMMON_INSTR_3(orr_32, orr_w, orr, Register, Register, AsmOperand)
740 COMMON_INSTR_3(eor_32, eor_w, eor, Register, Register, AsmOperand)
741 COMMON_INSTR_3(and_32, andr_w, andr, Register, Register, AsmOperand)
742
743
744 COMMON_INSTR_3(add_32, add_w, add, Register, Register, int)
745 COMMON_INSTR_3(adds_32, adds_w, adds, Register, Register, int)
746 COMMON_INSTR_3(sub_32, sub_w, sub, Register, Register, int)
747 COMMON_INSTR_3(subs_32, subs_w, subs, Register, Register, int)
748
749 COMMON_INSTR_2(tst_32, tst_w, tst, Register, unsigned int)
750 COMMON_INSTR_2(tst_32, tst_w, tst, Register, AsmOperand)
751
752 COMMON_INSTR_3(and_32, andr_w, andr, Register, Register, uint)
753 COMMON_INSTR_3(orr_32, orr_w, orr, Register, Register, uint)
754 COMMON_INSTR_3(eor_32, eor_w, eor, Register, Register, uint)
755
756 COMMON_INSTR_1(cmp_zero_float, fcmp0_s, fcmpzs, FloatRegister)
757 COMMON_INSTR_1(cmp_zero_double, fcmp0_d, fcmpzd, FloatRegister)
758
759 COMMON_INSTR_2(ldr_float, ldr_s, flds, FloatRegister, Address)
760 COMMON_INSTR_2(str_float, str_s, fsts, FloatRegister, Address)
761 COMMON_INSTR_2(mov_float, fmov_s, fcpys, FloatRegister, FloatRegister)
762 COMMON_INSTR_2(neg_float, fneg_s, fnegs, FloatRegister, FloatRegister)
763 COMMON_INSTR_2(abs_float, fabs_s, fabss, FloatRegister, FloatRegister)
764 COMMON_INSTR_2(sqrt_float, fsqrt_s, fsqrts, FloatRegister, FloatRegister)
765 COMMON_INSTR_2(cmp_float, fcmp_s, fcmps, FloatRegister, FloatRegister)
766
767 COMMON_INSTR_3(add_float, fadd_s, fadds, FloatRegister, FloatRegister, FloatRegister)
768 COMMON_INSTR_3(sub_float, fsub_s, fsubs, FloatRegister, FloatRegister, FloatRegister)
769 COMMON_INSTR_3(mul_float, fmul_s, fmuls, FloatRegister, FloatRegister, FloatRegister)
770 COMMON_INSTR_3(div_float, fdiv_s, fdivs, FloatRegister, FloatRegister, FloatRegister)
771
772 COMMON_INSTR_2(ldr_double, ldr_d, fldd, FloatRegister, Address)
773 COMMON_INSTR_2(str_double, str_d, fstd, FloatRegister, Address)
774 COMMON_INSTR_2(mov_double, fmov_d, fcpyd, FloatRegister, FloatRegister)
775 COMMON_INSTR_2(neg_double, fneg_d, fnegd, FloatRegister, FloatRegister)
776 COMMON_INSTR_2(cmp_double, fcmp_d, fcmpd, FloatRegister, FloatRegister)
777 COMMON_INSTR_2(abs_double, fabs_d, fabsd, FloatRegister, FloatRegister)
778 COMMON_INSTR_2(sqrt_double, fsqrt_d, fsqrtd, FloatRegister, FloatRegister)
779
780 COMMON_INSTR_3(add_double, fadd_d, faddd, FloatRegister, FloatRegister, FloatRegister)
781 COMMON_INSTR_3(sub_double, fsub_d, fsubd, FloatRegister, FloatRegister, FloatRegister)
782 COMMON_INSTR_3(mul_double, fmul_d, fmuld, FloatRegister, FloatRegister, FloatRegister)
783 COMMON_INSTR_3(div_double, fdiv_d, fdivd, FloatRegister, FloatRegister, FloatRegister)
784
785 COMMON_INSTR_2(convert_f2d, fcvt_ds, fcvtds, FloatRegister, FloatRegister)
786 COMMON_INSTR_2(convert_d2f, fcvt_sd, fcvtsd, FloatRegister, FloatRegister)
787
788 COMMON_INSTR_2(mov_fpr2gpr_float, fmov_ws, fmrs, Register, FloatRegister)
789
790 #undef COMMON_INSTR_1
791 #undef COMMON_INSTR_2
792 #undef COMMON_INSTR_3
793
794
795 #ifdef AARCH64
796
797 void mov(Register dst, Register src, AsmCondition cond) {
798 if (cond == al) {
799 mov(dst, src);
800 } else {
801 csel(dst, src, dst, cond);
802 }
803 }
804
805 // Propagate other overloaded "mov" methods from Assembler.
806 void mov(Register dst, Register src) { Assembler::mov(dst, src); }
807 void mov(Register rd, int imm) { Assembler::mov(rd, imm); }
808
809 void mov(Register dst, int imm, AsmCondition cond) {
810 assert(imm == 0 || imm == 1, "");
811 if (imm == 0) {
812 mov(dst, ZR, cond);
813 } else if (imm == 1) {
814 csinc(dst, dst, ZR, inverse(cond));
815 } else if (imm == -1) {
816 csinv(dst, dst, ZR, inverse(cond));
817 } else {
818 fatal("illegal mov(R%d,%d,cond)", dst->encoding(), imm);
819 }
820 }
821
822 void movs(Register dst, Register src) { adds(dst, src, 0); }
823
824 #else // AARCH64
825
826 void tbz(Register rt, int bit, Label& L) {
827 assert(0 <= bit && bit < BitsPerWord, "bit number is out of range");
828 tst(rt, 1 << bit);
829 b(L, eq);
830 }
831
832 void tbnz(Register rt, int bit, Label& L) {
833 assert(0 <= bit && bit < BitsPerWord, "bit number is out of range");
834 tst(rt, 1 << bit);
835 b(L, ne);
836 }
837
838 void cbz(Register rt, Label& L) {
839 cmp(rt, 0);
840 b(L, eq);
841 }
842
843 void cbz(Register rt, address target) {
844 cmp(rt, 0);
845 b(target, eq);
846 }
847
848 void cbnz(Register rt, Label& L) {
849 cmp(rt, 0);
850 b(L, ne);
851 }
852
853 void ret(Register dst = LR) {
854 bx(dst);
855 }
856
857 #endif // AARCH64
858
859 Register zero_register(Register tmp) {
860 #ifdef AARCH64
861 return ZR;
862 #else
863 mov(tmp, 0);
864 return tmp;
865 #endif
866 }
867
868 void logical_shift_left(Register dst, Register src, int shift) {
869 #ifdef AARCH64
870 _lsl(dst, src, shift);
871 #else
872 mov(dst, AsmOperand(src, lsl, shift));
873 #endif
874 }
875
876 void logical_shift_left_32(Register dst, Register src, int shift) {
877 #ifdef AARCH64
878 _lsl_w(dst, src, shift);
879 #else
880 mov(dst, AsmOperand(src, lsl, shift));
881 #endif
882 }
883
884 void logical_shift_right(Register dst, Register src, int shift) {
885 #ifdef AARCH64
886 _lsr(dst, src, shift);
887 #else
888 mov(dst, AsmOperand(src, lsr, shift));
889 #endif
890 }
891
892 void arith_shift_right(Register dst, Register src, int shift) {
893 #ifdef AARCH64
894 _asr(dst, src, shift);
895 #else
896 mov(dst, AsmOperand(src, asr, shift));
897 #endif
898 }
899
900 void asr_32(Register dst, Register src, int shift) {
901 #ifdef AARCH64
902 _asr_w(dst, src, shift);
903 #else
904 mov(dst, AsmOperand(src, asr, shift));
905 #endif
906 }
907
908 // If <cond> holds, compares r1 and r2. Otherwise, flags are set so that <cond> does not hold.
909 void cond_cmp(Register r1, Register r2, AsmCondition cond) {
910 #ifdef AARCH64
911 ccmp(r1, r2, flags_for_condition(inverse(cond)), cond);
912 #else
913 cmp(r1, r2, cond);
914 #endif
915 }
916
917 // If <cond> holds, compares r and imm. Otherwise, flags are set so that <cond> does not hold.
918 void cond_cmp(Register r, int imm, AsmCondition cond) {
919 #ifdef AARCH64
920 ccmp(r, imm, flags_for_condition(inverse(cond)), cond);
921 #else
922 cmp(r, imm, cond);
923 #endif
924 }
925
926 void align_reg(Register dst, Register src, int align) {
927 assert (is_power_of_2(align), "should be");
928 #ifdef AARCH64
929 andr(dst, src, ~(uintx)(align-1));
930 #else
931 bic(dst, src, align-1);
932 #endif
933 }
934
935 void prefetch_read(Address addr) {
936 #ifdef AARCH64
937 prfm(pldl1keep, addr);
938 #else
939 pld(addr);
940 #endif
941 }
942
943 void raw_push(Register r1, Register r2) {
944 #ifdef AARCH64
945 stp(r1, r2, Address(SP, -2*wordSize, pre_indexed));
946 #else
947 assert(r1->encoding() < r2->encoding(), "should be ordered");
948 push(RegisterSet(r1) | RegisterSet(r2));
949 #endif
950 }
951
952 void raw_pop(Register r1, Register r2) {
953 #ifdef AARCH64
954 ldp(r1, r2, Address(SP, 2*wordSize, post_indexed));
955 #else
956 assert(r1->encoding() < r2->encoding(), "should be ordered");
957 pop(RegisterSet(r1) | RegisterSet(r2));
958 #endif
959 }
960
961 void raw_push(Register r1, Register r2, Register r3) {
962 #ifdef AARCH64
963 raw_push(r1, r2);
964 raw_push(r3, ZR);
965 #else
966 assert(r1->encoding() < r2->encoding() && r2->encoding() < r3->encoding(), "should be ordered");
967 push(RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3));
968 #endif
969 }
970
971 void raw_pop(Register r1, Register r2, Register r3) {
972 #ifdef AARCH64
973 raw_pop(r3, ZR);
974 raw_pop(r1, r2);
975 #else
976 assert(r1->encoding() < r2->encoding() && r2->encoding() < r3->encoding(), "should be ordered");
977 pop(RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3));
978 #endif
979 }
980
981 // Restores registers r1 and r2 previously saved by raw_push(r1, r2, ret_addr) and returns by ret_addr. Clobbers LR.
982 void raw_pop_and_ret(Register r1, Register r2) {
983 #ifdef AARCH64
984 raw_pop(r1, r2, LR);
985 ret();
986 #else
987 raw_pop(r1, r2, PC);
988 #endif
989 }
990
991 void indirect_jump(Address addr, Register scratch) {
992 #ifdef AARCH64
993 ldr(scratch, addr);
994 br(scratch);
995 #else
996 ldr(PC, addr);
997 #endif
998 }
999
1000 void indirect_jump(InlinedAddress& literal, Register scratch) {
1001 #ifdef AARCH64
1002 ldr_literal(scratch, literal);
1003 br(scratch);
1004 #else
1005 ldr_literal(PC, literal);
1006 #endif
1007 }
1008
1009 #ifndef AARCH64
1010 void neg(Register dst, Register src) {
1011 rsb(dst, src, 0);
1012 }
1013 #endif
1014
1015 void branch_if_negative_32(Register r, Label& L) {
1016 // Note about branch_if_negative_32() / branch_if_any_negative_32() implementation for AArch64:
1017 // tbnz is not used instead of tst & b.mi because destination may be out of tbnz range (+-32KB)
1018 // since these methods are used in LIR_Assembler::emit_arraycopy() to jump to stub entry.
1019 tst_32(r, r);
1020 b(L, mi);
1021 }
1022
1023 void branch_if_any_negative_32(Register r1, Register r2, Register tmp, Label& L) {
1024 #ifdef AARCH64
1025 orr_32(tmp, r1, r2);
1026 tst_32(tmp, tmp);
1027 #else
1028 orrs(tmp, r1, r2);
1029 #endif
1030 b(L, mi);
1031 }
1032
1033 void branch_if_any_negative_32(Register r1, Register r2, Register r3, Register tmp, Label& L) {
1034 orr_32(tmp, r1, r2);
1035 #ifdef AARCH64
1036 orr_32(tmp, tmp, r3);
1037 tst_32(tmp, tmp);
1038 #else
1039 orrs(tmp, tmp, r3);
1040 #endif
1041 b(L, mi);
1042 }
1043
1044 void add_ptr_scaled_int32(Register dst, Register r1, Register r2, int shift) {
1045 #ifdef AARCH64
1046 add(dst, r1, r2, ex_sxtw, shift);
1047 #else
1048 add(dst, r1, AsmOperand(r2, lsl, shift));
1049 #endif
1050 }
1051
1052 void sub_ptr_scaled_int32(Register dst, Register r1, Register r2, int shift) {
1053 #ifdef AARCH64
1054 sub(dst, r1, r2, ex_sxtw, shift);
1055 #else
1056 sub(dst, r1, AsmOperand(r2, lsl, shift));
1057 #endif
1058 }
1059
1060
1061 // klass oop manipulations if compressed
1062
1063 #ifdef AARCH64
1064 void load_klass(Register dst_klass, Register src_oop);
1065 #else
1066 void load_klass(Register dst_klass, Register src_oop, AsmCondition cond = al);
1067 #endif // AARCH64
1068
1069 void store_klass(Register src_klass, Register dst_oop);
1070
1071 #ifdef AARCH64
1072 void store_klass_gap(Register dst);
1073 #endif // AARCH64
1074
1075 // oop manipulations
1076
1077 void load_heap_oop(Register dst, Address src);
1078 void store_heap_oop(Register src, Address dst);
1079 void store_heap_oop(Address dst, Register src) {
1080 store_heap_oop(src, dst);
1081 }
1082 void store_heap_oop_null(Register src, Address dst);
1083
1084 #ifdef AARCH64
1085 void encode_heap_oop(Register dst, Register src);
1086 void encode_heap_oop(Register r) {
1087 encode_heap_oop(r, r);
1088 }
1089 void decode_heap_oop(Register dst, Register src);
1090 void decode_heap_oop(Register r) {
1091 decode_heap_oop(r, r);
1092 }
1093
1094 #ifdef COMPILER2
1095 void encode_heap_oop_not_null(Register dst, Register src);
1096 void decode_heap_oop_not_null(Register dst, Register src);
1097
1098 void set_narrow_klass(Register dst, Klass* k);
1099 void set_narrow_oop(Register dst, jobject obj);
1100 #endif
1101
1102 void encode_klass_not_null(Register r);
1103 void encode_klass_not_null(Register dst, Register src);
1104 void decode_klass_not_null(Register r);
1105 void decode_klass_not_null(Register dst, Register src);
1106
1107 void reinit_heapbase();
1108
1109 #ifdef ASSERT
1110 void verify_heapbase(const char* msg);
1111 #endif // ASSERT
1112
1113 static int instr_count_for_mov_slow(intptr_t c);
1114 static int instr_count_for_mov_slow(address addr);
1115 static int instr_count_for_decode_klass_not_null();
1116 #endif // AARCH64
1117
1118 void ldr_global_ptr(Register reg, address address_of_global);
1119 void ldr_global_s32(Register reg, address address_of_global);
1120 void ldrb_global(Register reg, address address_of_global);
1121
1122 // address_placeholder_instruction is invalid instruction and is used
1123 // as placeholder in code for address of label
1124 enum { address_placeholder_instruction = 0xFFFFFFFF };
1125
1126 void emit_address(Label& L) {
1127 assert(!L.is_bound(), "otherwise address will not be patched");
1128 target(L); // creates relocation which will be patched later
1129
1130 assert ((offset() & (wordSize-1)) == 0, "should be aligned by word size");
1131
1132 #ifdef AARCH64
1133 emit_int32(address_placeholder_instruction);
1134 emit_int32(address_placeholder_instruction);
1135 #else
1136 AbstractAssembler::emit_address((address)address_placeholder_instruction);
1137 #endif
1138 }
1139
1140 void b(address target, AsmCondition cond = al) {
1141 Assembler::b(target, cond); \
1142 }
1143 void b(Label& L, AsmCondition cond = al) {
1144 // internal jumps
1145 Assembler::b(target(L), cond);
1146 }
1147
1148 void bl(address target NOT_AARCH64_ARG(AsmCondition cond = al)) {
1149 Assembler::bl(target NOT_AARCH64_ARG(cond));
1150 }
1151 void bl(Label& L NOT_AARCH64_ARG(AsmCondition cond = al)) {
1152 // internal calls
1153 Assembler::bl(target(L) NOT_AARCH64_ARG(cond));
1154 }
1155
1156 #ifndef AARCH64
1157 void adr(Register dest, Label& L, AsmCondition cond = al) {
1158 int delta = target(L) - pc() - 8;
1159 if (delta >= 0) {
1160 add(dest, PC, delta, cond);
1161 } else {
1162 sub(dest, PC, -delta, cond);
1163 }
1164 }
1165 #endif // !AARCH64
1166
1167 // Variable-length jump and calls. We now distinguish only the
1168 // patchable case from the other cases. Patchable must be
1169 // distinguised from relocable. Relocable means the generated code
1170 // containing the jump/call may move. Patchable means that the
1171 // targeted address may be changed later.
1172
1173 // Non patchable versions.
1174 // - used only for relocInfo::runtime_call_type and relocInfo::none
1175 // - may use relative or absolute format (do not use relocInfo::none
1176 // if the generated code may move)
1177 // - the implementation takes into account switch to THUMB mode if the
1178 // destination is a THUMB address
1179 // - the implementation supports far targets
1180 //
1181 // To reduce regression risk, scratch still defaults to noreg on
1182 // arm32. This results in patchable instructions. However, if
1183 // patching really matters, the call sites should be modified and
1184 // use patchable_call or patchable_jump. If patching is not required
1185 // and if a register can be cloberred, it should be explicitly
1186 // specified to allow future optimizations.
1187 void jump(address target,
1188 relocInfo::relocType rtype = relocInfo::runtime_call_type,
1189 Register scratch = AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg)
1190 #ifndef AARCH64
1191 , AsmCondition cond = al
1192 #endif
1193 );
1194
1195 void call(address target,
1196 RelocationHolder rspec
1197 NOT_AARCH64_ARG(AsmCondition cond = al));
1198
1199 void call(address target,
1200 relocInfo::relocType rtype = relocInfo::runtime_call_type
1201 NOT_AARCH64_ARG(AsmCondition cond = al)) {
1202 call(target, Relocation::spec_simple(rtype) NOT_AARCH64_ARG(cond));
1203 }
1204
1205 void jump(AddressLiteral dest) {
1206 jump(dest.target(), dest.reloc());
1207 }
1208 #ifndef AARCH64
1209 void jump(address dest, relocInfo::relocType rtype, AsmCondition cond) {
1210 jump(dest, rtype, Rtemp, cond);
1211 }
1212 #endif
1213
1214 void call(AddressLiteral dest) {
1215 call(dest.target(), dest.reloc());
1216 }
1217
1218 // Patchable version:
1219 // - set_destination can be used to atomically change the target
1220 //
1221 // The targets for patchable_jump and patchable_call must be in the
1222 // code cache.
1223 // [ including possible extensions of the code cache, like AOT code ]
1224 //
1225 // To reduce regression risk, scratch still defaults to noreg on
1226 // arm32. If a register can be cloberred, it should be explicitly
1227 // specified to allow future optimizations.
1228 void patchable_jump(address target,
1229 relocInfo::relocType rtype = relocInfo::runtime_call_type,
1230 Register scratch = AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg)
1231 #ifndef AARCH64
1232 , AsmCondition cond = al
1233 #endif
1234 );
1235
1236 // patchable_call may scratch Rtemp
1237 int patchable_call(address target,
1238 RelocationHolder const& rspec,
1239 bool c2 = false);
1240
1241 int patchable_call(address target,
1242 relocInfo::relocType rtype,
1243 bool c2 = false) {
1244 return patchable_call(target, Relocation::spec_simple(rtype), c2);
1245 }
1246
1247 #if defined(AARCH64) && defined(COMPILER2)
1248 static int call_size(address target, bool far, bool patchable);
1249 #endif
1250
1251 #ifdef AARCH64
1252 static bool page_reachable_from_cache(address target);
1253 #endif
1254 static bool _reachable_from_cache(address target);
1255 static bool _cache_fully_reachable();
1256 bool cache_fully_reachable();
1257 bool reachable_from_cache(address target);
1258
1259 void zero_extend(Register rd, Register rn, int bits);
1260 void sign_extend(Register rd, Register rn, int bits);
1261
1262 inline void zap_high_non_significant_bits(Register r) {
1263 #ifdef AARCH64
1264 if(ZapHighNonSignificantBits) {
1265 movk(r, 0xBAAD, 48);
1266 movk(r, 0xF00D, 32);
1267 }
1268 #endif
1269 }
1270
1271 #ifndef AARCH64
1272 void long_move(Register rd_lo, Register rd_hi,
1273 Register rn_lo, Register rn_hi,
1274 AsmCondition cond = al);
1275 void long_shift(Register rd_lo, Register rd_hi,
1276 Register rn_lo, Register rn_hi,
1277 AsmShift shift, Register count);
1278 void long_shift(Register rd_lo, Register rd_hi,
1279 Register rn_lo, Register rn_hi,
1280 AsmShift shift, int count);
1281
1282 void atomic_cas(Register tmpreg1, Register tmpreg2, Register oldval, Register newval, Register base, int offset);
1283 void atomic_cas_bool(Register oldval, Register newval, Register base, int offset, Register tmpreg);
1284 void atomic_cas64(Register temp_lo, Register temp_hi, Register temp_result, Register oldval_lo, Register oldval_hi, Register newval_lo, Register newval_hi, Register base, int offset);
1285 #endif // !AARCH64
1286
1287 void cas_for_lock_acquire(Register oldval, Register newval, Register base, Register tmp, Label &slow_case, bool allow_fallthrough_on_failure = false, bool one_shot = false);
1288 void cas_for_lock_release(Register oldval, Register newval, Register base, Register tmp, Label &slow_case, bool allow_fallthrough_on_failure = false, bool one_shot = false);
1289
1290 #ifndef PRODUCT
1291 // Preserves flags and all registers.
1292 // On SMP the updated value might not be visible to external observers without a sychronization barrier
1293 void cond_atomic_inc32(AsmCondition cond, int* counter_addr);
1294 #endif // !PRODUCT
1295
1296 // unconditional non-atomic increment
1297 void inc_counter(address counter_addr, Register tmpreg1, Register tmpreg2);
1298 void inc_counter(int* counter_addr, Register tmpreg1, Register tmpreg2) {
1299 inc_counter((address) counter_addr, tmpreg1, tmpreg2);
1300 }
1301
1302 void pd_patch_instruction(address branch, address target);
1303
1304 // Loading and storing values by size and signed-ness;
1305 // size must not exceed wordSize (i.e. 8-byte values are not supported on 32-bit ARM);
1306 // each of these calls generates exactly one load or store instruction,
1307 // so src can be pre- or post-indexed address.
1308 #ifdef AARCH64
1309 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
1310 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1311 #else
1312 // 32-bit ARM variants also support conditional execution
1313 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, AsmCondition cond = al);
1314 void store_sized_value(Register src, Address dst, size_t size_in_bytes, AsmCondition cond = al);
1315 #endif
1316
1317 void lookup_interface_method(Register recv_klass,
1318 Register intf_klass,
1319 Register itable_index,
1320 Register method_result,
1321 Register temp_reg1,
1322 Register temp_reg2,
1323 Label& L_no_such_interface);
1324
1325 // Compare char[] arrays aligned to 4 bytes.
1326 void char_arrays_equals(Register ary1, Register ary2,
1327 Register limit, Register result,
1328 Register chr1, Register chr2, Label& Ldone);
1329
1330
1331 void floating_cmp(Register dst);
1332
1333 // improved x86 portability (minimizing source code changes)
1334
1335 void ldr_literal(Register rd, AddressLiteral addr) {
1336 relocate(addr.rspec());
1337 #ifdef AARCH64
1338 ldr(rd, addr.target());
1339 #else
1340 ldr(rd, Address(PC, addr.target() - pc() - 8));
1341 #endif
1342 }
1343
1344 void lea(Register Rd, AddressLiteral addr) {
1345 // Never dereferenced, as on x86 (lval status ignored)
1346 mov_address(Rd, addr.target(), addr.rspec());
1347 }
1348
1349 void restore_default_fp_mode();
1350
1351 #ifdef COMPILER2
1352 #ifdef AARCH64
1353 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
1354 void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
1355 void fast_unlock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
1356 #else
1357 void fast_lock(Register obj, Register box, Register scratch, Register scratch2);
1358 void fast_unlock(Register obj, Register box, Register scratch, Register scratch2);
1359 #endif
1360 #endif
1361
1362 #ifdef AARCH64
1363
1364 #define F(mnemonic) \
1365 void mnemonic(Register rt, address target) { \
1366 Assembler::mnemonic(rt, target); \
1367 } \
1368 void mnemonic(Register rt, Label& L) { \
1369 Assembler::mnemonic(rt, target(L)); \
1370 }
1371
1372 F(cbz_w);
1373 F(cbnz_w);
1374 F(cbz);
1375 F(cbnz);
1376
1377 #undef F
1378
1379 #define F(mnemonic) \
1380 void mnemonic(Register rt, int bit, address target) { \
1381 Assembler::mnemonic(rt, bit, target); \
1382 } \
1383 void mnemonic(Register rt, int bit, Label& L) { \
1384 Assembler::mnemonic(rt, bit, target(L)); \
1385 }
1386
1387 F(tbz);
1388 F(tbnz);
1389 #undef F
1390
1391 #endif // AARCH64
1392
1393 };
1394
1395
1396 // The purpose of this class is to build several code fragments of the same size
1397 // in order to allow fast table branch.
1398
1399 class FixedSizeCodeBlock VALUE_OBJ_CLASS_SPEC {
1400 public:
1401 FixedSizeCodeBlock(MacroAssembler* masm, int size_in_instrs, bool enabled);
1402 ~FixedSizeCodeBlock();
1403
1404 private:
1405 MacroAssembler* _masm;
1406 address _start;
1407 int _size_in_instrs;
1408 bool _enabled;
1409 };
1410
1411
1412 #endif // CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
1413