1 /*
2 * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_S390_VM_MACROASSEMBLER_S390_HPP
27 #define CPU_S390_VM_MACROASSEMBLER_S390_HPP
28
29 #include "asm/assembler.hpp"
30
31 #define MODERN_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)
32 #define CLASSIC_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)
33 #define MODERN_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)
34 #define CLASSIC_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)
35
36 class MacroAssembler: public Assembler {
37 public:
38 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
39
40 //
41 // Optimized instruction emitters
42 //
43
44 // Move register if destination register and target register are different.
45 void lr_if_needed(Register rd, Register rs);
46 void lgr_if_needed(Register rd, Register rs);
47 void llgfr_if_needed(Register rd, Register rs);
48 void ldr_if_needed(FloatRegister rd, FloatRegister rs);
49
50 void move_reg_if_needed(Register dest, BasicType dest_type, Register src, BasicType src_type);
51 void move_freg_if_needed(FloatRegister dest, BasicType dest_type, FloatRegister src, BasicType src_type);
52
53 void freg2mem_opt(FloatRegister reg,
54 int64_t disp,
55 Register index,
56 Register base,
57 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
58 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
59 Register scratch = Z_R0);
60 void freg2mem_opt(FloatRegister reg,
61 const Address &a, bool is_double = true);
62
63 void mem2freg_opt(FloatRegister reg,
64 int64_t disp,
65 Register index,
66 Register base,
67 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
68 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
69 Register scratch = Z_R0);
70 void mem2freg_opt(FloatRegister reg,
71 const Address &a, bool is_double = true);
72
73 void reg2mem_opt(Register reg,
74 int64_t disp,
75 Register index,
76 Register base,
77 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
78 void (MacroAssembler::*classic)(Register, int64_t, Register, Register),
79 Register scratch = Z_R0);
80 // returns offset of the store instruction
81 int reg2mem_opt(Register reg, const Address &a, bool is_double = true);
82
83 void mem2reg_opt(Register reg,
84 int64_t disp,
85 Register index,
86 Register base,
87 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
88 void (MacroAssembler::*classic)(Register, int64_t, Register, Register));
89 void mem2reg_opt(Register reg, const Address &a, bool is_double = true);
90 void mem2reg_signed_opt(Register reg, const Address &a);
91
92 // AND immediate and set condition code, works for 64 bit immediates/operation as well.
93 void and_imm(Register r, long mask, Register tmp = Z_R0, bool wide = false);
94
95 // 1's complement, 32bit or 64bit. Optimized to exploit distinct operands facility.
96 // Note: The condition code is neither preserved nor correctly set by this code!!!
97 // Note: (wide == false) does not protect the high order half of the target register
98 // from alternation. It only serves as optimization hint for 32-bit results.
99 void not_(Register r1, Register r2 = noreg, bool wide = false); // r1 = ~r2
100
101 // Expanded support of all "rotate_then_<logicalOP>" instructions.
102 //
103 // Generalize and centralize rotate_then_<logicalOP> emitter.
104 // Functional description. For details, see Principles of Operation, Chapter 7, "Rotate Then Insert..."
105 // - Bits in a register are numbered left (most significant) to right (least significant), i.e. [0..63].
106 // - Bytes in a register are numbered left (most significant) to right (least significant), i.e. [0..7].
107 // - Register src is rotated to the left by (nRotate&0x3f) positions.
108 // - Negative values for nRotate result in a rotation to the right by abs(nRotate) positions.
109 // - The bits in positions [lBitPos..rBitPos] of the _ROTATED_ src operand take part in the
110 // logical operation performed on the contents (in those positions) of the dst operand.
111 // - The logical operation that is performed on the dst operand is one of
112 // o insert the selected bits (replacing the original contents of those bit positions)
113 // o and the selected bits with the corresponding bits of the dst operand
114 // o or the selected bits with the corresponding bits of the dst operand
115 // o xor the selected bits with the corresponding bits of the dst operand
116 // - For clear_dst == true, the destination register is cleared before the bits are inserted.
117 // For clear_dst == false, only the bit positions that get data inserted from src
118 // are changed. All other bit positions remain unchanged.
119 // - For test_only == true, the result of the logicalOP is only used to set the condition code, dst remains unchanged.
120 // For test_only == false, the result of the logicalOP replaces the selected bits of dst.
121 // - src32bit and dst32bit indicate the respective register is used as 32bit value only.
122 // Knowledge can simplify code generation.
123 //
124 // Here is an important performance note, valid for all <logicalOP>s except "insert":
125 // Due to the too complex nature of the operation, it cannot be done in a single cycle.
126 // Timing constraints require the instructions to be cracked into two micro-ops, taking
127 // one or two cycles each to execute. In some cases, an additional pipeline bubble might get added.
128 // Macroscopically, that makes up for a three- or four-cycle instruction where you would
129 // expect just a single cycle.
130 // It is thus not beneficial from a performance point of view to exploit those instructions.
131 // Other reasons (code compactness, register pressure, ...) might outweigh this penalty.
132 //
133 unsigned long create_mask(int lBitPos, int rBitPos);
134 void rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
135 int nRotate, bool src32bit, bool dst32bit, bool oneBits);
136 void rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
137 bool clear_dst);
138 void rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
139 bool test_only);
140 void rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
141 bool test_onlyt);
142 void rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
143 bool test_only);
144
145 void add64(Register r1, RegisterOrConstant inc);
146
147 // Helper function to multiply the 64bit contents of a register by a 16bit constant.
148 // The optimization tries to avoid the mghi instruction, since it uses the FPU for
149 // calculation and is thus rather slow.
150 //
151 // There is no handling for special cases, e.g. cval==0 or cval==1.
152 //
153 // Returns len of generated code block.
154 unsigned int mul_reg64_const16(Register rval, Register work, int cval);
155
156 // Generic operation r1 := r2 + imm.
157 void add2reg(Register r1, int64_t imm, Register r2 = noreg);
158 // Generic operation r := b + x + d.
159 void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg);
160
161 // Add2mem* methods for direct memory increment.
162 void add2mem_32(const Address &a, int64_t imm, Register tmp);
163 void add2mem_64(const Address &a, int64_t imm, Register tmp);
164
165 // *((int8_t*)(dst)) |= imm8
166 inline void or2mem_8(Address& dst, int64_t imm8);
167
168 // Load values by size and signedness.
169 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
170 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
171
172 // Load values with large offsets to base address.
173 private:
174 int split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate);
175 public:
176 void load_long_largeoffset(Register t, int64_t si20, Register a, Register tmp);
177 void load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);
178 void load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);
179
180 private:
181 long toc_distance();
182 public:
183 void load_toc(Register Rtoc);
184 void load_long_pcrelative(Register Rdst, address dataLocation);
185 static int load_long_pcrelative_size() { return 6; }
186 void load_addr_pcrelative(Register Rdst, address dataLocation);
187 static int load_addr_pcrel_size() { return 6; } // Just a LARL.
188
189 // Load a value from memory and test (set CC).
190 void load_and_test_byte (Register dst, const Address &a);
191 void load_and_test_short (Register dst, const Address &a);
192 void load_and_test_int (Register dst, const Address &a);
193 void load_and_test_int2long(Register dst, const Address &a);
194 void load_and_test_long (Register dst, const Address &a);
195
196 // Test a bit in memory. Result is reflected in CC.
197 void testbit(const Address &a, unsigned int bit);
198 // Test a bit in a register. Result is reflected in CC.
199 void testbit(Register r, unsigned int bitPos);
200
201 // Clear a register, i.e. load const zero into reg. Return len (in bytes) of
202 // generated instruction(s).
203 // whole_reg: Clear 64 bits if true, 32 bits otherwise.
204 // set_cc: Use instruction that sets the condition code, if true.
205 int clear_reg(Register r, bool whole_reg = true, bool set_cc = true);
206
207 #ifdef ASSERT
208 int preset_reg(Register r, unsigned long pattern, int pattern_len);
209 #endif
210
211 // Clear (store zeros) a small piece of memory.
212 // CAUTION: Do not use this for atomic memory clearing. Use store_const() instead.
213 // addr: Address descriptor of memory to clear.
214 // Index register will not be used!
215 // size: Number of bytes to clear.
216 void clear_mem(const Address& addr, unsigned size);
217
218 // Move immediate values to memory. Currently supports 32 and 64 bit stores,
219 // but may be extended to 16 bit store operation, if needed.
220 // For details, see implementation in *.cpp file.
221 int store_const(const Address &dest, long imm,
222 unsigned int lm, unsigned int lc,
223 Register scratch = Z_R0);
224 inline int store_const(const Address &dest, long imm,
225 Register scratch = Z_R0, bool is_long = true);
226
227 // Move/initialize arbitrarily large memory area. No check for destructive overlap.
228 // Being interruptible, these instructions need a retry-loop.
229 void move_long_ext(Register dst, Register src, unsigned int pad);
230
231 void compare_long_ext(Register left, Register right, unsigned int pad);
232 void compare_long_uni(Register left, Register right, unsigned int pad);
233
234 void search_string(Register end, Register start);
235 void search_string_uni(Register end, Register start);
236
237 // Translate instructions
238 // Being interruptible, these instructions need a retry-loop.
239 void translate_oo(Register dst, Register src, uint mask);
240 void translate_ot(Register dst, Register src, uint mask);
241 void translate_to(Register dst, Register src, uint mask);
242 void translate_tt(Register dst, Register src, uint mask);
243
244 // Crypto instructions.
245 // Being interruptible, these instructions need a retry-loop.
246 void cksm(Register crcBuff, Register srcBuff);
247 void km( Register dstBuff, Register srcBuff);
248 void kmc(Register dstBuff, Register srcBuff);
249 void kimd(Register srcBuff);
250 void klmd(Register srcBuff);
251 void kmac(Register srcBuff);
252
253 // nop padding
254 void align(int modulus);
255 void align_address(int modulus);
256
257 //
258 // Constants, loading constants, TOC support
259 //
260 // Safepoint check factored out.
261 void generate_safepoint_check(Label& slow_path, Register scratch = noreg, bool may_relocate = true);
262
263 // Load generic address: d <- base(a) + index(a) + disp(a).
264 inline void load_address(Register d, const Address &a);
265 // Load absolute address (and try to optimize).
266 void load_absolute_address(Register d, address addr);
267
268 // Address of Z_ARG1 and argument_offset.
269 // If temp_reg == arg_slot, arg_slot will be overwritten.
270 Address argument_address(RegisterOrConstant arg_slot,
271 Register temp_reg = noreg,
272 int64_t extra_slot_offset = 0);
273
274 // Load a narrow ptr constant (oop or klass ptr).
275 void load_narrow_oop( Register t, narrowOop a);
276 void load_narrow_klass(Register t, Klass* k);
277
278 static bool is_load_const_32to64(address pos);
279 static bool is_load_narrow_oop(address pos) { return is_load_const_32to64(pos); }
280 static bool is_load_narrow_klass(address pos) { return is_load_const_32to64(pos); }
281
282 static int load_const_32to64_size() { return 6; }
283 static bool load_narrow_oop_size() { return load_const_32to64_size(); }
284 static bool load_narrow_klass_size() { return load_const_32to64_size(); }
285
286 static int patch_load_const_32to64(address pos, int64_t a);
287 static int patch_load_narrow_oop(address pos, oop o);
288 static int patch_load_narrow_klass(address pos, Klass* k);
289
290 // cOops. CLFI exploit.
291 void compare_immediate_narrow_oop(Register oop1, narrowOop oop2);
292 void compare_immediate_narrow_klass(Register op1, Klass* op2);
293 static bool is_compare_immediate32(address pos);
294 static bool is_compare_immediate_narrow_oop(address pos);
295 static bool is_compare_immediate_narrow_klass(address pos);
296 static int compare_immediate_narrow_size() { return 6; }
297 static int compare_immediate_narrow_oop_size() { return compare_immediate_narrow_size(); }
298 static int compare_immediate_narrow_klass_size() { return compare_immediate_narrow_size(); }
299 static int patch_compare_immediate_32(address pos, int64_t a);
300 static int patch_compare_immediate_narrow_oop(address pos, oop o);
301 static int patch_compare_immediate_narrow_klass(address pos, Klass* k);
302
303 // Load a 32bit constant into a 64bit register.
304 void load_const_32to64(Register t, int64_t x, bool sign_extend=true);
305 // Load a 64 bit constant.
306 void load_const(Register t, long a);
307 inline void load_const(Register t, void* a);
308 inline void load_const(Register t, Label& L);
309 inline void load_const(Register t, const AddressLiteral& a);
310 // Get the 64 bit constant from a `load_const' sequence.
311 static long get_const(address load_const);
312 // Patch the 64 bit constant of a `load_const' sequence. This is a low level
313 // procedure. It neither flushes the instruction cache nor is it atomic.
314 static void patch_const(address load_const, long x);
315 static int load_const_size() { return 12; }
316
317 // Turn a char into boolean. NOTE: destroys r.
318 void c2bool(Register r, Register t = Z_R0);
319
320 // Optimized version of load_const for constants that do not need to be
321 // loaded by a sequence of instructions of fixed length and that do not
322 // need to be patched.
323 int load_const_optimized_rtn_len(Register t, long x, bool emit);
324 inline void load_const_optimized(Register t, long x);
325 inline void load_const_optimized(Register t, void* a);
326 inline void load_const_optimized(Register t, Label& L);
327 inline void load_const_optimized(Register t, const AddressLiteral& a);
328
329 public:
330
331 //----------------------------------------------------------
332 // oops in code -------------
333 // including compressed oops support -------------
334 //----------------------------------------------------------
335
336 // Metadata in code that we have to keep track of.
337 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
338 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
339
340 // allocate_index
341 AddressLiteral allocate_oop_address(jobject obj);
342 // find_index
343 AddressLiteral constant_oop_address(jobject obj);
344 // Uses allocate_oop_address.
345 inline void set_oop (jobject obj, Register d);
346 // Uses constant_oop_address.
347 inline void set_oop_constant(jobject obj, Register d);
348 // Uses constant_metadata_address.
349 inline bool set_metadata_constant(Metadata* md, Register d);
350
351 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
352 Register tmp,
353 int offset);
354 //
355 // branch, jump
356 //
357
358 // Use one generic function for all branch patches.
359 static unsigned long patched_branch(address dest_pos, unsigned long inst, address inst_pos);
360
361 void pd_patch_instruction(address branch, address target);
362
363 // Extract relative address from "relative" instructions.
364 static long get_pcrel_offset(unsigned long inst);
365 static long get_pcrel_offset(address pc);
366 static address get_target_addr_pcrel(address pc);
367
368 static inline bool is_call_pcrelative_short(unsigned long inst);
369 static inline bool is_call_pcrelative_long(unsigned long inst);
370 static inline bool is_branch_pcrelative_short(unsigned long inst);
371 static inline bool is_branch_pcrelative_long(unsigned long inst);
372 static inline bool is_compareandbranch_pcrelative_short(unsigned long inst);
373 static inline bool is_branchoncount_pcrelative_short(unsigned long inst);
374 static inline bool is_branchonindex32_pcrelative_short(unsigned long inst);
375 static inline bool is_branchonindex64_pcrelative_short(unsigned long inst);
376 static inline bool is_branchonindex_pcrelative_short(unsigned long inst);
377 static inline bool is_branch_pcrelative16(unsigned long inst);
378 static inline bool is_branch_pcrelative32(unsigned long inst);
379 static inline bool is_branch_pcrelative(unsigned long inst);
380 static inline bool is_load_pcrelative_long(unsigned long inst);
381 static inline bool is_misc_pcrelative_long(unsigned long inst);
382 static inline bool is_pcrelative_short(unsigned long inst);
383 static inline bool is_pcrelative_long(unsigned long inst);
384 // PCrelative TOC access. Variants with address argument.
385 static inline bool is_load_pcrelative_long(address iLoc);
386 static inline bool is_pcrelative_short(address iLoc);
387 static inline bool is_pcrelative_long(address iLoc);
388
389 static inline bool is_pcrelative_instruction(address iloc);
390 static inline bool is_load_addr_pcrel(address a);
391
392 static void patch_target_addr_pcrel(address pc, address con);
393 static void patch_addr_pcrel(address pc, address con) {
394 patch_target_addr_pcrel(pc, con); // Just delegate. This is only for nativeInst_s390.cpp.
395 }
396
397 //---------------------------------------------------------
398 // Some macros for more comfortable assembler programming.
399 //---------------------------------------------------------
400
401 // NOTE: pass NearLabel T to signal that the branch target T will be bound to a near address.
402
403 void compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
404 void compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
405 void compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
406 void compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
407
408 void branch_optimized(Assembler::branch_condition cond, address branch_target);
409 void branch_optimized(Assembler::branch_condition cond, Label& branch_target);
410 void compare_and_branch_optimized(Register r1,
411 Register r2,
412 Assembler::branch_condition cond,
413 address branch_addr,
414 bool len64,
415 bool has_sign);
416 void compare_and_branch_optimized(Register r1,
417 jlong x2,
418 Assembler::branch_condition cond,
419 Label& branch_target,
420 bool len64,
421 bool has_sign);
422 void compare_and_branch_optimized(Register r1,
423 Register r2,
424 Assembler::branch_condition cond,
425 Label& branch_target,
426 bool len64,
427 bool has_sign);
428
429 //
430 // Support for frame handling
431 //
432 // Specify the register that should be stored as the return pc in the
433 // current frame (default is R14).
434 inline void save_return_pc(Register pc = Z_R14);
435 inline void restore_return_pc();
436
437 // Get current PC.
438 address get_PC(Register result);
439
440 // Get current PC + offset. Offset given in bytes, must be even!
441 address get_PC(Register result, int64_t offset);
442
443 // Accessing, and in particular modifying, a stack location is only safe if
444 // the stack pointer (Z_SP) is set such that the accessed stack location is
445 // in the reserved range.
446 //
447 // From a performance point of view, it is desirable not to change the SP
448 // first and then immediately use it to access the freshly reserved space.
449 // That opens a small gap, though. If, just after storing some value (the
450 // frame pointer) into the to-be-reserved space, an interrupt is caught,
451 // the handler might use the space beyond Z_SP for it's own purpose.
452 // If that happens, the stored value might get altered.
453
454 // Resize current frame either relatively wrt to current SP or absolute.
455 void resize_frame_sub(Register offset, Register fp, bool load_fp=true);
456 void resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp);
457 void resize_frame_absolute(Register addr, Register fp, bool load_fp);
458 void resize_frame(RegisterOrConstant offset, Register fp, bool load_fp=true);
459
460 // Push a frame of size bytes, if copy_sp is false, old_sp must already
461 // contain a copy of Z_SP.
462 void push_frame(Register bytes, Register old_sp, bool copy_sp = true, bool bytes_with_inverted_sign = false);
463
464 // Push a frame of size `bytes'. no abi space provided.
465 // Don't rely on register locking, instead pass a scratch register
466 // (Z_R0 by default).
467 // CAUTION! passing registers >= Z_R2 may produce bad results on
468 // old CPUs!
469 unsigned int push_frame(unsigned int bytes, Register scratch = Z_R0);
470
471 // Push a frame of size `bytes' with abi160 on top.
472 unsigned int push_frame_abi160(unsigned int bytes);
473
474 // Pop current C frame.
475 void pop_frame();
476 // Pop current C frame and restore return PC register (Z_R14).
477 void pop_frame_restore_retPC(int frame_size_in_bytes);
478
479 //
480 // Calls
481 //
482
483 private:
484 address _last_calls_return_pc;
485
486 public:
487 // Support for VM calls. This is the base routine called by the
488 // different versions of call_VM_leaf. The interpreter may customize
489 // this version by overriding it for its purposes (e.g., to
490 // save/restore additional registers when doing a VM call).
491 void call_VM_leaf_base(address entry_point);
492 void call_VM_leaf_base(address entry_point, bool allow_relocation);
493
494 // It is imperative that all calls into the VM are handled via the
495 // call_VM macros. They make sure that the stack linkage is setup
496 // correctly. Call_VM's correspond to ENTRY/ENTRY_X entry points
497 // while call_VM_leaf's correspond to LEAF entry points.
498 //
499 // This is the base routine called by the different versions of
500 // call_VM. The interpreter may customize this version by overriding
501 // it for its purposes (e.g., to save/restore additional registers
502 // when doing a VM call).
503
504 // If no last_java_sp is specified (noreg) then SP will be used instead.
505
506 virtual void call_VM_base(
507 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise.
508 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
509 address entry_point, // The entry point.
510 bool check_exception); // Flag which indicates if exception should be checked.
511 virtual void call_VM_base(
512 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise.
513 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
514 address entry_point, // The entry point.
515 bool allow_relocation, // Flag to request generation of relocatable code.
516 bool check_exception); // Flag which indicates if exception should be checked.
517
518 // Call into the VM.
519 // Passes the thread pointer (in Z_ARG1) as a prepended argument.
520 // Makes sure oop return values are visible to the GC.
521 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
522 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
523 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
524 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
525 Register arg_3, bool check_exceptions = true);
526
527 void call_VM_static(Register oop_result, address entry_point, bool check_exceptions = true);
528 void call_VM_static(Register oop_result, address entry_point, Register arg_1, Register arg_2,
529 Register arg_3, bool check_exceptions = true);
530
531 // Overloaded with last_java_sp.
532 void call_VM(Register oop_result, Register last_java_sp, address entry_point, bool check_exceptions = true);
533 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
534 Register arg_1, bool check_exceptions = true);
535 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
536 Register arg_1, Register arg_2, bool check_exceptions = true);
537 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
538 Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
539
540 void call_VM_leaf(address entry_point);
541 void call_VM_leaf(address entry_point, Register arg_1);
542 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
543 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
544
545 // Really static VM leaf call (never patched).
546 void call_VM_leaf_static(address entry_point);
547 void call_VM_leaf_static(address entry_point, Register arg_1);
548 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2);
549 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2, Register arg_3);
550
551 // Call a C function via its function entry. Updates and returns _last_calls_return_pc.
552 inline address call(Register function_entry);
553 inline address call_c(Register function_entry);
554 address call_c(address function_entry);
555 // Variant for really static (non-relocatable) calls which are never patched.
556 address call_c_static(address function_entry);
557 // TOC or pc-relative call + emits a runtime_call relocation.
558 address call_c_opt(address function_entry);
559
560 inline address call_stub(Register function_entry);
561 inline address call_stub(address function_entry);
562
563 // Get the pc where the last call will return to. Returns _last_calls_return_pc.
564 inline address last_calls_return_pc();
565
566 private:
567 static bool is_call_far_patchable_variant0_at(address instruction_addr); // Dynamic TOC: load target addr from CP and call.
568 static bool is_call_far_patchable_variant2_at(address instruction_addr); // PC-relative call, prefixed with NOPs.
569
570
571 public:
572 bool call_far_patchable(address target, int64_t toc_offset);
573 static bool is_call_far_patchable_at(address inst_start); // All supported forms of patchable calls.
574 static bool is_call_far_patchable_pcrelative_at(address inst_start); // Pc-relative call with leading nops.
575 static bool is_call_far_pcrelative(address instruction_addr); // Pure far pc-relative call, with one leading size adjustment nop.
576 static void set_dest_of_call_far_patchable_at(address inst_start, address target, int64_t toc_offset);
577 static address get_dest_of_call_far_patchable_at(address inst_start, address toc_start);
578
579 void align_call_far_patchable(address pc);
580
581 // PCrelative TOC access.
582
583 // This value is independent of code position - constant for the lifetime of the VM.
584 static int call_far_patchable_size() {
585 return load_const_from_toc_size() + call_byregister_size();
586 }
587
588 static int call_far_patchable_ret_addr_offset() { return call_far_patchable_size(); }
589
590 static bool call_far_patchable_requires_alignment_nop(address pc) {
591 if (!os::is_MP()) return false;
592 int size = call_far_patchable_size();
593 return ((intptr_t)(pc + size) & 0x03L) != 0;
594 }
595
596 // END OF PCrelative TOC access.
597
598 static int jump_byregister_size() { return 2; }
599 static int jump_pcrelative_size() { return 4; }
600 static int jump_far_pcrelative_size() { return 6; }
601 static int call_byregister_size() { return 2; }
602 static int call_pcrelative_size() { return 4; }
603 static int call_far_pcrelative_size() { return 2 + 6; } // Prepend each BRASL with a nop.
604 static int call_far_pcrelative_size_raw() { return 6; } // Prepend each BRASL with a nop.
605
606 //
607 // Java utilities
608 //
609
610 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
611 // The implementation is only non-empty for the InterpreterMacroAssembler,
612 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
613 virtual void check_and_handle_popframe(Register java_thread);
614 virtual void check_and_handle_earlyret(Register java_thread);
615
616 // Polling page support.
617 enum poll_mask {
618 mask_stackbang = 0xde, // 222 (dec)
619 mask_safepoint = 0x6f, // 111 (dec)
620 mask_profiling = 0xba // 186 (dec)
621 };
622
623 // Read from the polling page.
624 void load_from_polling_page(Register polling_page_address, int64_t offset = 0);
625
626 // Check if given instruction is a read from the polling page
627 // as emitted by load_from_polling_page.
628 static bool is_load_from_polling_page(address instr_loc);
629 // Extract poll address from instruction and ucontext.
630 static address get_poll_address(address instr_loc, void* ucontext);
631 // Extract poll register from instruction.
632 static uint get_poll_register(address instr_loc);
633
634 // Check if instruction is a write access to the memory serialization page
635 // realized by one of the instructions stw, stwu, stwx, or stwux.
636 static bool is_memory_serialization(int instruction, JavaThread* thread, void* ucontext);
637
638 // Support for serializing memory accesses between threads.
639 void serialize_memory(Register thread, Register tmp1, Register tmp2);
640
641 // Stack overflow checking
642 void bang_stack_with_offset(int offset);
643
644 // Check for reserved stack access in method being exited. If the reserved
645 // stack area was accessed, protect it again and throw StackOverflowError.
646 // Uses Z_R1.
647 void reserved_stack_check(Register return_pc);
648
649 // Atomics
650 // -- none?
651
652 void tlab_allocate(Register obj, // Result: pointer to object after successful allocation
653 Register var_size_in_bytes, // Object size in bytes if unknown at compile time; invalid otherwise.
654 int con_size_in_bytes, // Object size in bytes if known at compile time.
655 Register t1, // temp register
656 Label& slow_case); // Continuation point if fast allocation fails.
657
658 // Emitter for interface method lookup.
659 // input: recv_klass, intf_klass, itable_index
660 // output: method_result
661 // kills: itable_index, temp1_reg, Z_R0, Z_R1
662 void lookup_interface_method(Register recv_klass,
663 Register intf_klass,
664 RegisterOrConstant itable_index,
665 Register method_result,
666 Register temp1_reg,
667 Register temp2_reg,
668 Label& no_such_interface);
669
670 // virtual method calling
671 void lookup_virtual_method(Register recv_klass,
672 RegisterOrConstant vtable_index,
673 Register method_result);
674
675 // Factor out code to call ic_miss_handler.
676 unsigned int call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch);
677 void nmethod_UEP(Label& ic_miss);
678
679 // Emitters for "partial subtype" checks.
680
681 // Test sub_klass against super_klass, with fast and slow paths.
682
683 // The fast path produces a tri-state answer: yes / no / maybe-slow.
684 // One of the three labels can be NULL, meaning take the fall-through.
685 // If super_check_offset is -1, the value is loaded up from super_klass.
686 // No registers are killed, except temp_reg and temp2_reg.
687 // If super_check_offset is not -1, temp1_reg is not used and can be noreg.
688 void check_klass_subtype_fast_path(Register sub_klass,
689 Register super_klass,
690 Register temp1_reg,
691 Label* L_success,
692 Label* L_failure,
693 Label* L_slow_path,
694 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
695
696 // The rest of the type check; must be wired to a corresponding fast path.
697 // It does not repeat the fast path logic, so don't use it standalone.
698 // The temp_reg can be noreg, if no temps are available.
699 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
700 // Updates the sub's secondary super cache as necessary.
701 void check_klass_subtype_slow_path(Register Rsubklass,
702 Register Rsuperklas,
703 Register Rarray_ptr, // tmp
704 Register Rlength, // tmp
705 Label* L_success,
706 Label* L_failure);
707
708 // Simplified, combined version, good for typical uses.
709 // Falls through on failure.
710 void check_klass_subtype(Register sub_klass,
711 Register super_klass,
712 Register temp1_reg,
713 Register temp2_reg,
714 Label& L_success);
715
716 // Increment a counter at counter_address when the eq condition code is set.
717 // Kills registers tmp1_reg and tmp2_reg and preserves the condition code.
718 void increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg);
719 // Biased locking support
720 // Upon entry,obj_reg must contain the target object, and mark_reg
721 // must contain the target object's header.
722 // Destroys mark_reg if an attempt is made to bias an anonymously
723 // biased lock. In this case a failure will go either to the slow
724 // case or fall through with the notEqual condition code set with
725 // the expectation that the slow case in the runtime will be called.
726 // In the fall-through case where the CAS-based lock is done,
727 // mark_reg is not destroyed.
728 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
729 Register temp2_reg, Label& done, Label* slow_case = NULL);
730 // Upon entry, the base register of mark_addr must contain the oop.
731 // Destroys temp_reg.
732 // If allow_delay_slot_filling is set to true, the next instruction
733 // emitted after this one will go in an annulled delay slot if the
734 // biased locking exit case failed.
735 void biased_locking_exit(Register mark_addr, Register temp_reg, Label& done);
736
737 void compiler_fast_lock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias = UseBiasedLocking);
738 void compiler_fast_unlock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias = UseBiasedLocking);
739
740 // Write to card table for modification at store_addr - register is destroyed afterwards.
741 void card_write_barrier_post(Register store_addr, Register tmp);
742
743 void resolve_jobject(Register value, Register tmp1, Register tmp2);
744
745 #if INCLUDE_ALL_GCS
746 // General G1 pre-barrier generator.
747 // Purpose: record the previous value if it is not null.
748 // All non-tmps are preserved.
749 void g1_write_barrier_pre(Register Robj,
750 RegisterOrConstant offset,
751 Register Rpre_val, // Ideally, this is a non-volatile register.
752 Register Rval, // Will be preserved.
753 Register Rtmp1, // If Rpre_val is volatile, either Rtmp1
754 Register Rtmp2, // or Rtmp2 has to be non-volatile.
755 bool pre_val_needed); // Save Rpre_val across runtime call, caller uses it.
756
757 // General G1 post-barrier generator.
758 // Purpose: Store cross-region card.
759 void g1_write_barrier_post(Register Rstore_addr,
760 Register Rnew_val,
761 Register Rtmp1,
762 Register Rtmp2,
763 Register Rtmp3);
764 #endif // INCLUDE_ALL_GCS
765
766 // Support for last Java frame (but use call_VM instead where possible).
767 private:
768 void set_last_Java_frame(Register last_Java_sp, Register last_Java_pc, bool allow_relocation);
769 void reset_last_Java_frame(bool allow_relocation);
770 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, bool allow_relocation);
771 public:
772 inline void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
773 inline void set_last_Java_frame_static(Register last_java_sp, Register last_Java_pc);
774 inline void reset_last_Java_frame(void);
775 inline void reset_last_Java_frame_static(void);
776 inline void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1);
777 inline void set_top_ijava_frame_at_SP_as_last_Java_frame_static(Register sp, Register tmp1);
778
779 void set_thread_state(JavaThreadState new_state);
780
781 // Read vm result from thread.
782 void get_vm_result (Register oop_result);
783 void get_vm_result_2(Register result);
784
785 // Vm result is currently getting hijacked to for oop preservation.
786 void set_vm_result(Register oop_result);
787
788 // Support for NULL-checks
789 //
790 // Generates code that causes a NULL OS exception if the content of reg is NULL.
791 // If the accessed location is M[reg + offset] and the offset is known, provide the
792 // offset. No explicit code generation is needed if the offset is within a certain
793 // range (0 <= offset <= page_size).
794 //
795 // %%%%%% Currently not done for z/Architecture
796
797 void null_check(Register reg, Register tmp = Z_R0, int64_t offset = -1);
798 static bool needs_explicit_null_check(intptr_t offset); // Implemented in shared file ?!
799
800 // Klass oop manipulations if compressed.
801 void encode_klass_not_null(Register dst, Register src = noreg);
802 void decode_klass_not_null(Register dst, Register src);
803 void decode_klass_not_null(Register dst);
804 void load_klass(Register klass, Address mem);
805 void load_klass(Register klass, Register src_oop);
806 void load_prototype_header(Register Rheader, Register Rsrc_oop);
807 void store_klass(Register klass, Register dst_oop, Register ck = noreg); // Klass will get compressed if ck not provided.
808 void store_klass_gap(Register s, Register dst_oop);
809
810 // This function calculates the size of the code generated by
811 // decode_klass_not_null(register dst)
812 // when (Universe::heap() != NULL). Hence, if the instructions
813 // it generates change, then this method needs to be updated.
814 static int instr_size_for_decode_klass_not_null();
815
816 void encode_heap_oop(Register oop);
817 void encode_heap_oop_not_null(Register oop);
818
819 static int get_oop_base_pow2_offset(uint64_t oop_base);
820 int get_oop_base(Register Rbase, uint64_t oop_base);
821 int get_oop_base_complement(Register Rbase, uint64_t oop_base);
822 void compare_heap_oop(Register Rop1, Address mem, bool maybeNULL);
823 void compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybeNULL);
824 void load_heap_oop(Register dest, const Address &a);
825 void load_heap_oop(Register d, int64_t si16, Register s1);
826 void load_heap_oop_not_null(Register d, int64_t si16, Register s1);
827 void store_heap_oop(Register Roop, RegisterOrConstant offset, Register base);
828 void store_heap_oop_not_null(Register Roop, RegisterOrConstant offset, Register base);
829 void store_heap_oop_null(Register zero, RegisterOrConstant offset, Register base);
830 void oop_encoder(Register Rdst, Register Rsrc, bool maybeNULL,
831 Register Rbase = Z_R1, int pow2_offset = -1, bool only32bitValid = false);
832 void oop_decoder(Register Rdst, Register Rsrc, bool maybeNULL,
833 Register Rbase = Z_R1, int pow2_offset = -1);
834
835 void load_mirror(Register mirror, Register method);
836
837 //--------------------------
838 //--- perations on arrays.
839 //--------------------------
840 unsigned int Clear_Array(Register cnt_arg, Register base_pointer_arg, Register src_addr, Register src_len);
841 unsigned int Clear_Array_Const(long cnt, Register base);
842 unsigned int Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register src_addr, Register src_len);
843 unsigned int CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
844 Register cnt_reg,
845 Register tmp1_reg, Register tmp2_reg);
846
847 //-------------------------------------------
848 // Special String Intrinsics Implementation.
849 //-------------------------------------------
850 // Intrinsics for CompactStrings
851 // Compress char[] to byte[]. odd_reg contains cnt. tmp3 is only needed for precise behavior in failure case. Kills dst.
852 unsigned int string_compress(Register result, Register src, Register dst, Register odd_reg,
853 Register even_reg, Register tmp, Register tmp2 = noreg);
854
855 // Kills src.
856 unsigned int has_negatives(Register result, Register src, Register cnt,
857 Register odd_reg, Register even_reg, Register tmp);
858
859 // Inflate byte[] to char[].
860 unsigned int string_inflate_trot(Register src, Register dst, Register cnt, Register tmp);
861 // Odd_reg contains cnt. Kills src.
862 unsigned int string_inflate(Register src, Register dst, Register odd_reg,
863 Register even_reg, Register tmp);
864
865 unsigned int string_compare(Register str1, Register str2, Register cnt1, Register cnt2,
866 Register odd_reg, Register even_reg, Register result, int ae);
867
868 unsigned int array_equals(bool is_array_equ, Register ary1, Register ary2, Register limit,
869 Register odd_reg, Register even_reg, Register result, bool is_byte);
870
871 unsigned int string_indexof(Register result, Register haystack, Register haycnt,
872 Register needle, Register needlecnt, int needlecntval,
873 Register odd_reg, Register even_reg, int ae);
874
875 unsigned int string_indexof_char(Register result, Register haystack, Register haycnt,
876 Register needle, jchar needleChar, Register odd_reg, Register even_reg, bool is_byte);
877
878 // Emit an oop const to the constant pool and set a relocation info
879 // with address current_pc. Return the TOC offset of the constant.
880 int store_const_in_toc(AddressLiteral& val);
881 int store_oop_in_toc(AddressLiteral& oop);
882 // Emit an oop const to the constant pool via store_oop_in_toc, or
883 // emit a scalar const to the constant pool via store_const_in_toc,
884 // and load the constant into register dst.
885 bool load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg);
886 // Get CPU version dependent size of load_const sequence.
887 // The returned value is valid only for code sequences
888 // generated by load_const, not load_const_optimized.
889 static int load_const_from_toc_size() {
890 return load_long_pcrelative_size();
891 }
892 bool load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg);
893 static intptr_t get_const_from_toc(address pc);
894 static void set_const_in_toc(address pc, unsigned long new_data, CodeBlob *cb);
895
896 // Dynamic TOC.
897 static bool is_load_const(address a);
898 static bool is_load_const_from_toc_pcrelative(address a);
899 static bool is_load_const_from_toc(address a) { return is_load_const_from_toc_pcrelative(a); }
900
901 // PCrelative TOC access.
902 static bool is_call_byregister(address a) { return is_z_basr(*(short*)a); }
903 static bool is_load_const_from_toc_call(address a);
904 static bool is_load_const_call(address a);
905 static int load_const_call_size() { return load_const_size() + call_byregister_size(); }
906 static int load_const_from_toc_call_size() { return load_const_from_toc_size() + call_byregister_size(); }
907 // Offset is +/- 2**32 -> use long.
908 static long get_load_const_from_toc_offset(address a);
909
910
911 void generate_type_profiling(const Register Rdata,
912 const Register Rreceiver_klass,
913 const Register Rwanted_receiver_klass,
914 const Register Rmatching_row,
915 bool is_virtual_call);
916
917 // Bit operations for single register operands.
918 inline void lshift(Register r, int places, bool doubl = true); // <<
919 inline void rshift(Register r, int places, bool doubl = true); // >>
920
921 //
922 // Debugging
923 //
924
925 // Assert on CC (condition code in CPU state).
926 void asm_assert(bool check_equal, const char* msg, int id) PRODUCT_RETURN;
927 void asm_assert_low(const char *msg, int id) PRODUCT_RETURN;
928 void asm_assert_high(const char *msg, int id) PRODUCT_RETURN;
929 void asm_assert_eq(const char* msg, int id) { asm_assert(true, msg, id); }
930 void asm_assert_ne(const char* msg, int id) { asm_assert(false, msg, id); }
931
932 void asm_assert_static(bool check_equal, const char* msg, int id) PRODUCT_RETURN;
933
934 private:
935 // Emit assertions.
936 void asm_assert_mems_zero(bool check_equal, bool allow_relocation, int size, int64_t mem_offset,
937 Register mem_base, const char* msg, int id) PRODUCT_RETURN;
938
939 public:
940 inline void asm_assert_mem4_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
941 asm_assert_mems_zero(true, true, 4, mem_offset, mem_base, msg, id);
942 }
943 inline void asm_assert_mem8_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
944 asm_assert_mems_zero(true, true, 8, mem_offset, mem_base, msg, id);
945 }
946 inline void asm_assert_mem4_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
947 asm_assert_mems_zero(false, true, 4, mem_offset, mem_base, msg, id);
948 }
949 inline void asm_assert_mem8_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
950 asm_assert_mems_zero(false, true, 8, mem_offset, mem_base, msg, id);
951 }
952
953 inline void asm_assert_mem4_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
954 asm_assert_mems_zero(true, false, 4, mem_offset, mem_base, msg, id);
955 }
956 inline void asm_assert_mem8_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
957 asm_assert_mems_zero(true, false, 8, mem_offset, mem_base, msg, id);
958 }
959 inline void asm_assert_mem4_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
960 asm_assert_mems_zero(false, false, 4, mem_offset, mem_base, msg, id);
961 }
962 inline void asm_assert_mem8_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
963 asm_assert_mems_zero(false, false, 8, mem_offset, mem_base, msg, id);
964 }
965 void asm_assert_frame_size(Register expected_size, Register tmp, const char* msg, int id) PRODUCT_RETURN;
966
967 // Verify Z_thread contents.
968 void verify_thread();
969
970 // Only if +VerifyOops.
971 void verify_oop(Register reg, const char* s = "broken oop");
972
973 // TODO: verify_method and klass metadata (compare against vptr?).
974 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
975 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
976
977 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
978 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
979
980 private:
981 // Generate printout in stop().
982 static const char* stop_types[];
983 enum {
984 stop_stop = 0,
985 stop_untested = 1,
986 stop_unimplemented = 2,
987 stop_shouldnotreachhere = 3,
988 stop_end = 4
989 };
990 // Prints msg and stops execution.
991 void stop(int type, const char* msg, int id = 0);
992 address stop_chain(address reentry, int type, const char* msg, int id, bool allow_relocation); // Non-relocateable code only!!
993 void stop_static(int type, const char* msg, int id); // Non-relocateable code only!!
994
995 public:
996
997 // Prints msg and stops.
998 address stop_chain( address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, true); }
999 address stop_chain_static(address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, false); }
1000 void stop_static (const char* msg = "", int id = 0) { stop_static(stop_stop, msg, id); }
1001 void stop (const char* msg = "", int id = 0) { stop(stop_stop, msg, id); }
1002 void untested (const char* msg = "", int id = 0) { stop(stop_untested, msg, id); }
1003 void unimplemented(const char* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); }
1004 void should_not_reach_here(const char* msg = "", int id = -1) { stop(stop_shouldnotreachhere, msg, id); }
1005
1006 // Factor out part of stop into subroutine to save space.
1007 void stop_subroutine();
1008
1009 // Prints msg, but don't stop.
1010 void warn(const char* msg);
1011
1012 //-----------------------------
1013 //--- basic block tracing code
1014 //-----------------------------
1015 void trace_basic_block(uint i);
1016 void init_basic_block_trace();
1017 // Number of bytes a basic block gets larger due to the tracing code macro (worst case).
1018 // Currently, worst case is 48 bytes. 64 puts us securely on the safe side.
1019 static int basic_blck_trace_blk_size_incr() { return 64; }
1020
1021 // Write pattern 0x0101010101010101 in region [low-before, high+after].
1022 // Low and high may be the same registers. Before and after are
1023 // the numbers of 8-byte words.
1024 void zap_from_to(Register low, Register high, Register tmp1 = Z_R0, Register tmp2 = Z_R1,
1025 int before = 0, int after = 0) PRODUCT_RETURN;
1026
1027 // Emitters for CRC32 calculation.
1028 // A note on invertCRC:
1029 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
1030 // CRC32 holds it's current crc value in the externally visible representation.
1031 // CRC32C holds it's current crc value in internal format, ready for updating.
1032 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
1033 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
1034 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
1035 private:
1036 void fold_byte_crc32(Register crc, Register table, Register val, Register tmp);
1037 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1038 void update_byte_crc32( Register crc, Register val, Register table);
1039 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
1040 Register data);
1041 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
1042 Register t0, Register t1, Register t2, Register t3);
1043 public:
1044 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
1045 bool invertCRC);
1046 void kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp,
1047 bool invertCRC);
1048 void kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
1049 Register t0, Register t1, Register t2, Register t3,
1050 bool invertCRC);
1051 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
1052 Register t0, Register t1, Register t2, Register t3,
1053 bool invertCRC);
1054 void kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
1055 Register t0, Register t1, Register t2, Register t3,
1056 bool invertCRC);
1057
1058 // Emitters for BigInteger.multiplyToLen intrinsic
1059 // note: length of result array (zlen) is passed on the stack
1060 private:
1061 void add2_with_carry(Register dest_hi, Register dest_lo,
1062 Register src1, Register src2);
1063 void multiply_64_x_64_loop(Register x, Register xstart,
1064 Register x_xstart,
1065 Register y, Register y_idx, Register z,
1066 Register carry, Register product,
1067 Register idx, Register kdx);
1068 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1069 Register yz_idx, Register idx,
1070 Register carry, Register product, int offset);
1071 void multiply_128_x_128_loop(Register x_xstart,
1072 Register y, Register z,
1073 Register yz_idx, Register idx,
1074 Register jdx,
1075 Register carry, Register product,
1076 Register carry2);
1077 public:
1078 void multiply_to_len(Register x, Register xlen,
1079 Register y, Register ylen,
1080 Register z,
1081 Register tmp1, Register tmp2,
1082 Register tmp3, Register tmp4, Register tmp5);
1083 };
1084
1085 /**
1086 * class SkipIfEqual:
1087 *
1088 * Instantiating this class will result in assembly code being output that will
1089 * jump around any code emitted between the creation of the instance and it's
1090 * automatic destruction at the end of a scope block, depending on the value of
1091 * the flag passed to the constructor, which will be checked at run-time.
1092 */
1093 class SkipIfEqual {
1094 private:
1095 MacroAssembler* _masm;
1096 Label _label;
1097
1098 public:
1099 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value, Register _rscratch);
1100 ~SkipIfEqual();
1101 };
1102
1103 #ifdef ASSERT
1104 // Return false (e.g. important for our impl. of virtual calls).
1105 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1106 #endif
1107
1108 #endif // CPU_S390_VM_MACROASSEMBLER_S390_HPP