1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/jvm.h"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "runtime/thread.hpp"
44 #include "utilities/macros.hpp"
45 #if INCLUDE_ALL_GCS
46 #include "gc/g1/g1CollectedHeap.inline.hpp"
47 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
48 #include "gc/g1/heapRegion.hpp"
49 #endif // INCLUDE_ALL_GCS
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::extend_sign(Register hi, Register lo) {
130 // According to Intel Doc. AP-526, "Integer Divide", p.18.
131 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
132 cdql();
133 } else {
134 movl(hi, lo);
135 sarl(hi, 31);
136 }
137 }
138
139 void MacroAssembler::jC2(Register tmp, Label& L) {
140 // set parity bit if FPU flag C2 is set (via rax)
141 save_rax(tmp);
142 fwait(); fnstsw_ax();
143 sahf();
144 restore_rax(tmp);
145 // branch
146 jcc(Assembler::parity, L);
147 }
148
149 void MacroAssembler::jnC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::noParity, L);
157 }
158
159 // 32bit can do a case table jump in one instruction but we no longer allow the base
160 // to be installed in the Address class
161 void MacroAssembler::jump(ArrayAddress entry) {
162 jmp(as_Address(entry));
163 }
164
165 // Note: y_lo will be destroyed
166 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
167 // Long compare for Java (semantics as described in JVM spec.)
168 Label high, low, done;
169
170 cmpl(x_hi, y_hi);
171 jcc(Assembler::less, low);
172 jcc(Assembler::greater, high);
173 // x_hi is the return register
174 xorl(x_hi, x_hi);
175 cmpl(x_lo, y_lo);
176 jcc(Assembler::below, low);
177 jcc(Assembler::equal, done);
178
179 bind(high);
180 xorl(x_hi, x_hi);
181 increment(x_hi);
182 jmp(done);
183
184 bind(low);
185 xorl(x_hi, x_hi);
186 decrementl(x_hi);
187
188 bind(done);
189 }
190
191 void MacroAssembler::lea(Register dst, AddressLiteral src) {
192 mov_literal32(dst, (int32_t)src.target(), src.rspec());
193 }
194
195 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
196 // leal(dst, as_Address(adr));
197 // see note in movl as to why we must use a move
198 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
199 }
200
201 void MacroAssembler::leave() {
202 mov(rsp, rbp);
203 pop(rbp);
204 }
205
206 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
207 // Multiplication of two Java long values stored on the stack
208 // as illustrated below. Result is in rdx:rax.
209 //
210 // rsp ---> [ ?? ] \ \
211 // .... | y_rsp_offset |
212 // [ y_lo ] / (in bytes) | x_rsp_offset
213 // [ y_hi ] | (in bytes)
214 // .... |
215 // [ x_lo ] /
216 // [ x_hi ]
217 // ....
218 //
219 // Basic idea: lo(result) = lo(x_lo * y_lo)
220 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
221 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
222 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
223 Label quick;
224 // load x_hi, y_hi and check if quick
225 // multiplication is possible
226 movl(rbx, x_hi);
227 movl(rcx, y_hi);
228 movl(rax, rbx);
229 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
230 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
231 // do full multiplication
232 // 1st step
233 mull(y_lo); // x_hi * y_lo
234 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
235 // 2nd step
236 movl(rax, x_lo);
237 mull(rcx); // x_lo * y_hi
238 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
239 // 3rd step
240 bind(quick); // note: rbx, = 0 if quick multiply!
241 movl(rax, x_lo);
242 mull(y_lo); // x_lo * y_lo
243 addl(rdx, rbx); // correct hi(x_lo * y_lo)
244 }
245
246 void MacroAssembler::lneg(Register hi, Register lo) {
247 negl(lo);
248 adcl(hi, 0);
249 negl(hi);
250 }
251
252 void MacroAssembler::lshl(Register hi, Register lo) {
253 // Java shift left long support (semantics as described in JVM spec., p.305)
254 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
255 // shift value is in rcx !
256 assert(hi != rcx, "must not use rcx");
257 assert(lo != rcx, "must not use rcx");
258 const Register s = rcx; // shift count
259 const int n = BitsPerWord;
260 Label L;
261 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
262 cmpl(s, n); // if (s < n)
263 jcc(Assembler::less, L); // else (s >= n)
264 movl(hi, lo); // x := x << n
265 xorl(lo, lo);
266 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
267 bind(L); // s (mod n) < n
268 shldl(hi, lo); // x := x << s
269 shll(lo);
270 }
271
272
273 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
274 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
275 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
276 assert(hi != rcx, "must not use rcx");
277 assert(lo != rcx, "must not use rcx");
278 const Register s = rcx; // shift count
279 const int n = BitsPerWord;
280 Label L;
281 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
282 cmpl(s, n); // if (s < n)
283 jcc(Assembler::less, L); // else (s >= n)
284 movl(lo, hi); // x := x >> n
285 if (sign_extension) sarl(hi, 31);
286 else xorl(hi, hi);
287 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
288 bind(L); // s (mod n) < n
289 shrdl(lo, hi); // x := x >> s
290 if (sign_extension) sarl(hi);
291 else shrl(hi);
292 }
293
294 void MacroAssembler::movoop(Register dst, jobject obj) {
295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
296 }
297
298 void MacroAssembler::movoop(Address dst, jobject obj) {
299 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
300 }
301
302 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
304 }
305
306 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
307 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
308 }
309
310 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
311 // scratch register is not used,
312 // it is defined to match parameters of 64-bit version of this method.
313 if (src.is_lval()) {
314 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
315 } else {
316 movl(dst, as_Address(src));
317 }
318 }
319
320 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
321 movl(as_Address(dst), src);
322 }
323
324 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
325 movl(dst, as_Address(src));
326 }
327
328 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
329 void MacroAssembler::movptr(Address dst, intptr_t src) {
330 movl(dst, src);
331 }
332
333
334 void MacroAssembler::pop_callee_saved_registers() {
335 pop(rcx);
336 pop(rdx);
337 pop(rdi);
338 pop(rsi);
339 }
340
341 void MacroAssembler::pop_fTOS() {
342 fld_d(Address(rsp, 0));
343 addl(rsp, 2 * wordSize);
344 }
345
346 void MacroAssembler::push_callee_saved_registers() {
347 push(rsi);
348 push(rdi);
349 push(rdx);
350 push(rcx);
351 }
352
353 void MacroAssembler::push_fTOS() {
354 subl(rsp, 2 * wordSize);
355 fstp_d(Address(rsp, 0));
356 }
357
358
359 void MacroAssembler::pushoop(jobject obj) {
360 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
361 }
362
363 void MacroAssembler::pushklass(Metadata* obj) {
364 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
365 }
366
367 void MacroAssembler::pushptr(AddressLiteral src) {
368 if (src.is_lval()) {
369 push_literal32((int32_t)src.target(), src.rspec());
370 } else {
371 pushl(as_Address(src));
372 }
373 }
374
375 void MacroAssembler::set_word_if_not_zero(Register dst) {
376 xorl(dst, dst);
377 set_byte_if_not_zero(dst);
378 }
379
380 static void pass_arg0(MacroAssembler* masm, Register arg) {
381 masm->push(arg);
382 }
383
384 static void pass_arg1(MacroAssembler* masm, Register arg) {
385 masm->push(arg);
386 }
387
388 static void pass_arg2(MacroAssembler* masm, Register arg) {
389 masm->push(arg);
390 }
391
392 static void pass_arg3(MacroAssembler* masm, Register arg) {
393 masm->push(arg);
394 }
395
396 #ifndef PRODUCT
397 extern "C" void findpc(intptr_t x);
398 #endif
399
400 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
401 // In order to get locks to work, we need to fake a in_VM state
402 JavaThread* thread = JavaThread::current();
403 JavaThreadState saved_state = thread->thread_state();
404 thread->set_thread_state(_thread_in_vm);
405 if (ShowMessageBoxOnError) {
406 JavaThread* thread = JavaThread::current();
407 JavaThreadState saved_state = thread->thread_state();
408 thread->set_thread_state(_thread_in_vm);
409 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
410 ttyLocker ttyl;
411 BytecodeCounter::print();
412 }
413 // To see where a verify_oop failed, get $ebx+40/X for this frame.
414 // This is the value of eip which points to where verify_oop will return.
415 if (os::message_box(msg, "Execution stopped, print registers?")) {
416 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
417 BREAKPOINT;
418 }
419 } else {
420 ttyLocker ttyl;
421 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
422 }
423 // Don't assert holding the ttyLock
424 assert(false, "DEBUG MESSAGE: %s", msg);
425 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
426 }
427
428 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
429 ttyLocker ttyl;
430 FlagSetting fs(Debugging, true);
431 tty->print_cr("eip = 0x%08x", eip);
432 #ifndef PRODUCT
433 if ((WizardMode || Verbose) && PrintMiscellaneous) {
434 tty->cr();
435 findpc(eip);
436 tty->cr();
437 }
438 #endif
439 #define PRINT_REG(rax) \
440 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
441 PRINT_REG(rax);
442 PRINT_REG(rbx);
443 PRINT_REG(rcx);
444 PRINT_REG(rdx);
445 PRINT_REG(rdi);
446 PRINT_REG(rsi);
447 PRINT_REG(rbp);
448 PRINT_REG(rsp);
449 #undef PRINT_REG
450 // Print some words near top of staack.
451 int* dump_sp = (int*) rsp;
452 for (int col1 = 0; col1 < 8; col1++) {
453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
454 os::print_location(tty, *dump_sp++);
455 }
456 for (int row = 0; row < 16; row++) {
457 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
458 for (int col = 0; col < 8; col++) {
459 tty->print(" 0x%08x", *dump_sp++);
460 }
461 tty->cr();
462 }
463 // Print some instructions around pc:
464 Disassembler::decode((address)eip-64, (address)eip);
465 tty->print_cr("--------");
466 Disassembler::decode((address)eip, (address)eip+32);
467 }
468
469 void MacroAssembler::stop(const char* msg) {
470 ExternalAddress message((address)msg);
471 // push address of message
472 pushptr(message.addr());
473 { Label L; call(L, relocInfo::none); bind(L); } // push eip
474 pusha(); // push registers
475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
476 hlt();
477 }
478
479 void MacroAssembler::warn(const char* msg) {
480 push_CPU_state();
481
482 ExternalAddress message((address) msg);
483 // push address of message
484 pushptr(message.addr());
485
486 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
487 addl(rsp, wordSize); // discard argument
488 pop_CPU_state();
489 }
490
491 void MacroAssembler::print_state() {
492 { Label L; call(L, relocInfo::none); bind(L); } // push eip
493 pusha(); // push registers
494
495 push_CPU_state();
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
497 pop_CPU_state();
498
499 popa();
500 addl(rsp, wordSize);
501 }
502
503 #else // _LP64
504
505 // 64 bit versions
506
507 Address MacroAssembler::as_Address(AddressLiteral adr) {
508 // amd64 always does this as a pc-rel
509 // we can be absolute or disp based on the instruction type
510 // jmp/call are displacements others are absolute
511 assert(!adr.is_lval(), "must be rval");
512 assert(reachable(adr), "must be");
513 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
514
515 }
516
517 Address MacroAssembler::as_Address(ArrayAddress adr) {
518 AddressLiteral base = adr.base();
519 lea(rscratch1, base);
520 Address index = adr.index();
521 assert(index._disp == 0, "must not have disp"); // maybe it can?
522 Address array(rscratch1, index._index, index._scale, index._disp);
523 return array;
524 }
525
526 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
527 Label L, E;
528
529 #ifdef _WIN64
530 // Windows always allocates space for it's register args
531 assert(num_args <= 4, "only register arguments supported");
532 subq(rsp, frame::arg_reg_save_area_bytes);
533 #endif
534
535 // Align stack if necessary
536 testl(rsp, 15);
537 jcc(Assembler::zero, L);
538
539 subq(rsp, 8);
540 {
541 call(RuntimeAddress(entry_point));
542 }
543 addq(rsp, 8);
544 jmp(E);
545
546 bind(L);
547 {
548 call(RuntimeAddress(entry_point));
549 }
550
551 bind(E);
552
553 #ifdef _WIN64
554 // restore stack pointer
555 addq(rsp, frame::arg_reg_save_area_bytes);
556 #endif
557
558 }
559
560 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
561 assert(!src2.is_lval(), "should use cmpptr");
562
563 if (reachable(src2)) {
564 cmpq(src1, as_Address(src2));
565 } else {
566 lea(rscratch1, src2);
567 Assembler::cmpq(src1, Address(rscratch1, 0));
568 }
569 }
570
571 int MacroAssembler::corrected_idivq(Register reg) {
572 // Full implementation of Java ldiv and lrem; checks for special
573 // case as described in JVM spec., p.243 & p.271. The function
574 // returns the (pc) offset of the idivl instruction - may be needed
575 // for implicit exceptions.
576 //
577 // normal case special case
578 //
579 // input : rax: dividend min_long
580 // reg: divisor (may not be eax/edx) -1
581 //
582 // output: rax: quotient (= rax idiv reg) min_long
583 // rdx: remainder (= rax irem reg) 0
584 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
585 static const int64_t min_long = 0x8000000000000000;
586 Label normal_case, special_case;
587
588 // check for special case
589 cmp64(rax, ExternalAddress((address) &min_long));
590 jcc(Assembler::notEqual, normal_case);
591 xorl(rdx, rdx); // prepare rdx for possible special case (where
592 // remainder = 0)
593 cmpq(reg, -1);
594 jcc(Assembler::equal, special_case);
595
596 // handle normal case
597 bind(normal_case);
598 cdqq();
599 int idivq_offset = offset();
600 idivq(reg);
601
602 // normal and special case exit
603 bind(special_case);
604
605 return idivq_offset;
606 }
607
608 void MacroAssembler::decrementq(Register reg, int value) {
609 if (value == min_jint) { subq(reg, value); return; }
610 if (value < 0) { incrementq(reg, -value); return; }
611 if (value == 0) { ; return; }
612 if (value == 1 && UseIncDec) { decq(reg) ; return; }
613 /* else */ { subq(reg, value) ; return; }
614 }
615
616 void MacroAssembler::decrementq(Address dst, int value) {
617 if (value == min_jint) { subq(dst, value); return; }
618 if (value < 0) { incrementq(dst, -value); return; }
619 if (value == 0) { ; return; }
620 if (value == 1 && UseIncDec) { decq(dst) ; return; }
621 /* else */ { subq(dst, value) ; return; }
622 }
623
624 void MacroAssembler::incrementq(AddressLiteral dst) {
625 if (reachable(dst)) {
626 incrementq(as_Address(dst));
627 } else {
628 lea(rscratch1, dst);
629 incrementq(Address(rscratch1, 0));
630 }
631 }
632
633 void MacroAssembler::incrementq(Register reg, int value) {
634 if (value == min_jint) { addq(reg, value); return; }
635 if (value < 0) { decrementq(reg, -value); return; }
636 if (value == 0) { ; return; }
637 if (value == 1 && UseIncDec) { incq(reg) ; return; }
638 /* else */ { addq(reg, value) ; return; }
639 }
640
641 void MacroAssembler::incrementq(Address dst, int value) {
642 if (value == min_jint) { addq(dst, value); return; }
643 if (value < 0) { decrementq(dst, -value); return; }
644 if (value == 0) { ; return; }
645 if (value == 1 && UseIncDec) { incq(dst) ; return; }
646 /* else */ { addq(dst, value) ; return; }
647 }
648
649 // 32bit can do a case table jump in one instruction but we no longer allow the base
650 // to be installed in the Address class
651 void MacroAssembler::jump(ArrayAddress entry) {
652 lea(rscratch1, entry.base());
653 Address dispatch = entry.index();
654 assert(dispatch._base == noreg, "must be");
655 dispatch._base = rscratch1;
656 jmp(dispatch);
657 }
658
659 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
660 ShouldNotReachHere(); // 64bit doesn't use two regs
661 cmpq(x_lo, y_lo);
662 }
663
664 void MacroAssembler::lea(Register dst, AddressLiteral src) {
665 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
666 }
667
668 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
669 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
670 movptr(dst, rscratch1);
671 }
672
673 void MacroAssembler::leave() {
674 // %%% is this really better? Why not on 32bit too?
675 emit_int8((unsigned char)0xC9); // LEAVE
676 }
677
678 void MacroAssembler::lneg(Register hi, Register lo) {
679 ShouldNotReachHere(); // 64bit doesn't use two regs
680 negq(lo);
681 }
682
683 void MacroAssembler::movoop(Register dst, jobject obj) {
684 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
685 }
686
687 void MacroAssembler::movoop(Address dst, jobject obj) {
688 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
689 movq(dst, rscratch1);
690 }
691
692 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
693 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
694 }
695
696 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
697 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
698 movq(dst, rscratch1);
699 }
700
701 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
702 if (src.is_lval()) {
703 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
704 } else {
705 if (reachable(src)) {
706 movq(dst, as_Address(src));
707 } else {
708 lea(scratch, src);
709 movq(dst, Address(scratch, 0));
710 }
711 }
712 }
713
714 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
715 movq(as_Address(dst), src);
716 }
717
718 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
719 movq(dst, as_Address(src));
720 }
721
722 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
723 void MacroAssembler::movptr(Address dst, intptr_t src) {
724 mov64(rscratch1, src);
725 movq(dst, rscratch1);
726 }
727
728 // These are mostly for initializing NULL
729 void MacroAssembler::movptr(Address dst, int32_t src) {
730 movslq(dst, src);
731 }
732
733 void MacroAssembler::movptr(Register dst, int32_t src) {
734 mov64(dst, (intptr_t)src);
735 }
736
737 void MacroAssembler::pushoop(jobject obj) {
738 movoop(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushklass(Metadata* obj) {
743 mov_metadata(rscratch1, obj);
744 push(rscratch1);
745 }
746
747 void MacroAssembler::pushptr(AddressLiteral src) {
748 lea(rscratch1, src);
749 if (src.is_lval()) {
750 push(rscratch1);
751 } else {
752 pushq(Address(rscratch1, 0));
753 }
754 }
755
756 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
757 // we must set sp to zero to clear frame
758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
759 // must clear fp, so that compiled frames are not confused; it is
760 // possible that we need it only for debugging
761 if (clear_fp) {
762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
763 }
764
765 // Always clear the pc because it could have been set by make_walkable()
766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
767 vzeroupper();
768 }
769
770 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
771 Register last_java_fp,
772 address last_java_pc) {
773 vzeroupper();
774 // determine last_java_sp register
775 if (!last_java_sp->is_valid()) {
776 last_java_sp = rsp;
777 }
778
779 // last_java_fp is optional
780 if (last_java_fp->is_valid()) {
781 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
782 last_java_fp);
783 }
784
785 // last_java_pc is optional
786 if (last_java_pc != NULL) {
787 Address java_pc(r15_thread,
788 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
789 lea(rscratch1, InternalAddress(last_java_pc));
790 movptr(java_pc, rscratch1);
791 }
792
793 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
794 }
795
796 static void pass_arg0(MacroAssembler* masm, Register arg) {
797 if (c_rarg0 != arg ) {
798 masm->mov(c_rarg0, arg);
799 }
800 }
801
802 static void pass_arg1(MacroAssembler* masm, Register arg) {
803 if (c_rarg1 != arg ) {
804 masm->mov(c_rarg1, arg);
805 }
806 }
807
808 static void pass_arg2(MacroAssembler* masm, Register arg) {
809 if (c_rarg2 != arg ) {
810 masm->mov(c_rarg2, arg);
811 }
812 }
813
814 static void pass_arg3(MacroAssembler* masm, Register arg) {
815 if (c_rarg3 != arg ) {
816 masm->mov(c_rarg3, arg);
817 }
818 }
819
820 void MacroAssembler::stop(const char* msg) {
821 address rip = pc();
822 pusha(); // get regs on stack
823 lea(c_rarg0, ExternalAddress((address) msg));
824 lea(c_rarg1, InternalAddress(rip));
825 movq(c_rarg2, rsp); // pass pointer to regs array
826 andq(rsp, -16); // align stack as required by ABI
827 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
828 hlt();
829 }
830
831 void MacroAssembler::warn(const char* msg) {
832 push(rbp);
833 movq(rbp, rsp);
834 andq(rsp, -16); // align stack as required by push_CPU_state and call
835 push_CPU_state(); // keeps alignment at 16 bytes
836 lea(c_rarg0, ExternalAddress((address) msg));
837 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
838 pop_CPU_state();
839 mov(rsp, rbp);
840 pop(rbp);
841 }
842
843 void MacroAssembler::print_state() {
844 address rip = pc();
845 pusha(); // get regs on stack
846 push(rbp);
847 movq(rbp, rsp);
848 andq(rsp, -16); // align stack as required by push_CPU_state and call
849 push_CPU_state(); // keeps alignment at 16 bytes
850
851 lea(c_rarg0, InternalAddress(rip));
852 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
853 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
854
855 pop_CPU_state();
856 mov(rsp, rbp);
857 pop(rbp);
858 popa();
859 }
860
861 #ifndef PRODUCT
862 extern "C" void findpc(intptr_t x);
863 #endif
864
865 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
866 // In order to get locks to work, we need to fake a in_VM state
867 if (ShowMessageBoxOnError) {
868 JavaThread* thread = JavaThread::current();
869 JavaThreadState saved_state = thread->thread_state();
870 thread->set_thread_state(_thread_in_vm);
871 #ifndef PRODUCT
872 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
873 ttyLocker ttyl;
874 BytecodeCounter::print();
875 }
876 #endif
877 // To see where a verify_oop failed, get $ebx+40/X for this frame.
878 // XXX correct this offset for amd64
879 // This is the value of eip which points to where verify_oop will return.
880 if (os::message_box(msg, "Execution stopped, print registers?")) {
881 print_state64(pc, regs);
882 BREAKPOINT;
883 assert(false, "start up GDB");
884 }
885 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
886 } else {
887 ttyLocker ttyl;
888 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
889 msg);
890 assert(false, "DEBUG MESSAGE: %s", msg);
891 }
892 }
893
894 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
895 ttyLocker ttyl;
896 FlagSetting fs(Debugging, true);
897 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
898 #ifndef PRODUCT
899 tty->cr();
900 findpc(pc);
901 tty->cr();
902 #endif
903 #define PRINT_REG(rax, value) \
904 { tty->print("%s = ", #rax); os::print_location(tty, value); }
905 PRINT_REG(rax, regs[15]);
906 PRINT_REG(rbx, regs[12]);
907 PRINT_REG(rcx, regs[14]);
908 PRINT_REG(rdx, regs[13]);
909 PRINT_REG(rdi, regs[8]);
910 PRINT_REG(rsi, regs[9]);
911 PRINT_REG(rbp, regs[10]);
912 PRINT_REG(rsp, regs[11]);
913 PRINT_REG(r8 , regs[7]);
914 PRINT_REG(r9 , regs[6]);
915 PRINT_REG(r10, regs[5]);
916 PRINT_REG(r11, regs[4]);
917 PRINT_REG(r12, regs[3]);
918 PRINT_REG(r13, regs[2]);
919 PRINT_REG(r14, regs[1]);
920 PRINT_REG(r15, regs[0]);
921 #undef PRINT_REG
922 // Print some words near top of staack.
923 int64_t* rsp = (int64_t*) regs[11];
924 int64_t* dump_sp = rsp;
925 for (int col1 = 0; col1 < 8; col1++) {
926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
927 os::print_location(tty, *dump_sp++);
928 }
929 for (int row = 0; row < 25; row++) {
930 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
931 for (int col = 0; col < 4; col++) {
932 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
933 }
934 tty->cr();
935 }
936 // Print some instructions around pc:
937 Disassembler::decode((address)pc-64, (address)pc);
938 tty->print_cr("--------");
939 Disassembler::decode((address)pc, (address)pc+32);
940 }
941
942 #endif // _LP64
943
944 // Now versions that are common to 32/64 bit
945
946 void MacroAssembler::addptr(Register dst, int32_t imm32) {
947 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
948 }
949
950 void MacroAssembler::addptr(Register dst, Register src) {
951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
952 }
953
954 void MacroAssembler::addptr(Address dst, Register src) {
955 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
956 }
957
958 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
959 if (reachable(src)) {
960 Assembler::addsd(dst, as_Address(src));
961 } else {
962 lea(rscratch1, src);
963 Assembler::addsd(dst, Address(rscratch1, 0));
964 }
965 }
966
967 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
968 if (reachable(src)) {
969 addss(dst, as_Address(src));
970 } else {
971 lea(rscratch1, src);
972 addss(dst, Address(rscratch1, 0));
973 }
974 }
975
976 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
977 if (reachable(src)) {
978 Assembler::addpd(dst, as_Address(src));
979 } else {
980 lea(rscratch1, src);
981 Assembler::addpd(dst, Address(rscratch1, 0));
982 }
983 }
984
985 void MacroAssembler::align(int modulus) {
986 align(modulus, offset());
987 }
988
989 void MacroAssembler::align(int modulus, int target) {
990 if (target % modulus != 0) {
991 nop(modulus - (target % modulus));
992 }
993 }
994
995 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
996 // Used in sign-masking with aligned address.
997 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
998 if (reachable(src)) {
999 Assembler::andpd(dst, as_Address(src));
1000 } else {
1001 lea(rscratch1, src);
1002 Assembler::andpd(dst, Address(rscratch1, 0));
1003 }
1004 }
1005
1006 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andps(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andps(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1018 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1019 }
1020
1021 void MacroAssembler::atomic_incl(Address counter_addr) {
1022 if (os::is_MP())
1023 lock();
1024 incrementl(counter_addr);
1025 }
1026
1027 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1028 if (reachable(counter_addr)) {
1029 atomic_incl(as_Address(counter_addr));
1030 } else {
1031 lea(scr, counter_addr);
1032 atomic_incl(Address(scr, 0));
1033 }
1034 }
1035
1036 #ifdef _LP64
1037 void MacroAssembler::atomic_incq(Address counter_addr) {
1038 if (os::is_MP())
1039 lock();
1040 incrementq(counter_addr);
1041 }
1042
1043 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1044 if (reachable(counter_addr)) {
1045 atomic_incq(as_Address(counter_addr));
1046 } else {
1047 lea(scr, counter_addr);
1048 atomic_incq(Address(scr, 0));
1049 }
1050 }
1051 #endif
1052
1053 // Writes to stack successive pages until offset reached to check for
1054 // stack overflow + shadow pages. This clobbers tmp.
1055 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1056 movptr(tmp, rsp);
1057 // Bang stack for total size given plus shadow page size.
1058 // Bang one page at a time because large size can bang beyond yellow and
1059 // red zones.
1060 Label loop;
1061 bind(loop);
1062 movl(Address(tmp, (-os::vm_page_size())), size );
1063 subptr(tmp, os::vm_page_size());
1064 subl(size, os::vm_page_size());
1065 jcc(Assembler::greater, loop);
1066
1067 // Bang down shadow pages too.
1068 // At this point, (tmp-0) is the last address touched, so don't
1069 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1070 // was post-decremented.) Skip this address by starting at i=1, and
1071 // touch a few more pages below. N.B. It is important to touch all
1072 // the way down including all pages in the shadow zone.
1073 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1074 // this could be any sized move but this is can be a debugging crumb
1075 // so the bigger the better.
1076 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1077 }
1078 }
1079
1080 void MacroAssembler::reserved_stack_check() {
1081 // testing if reserved zone needs to be enabled
1082 Label no_reserved_zone_enabling;
1083 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1084 NOT_LP64(get_thread(rsi);)
1085
1086 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1087 jcc(Assembler::below, no_reserved_zone_enabling);
1088
1089 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1090 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1091 should_not_reach_here();
1092
1093 bind(no_reserved_zone_enabling);
1094 }
1095
1096 int MacroAssembler::biased_locking_enter(Register lock_reg,
1097 Register obj_reg,
1098 Register swap_reg,
1099 Register tmp_reg,
1100 bool swap_reg_contains_mark,
1101 Label& done,
1102 Label* slow_case,
1103 BiasedLockingCounters* counters) {
1104 assert(UseBiasedLocking, "why call this otherwise?");
1105 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1106 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1107 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1108 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1109 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1110 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1111
1112 if (PrintBiasedLockingStatistics && counters == NULL) {
1113 counters = BiasedLocking::counters();
1114 }
1115 // Biased locking
1116 // See whether the lock is currently biased toward our thread and
1117 // whether the epoch is still valid
1118 // Note that the runtime guarantees sufficient alignment of JavaThread
1119 // pointers to allow age to be placed into low bits
1120 // First check to see whether biasing is even enabled for this object
1121 Label cas_label;
1122 int null_check_offset = -1;
1123 if (!swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 movptr(swap_reg, mark_addr);
1126 }
1127 movptr(tmp_reg, swap_reg);
1128 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1129 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1130 jcc(Assembler::notEqual, cas_label);
1131 // The bias pattern is present in the object's header. Need to check
1132 // whether the bias owner and the epoch are both still current.
1133 #ifndef _LP64
1134 // Note that because there is no current thread register on x86_32 we
1135 // need to store off the mark word we read out of the object to
1136 // avoid reloading it and needing to recheck invariants below. This
1137 // store is unfortunate but it makes the overall code shorter and
1138 // simpler.
1139 movptr(saved_mark_addr, swap_reg);
1140 #endif
1141 if (swap_reg_contains_mark) {
1142 null_check_offset = offset();
1143 }
1144 load_prototype_header(tmp_reg, obj_reg);
1145 #ifdef _LP64
1146 orptr(tmp_reg, r15_thread);
1147 xorptr(tmp_reg, swap_reg);
1148 Register header_reg = tmp_reg;
1149 #else
1150 xorptr(tmp_reg, swap_reg);
1151 get_thread(swap_reg);
1152 xorptr(swap_reg, tmp_reg);
1153 Register header_reg = swap_reg;
1154 #endif
1155 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1156 if (counters != NULL) {
1157 cond_inc32(Assembler::zero,
1158 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1159 }
1160 jcc(Assembler::equal, done);
1161
1162 Label try_revoke_bias;
1163 Label try_rebias;
1164
1165 // At this point we know that the header has the bias pattern and
1166 // that we are not the bias owner in the current epoch. We need to
1167 // figure out more details about the state of the header in order to
1168 // know what operations can be legally performed on the object's
1169 // header.
1170
1171 // If the low three bits in the xor result aren't clear, that means
1172 // the prototype header is no longer biased and we have to revoke
1173 // the bias on this object.
1174 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1175 jccb(Assembler::notZero, try_revoke_bias);
1176
1177 // Biasing is still enabled for this data type. See whether the
1178 // epoch of the current bias is still valid, meaning that the epoch
1179 // bits of the mark word are equal to the epoch bits of the
1180 // prototype header. (Note that the prototype header's epoch bits
1181 // only change at a safepoint.) If not, attempt to rebias the object
1182 // toward the current thread. Note that we must be absolutely sure
1183 // that the current epoch is invalid in order to do this because
1184 // otherwise the manipulations it performs on the mark word are
1185 // illegal.
1186 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1187 jccb(Assembler::notZero, try_rebias);
1188
1189 // The epoch of the current bias is still valid but we know nothing
1190 // about the owner; it might be set or it might be clear. Try to
1191 // acquire the bias of the object using an atomic operation. If this
1192 // fails we will go in to the runtime to revoke the object's bias.
1193 // Note that we first construct the presumed unbiased header so we
1194 // don't accidentally blow away another thread's valid bias.
1195 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1196 andptr(swap_reg,
1197 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1198 #ifdef _LP64
1199 movptr(tmp_reg, swap_reg);
1200 orptr(tmp_reg, r15_thread);
1201 #else
1202 get_thread(tmp_reg);
1203 orptr(tmp_reg, swap_reg);
1204 #endif
1205 if (os::is_MP()) {
1206 lock();
1207 }
1208 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1209 // If the biasing toward our thread failed, this means that
1210 // another thread succeeded in biasing it toward itself and we
1211 // need to revoke that bias. The revocation will occur in the
1212 // interpreter runtime in the slow case.
1213 if (counters != NULL) {
1214 cond_inc32(Assembler::zero,
1215 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1216 }
1217 if (slow_case != NULL) {
1218 jcc(Assembler::notZero, *slow_case);
1219 }
1220 jmp(done);
1221
1222 bind(try_rebias);
1223 // At this point we know the epoch has expired, meaning that the
1224 // current "bias owner", if any, is actually invalid. Under these
1225 // circumstances _only_, we are allowed to use the current header's
1226 // value as the comparison value when doing the cas to acquire the
1227 // bias in the current epoch. In other words, we allow transfer of
1228 // the bias from one thread to another directly in this situation.
1229 //
1230 // FIXME: due to a lack of registers we currently blow away the age
1231 // bits in this situation. Should attempt to preserve them.
1232 load_prototype_header(tmp_reg, obj_reg);
1233 #ifdef _LP64
1234 orptr(tmp_reg, r15_thread);
1235 #else
1236 get_thread(swap_reg);
1237 orptr(tmp_reg, swap_reg);
1238 movptr(swap_reg, saved_mark_addr);
1239 #endif
1240 if (os::is_MP()) {
1241 lock();
1242 }
1243 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1244 // If the biasing toward our thread failed, then another thread
1245 // succeeded in biasing it toward itself and we need to revoke that
1246 // bias. The revocation will occur in the runtime in the slow case.
1247 if (counters != NULL) {
1248 cond_inc32(Assembler::zero,
1249 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1250 }
1251 if (slow_case != NULL) {
1252 jcc(Assembler::notZero, *slow_case);
1253 }
1254 jmp(done);
1255
1256 bind(try_revoke_bias);
1257 // The prototype mark in the klass doesn't have the bias bit set any
1258 // more, indicating that objects of this data type are not supposed
1259 // to be biased any more. We are going to try to reset the mark of
1260 // this object to the prototype value and fall through to the
1261 // CAS-based locking scheme. Note that if our CAS fails, it means
1262 // that another thread raced us for the privilege of revoking the
1263 // bias of this particular object, so it's okay to continue in the
1264 // normal locking code.
1265 //
1266 // FIXME: due to a lack of registers we currently blow away the age
1267 // bits in this situation. Should attempt to preserve them.
1268 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 // Fall through to the normal CAS-based lock, because no matter what
1275 // the result of the above CAS, some thread must have succeeded in
1276 // removing the bias bit from the object's header.
1277 if (counters != NULL) {
1278 cond_inc32(Assembler::zero,
1279 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1280 }
1281
1282 bind(cas_label);
1283
1284 return null_check_offset;
1285 }
1286
1287 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1288 assert(UseBiasedLocking, "why call this otherwise?");
1289
1290 // Check for biased locking unlock case, which is a no-op
1291 // Note: we do not have to check the thread ID for two reasons.
1292 // First, the interpreter checks for IllegalMonitorStateException at
1293 // a higher level. Second, if the bias was revoked while we held the
1294 // lock, the object could not be rebiased toward another thread, so
1295 // the bias bit would be clear.
1296 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1297 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1298 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1299 jcc(Assembler::equal, done);
1300 }
1301
1302 #ifdef COMPILER2
1303
1304 #if INCLUDE_RTM_OPT
1305
1306 // Update rtm_counters based on abort status
1307 // input: abort_status
1308 // rtm_counters (RTMLockingCounters*)
1309 // flags are killed
1310 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1311
1312 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1313 if (PrintPreciseRTMLockingStatistics) {
1314 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1315 Label check_abort;
1316 testl(abort_status, (1<<i));
1317 jccb(Assembler::equal, check_abort);
1318 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1319 bind(check_abort);
1320 }
1321 }
1322 }
1323
1324 // Branch if (random & (count-1) != 0), count is 2^n
1325 // tmp, scr and flags are killed
1326 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1327 assert(tmp == rax, "");
1328 assert(scr == rdx, "");
1329 rdtsc(); // modifies EDX:EAX
1330 andptr(tmp, count-1);
1331 jccb(Assembler::notZero, brLabel);
1332 }
1333
1334 // Perform abort ratio calculation, set no_rtm bit if high ratio
1335 // input: rtm_counters_Reg (RTMLockingCounters* address)
1336 // tmpReg, rtm_counters_Reg and flags are killed
1337 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1338 Register rtm_counters_Reg,
1339 RTMLockingCounters* rtm_counters,
1340 Metadata* method_data) {
1341 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1342
1343 if (RTMLockingCalculationDelay > 0) {
1344 // Delay calculation
1345 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1346 testptr(tmpReg, tmpReg);
1347 jccb(Assembler::equal, L_done);
1348 }
1349 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1350 // Aborted transactions = abort_count * 100
1351 // All transactions = total_count * RTMTotalCountIncrRate
1352 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1353
1354 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1355 cmpptr(tmpReg, RTMAbortThreshold);
1356 jccb(Assembler::below, L_check_always_rtm2);
1357 imulptr(tmpReg, tmpReg, 100);
1358
1359 Register scrReg = rtm_counters_Reg;
1360 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1361 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1362 imulptr(scrReg, scrReg, RTMAbortRatio);
1363 cmpptr(tmpReg, scrReg);
1364 jccb(Assembler::below, L_check_always_rtm1);
1365 if (method_data != NULL) {
1366 // set rtm_state to "no rtm" in MDO
1367 mov_metadata(tmpReg, method_data);
1368 if (os::is_MP()) {
1369 lock();
1370 }
1371 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1372 }
1373 jmpb(L_done);
1374 bind(L_check_always_rtm1);
1375 // Reload RTMLockingCounters* address
1376 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1377 bind(L_check_always_rtm2);
1378 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1379 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1380 jccb(Assembler::below, L_done);
1381 if (method_data != NULL) {
1382 // set rtm_state to "always rtm" in MDO
1383 mov_metadata(tmpReg, method_data);
1384 if (os::is_MP()) {
1385 lock();
1386 }
1387 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1388 }
1389 bind(L_done);
1390 }
1391
1392 // Update counters and perform abort ratio calculation
1393 // input: abort_status_Reg
1394 // rtm_counters_Reg, flags are killed
1395 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1396 Register rtm_counters_Reg,
1397 RTMLockingCounters* rtm_counters,
1398 Metadata* method_data,
1399 bool profile_rtm) {
1400
1401 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1402 // update rtm counters based on rax value at abort
1403 // reads abort_status_Reg, updates flags
1404 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1405 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1406 if (profile_rtm) {
1407 // Save abort status because abort_status_Reg is used by following code.
1408 if (RTMRetryCount > 0) {
1409 push(abort_status_Reg);
1410 }
1411 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1412 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1413 // restore abort status
1414 if (RTMRetryCount > 0) {
1415 pop(abort_status_Reg);
1416 }
1417 }
1418 }
1419
1420 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1421 // inputs: retry_count_Reg
1422 // : abort_status_Reg
1423 // output: retry_count_Reg decremented by 1
1424 // flags are killed
1425 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1426 Label doneRetry;
1427 assert(abort_status_Reg == rax, "");
1428 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1429 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1430 // if reason is in 0x6 and retry count != 0 then retry
1431 andptr(abort_status_Reg, 0x6);
1432 jccb(Assembler::zero, doneRetry);
1433 testl(retry_count_Reg, retry_count_Reg);
1434 jccb(Assembler::zero, doneRetry);
1435 pause();
1436 decrementl(retry_count_Reg);
1437 jmp(retryLabel);
1438 bind(doneRetry);
1439 }
1440
1441 // Spin and retry if lock is busy,
1442 // inputs: box_Reg (monitor address)
1443 // : retry_count_Reg
1444 // output: retry_count_Reg decremented by 1
1445 // : clear z flag if retry count exceeded
1446 // tmp_Reg, scr_Reg, flags are killed
1447 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1448 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1449 Label SpinLoop, SpinExit, doneRetry;
1450 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1451
1452 testl(retry_count_Reg, retry_count_Reg);
1453 jccb(Assembler::zero, doneRetry);
1454 decrementl(retry_count_Reg);
1455 movptr(scr_Reg, RTMSpinLoopCount);
1456
1457 bind(SpinLoop);
1458 pause();
1459 decrementl(scr_Reg);
1460 jccb(Assembler::lessEqual, SpinExit);
1461 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1462 testptr(tmp_Reg, tmp_Reg);
1463 jccb(Assembler::notZero, SpinLoop);
1464
1465 bind(SpinExit);
1466 jmp(retryLabel);
1467 bind(doneRetry);
1468 incrementl(retry_count_Reg); // clear z flag
1469 }
1470
1471 // Use RTM for normal stack locks
1472 // Input: objReg (object to lock)
1473 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1474 Register retry_on_abort_count_Reg,
1475 RTMLockingCounters* stack_rtm_counters,
1476 Metadata* method_data, bool profile_rtm,
1477 Label& DONE_LABEL, Label& IsInflated) {
1478 assert(UseRTMForStackLocks, "why call this otherwise?");
1479 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1480 assert(tmpReg == rax, "");
1481 assert(scrReg == rdx, "");
1482 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1483
1484 if (RTMRetryCount > 0) {
1485 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1486 bind(L_rtm_retry);
1487 }
1488 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1489 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1490 jcc(Assembler::notZero, IsInflated);
1491
1492 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1493 Label L_noincrement;
1494 if (RTMTotalCountIncrRate > 1) {
1495 // tmpReg, scrReg and flags are killed
1496 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1497 }
1498 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1499 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1500 bind(L_noincrement);
1501 }
1502 xbegin(L_on_abort);
1503 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1504 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1505 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1506 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1507
1508 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1509 if (UseRTMXendForLockBusy) {
1510 xend();
1511 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1512 jmp(L_decrement_retry);
1513 }
1514 else {
1515 xabort(0);
1516 }
1517 bind(L_on_abort);
1518 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1519 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1520 }
1521 bind(L_decrement_retry);
1522 if (RTMRetryCount > 0) {
1523 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1524 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1525 }
1526 }
1527
1528 // Use RTM for inflating locks
1529 // inputs: objReg (object to lock)
1530 // boxReg (on-stack box address (displaced header location) - KILLED)
1531 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1532 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1533 Register scrReg, Register retry_on_busy_count_Reg,
1534 Register retry_on_abort_count_Reg,
1535 RTMLockingCounters* rtm_counters,
1536 Metadata* method_data, bool profile_rtm,
1537 Label& DONE_LABEL) {
1538 assert(UseRTMLocking, "why call this otherwise?");
1539 assert(tmpReg == rax, "");
1540 assert(scrReg == rdx, "");
1541 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1542 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1543
1544 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1545 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1546 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1547
1548 if (RTMRetryCount > 0) {
1549 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1550 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1551 bind(L_rtm_retry);
1552 }
1553 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1554 Label L_noincrement;
1555 if (RTMTotalCountIncrRate > 1) {
1556 // tmpReg, scrReg and flags are killed
1557 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1558 }
1559 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1560 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1561 bind(L_noincrement);
1562 }
1563 xbegin(L_on_abort);
1564 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1565 movptr(tmpReg, Address(tmpReg, owner_offset));
1566 testptr(tmpReg, tmpReg);
1567 jcc(Assembler::zero, DONE_LABEL);
1568 if (UseRTMXendForLockBusy) {
1569 xend();
1570 jmp(L_decrement_retry);
1571 }
1572 else {
1573 xabort(0);
1574 }
1575 bind(L_on_abort);
1576 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1577 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1578 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1579 }
1580 if (RTMRetryCount > 0) {
1581 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1582 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1583 }
1584
1585 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1586 testptr(tmpReg, tmpReg) ;
1587 jccb(Assembler::notZero, L_decrement_retry) ;
1588
1589 // Appears unlocked - try to swing _owner from null to non-null.
1590 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1591 #ifdef _LP64
1592 Register threadReg = r15_thread;
1593 #else
1594 get_thread(scrReg);
1595 Register threadReg = scrReg;
1596 #endif
1597 if (os::is_MP()) {
1598 lock();
1599 }
1600 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1601
1602 if (RTMRetryCount > 0) {
1603 // success done else retry
1604 jccb(Assembler::equal, DONE_LABEL) ;
1605 bind(L_decrement_retry);
1606 // Spin and retry if lock is busy.
1607 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1608 }
1609 else {
1610 bind(L_decrement_retry);
1611 }
1612 }
1613
1614 #endif // INCLUDE_RTM_OPT
1615
1616 // Fast_Lock and Fast_Unlock used by C2
1617
1618 // Because the transitions from emitted code to the runtime
1619 // monitorenter/exit helper stubs are so slow it's critical that
1620 // we inline both the stack-locking fast-path and the inflated fast path.
1621 //
1622 // See also: cmpFastLock and cmpFastUnlock.
1623 //
1624 // What follows is a specialized inline transliteration of the code
1625 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1626 // another option would be to emit TrySlowEnter and TrySlowExit methods
1627 // at startup-time. These methods would accept arguments as
1628 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1629 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1630 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1631 // In practice, however, the # of lock sites is bounded and is usually small.
1632 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1633 // if the processor uses simple bimodal branch predictors keyed by EIP
1634 // Since the helper routines would be called from multiple synchronization
1635 // sites.
1636 //
1637 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1638 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1639 // to those specialized methods. That'd give us a mostly platform-independent
1640 // implementation that the JITs could optimize and inline at their pleasure.
1641 // Done correctly, the only time we'd need to cross to native could would be
1642 // to park() or unpark() threads. We'd also need a few more unsafe operators
1643 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1644 // (b) explicit barriers or fence operations.
1645 //
1646 // TODO:
1647 //
1648 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1649 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1650 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1651 // the lock operators would typically be faster than reifying Self.
1652 //
1653 // * Ideally I'd define the primitives as:
1654 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1655 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1656 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1657 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1658 // Furthermore the register assignments are overconstrained, possibly resulting in
1659 // sub-optimal code near the synchronization site.
1660 //
1661 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1662 // Alternately, use a better sp-proximity test.
1663 //
1664 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1665 // Either one is sufficient to uniquely identify a thread.
1666 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1667 //
1668 // * Intrinsify notify() and notifyAll() for the common cases where the
1669 // object is locked by the calling thread but the waitlist is empty.
1670 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1671 //
1672 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1673 // But beware of excessive branch density on AMD Opterons.
1674 //
1675 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1676 // or failure of the fast-path. If the fast-path fails then we pass
1677 // control to the slow-path, typically in C. In Fast_Lock and
1678 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1679 // will emit a conditional branch immediately after the node.
1680 // So we have branches to branches and lots of ICC.ZF games.
1681 // Instead, it might be better to have C2 pass a "FailureLabel"
1682 // into Fast_Lock and Fast_Unlock. In the case of success, control
1683 // will drop through the node. ICC.ZF is undefined at exit.
1684 // In the case of failure, the node will branch directly to the
1685 // FailureLabel
1686
1687
1688 // obj: object to lock
1689 // box: on-stack box address (displaced header location) - KILLED
1690 // rax,: tmp -- KILLED
1691 // scr: tmp -- KILLED
1692 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1693 Register scrReg, Register cx1Reg, Register cx2Reg,
1694 BiasedLockingCounters* counters,
1695 RTMLockingCounters* rtm_counters,
1696 RTMLockingCounters* stack_rtm_counters,
1697 Metadata* method_data,
1698 bool use_rtm, bool profile_rtm) {
1699 // Ensure the register assignments are disjoint
1700 assert(tmpReg == rax, "");
1701
1702 if (use_rtm) {
1703 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1704 } else {
1705 assert(cx1Reg == noreg, "");
1706 assert(cx2Reg == noreg, "");
1707 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1708 }
1709
1710 if (counters != NULL) {
1711 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1712 }
1713 if (EmitSync & 1) {
1714 // set box->dhw = markOopDesc::unused_mark()
1715 // Force all sync thru slow-path: slow_enter() and slow_exit()
1716 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1717 cmpptr (rsp, (int32_t)NULL_WORD);
1718 } else {
1719 // Possible cases that we'll encounter in fast_lock
1720 // ------------------------------------------------
1721 // * Inflated
1722 // -- unlocked
1723 // -- Locked
1724 // = by self
1725 // = by other
1726 // * biased
1727 // -- by Self
1728 // -- by other
1729 // * neutral
1730 // * stack-locked
1731 // -- by self
1732 // = sp-proximity test hits
1733 // = sp-proximity test generates false-negative
1734 // -- by other
1735 //
1736
1737 Label IsInflated, DONE_LABEL;
1738
1739 // it's stack-locked, biased or neutral
1740 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1741 // order to reduce the number of conditional branches in the most common cases.
1742 // Beware -- there's a subtle invariant that fetch of the markword
1743 // at [FETCH], below, will never observe a biased encoding (*101b).
1744 // If this invariant is not held we risk exclusion (safety) failure.
1745 if (UseBiasedLocking && !UseOptoBiasInlining) {
1746 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1747 }
1748
1749 #if INCLUDE_RTM_OPT
1750 if (UseRTMForStackLocks && use_rtm) {
1751 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1752 stack_rtm_counters, method_data, profile_rtm,
1753 DONE_LABEL, IsInflated);
1754 }
1755 #endif // INCLUDE_RTM_OPT
1756
1757 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1758 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1759 jccb(Assembler::notZero, IsInflated);
1760
1761 // Attempt stack-locking ...
1762 orptr (tmpReg, markOopDesc::unlocked_value);
1763 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1764 if (os::is_MP()) {
1765 lock();
1766 }
1767 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1768 if (counters != NULL) {
1769 cond_inc32(Assembler::equal,
1770 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1771 }
1772 jcc(Assembler::equal, DONE_LABEL); // Success
1773
1774 // Recursive locking.
1775 // The object is stack-locked: markword contains stack pointer to BasicLock.
1776 // Locked by current thread if difference with current SP is less than one page.
1777 subptr(tmpReg, rsp);
1778 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1779 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1780 movptr(Address(boxReg, 0), tmpReg);
1781 if (counters != NULL) {
1782 cond_inc32(Assembler::equal,
1783 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1784 }
1785 jmp(DONE_LABEL);
1786
1787 bind(IsInflated);
1788 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1789
1790 #if INCLUDE_RTM_OPT
1791 // Use the same RTM locking code in 32- and 64-bit VM.
1792 if (use_rtm) {
1793 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1794 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1795 } else {
1796 #endif // INCLUDE_RTM_OPT
1797
1798 #ifndef _LP64
1799 // The object is inflated.
1800
1801 // boxReg refers to the on-stack BasicLock in the current frame.
1802 // We'd like to write:
1803 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1804 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1805 // additional latency as we have another ST in the store buffer that must drain.
1806
1807 if (EmitSync & 8192) {
1808 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1809 get_thread (scrReg);
1810 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1811 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1812 if (os::is_MP()) {
1813 lock();
1814 }
1815 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1816 } else
1817 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1818 // register juggle because we need tmpReg for cmpxchgptr below
1819 movptr(scrReg, boxReg);
1820 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1821
1822 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1823 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1824 // prefetchw [eax + Offset(_owner)-2]
1825 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1826 }
1827
1828 if ((EmitSync & 64) == 0) {
1829 // Optimistic form: consider XORL tmpReg,tmpReg
1830 movptr(tmpReg, NULL_WORD);
1831 } else {
1832 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1833 // Test-And-CAS instead of CAS
1834 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1835 testptr(tmpReg, tmpReg); // Locked ?
1836 jccb (Assembler::notZero, DONE_LABEL);
1837 }
1838
1839 // Appears unlocked - try to swing _owner from null to non-null.
1840 // Ideally, I'd manifest "Self" with get_thread and then attempt
1841 // to CAS the register containing Self into m->Owner.
1842 // But we don't have enough registers, so instead we can either try to CAS
1843 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1844 // we later store "Self" into m->Owner. Transiently storing a stack address
1845 // (rsp or the address of the box) into m->owner is harmless.
1846 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1847 if (os::is_MP()) {
1848 lock();
1849 }
1850 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1851 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1852 // If we weren't able to swing _owner from NULL to the BasicLock
1853 // then take the slow path.
1854 jccb (Assembler::notZero, DONE_LABEL);
1855 // update _owner from BasicLock to thread
1856 get_thread (scrReg); // beware: clobbers ICCs
1857 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1858 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1859
1860 // If the CAS fails we can either retry or pass control to the slow-path.
1861 // We use the latter tactic.
1862 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1863 // If the CAS was successful ...
1864 // Self has acquired the lock
1865 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1866 // Intentional fall-through into DONE_LABEL ...
1867 } else {
1868 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1869 movptr(boxReg, tmpReg);
1870
1871 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1872 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1873 // prefetchw [eax + Offset(_owner)-2]
1874 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1875 }
1876
1877 if ((EmitSync & 64) == 0) {
1878 // Optimistic form
1879 xorptr (tmpReg, tmpReg);
1880 } else {
1881 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1882 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1883 testptr(tmpReg, tmpReg); // Locked ?
1884 jccb (Assembler::notZero, DONE_LABEL);
1885 }
1886
1887 // Appears unlocked - try to swing _owner from null to non-null.
1888 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1889 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1890 get_thread (scrReg);
1891 if (os::is_MP()) {
1892 lock();
1893 }
1894 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1895
1896 // If the CAS fails we can either retry or pass control to the slow-path.
1897 // We use the latter tactic.
1898 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1899 // If the CAS was successful ...
1900 // Self has acquired the lock
1901 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1902 // Intentional fall-through into DONE_LABEL ...
1903 }
1904 #else // _LP64
1905 // It's inflated
1906 movq(scrReg, tmpReg);
1907 xorq(tmpReg, tmpReg);
1908
1909 if (os::is_MP()) {
1910 lock();
1911 }
1912 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1913 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1914 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1915 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1916 // Intentional fall-through into DONE_LABEL ...
1917 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1918 #endif // _LP64
1919 #if INCLUDE_RTM_OPT
1920 } // use_rtm()
1921 #endif
1922 // DONE_LABEL is a hot target - we'd really like to place it at the
1923 // start of cache line by padding with NOPs.
1924 // See the AMD and Intel software optimization manuals for the
1925 // most efficient "long" NOP encodings.
1926 // Unfortunately none of our alignment mechanisms suffice.
1927 bind(DONE_LABEL);
1928
1929 // At DONE_LABEL the icc ZFlag is set as follows ...
1930 // Fast_Unlock uses the same protocol.
1931 // ZFlag == 1 -> Success
1932 // ZFlag == 0 -> Failure - force control through the slow-path
1933 }
1934 }
1935
1936 // obj: object to unlock
1937 // box: box address (displaced header location), killed. Must be EAX.
1938 // tmp: killed, cannot be obj nor box.
1939 //
1940 // Some commentary on balanced locking:
1941 //
1942 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1943 // Methods that don't have provably balanced locking are forced to run in the
1944 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1945 // The interpreter provides two properties:
1946 // I1: At return-time the interpreter automatically and quietly unlocks any
1947 // objects acquired the current activation (frame). Recall that the
1948 // interpreter maintains an on-stack list of locks currently held by
1949 // a frame.
1950 // I2: If a method attempts to unlock an object that is not held by the
1951 // the frame the interpreter throws IMSX.
1952 //
1953 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1954 // B() doesn't have provably balanced locking so it runs in the interpreter.
1955 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1956 // is still locked by A().
1957 //
1958 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1959 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1960 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1961 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1962 // Arguably given that the spec legislates the JNI case as undefined our implementation
1963 // could reasonably *avoid* checking owner in Fast_Unlock().
1964 // In the interest of performance we elide m->Owner==Self check in unlock.
1965 // A perfectly viable alternative is to elide the owner check except when
1966 // Xcheck:jni is enabled.
1967
1968 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1969 assert(boxReg == rax, "");
1970 assert_different_registers(objReg, boxReg, tmpReg);
1971
1972 if (EmitSync & 4) {
1973 // Disable - inhibit all inlining. Force control through the slow-path
1974 cmpptr (rsp, 0);
1975 } else {
1976 Label DONE_LABEL, Stacked, CheckSucc;
1977
1978 // Critically, the biased locking test must have precedence over
1979 // and appear before the (box->dhw == 0) recursive stack-lock test.
1980 if (UseBiasedLocking && !UseOptoBiasInlining) {
1981 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1982 }
1983
1984 #if INCLUDE_RTM_OPT
1985 if (UseRTMForStackLocks && use_rtm) {
1986 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1987 Label L_regular_unlock;
1988 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1989 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1990 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1991 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1992 xend(); // otherwise end...
1993 jmp(DONE_LABEL); // ... and we're done
1994 bind(L_regular_unlock);
1995 }
1996 #endif
1997
1998 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1999 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2000 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2001 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2002 jccb (Assembler::zero, Stacked);
2003
2004 // It's inflated.
2005 #if INCLUDE_RTM_OPT
2006 if (use_rtm) {
2007 Label L_regular_inflated_unlock;
2008 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2009 movptr(boxReg, Address(tmpReg, owner_offset));
2010 testptr(boxReg, boxReg);
2011 jccb(Assembler::notZero, L_regular_inflated_unlock);
2012 xend();
2013 jmpb(DONE_LABEL);
2014 bind(L_regular_inflated_unlock);
2015 }
2016 #endif
2017
2018 // Despite our balanced locking property we still check that m->_owner == Self
2019 // as java routines or native JNI code called by this thread might
2020 // have released the lock.
2021 // Refer to the comments in synchronizer.cpp for how we might encode extra
2022 // state in _succ so we can avoid fetching EntryList|cxq.
2023 //
2024 // I'd like to add more cases in fast_lock() and fast_unlock() --
2025 // such as recursive enter and exit -- but we have to be wary of
2026 // I$ bloat, T$ effects and BP$ effects.
2027 //
2028 // If there's no contention try a 1-0 exit. That is, exit without
2029 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2030 // we detect and recover from the race that the 1-0 exit admits.
2031 //
2032 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2033 // before it STs null into _owner, releasing the lock. Updates
2034 // to data protected by the critical section must be visible before
2035 // we drop the lock (and thus before any other thread could acquire
2036 // the lock and observe the fields protected by the lock).
2037 // IA32's memory-model is SPO, so STs are ordered with respect to
2038 // each other and there's no need for an explicit barrier (fence).
2039 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2040 #ifndef _LP64
2041 get_thread (boxReg);
2042 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2043 // prefetchw [ebx + Offset(_owner)-2]
2044 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2045 }
2046
2047 // Note that we could employ various encoding schemes to reduce
2048 // the number of loads below (currently 4) to just 2 or 3.
2049 // Refer to the comments in synchronizer.cpp.
2050 // In practice the chain of fetches doesn't seem to impact performance, however.
2051 xorptr(boxReg, boxReg);
2052 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2053 // Attempt to reduce branch density - AMD's branch predictor.
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2056 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2057 jccb (Assembler::notZero, DONE_LABEL);
2058 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2059 jmpb (DONE_LABEL);
2060 } else {
2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2062 jccb (Assembler::notZero, DONE_LABEL);
2063 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2064 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2065 jccb (Assembler::notZero, CheckSucc);
2066 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2067 jmpb (DONE_LABEL);
2068 }
2069
2070 // The Following code fragment (EmitSync & 65536) improves the performance of
2071 // contended applications and contended synchronization microbenchmarks.
2072 // Unfortunately the emission of the code - even though not executed - causes regressions
2073 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2074 // with an equal number of never-executed NOPs results in the same regression.
2075 // We leave it off by default.
2076
2077 if ((EmitSync & 65536) != 0) {
2078 Label LSuccess, LGoSlowPath ;
2079
2080 bind (CheckSucc);
2081
2082 // Optional pre-test ... it's safe to elide this
2083 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2084 jccb(Assembler::zero, LGoSlowPath);
2085
2086 // We have a classic Dekker-style idiom:
2087 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2088 // There are a number of ways to implement the barrier:
2089 // (1) lock:andl &m->_owner, 0
2090 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2091 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2092 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2093 // (2) If supported, an explicit MFENCE is appealing.
2094 // In older IA32 processors MFENCE is slower than lock:add or xchg
2095 // particularly if the write-buffer is full as might be the case if
2096 // if stores closely precede the fence or fence-equivalent instruction.
2097 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2098 // as the situation has changed with Nehalem and Shanghai.
2099 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2100 // The $lines underlying the top-of-stack should be in M-state.
2101 // The locked add instruction is serializing, of course.
2102 // (4) Use xchg, which is serializing
2103 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2104 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2105 // The integer condition codes will tell us if succ was 0.
2106 // Since _succ and _owner should reside in the same $line and
2107 // we just stored into _owner, it's likely that the $line
2108 // remains in M-state for the lock:orl.
2109 //
2110 // We currently use (3), although it's likely that switching to (2)
2111 // is correct for the future.
2112
2113 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2114 if (os::is_MP()) {
2115 lock(); addptr(Address(rsp, 0), 0);
2116 }
2117 // Ratify _succ remains non-null
2118 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2119 jccb (Assembler::notZero, LSuccess);
2120
2121 xorptr(boxReg, boxReg); // box is really EAX
2122 if (os::is_MP()) { lock(); }
2123 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2124 // There's no successor so we tried to regrab the lock with the
2125 // placeholder value. If that didn't work, then another thread
2126 // grabbed the lock so we're done (and exit was a success).
2127 jccb (Assembler::notEqual, LSuccess);
2128 // Since we're low on registers we installed rsp as a placeholding in _owner.
2129 // Now install Self over rsp. This is safe as we're transitioning from
2130 // non-null to non=null
2131 get_thread (boxReg);
2132 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2133 // Intentional fall-through into LGoSlowPath ...
2134
2135 bind (LGoSlowPath);
2136 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2137 jmpb (DONE_LABEL);
2138
2139 bind (LSuccess);
2140 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2141 jmpb (DONE_LABEL);
2142 }
2143
2144 bind (Stacked);
2145 // It's not inflated and it's not recursively stack-locked and it's not biased.
2146 // It must be stack-locked.
2147 // Try to reset the header to displaced header.
2148 // The "box" value on the stack is stable, so we can reload
2149 // and be assured we observe the same value as above.
2150 movptr(tmpReg, Address(boxReg, 0));
2151 if (os::is_MP()) {
2152 lock();
2153 }
2154 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2155 // Intention fall-thru into DONE_LABEL
2156
2157 // DONE_LABEL is a hot target - we'd really like to place it at the
2158 // start of cache line by padding with NOPs.
2159 // See the AMD and Intel software optimization manuals for the
2160 // most efficient "long" NOP encodings.
2161 // Unfortunately none of our alignment mechanisms suffice.
2162 if ((EmitSync & 65536) == 0) {
2163 bind (CheckSucc);
2164 }
2165 #else // _LP64
2166 // It's inflated
2167 if (EmitSync & 1024) {
2168 // Emit code to check that _owner == Self
2169 // We could fold the _owner test into subsequent code more efficiently
2170 // than using a stand-alone check, but since _owner checking is off by
2171 // default we don't bother. We also might consider predicating the
2172 // _owner==Self check on Xcheck:jni or running on a debug build.
2173 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2174 xorptr(boxReg, r15_thread);
2175 } else {
2176 xorptr(boxReg, boxReg);
2177 }
2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2179 jccb (Assembler::notZero, DONE_LABEL);
2180 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2181 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2182 jccb (Assembler::notZero, CheckSucc);
2183 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2184 jmpb (DONE_LABEL);
2185
2186 if ((EmitSync & 65536) == 0) {
2187 // Try to avoid passing control into the slow_path ...
2188 Label LSuccess, LGoSlowPath ;
2189 bind (CheckSucc);
2190
2191 // The following optional optimization can be elided if necessary
2192 // Effectively: if (succ == null) goto SlowPath
2193 // The code reduces the window for a race, however,
2194 // and thus benefits performance.
2195 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2196 jccb (Assembler::zero, LGoSlowPath);
2197
2198 xorptr(boxReg, boxReg);
2199 if ((EmitSync & 16) && os::is_MP()) {
2200 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2201 } else {
2202 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2203 if (os::is_MP()) {
2204 // Memory barrier/fence
2205 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2206 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2207 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2208 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2209 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2210 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2211 lock(); addl(Address(rsp, 0), 0);
2212 }
2213 }
2214 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2215 jccb (Assembler::notZero, LSuccess);
2216
2217 // Rare inopportune interleaving - race.
2218 // The successor vanished in the small window above.
2219 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2220 // We need to ensure progress and succession.
2221 // Try to reacquire the lock.
2222 // If that fails then the new owner is responsible for succession and this
2223 // thread needs to take no further action and can exit via the fast path (success).
2224 // If the re-acquire succeeds then pass control into the slow path.
2225 // As implemented, this latter mode is horrible because we generated more
2226 // coherence traffic on the lock *and* artifically extended the critical section
2227 // length while by virtue of passing control into the slow path.
2228
2229 // box is really RAX -- the following CMPXCHG depends on that binding
2230 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2231 if (os::is_MP()) { lock(); }
2232 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2233 // There's no successor so we tried to regrab the lock.
2234 // If that didn't work, then another thread grabbed the
2235 // lock so we're done (and exit was a success).
2236 jccb (Assembler::notEqual, LSuccess);
2237 // Intentional fall-through into slow-path
2238
2239 bind (LGoSlowPath);
2240 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2241 jmpb (DONE_LABEL);
2242
2243 bind (LSuccess);
2244 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2245 jmpb (DONE_LABEL);
2246 }
2247
2248 bind (Stacked);
2249 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2250 if (os::is_MP()) { lock(); }
2251 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2252
2253 if (EmitSync & 65536) {
2254 bind (CheckSucc);
2255 }
2256 #endif
2257 bind(DONE_LABEL);
2258 }
2259 }
2260 #endif // COMPILER2
2261
2262 void MacroAssembler::c2bool(Register x) {
2263 // implements x == 0 ? 0 : 1
2264 // note: must only look at least-significant byte of x
2265 // since C-style booleans are stored in one byte
2266 // only! (was bug)
2267 andl(x, 0xFF);
2268 setb(Assembler::notZero, x);
2269 }
2270
2271 // Wouldn't need if AddressLiteral version had new name
2272 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2273 Assembler::call(L, rtype);
2274 }
2275
2276 void MacroAssembler::call(Register entry) {
2277 Assembler::call(entry);
2278 }
2279
2280 void MacroAssembler::call(AddressLiteral entry) {
2281 if (reachable(entry)) {
2282 Assembler::call_literal(entry.target(), entry.rspec());
2283 } else {
2284 lea(rscratch1, entry);
2285 Assembler::call(rscratch1);
2286 }
2287 }
2288
2289 void MacroAssembler::ic_call(address entry, jint method_index) {
2290 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2291 movptr(rax, (intptr_t)Universe::non_oop_word());
2292 call(AddressLiteral(entry, rh));
2293 }
2294
2295 // Implementation of call_VM versions
2296
2297 void MacroAssembler::call_VM(Register oop_result,
2298 address entry_point,
2299 bool check_exceptions) {
2300 Label C, E;
2301 call(C, relocInfo::none);
2302 jmp(E);
2303
2304 bind(C);
2305 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2306 ret(0);
2307
2308 bind(E);
2309 }
2310
2311 void MacroAssembler::call_VM(Register oop_result,
2312 address entry_point,
2313 Register arg_1,
2314 bool check_exceptions) {
2315 Label C, E;
2316 call(C, relocInfo::none);
2317 jmp(E);
2318
2319 bind(C);
2320 pass_arg1(this, arg_1);
2321 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2322 ret(0);
2323
2324 bind(E);
2325 }
2326
2327 void MacroAssembler::call_VM(Register oop_result,
2328 address entry_point,
2329 Register arg_1,
2330 Register arg_2,
2331 bool check_exceptions) {
2332 Label C, E;
2333 call(C, relocInfo::none);
2334 jmp(E);
2335
2336 bind(C);
2337
2338 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2339
2340 pass_arg2(this, arg_2);
2341 pass_arg1(this, arg_1);
2342 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2343 ret(0);
2344
2345 bind(E);
2346 }
2347
2348 void MacroAssembler::call_VM(Register oop_result,
2349 address entry_point,
2350 Register arg_1,
2351 Register arg_2,
2352 Register arg_3,
2353 bool check_exceptions) {
2354 Label C, E;
2355 call(C, relocInfo::none);
2356 jmp(E);
2357
2358 bind(C);
2359
2360 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2361 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2362 pass_arg3(this, arg_3);
2363
2364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2365 pass_arg2(this, arg_2);
2366
2367 pass_arg1(this, arg_1);
2368 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2369 ret(0);
2370
2371 bind(E);
2372 }
2373
2374 void MacroAssembler::call_VM(Register oop_result,
2375 Register last_java_sp,
2376 address entry_point,
2377 int number_of_arguments,
2378 bool check_exceptions) {
2379 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2380 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2381 }
2382
2383 void MacroAssembler::call_VM(Register oop_result,
2384 Register last_java_sp,
2385 address entry_point,
2386 Register arg_1,
2387 bool check_exceptions) {
2388 pass_arg1(this, arg_1);
2389 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2390 }
2391
2392 void MacroAssembler::call_VM(Register oop_result,
2393 Register last_java_sp,
2394 address entry_point,
2395 Register arg_1,
2396 Register arg_2,
2397 bool check_exceptions) {
2398
2399 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2400 pass_arg2(this, arg_2);
2401 pass_arg1(this, arg_1);
2402 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2403 }
2404
2405 void MacroAssembler::call_VM(Register oop_result,
2406 Register last_java_sp,
2407 address entry_point,
2408 Register arg_1,
2409 Register arg_2,
2410 Register arg_3,
2411 bool check_exceptions) {
2412 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2413 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2414 pass_arg3(this, arg_3);
2415 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2416 pass_arg2(this, arg_2);
2417 pass_arg1(this, arg_1);
2418 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2419 }
2420
2421 void MacroAssembler::super_call_VM(Register oop_result,
2422 Register last_java_sp,
2423 address entry_point,
2424 int number_of_arguments,
2425 bool check_exceptions) {
2426 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2427 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2428 }
2429
2430 void MacroAssembler::super_call_VM(Register oop_result,
2431 Register last_java_sp,
2432 address entry_point,
2433 Register arg_1,
2434 bool check_exceptions) {
2435 pass_arg1(this, arg_1);
2436 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2437 }
2438
2439 void MacroAssembler::super_call_VM(Register oop_result,
2440 Register last_java_sp,
2441 address entry_point,
2442 Register arg_1,
2443 Register arg_2,
2444 bool check_exceptions) {
2445
2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2447 pass_arg2(this, arg_2);
2448 pass_arg1(this, arg_1);
2449 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2450 }
2451
2452 void MacroAssembler::super_call_VM(Register oop_result,
2453 Register last_java_sp,
2454 address entry_point,
2455 Register arg_1,
2456 Register arg_2,
2457 Register arg_3,
2458 bool check_exceptions) {
2459 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2460 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2461 pass_arg3(this, arg_3);
2462 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2463 pass_arg2(this, arg_2);
2464 pass_arg1(this, arg_1);
2465 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2466 }
2467
2468 void MacroAssembler::call_VM_base(Register oop_result,
2469 Register java_thread,
2470 Register last_java_sp,
2471 address entry_point,
2472 int number_of_arguments,
2473 bool check_exceptions) {
2474 // determine java_thread register
2475 if (!java_thread->is_valid()) {
2476 #ifdef _LP64
2477 java_thread = r15_thread;
2478 #else
2479 java_thread = rdi;
2480 get_thread(java_thread);
2481 #endif // LP64
2482 }
2483 // determine last_java_sp register
2484 if (!last_java_sp->is_valid()) {
2485 last_java_sp = rsp;
2486 }
2487 // debugging support
2488 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2489 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2490 #ifdef ASSERT
2491 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2492 // r12 is the heapbase.
2493 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2494 #endif // ASSERT
2495
2496 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2497 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2498
2499 // push java thread (becomes first argument of C function)
2500
2501 NOT_LP64(push(java_thread); number_of_arguments++);
2502 LP64_ONLY(mov(c_rarg0, r15_thread));
2503
2504 // set last Java frame before call
2505 assert(last_java_sp != rbp, "can't use ebp/rbp");
2506
2507 // Only interpreter should have to set fp
2508 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2509
2510 // do the call, remove parameters
2511 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2512
2513 // restore the thread (cannot use the pushed argument since arguments
2514 // may be overwritten by C code generated by an optimizing compiler);
2515 // however can use the register value directly if it is callee saved.
2516 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2517 // rdi & rsi (also r15) are callee saved -> nothing to do
2518 #ifdef ASSERT
2519 guarantee(java_thread != rax, "change this code");
2520 push(rax);
2521 { Label L;
2522 get_thread(rax);
2523 cmpptr(java_thread, rax);
2524 jcc(Assembler::equal, L);
2525 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2526 bind(L);
2527 }
2528 pop(rax);
2529 #endif
2530 } else {
2531 get_thread(java_thread);
2532 }
2533 // reset last Java frame
2534 // Only interpreter should have to clear fp
2535 reset_last_Java_frame(java_thread, true);
2536
2537 // C++ interp handles this in the interpreter
2538 check_and_handle_popframe(java_thread);
2539 check_and_handle_earlyret(java_thread);
2540
2541 if (check_exceptions) {
2542 // check for pending exceptions (java_thread is set upon return)
2543 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2544 #ifndef _LP64
2545 jump_cc(Assembler::notEqual,
2546 RuntimeAddress(StubRoutines::forward_exception_entry()));
2547 #else
2548 // This used to conditionally jump to forward_exception however it is
2549 // possible if we relocate that the branch will not reach. So we must jump
2550 // around so we can always reach
2551
2552 Label ok;
2553 jcc(Assembler::equal, ok);
2554 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2555 bind(ok);
2556 #endif // LP64
2557 }
2558
2559 // get oop result if there is one and reset the value in the thread
2560 if (oop_result->is_valid()) {
2561 get_vm_result(oop_result, java_thread);
2562 }
2563 }
2564
2565 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2566
2567 // Calculate the value for last_Java_sp
2568 // somewhat subtle. call_VM does an intermediate call
2569 // which places a return address on the stack just under the
2570 // stack pointer as the user finsihed with it. This allows
2571 // use to retrieve last_Java_pc from last_Java_sp[-1].
2572 // On 32bit we then have to push additional args on the stack to accomplish
2573 // the actual requested call. On 64bit call_VM only can use register args
2574 // so the only extra space is the return address that call_VM created.
2575 // This hopefully explains the calculations here.
2576
2577 #ifdef _LP64
2578 // We've pushed one address, correct last_Java_sp
2579 lea(rax, Address(rsp, wordSize));
2580 #else
2581 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2582 #endif // LP64
2583
2584 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2585
2586 }
2587
2588 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2589 void MacroAssembler::call_VM_leaf0(address entry_point) {
2590 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2591 }
2592
2593 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2594 call_VM_leaf_base(entry_point, number_of_arguments);
2595 }
2596
2597 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2598 pass_arg0(this, arg_0);
2599 call_VM_leaf(entry_point, 1);
2600 }
2601
2602 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2603
2604 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2605 pass_arg1(this, arg_1);
2606 pass_arg0(this, arg_0);
2607 call_VM_leaf(entry_point, 2);
2608 }
2609
2610 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2611 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2612 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2613 pass_arg2(this, arg_2);
2614 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2615 pass_arg1(this, arg_1);
2616 pass_arg0(this, arg_0);
2617 call_VM_leaf(entry_point, 3);
2618 }
2619
2620 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2621 pass_arg0(this, arg_0);
2622 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2623 }
2624
2625 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2626
2627 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2628 pass_arg1(this, arg_1);
2629 pass_arg0(this, arg_0);
2630 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2631 }
2632
2633 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2634 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2635 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2636 pass_arg2(this, arg_2);
2637 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2638 pass_arg1(this, arg_1);
2639 pass_arg0(this, arg_0);
2640 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2641 }
2642
2643 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2644 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2645 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2646 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2647 pass_arg3(this, arg_3);
2648 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2649 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2650 pass_arg2(this, arg_2);
2651 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2652 pass_arg1(this, arg_1);
2653 pass_arg0(this, arg_0);
2654 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2655 }
2656
2657 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2658 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2659 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2660 verify_oop(oop_result, "broken oop in call_VM_base");
2661 }
2662
2663 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2664 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2665 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2666 }
2667
2668 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2669 }
2670
2671 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2672 }
2673
2674 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2675 if (reachable(src1)) {
2676 cmpl(as_Address(src1), imm);
2677 } else {
2678 lea(rscratch1, src1);
2679 cmpl(Address(rscratch1, 0), imm);
2680 }
2681 }
2682
2683 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2684 assert(!src2.is_lval(), "use cmpptr");
2685 if (reachable(src2)) {
2686 cmpl(src1, as_Address(src2));
2687 } else {
2688 lea(rscratch1, src2);
2689 cmpl(src1, Address(rscratch1, 0));
2690 }
2691 }
2692
2693 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2694 Assembler::cmpl(src1, imm);
2695 }
2696
2697 void MacroAssembler::cmp32(Register src1, Address src2) {
2698 Assembler::cmpl(src1, src2);
2699 }
2700
2701 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2702 ucomisd(opr1, opr2);
2703
2704 Label L;
2705 if (unordered_is_less) {
2706 movl(dst, -1);
2707 jcc(Assembler::parity, L);
2708 jcc(Assembler::below , L);
2709 movl(dst, 0);
2710 jcc(Assembler::equal , L);
2711 increment(dst);
2712 } else { // unordered is greater
2713 movl(dst, 1);
2714 jcc(Assembler::parity, L);
2715 jcc(Assembler::above , L);
2716 movl(dst, 0);
2717 jcc(Assembler::equal , L);
2718 decrementl(dst);
2719 }
2720 bind(L);
2721 }
2722
2723 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2724 ucomiss(opr1, opr2);
2725
2726 Label L;
2727 if (unordered_is_less) {
2728 movl(dst, -1);
2729 jcc(Assembler::parity, L);
2730 jcc(Assembler::below , L);
2731 movl(dst, 0);
2732 jcc(Assembler::equal , L);
2733 increment(dst);
2734 } else { // unordered is greater
2735 movl(dst, 1);
2736 jcc(Assembler::parity, L);
2737 jcc(Assembler::above , L);
2738 movl(dst, 0);
2739 jcc(Assembler::equal , L);
2740 decrementl(dst);
2741 }
2742 bind(L);
2743 }
2744
2745
2746 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2747 if (reachable(src1)) {
2748 cmpb(as_Address(src1), imm);
2749 } else {
2750 lea(rscratch1, src1);
2751 cmpb(Address(rscratch1, 0), imm);
2752 }
2753 }
2754
2755 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2756 #ifdef _LP64
2757 if (src2.is_lval()) {
2758 movptr(rscratch1, src2);
2759 Assembler::cmpq(src1, rscratch1);
2760 } else if (reachable(src2)) {
2761 cmpq(src1, as_Address(src2));
2762 } else {
2763 lea(rscratch1, src2);
2764 Assembler::cmpq(src1, Address(rscratch1, 0));
2765 }
2766 #else
2767 if (src2.is_lval()) {
2768 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2769 } else {
2770 cmpl(src1, as_Address(src2));
2771 }
2772 #endif // _LP64
2773 }
2774
2775 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2776 assert(src2.is_lval(), "not a mem-mem compare");
2777 #ifdef _LP64
2778 // moves src2's literal address
2779 movptr(rscratch1, src2);
2780 Assembler::cmpq(src1, rscratch1);
2781 #else
2782 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2783 #endif // _LP64
2784 }
2785
2786 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2787 if (reachable(adr)) {
2788 if (os::is_MP())
2789 lock();
2790 cmpxchgptr(reg, as_Address(adr));
2791 } else {
2792 lea(rscratch1, adr);
2793 if (os::is_MP())
2794 lock();
2795 cmpxchgptr(reg, Address(rscratch1, 0));
2796 }
2797 }
2798
2799 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2800 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2801 }
2802
2803 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2804 if (reachable(src)) {
2805 Assembler::comisd(dst, as_Address(src));
2806 } else {
2807 lea(rscratch1, src);
2808 Assembler::comisd(dst, Address(rscratch1, 0));
2809 }
2810 }
2811
2812 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2813 if (reachable(src)) {
2814 Assembler::comiss(dst, as_Address(src));
2815 } else {
2816 lea(rscratch1, src);
2817 Assembler::comiss(dst, Address(rscratch1, 0));
2818 }
2819 }
2820
2821
2822 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2823 Condition negated_cond = negate_condition(cond);
2824 Label L;
2825 jcc(negated_cond, L);
2826 pushf(); // Preserve flags
2827 atomic_incl(counter_addr);
2828 popf();
2829 bind(L);
2830 }
2831
2832 int MacroAssembler::corrected_idivl(Register reg) {
2833 // Full implementation of Java idiv and irem; checks for
2834 // special case as described in JVM spec., p.243 & p.271.
2835 // The function returns the (pc) offset of the idivl
2836 // instruction - may be needed for implicit exceptions.
2837 //
2838 // normal case special case
2839 //
2840 // input : rax,: dividend min_int
2841 // reg: divisor (may not be rax,/rdx) -1
2842 //
2843 // output: rax,: quotient (= rax, idiv reg) min_int
2844 // rdx: remainder (= rax, irem reg) 0
2845 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2846 const int min_int = 0x80000000;
2847 Label normal_case, special_case;
2848
2849 // check for special case
2850 cmpl(rax, min_int);
2851 jcc(Assembler::notEqual, normal_case);
2852 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2853 cmpl(reg, -1);
2854 jcc(Assembler::equal, special_case);
2855
2856 // handle normal case
2857 bind(normal_case);
2858 cdql();
2859 int idivl_offset = offset();
2860 idivl(reg);
2861
2862 // normal and special case exit
2863 bind(special_case);
2864
2865 return idivl_offset;
2866 }
2867
2868
2869
2870 void MacroAssembler::decrementl(Register reg, int value) {
2871 if (value == min_jint) {subl(reg, value) ; return; }
2872 if (value < 0) { incrementl(reg, -value); return; }
2873 if (value == 0) { ; return; }
2874 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2875 /* else */ { subl(reg, value) ; return; }
2876 }
2877
2878 void MacroAssembler::decrementl(Address dst, int value) {
2879 if (value == min_jint) {subl(dst, value) ; return; }
2880 if (value < 0) { incrementl(dst, -value); return; }
2881 if (value == 0) { ; return; }
2882 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2883 /* else */ { subl(dst, value) ; return; }
2884 }
2885
2886 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2887 assert (shift_value > 0, "illegal shift value");
2888 Label _is_positive;
2889 testl (reg, reg);
2890 jcc (Assembler::positive, _is_positive);
2891 int offset = (1 << shift_value) - 1 ;
2892
2893 if (offset == 1) {
2894 incrementl(reg);
2895 } else {
2896 addl(reg, offset);
2897 }
2898
2899 bind (_is_positive);
2900 sarl(reg, shift_value);
2901 }
2902
2903 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2904 if (reachable(src)) {
2905 Assembler::divsd(dst, as_Address(src));
2906 } else {
2907 lea(rscratch1, src);
2908 Assembler::divsd(dst, Address(rscratch1, 0));
2909 }
2910 }
2911
2912 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2913 if (reachable(src)) {
2914 Assembler::divss(dst, as_Address(src));
2915 } else {
2916 lea(rscratch1, src);
2917 Assembler::divss(dst, Address(rscratch1, 0));
2918 }
2919 }
2920
2921 // !defined(COMPILER2) is because of stupid core builds
2922 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2923 void MacroAssembler::empty_FPU_stack() {
2924 if (VM_Version::supports_mmx()) {
2925 emms();
2926 } else {
2927 for (int i = 8; i-- > 0; ) ffree(i);
2928 }
2929 }
2930 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2931
2932
2933 // Defines obj, preserves var_size_in_bytes
2934 void MacroAssembler::eden_allocate(Register obj,
2935 Register var_size_in_bytes,
2936 int con_size_in_bytes,
2937 Register t1,
2938 Label& slow_case) {
2939 assert(obj == rax, "obj must be in rax, for cmpxchg");
2940 assert_different_registers(obj, var_size_in_bytes, t1);
2941 if (!Universe::heap()->supports_inline_contig_alloc()) {
2942 jmp(slow_case);
2943 } else {
2944 Register end = t1;
2945 Label retry;
2946 bind(retry);
2947 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2948 movptr(obj, heap_top);
2949 if (var_size_in_bytes == noreg) {
2950 lea(end, Address(obj, con_size_in_bytes));
2951 } else {
2952 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2953 }
2954 // if end < obj then we wrapped around => object too long => slow case
2955 cmpptr(end, obj);
2956 jcc(Assembler::below, slow_case);
2957 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2958 jcc(Assembler::above, slow_case);
2959 // Compare obj with the top addr, and if still equal, store the new top addr in
2960 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2961 // it otherwise. Use lock prefix for atomicity on MPs.
2962 locked_cmpxchgptr(end, heap_top);
2963 jcc(Assembler::notEqual, retry);
2964 }
2965 }
2966
2967 void MacroAssembler::enter() {
2968 push(rbp);
2969 mov(rbp, rsp);
2970 }
2971
2972 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2973 void MacroAssembler::fat_nop() {
2974 if (UseAddressNop) {
2975 addr_nop_5();
2976 } else {
2977 emit_int8(0x26); // es:
2978 emit_int8(0x2e); // cs:
2979 emit_int8(0x64); // fs:
2980 emit_int8(0x65); // gs:
2981 emit_int8((unsigned char)0x90);
2982 }
2983 }
2984
2985 void MacroAssembler::fcmp(Register tmp) {
2986 fcmp(tmp, 1, true, true);
2987 }
2988
2989 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2990 assert(!pop_right || pop_left, "usage error");
2991 if (VM_Version::supports_cmov()) {
2992 assert(tmp == noreg, "unneeded temp");
2993 if (pop_left) {
2994 fucomip(index);
2995 } else {
2996 fucomi(index);
2997 }
2998 if (pop_right) {
2999 fpop();
3000 }
3001 } else {
3002 assert(tmp != noreg, "need temp");
3003 if (pop_left) {
3004 if (pop_right) {
3005 fcompp();
3006 } else {
3007 fcomp(index);
3008 }
3009 } else {
3010 fcom(index);
3011 }
3012 // convert FPU condition into eflags condition via rax,
3013 save_rax(tmp);
3014 fwait(); fnstsw_ax();
3015 sahf();
3016 restore_rax(tmp);
3017 }
3018 // condition codes set as follows:
3019 //
3020 // CF (corresponds to C0) if x < y
3021 // PF (corresponds to C2) if unordered
3022 // ZF (corresponds to C3) if x = y
3023 }
3024
3025 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3026 fcmp2int(dst, unordered_is_less, 1, true, true);
3027 }
3028
3029 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3030 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3031 Label L;
3032 if (unordered_is_less) {
3033 movl(dst, -1);
3034 jcc(Assembler::parity, L);
3035 jcc(Assembler::below , L);
3036 movl(dst, 0);
3037 jcc(Assembler::equal , L);
3038 increment(dst);
3039 } else { // unordered is greater
3040 movl(dst, 1);
3041 jcc(Assembler::parity, L);
3042 jcc(Assembler::above , L);
3043 movl(dst, 0);
3044 jcc(Assembler::equal , L);
3045 decrementl(dst);
3046 }
3047 bind(L);
3048 }
3049
3050 void MacroAssembler::fld_d(AddressLiteral src) {
3051 fld_d(as_Address(src));
3052 }
3053
3054 void MacroAssembler::fld_s(AddressLiteral src) {
3055 fld_s(as_Address(src));
3056 }
3057
3058 void MacroAssembler::fld_x(AddressLiteral src) {
3059 Assembler::fld_x(as_Address(src));
3060 }
3061
3062 void MacroAssembler::fldcw(AddressLiteral src) {
3063 Assembler::fldcw(as_Address(src));
3064 }
3065
3066 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3067 if (reachable(src)) {
3068 Assembler::mulpd(dst, as_Address(src));
3069 } else {
3070 lea(rscratch1, src);
3071 Assembler::mulpd(dst, Address(rscratch1, 0));
3072 }
3073 }
3074
3075 void MacroAssembler::increase_precision() {
3076 subptr(rsp, BytesPerWord);
3077 fnstcw(Address(rsp, 0));
3078 movl(rax, Address(rsp, 0));
3079 orl(rax, 0x300);
3080 push(rax);
3081 fldcw(Address(rsp, 0));
3082 pop(rax);
3083 }
3084
3085 void MacroAssembler::restore_precision() {
3086 fldcw(Address(rsp, 0));
3087 addptr(rsp, BytesPerWord);
3088 }
3089
3090 void MacroAssembler::fpop() {
3091 ffree();
3092 fincstp();
3093 }
3094
3095 void MacroAssembler::load_float(Address src) {
3096 if (UseSSE >= 1) {
3097 movflt(xmm0, src);
3098 } else {
3099 LP64_ONLY(ShouldNotReachHere());
3100 NOT_LP64(fld_s(src));
3101 }
3102 }
3103
3104 void MacroAssembler::store_float(Address dst) {
3105 if (UseSSE >= 1) {
3106 movflt(dst, xmm0);
3107 } else {
3108 LP64_ONLY(ShouldNotReachHere());
3109 NOT_LP64(fstp_s(dst));
3110 }
3111 }
3112
3113 void MacroAssembler::load_double(Address src) {
3114 if (UseSSE >= 2) {
3115 movdbl(xmm0, src);
3116 } else {
3117 LP64_ONLY(ShouldNotReachHere());
3118 NOT_LP64(fld_d(src));
3119 }
3120 }
3121
3122 void MacroAssembler::store_double(Address dst) {
3123 if (UseSSE >= 2) {
3124 movdbl(dst, xmm0);
3125 } else {
3126 LP64_ONLY(ShouldNotReachHere());
3127 NOT_LP64(fstp_d(dst));
3128 }
3129 }
3130
3131 void MacroAssembler::fremr(Register tmp) {
3132 save_rax(tmp);
3133 { Label L;
3134 bind(L);
3135 fprem();
3136 fwait(); fnstsw_ax();
3137 #ifdef _LP64
3138 testl(rax, 0x400);
3139 jcc(Assembler::notEqual, L);
3140 #else
3141 sahf();
3142 jcc(Assembler::parity, L);
3143 #endif // _LP64
3144 }
3145 restore_rax(tmp);
3146 // Result is in ST0.
3147 // Note: fxch & fpop to get rid of ST1
3148 // (otherwise FPU stack could overflow eventually)
3149 fxch(1);
3150 fpop();
3151 }
3152
3153 // dst = c = a * b + c
3154 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3155 Assembler::vfmadd231sd(c, a, b);
3156 if (dst != c) {
3157 movdbl(dst, c);
3158 }
3159 }
3160
3161 // dst = c = a * b + c
3162 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3163 Assembler::vfmadd231ss(c, a, b);
3164 if (dst != c) {
3165 movflt(dst, c);
3166 }
3167 }
3168
3169 // dst = c = a * b + c
3170 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3171 Assembler::vfmadd231pd(c, a, b, vector_len);
3172 if (dst != c) {
3173 vmovdqu(dst, c);
3174 }
3175 }
3176
3177 // dst = c = a * b + c
3178 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3179 Assembler::vfmadd231ps(c, a, b, vector_len);
3180 if (dst != c) {
3181 vmovdqu(dst, c);
3182 }
3183 }
3184
3185 // dst = c = a * b + c
3186 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3187 Assembler::vfmadd231pd(c, a, b, vector_len);
3188 if (dst != c) {
3189 vmovdqu(dst, c);
3190 }
3191 }
3192
3193 // dst = c = a * b + c
3194 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3195 Assembler::vfmadd231ps(c, a, b, vector_len);
3196 if (dst != c) {
3197 vmovdqu(dst, c);
3198 }
3199 }
3200
3201 void MacroAssembler::incrementl(AddressLiteral dst) {
3202 if (reachable(dst)) {
3203 incrementl(as_Address(dst));
3204 } else {
3205 lea(rscratch1, dst);
3206 incrementl(Address(rscratch1, 0));
3207 }
3208 }
3209
3210 void MacroAssembler::incrementl(ArrayAddress dst) {
3211 incrementl(as_Address(dst));
3212 }
3213
3214 void MacroAssembler::incrementl(Register reg, int value) {
3215 if (value == min_jint) {addl(reg, value) ; return; }
3216 if (value < 0) { decrementl(reg, -value); return; }
3217 if (value == 0) { ; return; }
3218 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3219 /* else */ { addl(reg, value) ; return; }
3220 }
3221
3222 void MacroAssembler::incrementl(Address dst, int value) {
3223 if (value == min_jint) {addl(dst, value) ; return; }
3224 if (value < 0) { decrementl(dst, -value); return; }
3225 if (value == 0) { ; return; }
3226 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3227 /* else */ { addl(dst, value) ; return; }
3228 }
3229
3230 void MacroAssembler::jump(AddressLiteral dst) {
3231 if (reachable(dst)) {
3232 jmp_literal(dst.target(), dst.rspec());
3233 } else {
3234 lea(rscratch1, dst);
3235 jmp(rscratch1);
3236 }
3237 }
3238
3239 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3240 if (reachable(dst)) {
3241 InstructionMark im(this);
3242 relocate(dst.reloc());
3243 const int short_size = 2;
3244 const int long_size = 6;
3245 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3246 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3247 // 0111 tttn #8-bit disp
3248 emit_int8(0x70 | cc);
3249 emit_int8((offs - short_size) & 0xFF);
3250 } else {
3251 // 0000 1111 1000 tttn #32-bit disp
3252 emit_int8(0x0F);
3253 emit_int8((unsigned char)(0x80 | cc));
3254 emit_int32(offs - long_size);
3255 }
3256 } else {
3257 #ifdef ASSERT
3258 warning("reversing conditional branch");
3259 #endif /* ASSERT */
3260 Label skip;
3261 jccb(reverse[cc], skip);
3262 lea(rscratch1, dst);
3263 Assembler::jmp(rscratch1);
3264 bind(skip);
3265 }
3266 }
3267
3268 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3269 if (reachable(src)) {
3270 Assembler::ldmxcsr(as_Address(src));
3271 } else {
3272 lea(rscratch1, src);
3273 Assembler::ldmxcsr(Address(rscratch1, 0));
3274 }
3275 }
3276
3277 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3278 int off;
3279 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3280 off = offset();
3281 movsbl(dst, src); // movsxb
3282 } else {
3283 off = load_unsigned_byte(dst, src);
3284 shll(dst, 24);
3285 sarl(dst, 24);
3286 }
3287 return off;
3288 }
3289
3290 // Note: load_signed_short used to be called load_signed_word.
3291 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3292 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3293 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3294 int MacroAssembler::load_signed_short(Register dst, Address src) {
3295 int off;
3296 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3297 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3298 // version but this is what 64bit has always done. This seems to imply
3299 // that users are only using 32bits worth.
3300 off = offset();
3301 movswl(dst, src); // movsxw
3302 } else {
3303 off = load_unsigned_short(dst, src);
3304 shll(dst, 16);
3305 sarl(dst, 16);
3306 }
3307 return off;
3308 }
3309
3310 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3311 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3312 // and "3.9 Partial Register Penalties", p. 22).
3313 int off;
3314 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3315 off = offset();
3316 movzbl(dst, src); // movzxb
3317 } else {
3318 xorl(dst, dst);
3319 off = offset();
3320 movb(dst, src);
3321 }
3322 return off;
3323 }
3324
3325 // Note: load_unsigned_short used to be called load_unsigned_word.
3326 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3327 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3328 // and "3.9 Partial Register Penalties", p. 22).
3329 int off;
3330 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3331 off = offset();
3332 movzwl(dst, src); // movzxw
3333 } else {
3334 xorl(dst, dst);
3335 off = offset();
3336 movw(dst, src);
3337 }
3338 return off;
3339 }
3340
3341 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3342 switch (size_in_bytes) {
3343 #ifndef _LP64
3344 case 8:
3345 assert(dst2 != noreg, "second dest register required");
3346 movl(dst, src);
3347 movl(dst2, src.plus_disp(BytesPerInt));
3348 break;
3349 #else
3350 case 8: movq(dst, src); break;
3351 #endif
3352 case 4: movl(dst, src); break;
3353 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3354 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3355 default: ShouldNotReachHere();
3356 }
3357 }
3358
3359 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3360 switch (size_in_bytes) {
3361 #ifndef _LP64
3362 case 8:
3363 assert(src2 != noreg, "second source register required");
3364 movl(dst, src);
3365 movl(dst.plus_disp(BytesPerInt), src2);
3366 break;
3367 #else
3368 case 8: movq(dst, src); break;
3369 #endif
3370 case 4: movl(dst, src); break;
3371 case 2: movw(dst, src); break;
3372 case 1: movb(dst, src); break;
3373 default: ShouldNotReachHere();
3374 }
3375 }
3376
3377 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3378 if (reachable(dst)) {
3379 movl(as_Address(dst), src);
3380 } else {
3381 lea(rscratch1, dst);
3382 movl(Address(rscratch1, 0), src);
3383 }
3384 }
3385
3386 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3387 if (reachable(src)) {
3388 movl(dst, as_Address(src));
3389 } else {
3390 lea(rscratch1, src);
3391 movl(dst, Address(rscratch1, 0));
3392 }
3393 }
3394
3395 // C++ bool manipulation
3396
3397 void MacroAssembler::movbool(Register dst, Address src) {
3398 if(sizeof(bool) == 1)
3399 movb(dst, src);
3400 else if(sizeof(bool) == 2)
3401 movw(dst, src);
3402 else if(sizeof(bool) == 4)
3403 movl(dst, src);
3404 else
3405 // unsupported
3406 ShouldNotReachHere();
3407 }
3408
3409 void MacroAssembler::movbool(Address dst, bool boolconst) {
3410 if(sizeof(bool) == 1)
3411 movb(dst, (int) boolconst);
3412 else if(sizeof(bool) == 2)
3413 movw(dst, (int) boolconst);
3414 else if(sizeof(bool) == 4)
3415 movl(dst, (int) boolconst);
3416 else
3417 // unsupported
3418 ShouldNotReachHere();
3419 }
3420
3421 void MacroAssembler::movbool(Address dst, Register src) {
3422 if(sizeof(bool) == 1)
3423 movb(dst, src);
3424 else if(sizeof(bool) == 2)
3425 movw(dst, src);
3426 else if(sizeof(bool) == 4)
3427 movl(dst, src);
3428 else
3429 // unsupported
3430 ShouldNotReachHere();
3431 }
3432
3433 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3434 movb(as_Address(dst), src);
3435 }
3436
3437 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3438 if (reachable(src)) {
3439 movdl(dst, as_Address(src));
3440 } else {
3441 lea(rscratch1, src);
3442 movdl(dst, Address(rscratch1, 0));
3443 }
3444 }
3445
3446 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3447 if (reachable(src)) {
3448 movq(dst, as_Address(src));
3449 } else {
3450 lea(rscratch1, src);
3451 movq(dst, Address(rscratch1, 0));
3452 }
3453 }
3454
3455 void MacroAssembler::setvectmask(Register dst, Register src) {
3456 Assembler::movl(dst, 1);
3457 Assembler::shlxl(dst, dst, src);
3458 Assembler::decl(dst);
3459 Assembler::kmovdl(k1, dst);
3460 Assembler::movl(dst, src);
3461 }
3462
3463 void MacroAssembler::restorevectmask() {
3464 Assembler::knotwl(k1, k0);
3465 }
3466
3467 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3468 if (reachable(src)) {
3469 if (UseXmmLoadAndClearUpper) {
3470 movsd (dst, as_Address(src));
3471 } else {
3472 movlpd(dst, as_Address(src));
3473 }
3474 } else {
3475 lea(rscratch1, src);
3476 if (UseXmmLoadAndClearUpper) {
3477 movsd (dst, Address(rscratch1, 0));
3478 } else {
3479 movlpd(dst, Address(rscratch1, 0));
3480 }
3481 }
3482 }
3483
3484 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3485 if (reachable(src)) {
3486 movss(dst, as_Address(src));
3487 } else {
3488 lea(rscratch1, src);
3489 movss(dst, Address(rscratch1, 0));
3490 }
3491 }
3492
3493 void MacroAssembler::movptr(Register dst, Register src) {
3494 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3495 }
3496
3497 void MacroAssembler::movptr(Register dst, Address src) {
3498 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3499 }
3500
3501 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3502 void MacroAssembler::movptr(Register dst, intptr_t src) {
3503 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3504 }
3505
3506 void MacroAssembler::movptr(Address dst, Register src) {
3507 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3508 }
3509
3510 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3511 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3512 Assembler::vextractf32x4(dst, src, 0);
3513 } else {
3514 Assembler::movdqu(dst, src);
3515 }
3516 }
3517
3518 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3519 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3520 Assembler::vinsertf32x4(dst, dst, src, 0);
3521 } else {
3522 Assembler::movdqu(dst, src);
3523 }
3524 }
3525
3526 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3527 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3528 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3529 } else {
3530 Assembler::movdqu(dst, src);
3531 }
3532 }
3533
3534 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3535 if (reachable(src)) {
3536 movdqu(dst, as_Address(src));
3537 } else {
3538 lea(scratchReg, src);
3539 movdqu(dst, Address(scratchReg, 0));
3540 }
3541 }
3542
3543 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3544 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3545 vextractf64x4_low(dst, src);
3546 } else {
3547 Assembler::vmovdqu(dst, src);
3548 }
3549 }
3550
3551 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3552 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3553 vinsertf64x4_low(dst, src);
3554 } else {
3555 Assembler::vmovdqu(dst, src);
3556 }
3557 }
3558
3559 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3560 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3561 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3562 }
3563 else {
3564 Assembler::vmovdqu(dst, src);
3565 }
3566 }
3567
3568 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3569 if (reachable(src)) {
3570 vmovdqu(dst, as_Address(src));
3571 }
3572 else {
3573 lea(rscratch1, src);
3574 vmovdqu(dst, Address(rscratch1, 0));
3575 }
3576 }
3577
3578 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3579 if (reachable(src)) {
3580 Assembler::movdqa(dst, as_Address(src));
3581 } else {
3582 lea(rscratch1, src);
3583 Assembler::movdqa(dst, Address(rscratch1, 0));
3584 }
3585 }
3586
3587 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3588 if (reachable(src)) {
3589 Assembler::movsd(dst, as_Address(src));
3590 } else {
3591 lea(rscratch1, src);
3592 Assembler::movsd(dst, Address(rscratch1, 0));
3593 }
3594 }
3595
3596 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3597 if (reachable(src)) {
3598 Assembler::movss(dst, as_Address(src));
3599 } else {
3600 lea(rscratch1, src);
3601 Assembler::movss(dst, Address(rscratch1, 0));
3602 }
3603 }
3604
3605 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3606 if (reachable(src)) {
3607 Assembler::mulsd(dst, as_Address(src));
3608 } else {
3609 lea(rscratch1, src);
3610 Assembler::mulsd(dst, Address(rscratch1, 0));
3611 }
3612 }
3613
3614 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3615 if (reachable(src)) {
3616 Assembler::mulss(dst, as_Address(src));
3617 } else {
3618 lea(rscratch1, src);
3619 Assembler::mulss(dst, Address(rscratch1, 0));
3620 }
3621 }
3622
3623 void MacroAssembler::null_check(Register reg, int offset) {
3624 if (needs_explicit_null_check(offset)) {
3625 // provoke OS NULL exception if reg = NULL by
3626 // accessing M[reg] w/o changing any (non-CC) registers
3627 // NOTE: cmpl is plenty here to provoke a segv
3628 cmpptr(rax, Address(reg, 0));
3629 // Note: should probably use testl(rax, Address(reg, 0));
3630 // may be shorter code (however, this version of
3631 // testl needs to be implemented first)
3632 } else {
3633 // nothing to do, (later) access of M[reg + offset]
3634 // will provoke OS NULL exception if reg = NULL
3635 }
3636 }
3637
3638 void MacroAssembler::os_breakpoint() {
3639 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3640 // (e.g., MSVC can't call ps() otherwise)
3641 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3642 }
3643
3644 void MacroAssembler::unimplemented(const char* what) {
3645 char* b = new char[1024];
3646 jio_snprintf(b, 1024, "unimplemented: %s", what);
3647 stop(b);
3648 }
3649
3650 #ifdef _LP64
3651 #define XSTATE_BV 0x200
3652 #endif
3653
3654 void MacroAssembler::pop_CPU_state() {
3655 pop_FPU_state();
3656 pop_IU_state();
3657 }
3658
3659 void MacroAssembler::pop_FPU_state() {
3660 #ifndef _LP64
3661 frstor(Address(rsp, 0));
3662 #else
3663 fxrstor(Address(rsp, 0));
3664 #endif
3665 addptr(rsp, FPUStateSizeInWords * wordSize);
3666 }
3667
3668 void MacroAssembler::pop_IU_state() {
3669 popa();
3670 LP64_ONLY(addq(rsp, 8));
3671 popf();
3672 }
3673
3674 // Save Integer and Float state
3675 // Warning: Stack must be 16 byte aligned (64bit)
3676 void MacroAssembler::push_CPU_state() {
3677 push_IU_state();
3678 push_FPU_state();
3679 }
3680
3681 void MacroAssembler::push_FPU_state() {
3682 subptr(rsp, FPUStateSizeInWords * wordSize);
3683 #ifndef _LP64
3684 fnsave(Address(rsp, 0));
3685 fwait();
3686 #else
3687 fxsave(Address(rsp, 0));
3688 #endif // LP64
3689 }
3690
3691 void MacroAssembler::push_IU_state() {
3692 // Push flags first because pusha kills them
3693 pushf();
3694 // Make sure rsp stays 16-byte aligned
3695 LP64_ONLY(subq(rsp, 8));
3696 pusha();
3697 }
3698
3699 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3700 if (!java_thread->is_valid()) {
3701 java_thread = rdi;
3702 get_thread(java_thread);
3703 }
3704 // we must set sp to zero to clear frame
3705 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3706 if (clear_fp) {
3707 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3708 }
3709
3710 // Always clear the pc because it could have been set by make_walkable()
3711 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3712
3713 vzeroupper();
3714 }
3715
3716 void MacroAssembler::restore_rax(Register tmp) {
3717 if (tmp == noreg) pop(rax);
3718 else if (tmp != rax) mov(rax, tmp);
3719 }
3720
3721 void MacroAssembler::round_to(Register reg, int modulus) {
3722 addptr(reg, modulus - 1);
3723 andptr(reg, -modulus);
3724 }
3725
3726 void MacroAssembler::save_rax(Register tmp) {
3727 if (tmp == noreg) push(rax);
3728 else if (tmp != rax) mov(tmp, rax);
3729 }
3730
3731 // Write serialization page so VM thread can do a pseudo remote membar.
3732 // We use the current thread pointer to calculate a thread specific
3733 // offset to write to within the page. This minimizes bus traffic
3734 // due to cache line collision.
3735 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3736 movl(tmp, thread);
3737 shrl(tmp, os::get_serialize_page_shift_count());
3738 andl(tmp, (os::vm_page_size() - sizeof(int)));
3739
3740 Address index(noreg, tmp, Address::times_1);
3741 ExternalAddress page(os::get_memory_serialize_page());
3742
3743 // Size of store must match masking code above
3744 movl(as_Address(ArrayAddress(page, index)), tmp);
3745 }
3746
3747 // Calls to C land
3748 //
3749 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3750 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3751 // has to be reset to 0. This is required to allow proper stack traversal.
3752 void MacroAssembler::set_last_Java_frame(Register java_thread,
3753 Register last_java_sp,
3754 Register last_java_fp,
3755 address last_java_pc) {
3756 vzeroupper();
3757 // determine java_thread register
3758 if (!java_thread->is_valid()) {
3759 java_thread = rdi;
3760 get_thread(java_thread);
3761 }
3762 // determine last_java_sp register
3763 if (!last_java_sp->is_valid()) {
3764 last_java_sp = rsp;
3765 }
3766
3767 // last_java_fp is optional
3768
3769 if (last_java_fp->is_valid()) {
3770 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3771 }
3772
3773 // last_java_pc is optional
3774
3775 if (last_java_pc != NULL) {
3776 lea(Address(java_thread,
3777 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3778 InternalAddress(last_java_pc));
3779
3780 }
3781 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3782 }
3783
3784 void MacroAssembler::shlptr(Register dst, int imm8) {
3785 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3786 }
3787
3788 void MacroAssembler::shrptr(Register dst, int imm8) {
3789 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3790 }
3791
3792 void MacroAssembler::sign_extend_byte(Register reg) {
3793 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3794 movsbl(reg, reg); // movsxb
3795 } else {
3796 shll(reg, 24);
3797 sarl(reg, 24);
3798 }
3799 }
3800
3801 void MacroAssembler::sign_extend_short(Register reg) {
3802 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3803 movswl(reg, reg); // movsxw
3804 } else {
3805 shll(reg, 16);
3806 sarl(reg, 16);
3807 }
3808 }
3809
3810 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3811 assert(reachable(src), "Address should be reachable");
3812 testl(dst, as_Address(src));
3813 }
3814
3815 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3816 int dst_enc = dst->encoding();
3817 int src_enc = src->encoding();
3818 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3819 Assembler::pcmpeqb(dst, src);
3820 } else if ((dst_enc < 16) && (src_enc < 16)) {
3821 Assembler::pcmpeqb(dst, src);
3822 } else if (src_enc < 16) {
3823 subptr(rsp, 64);
3824 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3825 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3826 Assembler::pcmpeqb(xmm0, src);
3827 movdqu(dst, xmm0);
3828 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3829 addptr(rsp, 64);
3830 } else if (dst_enc < 16) {
3831 subptr(rsp, 64);
3832 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3833 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3834 Assembler::pcmpeqb(dst, xmm0);
3835 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3836 addptr(rsp, 64);
3837 } else {
3838 subptr(rsp, 64);
3839 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3840 subptr(rsp, 64);
3841 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3842 movdqu(xmm0, src);
3843 movdqu(xmm1, dst);
3844 Assembler::pcmpeqb(xmm1, xmm0);
3845 movdqu(dst, xmm1);
3846 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3847 addptr(rsp, 64);
3848 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3849 addptr(rsp, 64);
3850 }
3851 }
3852
3853 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3854 int dst_enc = dst->encoding();
3855 int src_enc = src->encoding();
3856 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3857 Assembler::pcmpeqw(dst, src);
3858 } else if ((dst_enc < 16) && (src_enc < 16)) {
3859 Assembler::pcmpeqw(dst, src);
3860 } else if (src_enc < 16) {
3861 subptr(rsp, 64);
3862 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3863 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3864 Assembler::pcmpeqw(xmm0, src);
3865 movdqu(dst, xmm0);
3866 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3867 addptr(rsp, 64);
3868 } else if (dst_enc < 16) {
3869 subptr(rsp, 64);
3870 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3871 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3872 Assembler::pcmpeqw(dst, xmm0);
3873 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3874 addptr(rsp, 64);
3875 } else {
3876 subptr(rsp, 64);
3877 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3878 subptr(rsp, 64);
3879 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3880 movdqu(xmm0, src);
3881 movdqu(xmm1, dst);
3882 Assembler::pcmpeqw(xmm1, xmm0);
3883 movdqu(dst, xmm1);
3884 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3885 addptr(rsp, 64);
3886 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3887 addptr(rsp, 64);
3888 }
3889 }
3890
3891 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3892 int dst_enc = dst->encoding();
3893 if (dst_enc < 16) {
3894 Assembler::pcmpestri(dst, src, imm8);
3895 } else {
3896 subptr(rsp, 64);
3897 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3898 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3899 Assembler::pcmpestri(xmm0, src, imm8);
3900 movdqu(dst, xmm0);
3901 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3902 addptr(rsp, 64);
3903 }
3904 }
3905
3906 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3907 int dst_enc = dst->encoding();
3908 int src_enc = src->encoding();
3909 if ((dst_enc < 16) && (src_enc < 16)) {
3910 Assembler::pcmpestri(dst, src, imm8);
3911 } else if (src_enc < 16) {
3912 subptr(rsp, 64);
3913 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3914 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3915 Assembler::pcmpestri(xmm0, src, imm8);
3916 movdqu(dst, xmm0);
3917 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3918 addptr(rsp, 64);
3919 } else if (dst_enc < 16) {
3920 subptr(rsp, 64);
3921 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3922 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3923 Assembler::pcmpestri(dst, xmm0, imm8);
3924 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3925 addptr(rsp, 64);
3926 } else {
3927 subptr(rsp, 64);
3928 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3929 subptr(rsp, 64);
3930 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3931 movdqu(xmm0, src);
3932 movdqu(xmm1, dst);
3933 Assembler::pcmpestri(xmm1, xmm0, imm8);
3934 movdqu(dst, xmm1);
3935 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3936 addptr(rsp, 64);
3937 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3938 addptr(rsp, 64);
3939 }
3940 }
3941
3942 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3943 int dst_enc = dst->encoding();
3944 int src_enc = src->encoding();
3945 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3946 Assembler::pmovzxbw(dst, src);
3947 } else if ((dst_enc < 16) && (src_enc < 16)) {
3948 Assembler::pmovzxbw(dst, src);
3949 } else if (src_enc < 16) {
3950 subptr(rsp, 64);
3951 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3952 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3953 Assembler::pmovzxbw(xmm0, src);
3954 movdqu(dst, xmm0);
3955 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3956 addptr(rsp, 64);
3957 } else if (dst_enc < 16) {
3958 subptr(rsp, 64);
3959 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3960 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3961 Assembler::pmovzxbw(dst, xmm0);
3962 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3963 addptr(rsp, 64);
3964 } else {
3965 subptr(rsp, 64);
3966 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3967 subptr(rsp, 64);
3968 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3969 movdqu(xmm0, src);
3970 movdqu(xmm1, dst);
3971 Assembler::pmovzxbw(xmm1, xmm0);
3972 movdqu(dst, xmm1);
3973 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3974 addptr(rsp, 64);
3975 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3976 addptr(rsp, 64);
3977 }
3978 }
3979
3980 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3981 int dst_enc = dst->encoding();
3982 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3983 Assembler::pmovzxbw(dst, src);
3984 } else if (dst_enc < 16) {
3985 Assembler::pmovzxbw(dst, src);
3986 } else {
3987 subptr(rsp, 64);
3988 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3989 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3990 Assembler::pmovzxbw(xmm0, src);
3991 movdqu(dst, xmm0);
3992 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3993 addptr(rsp, 64);
3994 }
3995 }
3996
3997 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3998 int src_enc = src->encoding();
3999 if (src_enc < 16) {
4000 Assembler::pmovmskb(dst, src);
4001 } else {
4002 subptr(rsp, 64);
4003 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4004 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4005 Assembler::pmovmskb(dst, xmm0);
4006 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4007 addptr(rsp, 64);
4008 }
4009 }
4010
4011 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4012 int dst_enc = dst->encoding();
4013 int src_enc = src->encoding();
4014 if ((dst_enc < 16) && (src_enc < 16)) {
4015 Assembler::ptest(dst, src);
4016 } else if (src_enc < 16) {
4017 subptr(rsp, 64);
4018 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4019 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4020 Assembler::ptest(xmm0, src);
4021 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4022 addptr(rsp, 64);
4023 } else if (dst_enc < 16) {
4024 subptr(rsp, 64);
4025 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4026 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4027 Assembler::ptest(dst, xmm0);
4028 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4029 addptr(rsp, 64);
4030 } else {
4031 subptr(rsp, 64);
4032 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4033 subptr(rsp, 64);
4034 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4035 movdqu(xmm0, src);
4036 movdqu(xmm1, dst);
4037 Assembler::ptest(xmm1, xmm0);
4038 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4039 addptr(rsp, 64);
4040 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4041 addptr(rsp, 64);
4042 }
4043 }
4044
4045 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4046 if (reachable(src)) {
4047 Assembler::sqrtsd(dst, as_Address(src));
4048 } else {
4049 lea(rscratch1, src);
4050 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4051 }
4052 }
4053
4054 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4055 if (reachable(src)) {
4056 Assembler::sqrtss(dst, as_Address(src));
4057 } else {
4058 lea(rscratch1, src);
4059 Assembler::sqrtss(dst, Address(rscratch1, 0));
4060 }
4061 }
4062
4063 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4064 if (reachable(src)) {
4065 Assembler::subsd(dst, as_Address(src));
4066 } else {
4067 lea(rscratch1, src);
4068 Assembler::subsd(dst, Address(rscratch1, 0));
4069 }
4070 }
4071
4072 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4073 if (reachable(src)) {
4074 Assembler::subss(dst, as_Address(src));
4075 } else {
4076 lea(rscratch1, src);
4077 Assembler::subss(dst, Address(rscratch1, 0));
4078 }
4079 }
4080
4081 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4082 if (reachable(src)) {
4083 Assembler::ucomisd(dst, as_Address(src));
4084 } else {
4085 lea(rscratch1, src);
4086 Assembler::ucomisd(dst, Address(rscratch1, 0));
4087 }
4088 }
4089
4090 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4091 if (reachable(src)) {
4092 Assembler::ucomiss(dst, as_Address(src));
4093 } else {
4094 lea(rscratch1, src);
4095 Assembler::ucomiss(dst, Address(rscratch1, 0));
4096 }
4097 }
4098
4099 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4100 // Used in sign-bit flipping with aligned address.
4101 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4102 if (reachable(src)) {
4103 Assembler::xorpd(dst, as_Address(src));
4104 } else {
4105 lea(rscratch1, src);
4106 Assembler::xorpd(dst, Address(rscratch1, 0));
4107 }
4108 }
4109
4110 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4111 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4112 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4113 }
4114 else {
4115 Assembler::xorpd(dst, src);
4116 }
4117 }
4118
4119 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4120 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4121 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4122 } else {
4123 Assembler::xorps(dst, src);
4124 }
4125 }
4126
4127 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4128 // Used in sign-bit flipping with aligned address.
4129 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4130 if (reachable(src)) {
4131 Assembler::xorps(dst, as_Address(src));
4132 } else {
4133 lea(rscratch1, src);
4134 Assembler::xorps(dst, Address(rscratch1, 0));
4135 }
4136 }
4137
4138 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4139 // Used in sign-bit flipping with aligned address.
4140 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4141 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4142 if (reachable(src)) {
4143 Assembler::pshufb(dst, as_Address(src));
4144 } else {
4145 lea(rscratch1, src);
4146 Assembler::pshufb(dst, Address(rscratch1, 0));
4147 }
4148 }
4149
4150 // AVX 3-operands instructions
4151
4152 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4153 if (reachable(src)) {
4154 vaddsd(dst, nds, as_Address(src));
4155 } else {
4156 lea(rscratch1, src);
4157 vaddsd(dst, nds, Address(rscratch1, 0));
4158 }
4159 }
4160
4161 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4162 if (reachable(src)) {
4163 vaddss(dst, nds, as_Address(src));
4164 } else {
4165 lea(rscratch1, src);
4166 vaddss(dst, nds, Address(rscratch1, 0));
4167 }
4168 }
4169
4170 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4171 int dst_enc = dst->encoding();
4172 int nds_enc = nds->encoding();
4173 int src_enc = src->encoding();
4174 if ((dst_enc < 16) && (nds_enc < 16)) {
4175 vandps(dst, nds, negate_field, vector_len);
4176 } else if ((src_enc < 16) && (dst_enc < 16)) {
4177 evmovdqul(src, nds, Assembler::AVX_512bit);
4178 vandps(dst, src, negate_field, vector_len);
4179 } else if (src_enc < 16) {
4180 evmovdqul(src, nds, Assembler::AVX_512bit);
4181 vandps(src, src, negate_field, vector_len);
4182 evmovdqul(dst, src, Assembler::AVX_512bit);
4183 } else if (dst_enc < 16) {
4184 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4185 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4186 vandps(dst, xmm0, negate_field, vector_len);
4187 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4188 } else {
4189 if (src_enc != dst_enc) {
4190 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4191 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4192 vandps(xmm0, xmm0, negate_field, vector_len);
4193 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4194 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4195 } else {
4196 subptr(rsp, 64);
4197 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4198 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4199 vandps(xmm0, xmm0, negate_field, vector_len);
4200 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4201 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4202 addptr(rsp, 64);
4203 }
4204 }
4205 }
4206
4207 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4208 int dst_enc = dst->encoding();
4209 int nds_enc = nds->encoding();
4210 int src_enc = src->encoding();
4211 if ((dst_enc < 16) && (nds_enc < 16)) {
4212 vandpd(dst, nds, negate_field, vector_len);
4213 } else if ((src_enc < 16) && (dst_enc < 16)) {
4214 evmovdqul(src, nds, Assembler::AVX_512bit);
4215 vandpd(dst, src, negate_field, vector_len);
4216 } else if (src_enc < 16) {
4217 evmovdqul(src, nds, Assembler::AVX_512bit);
4218 vandpd(src, src, negate_field, vector_len);
4219 evmovdqul(dst, src, Assembler::AVX_512bit);
4220 } else if (dst_enc < 16) {
4221 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4222 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4223 vandpd(dst, xmm0, negate_field, vector_len);
4224 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4225 } else {
4226 if (src_enc != dst_enc) {
4227 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4228 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4229 vandpd(xmm0, xmm0, negate_field, vector_len);
4230 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4231 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4232 } else {
4233 subptr(rsp, 64);
4234 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4235 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4236 vandpd(xmm0, xmm0, negate_field, vector_len);
4237 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4238 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4239 addptr(rsp, 64);
4240 }
4241 }
4242 }
4243
4244 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4245 int dst_enc = dst->encoding();
4246 int nds_enc = nds->encoding();
4247 int src_enc = src->encoding();
4248 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4249 Assembler::vpaddb(dst, nds, src, vector_len);
4250 } else if ((dst_enc < 16) && (src_enc < 16)) {
4251 Assembler::vpaddb(dst, dst, src, vector_len);
4252 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4253 // use nds as scratch for src
4254 evmovdqul(nds, src, Assembler::AVX_512bit);
4255 Assembler::vpaddb(dst, dst, nds, vector_len);
4256 } else if ((src_enc < 16) && (nds_enc < 16)) {
4257 // use nds as scratch for dst
4258 evmovdqul(nds, dst, Assembler::AVX_512bit);
4259 Assembler::vpaddb(nds, nds, src, vector_len);
4260 evmovdqul(dst, nds, Assembler::AVX_512bit);
4261 } else if (dst_enc < 16) {
4262 // use nds as scatch for xmm0 to hold src
4263 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4264 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4265 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4266 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4267 } else {
4268 // worse case scenario, all regs are in the upper bank
4269 subptr(rsp, 64);
4270 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4271 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4272 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4273 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4274 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4275 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4276 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4277 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4278 addptr(rsp, 64);
4279 }
4280 }
4281
4282 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4283 int dst_enc = dst->encoding();
4284 int nds_enc = nds->encoding();
4285 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4286 Assembler::vpaddb(dst, nds, src, vector_len);
4287 } else if (dst_enc < 16) {
4288 Assembler::vpaddb(dst, dst, src, vector_len);
4289 } else if (nds_enc < 16) {
4290 // implies dst_enc in upper bank with src as scratch
4291 evmovdqul(nds, dst, Assembler::AVX_512bit);
4292 Assembler::vpaddb(nds, nds, src, vector_len);
4293 evmovdqul(dst, nds, Assembler::AVX_512bit);
4294 } else {
4295 // worse case scenario, all regs in upper bank
4296 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4297 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4298 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4299 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4300 }
4301 }
4302
4303 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4304 int dst_enc = dst->encoding();
4305 int nds_enc = nds->encoding();
4306 int src_enc = src->encoding();
4307 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4308 Assembler::vpaddw(dst, nds, src, vector_len);
4309 } else if ((dst_enc < 16) && (src_enc < 16)) {
4310 Assembler::vpaddw(dst, dst, src, vector_len);
4311 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4312 // use nds as scratch for src
4313 evmovdqul(nds, src, Assembler::AVX_512bit);
4314 Assembler::vpaddw(dst, dst, nds, vector_len);
4315 } else if ((src_enc < 16) && (nds_enc < 16)) {
4316 // use nds as scratch for dst
4317 evmovdqul(nds, dst, Assembler::AVX_512bit);
4318 Assembler::vpaddw(nds, nds, src, vector_len);
4319 evmovdqul(dst, nds, Assembler::AVX_512bit);
4320 } else if (dst_enc < 16) {
4321 // use nds as scatch for xmm0 to hold src
4322 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4323 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4324 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4325 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4326 } else {
4327 // worse case scenario, all regs are in the upper bank
4328 subptr(rsp, 64);
4329 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4330 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4331 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4332 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4333 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4334 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4335 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4336 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4337 addptr(rsp, 64);
4338 }
4339 }
4340
4341 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4342 int dst_enc = dst->encoding();
4343 int nds_enc = nds->encoding();
4344 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4345 Assembler::vpaddw(dst, nds, src, vector_len);
4346 } else if (dst_enc < 16) {
4347 Assembler::vpaddw(dst, dst, src, vector_len);
4348 } else if (nds_enc < 16) {
4349 // implies dst_enc in upper bank with src as scratch
4350 evmovdqul(nds, dst, Assembler::AVX_512bit);
4351 Assembler::vpaddw(nds, nds, src, vector_len);
4352 evmovdqul(dst, nds, Assembler::AVX_512bit);
4353 } else {
4354 // worse case scenario, all regs in upper bank
4355 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4356 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4357 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4358 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4359 }
4360 }
4361
4362 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4363 if (reachable(src)) {
4364 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4365 } else {
4366 lea(rscratch1, src);
4367 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4368 }
4369 }
4370
4371 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4372 int dst_enc = dst->encoding();
4373 int src_enc = src->encoding();
4374 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4375 Assembler::vpbroadcastw(dst, src);
4376 } else if ((dst_enc < 16) && (src_enc < 16)) {
4377 Assembler::vpbroadcastw(dst, src);
4378 } else if (src_enc < 16) {
4379 subptr(rsp, 64);
4380 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4381 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4382 Assembler::vpbroadcastw(xmm0, src);
4383 movdqu(dst, xmm0);
4384 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4385 addptr(rsp, 64);
4386 } else if (dst_enc < 16) {
4387 subptr(rsp, 64);
4388 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4389 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4390 Assembler::vpbroadcastw(dst, xmm0);
4391 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4392 addptr(rsp, 64);
4393 } else {
4394 subptr(rsp, 64);
4395 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4396 subptr(rsp, 64);
4397 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4398 movdqu(xmm0, src);
4399 movdqu(xmm1, dst);
4400 Assembler::vpbroadcastw(xmm1, xmm0);
4401 movdqu(dst, xmm1);
4402 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4403 addptr(rsp, 64);
4404 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4405 addptr(rsp, 64);
4406 }
4407 }
4408
4409 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4410 int dst_enc = dst->encoding();
4411 int nds_enc = nds->encoding();
4412 int src_enc = src->encoding();
4413 assert(dst_enc == nds_enc, "");
4414 if ((dst_enc < 16) && (src_enc < 16)) {
4415 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4416 } else if (src_enc < 16) {
4417 subptr(rsp, 64);
4418 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4419 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4420 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4421 movdqu(dst, xmm0);
4422 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4423 addptr(rsp, 64);
4424 } else if (dst_enc < 16) {
4425 subptr(rsp, 64);
4426 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4427 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4428 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4429 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4430 addptr(rsp, 64);
4431 } else {
4432 subptr(rsp, 64);
4433 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4434 subptr(rsp, 64);
4435 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4436 movdqu(xmm0, src);
4437 movdqu(xmm1, dst);
4438 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4439 movdqu(dst, xmm1);
4440 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4441 addptr(rsp, 64);
4442 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4443 addptr(rsp, 64);
4444 }
4445 }
4446
4447 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4448 int dst_enc = dst->encoding();
4449 int nds_enc = nds->encoding();
4450 int src_enc = src->encoding();
4451 assert(dst_enc == nds_enc, "");
4452 if ((dst_enc < 16) && (src_enc < 16)) {
4453 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4454 } else if (src_enc < 16) {
4455 subptr(rsp, 64);
4456 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4457 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4458 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4459 movdqu(dst, xmm0);
4460 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4461 addptr(rsp, 64);
4462 } else if (dst_enc < 16) {
4463 subptr(rsp, 64);
4464 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4465 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4466 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4467 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4468 addptr(rsp, 64);
4469 } else {
4470 subptr(rsp, 64);
4471 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4472 subptr(rsp, 64);
4473 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4474 movdqu(xmm0, src);
4475 movdqu(xmm1, dst);
4476 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4477 movdqu(dst, xmm1);
4478 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4479 addptr(rsp, 64);
4480 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4481 addptr(rsp, 64);
4482 }
4483 }
4484
4485 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4486 int dst_enc = dst->encoding();
4487 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4488 Assembler::vpmovzxbw(dst, src, vector_len);
4489 } else if (dst_enc < 16) {
4490 Assembler::vpmovzxbw(dst, src, vector_len);
4491 } else {
4492 subptr(rsp, 64);
4493 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4494 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4495 Assembler::vpmovzxbw(xmm0, src, vector_len);
4496 movdqu(dst, xmm0);
4497 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4498 addptr(rsp, 64);
4499 }
4500 }
4501
4502 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4503 int src_enc = src->encoding();
4504 if (src_enc < 16) {
4505 Assembler::vpmovmskb(dst, src);
4506 } else {
4507 subptr(rsp, 64);
4508 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4509 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4510 Assembler::vpmovmskb(dst, xmm0);
4511 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4512 addptr(rsp, 64);
4513 }
4514 }
4515
4516 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4517 int dst_enc = dst->encoding();
4518 int nds_enc = nds->encoding();
4519 int src_enc = src->encoding();
4520 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4521 Assembler::vpmullw(dst, nds, src, vector_len);
4522 } else if ((dst_enc < 16) && (src_enc < 16)) {
4523 Assembler::vpmullw(dst, dst, src, vector_len);
4524 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4525 // use nds as scratch for src
4526 evmovdqul(nds, src, Assembler::AVX_512bit);
4527 Assembler::vpmullw(dst, dst, nds, vector_len);
4528 } else if ((src_enc < 16) && (nds_enc < 16)) {
4529 // use nds as scratch for dst
4530 evmovdqul(nds, dst, Assembler::AVX_512bit);
4531 Assembler::vpmullw(nds, nds, src, vector_len);
4532 evmovdqul(dst, nds, Assembler::AVX_512bit);
4533 } else if (dst_enc < 16) {
4534 // use nds as scatch for xmm0 to hold src
4535 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4536 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4537 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4538 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4539 } else {
4540 // worse case scenario, all regs are in the upper bank
4541 subptr(rsp, 64);
4542 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4543 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4544 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4545 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4546 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4547 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4548 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4549 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4550 addptr(rsp, 64);
4551 }
4552 }
4553
4554 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4555 int dst_enc = dst->encoding();
4556 int nds_enc = nds->encoding();
4557 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4558 Assembler::vpmullw(dst, nds, src, vector_len);
4559 } else if (dst_enc < 16) {
4560 Assembler::vpmullw(dst, dst, src, vector_len);
4561 } else if (nds_enc < 16) {
4562 // implies dst_enc in upper bank with src as scratch
4563 evmovdqul(nds, dst, Assembler::AVX_512bit);
4564 Assembler::vpmullw(nds, nds, src, vector_len);
4565 evmovdqul(dst, nds, Assembler::AVX_512bit);
4566 } else {
4567 // worse case scenario, all regs in upper bank
4568 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4569 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4570 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4571 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4572 }
4573 }
4574
4575 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4576 int dst_enc = dst->encoding();
4577 int nds_enc = nds->encoding();
4578 int src_enc = src->encoding();
4579 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4580 Assembler::vpsubb(dst, nds, src, vector_len);
4581 } else if ((dst_enc < 16) && (src_enc < 16)) {
4582 Assembler::vpsubb(dst, dst, src, vector_len);
4583 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4584 // use nds as scratch for src
4585 evmovdqul(nds, src, Assembler::AVX_512bit);
4586 Assembler::vpsubb(dst, dst, nds, vector_len);
4587 } else if ((src_enc < 16) && (nds_enc < 16)) {
4588 // use nds as scratch for dst
4589 evmovdqul(nds, dst, Assembler::AVX_512bit);
4590 Assembler::vpsubb(nds, nds, src, vector_len);
4591 evmovdqul(dst, nds, Assembler::AVX_512bit);
4592 } else if (dst_enc < 16) {
4593 // use nds as scatch for xmm0 to hold src
4594 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4595 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4596 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4597 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4598 } else {
4599 // worse case scenario, all regs are in the upper bank
4600 subptr(rsp, 64);
4601 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4602 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4603 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4604 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4605 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4606 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4607 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4608 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4609 addptr(rsp, 64);
4610 }
4611 }
4612
4613 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4614 int dst_enc = dst->encoding();
4615 int nds_enc = nds->encoding();
4616 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4617 Assembler::vpsubb(dst, nds, src, vector_len);
4618 } else if (dst_enc < 16) {
4619 Assembler::vpsubb(dst, dst, src, vector_len);
4620 } else if (nds_enc < 16) {
4621 // implies dst_enc in upper bank with src as scratch
4622 evmovdqul(nds, dst, Assembler::AVX_512bit);
4623 Assembler::vpsubb(nds, nds, src, vector_len);
4624 evmovdqul(dst, nds, Assembler::AVX_512bit);
4625 } else {
4626 // worse case scenario, all regs in upper bank
4627 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4628 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4629 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4630 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4631 }
4632 }
4633
4634 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4635 int dst_enc = dst->encoding();
4636 int nds_enc = nds->encoding();
4637 int src_enc = src->encoding();
4638 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4639 Assembler::vpsubw(dst, nds, src, vector_len);
4640 } else if ((dst_enc < 16) && (src_enc < 16)) {
4641 Assembler::vpsubw(dst, dst, src, vector_len);
4642 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4643 // use nds as scratch for src
4644 evmovdqul(nds, src, Assembler::AVX_512bit);
4645 Assembler::vpsubw(dst, dst, nds, vector_len);
4646 } else if ((src_enc < 16) && (nds_enc < 16)) {
4647 // use nds as scratch for dst
4648 evmovdqul(nds, dst, Assembler::AVX_512bit);
4649 Assembler::vpsubw(nds, nds, src, vector_len);
4650 evmovdqul(dst, nds, Assembler::AVX_512bit);
4651 } else if (dst_enc < 16) {
4652 // use nds as scatch for xmm0 to hold src
4653 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4654 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4655 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4656 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4657 } else {
4658 // worse case scenario, all regs are in the upper bank
4659 subptr(rsp, 64);
4660 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4661 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4662 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4663 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4664 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4665 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4666 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4667 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4668 addptr(rsp, 64);
4669 }
4670 }
4671
4672 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4673 int dst_enc = dst->encoding();
4674 int nds_enc = nds->encoding();
4675 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4676 Assembler::vpsubw(dst, nds, src, vector_len);
4677 } else if (dst_enc < 16) {
4678 Assembler::vpsubw(dst, dst, src, vector_len);
4679 } else if (nds_enc < 16) {
4680 // implies dst_enc in upper bank with src as scratch
4681 evmovdqul(nds, dst, Assembler::AVX_512bit);
4682 Assembler::vpsubw(nds, nds, src, vector_len);
4683 evmovdqul(dst, nds, Assembler::AVX_512bit);
4684 } else {
4685 // worse case scenario, all regs in upper bank
4686 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4687 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4688 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4689 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4690 }
4691 }
4692
4693 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4694 int dst_enc = dst->encoding();
4695 int nds_enc = nds->encoding();
4696 int shift_enc = shift->encoding();
4697 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4698 Assembler::vpsraw(dst, nds, shift, vector_len);
4699 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4700 Assembler::vpsraw(dst, dst, shift, vector_len);
4701 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4702 // use nds_enc as scratch with shift
4703 evmovdqul(nds, shift, Assembler::AVX_512bit);
4704 Assembler::vpsraw(dst, dst, nds, vector_len);
4705 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4706 // use nds as scratch with dst
4707 evmovdqul(nds, dst, Assembler::AVX_512bit);
4708 Assembler::vpsraw(nds, nds, shift, vector_len);
4709 evmovdqul(dst, nds, Assembler::AVX_512bit);
4710 } else if (dst_enc < 16) {
4711 // use nds to save a copy of xmm0 and hold shift
4712 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4713 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4714 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4715 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4716 } else if (nds_enc < 16) {
4717 // use nds as dest as temps
4718 evmovdqul(nds, dst, Assembler::AVX_512bit);
4719 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4720 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4721 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4722 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4723 evmovdqul(dst, nds, Assembler::AVX_512bit);
4724 } else {
4725 // worse case scenario, all regs are in the upper bank
4726 subptr(rsp, 64);
4727 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4728 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4729 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4730 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4731 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4732 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4733 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4734 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4735 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4736 addptr(rsp, 64);
4737 }
4738 }
4739
4740 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4741 int dst_enc = dst->encoding();
4742 int nds_enc = nds->encoding();
4743 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4744 Assembler::vpsraw(dst, nds, shift, vector_len);
4745 } else if (dst_enc < 16) {
4746 Assembler::vpsraw(dst, dst, shift, vector_len);
4747 } else if (nds_enc < 16) {
4748 // use nds as scratch
4749 evmovdqul(nds, dst, Assembler::AVX_512bit);
4750 Assembler::vpsraw(nds, nds, shift, vector_len);
4751 evmovdqul(dst, nds, Assembler::AVX_512bit);
4752 } else {
4753 // use nds as scratch for xmm0
4754 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4755 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4756 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4757 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4758 }
4759 }
4760
4761 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4762 int dst_enc = dst->encoding();
4763 int nds_enc = nds->encoding();
4764 int shift_enc = shift->encoding();
4765 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4766 Assembler::vpsrlw(dst, nds, shift, vector_len);
4767 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4768 Assembler::vpsrlw(dst, dst, shift, vector_len);
4769 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4770 // use nds_enc as scratch with shift
4771 evmovdqul(nds, shift, Assembler::AVX_512bit);
4772 Assembler::vpsrlw(dst, dst, nds, vector_len);
4773 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4774 // use nds as scratch with dst
4775 evmovdqul(nds, dst, Assembler::AVX_512bit);
4776 Assembler::vpsrlw(nds, nds, shift, vector_len);
4777 evmovdqul(dst, nds, Assembler::AVX_512bit);
4778 } else if (dst_enc < 16) {
4779 // use nds to save a copy of xmm0 and hold shift
4780 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4781 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4782 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4783 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4784 } else if (nds_enc < 16) {
4785 // use nds as dest as temps
4786 evmovdqul(nds, dst, Assembler::AVX_512bit);
4787 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4788 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4789 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4790 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4791 evmovdqul(dst, nds, Assembler::AVX_512bit);
4792 } else {
4793 // worse case scenario, all regs are in the upper bank
4794 subptr(rsp, 64);
4795 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4796 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4797 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4798 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4799 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4800 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4801 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4802 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4803 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4804 addptr(rsp, 64);
4805 }
4806 }
4807
4808 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4809 int dst_enc = dst->encoding();
4810 int nds_enc = nds->encoding();
4811 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4812 Assembler::vpsrlw(dst, nds, shift, vector_len);
4813 } else if (dst_enc < 16) {
4814 Assembler::vpsrlw(dst, dst, shift, vector_len);
4815 } else if (nds_enc < 16) {
4816 // use nds as scratch
4817 evmovdqul(nds, dst, Assembler::AVX_512bit);
4818 Assembler::vpsrlw(nds, nds, shift, vector_len);
4819 evmovdqul(dst, nds, Assembler::AVX_512bit);
4820 } else {
4821 // use nds as scratch for xmm0
4822 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4823 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4824 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4825 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4826 }
4827 }
4828
4829 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4830 int dst_enc = dst->encoding();
4831 int nds_enc = nds->encoding();
4832 int shift_enc = shift->encoding();
4833 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4834 Assembler::vpsllw(dst, nds, shift, vector_len);
4835 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4836 Assembler::vpsllw(dst, dst, shift, vector_len);
4837 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4838 // use nds_enc as scratch with shift
4839 evmovdqul(nds, shift, Assembler::AVX_512bit);
4840 Assembler::vpsllw(dst, dst, nds, vector_len);
4841 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4842 // use nds as scratch with dst
4843 evmovdqul(nds, dst, Assembler::AVX_512bit);
4844 Assembler::vpsllw(nds, nds, shift, vector_len);
4845 evmovdqul(dst, nds, Assembler::AVX_512bit);
4846 } else if (dst_enc < 16) {
4847 // use nds to save a copy of xmm0 and hold shift
4848 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4849 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4850 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4851 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4852 } else if (nds_enc < 16) {
4853 // use nds as dest as temps
4854 evmovdqul(nds, dst, Assembler::AVX_512bit);
4855 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4856 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4857 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4858 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4859 evmovdqul(dst, nds, Assembler::AVX_512bit);
4860 } else {
4861 // worse case scenario, all regs are in the upper bank
4862 subptr(rsp, 64);
4863 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4864 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4865 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4866 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4867 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4868 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4869 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4870 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4871 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4872 addptr(rsp, 64);
4873 }
4874 }
4875
4876 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4877 int dst_enc = dst->encoding();
4878 int nds_enc = nds->encoding();
4879 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4880 Assembler::vpsllw(dst, nds, shift, vector_len);
4881 } else if (dst_enc < 16) {
4882 Assembler::vpsllw(dst, dst, shift, vector_len);
4883 } else if (nds_enc < 16) {
4884 // use nds as scratch
4885 evmovdqul(nds, dst, Assembler::AVX_512bit);
4886 Assembler::vpsllw(nds, nds, shift, vector_len);
4887 evmovdqul(dst, nds, Assembler::AVX_512bit);
4888 } else {
4889 // use nds as scratch for xmm0
4890 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4891 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4892 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4893 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4894 }
4895 }
4896
4897 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4898 int dst_enc = dst->encoding();
4899 int src_enc = src->encoding();
4900 if ((dst_enc < 16) && (src_enc < 16)) {
4901 Assembler::vptest(dst, src);
4902 } else if (src_enc < 16) {
4903 subptr(rsp, 64);
4904 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4905 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4906 Assembler::vptest(xmm0, src);
4907 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4908 addptr(rsp, 64);
4909 } else if (dst_enc < 16) {
4910 subptr(rsp, 64);
4911 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4912 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4913 Assembler::vptest(dst, xmm0);
4914 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4915 addptr(rsp, 64);
4916 } else {
4917 subptr(rsp, 64);
4918 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4919 subptr(rsp, 64);
4920 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4921 movdqu(xmm0, src);
4922 movdqu(xmm1, dst);
4923 Assembler::vptest(xmm1, xmm0);
4924 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4925 addptr(rsp, 64);
4926 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4927 addptr(rsp, 64);
4928 }
4929 }
4930
4931 // This instruction exists within macros, ergo we cannot control its input
4932 // when emitted through those patterns.
4933 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4934 if (VM_Version::supports_avx512nobw()) {
4935 int dst_enc = dst->encoding();
4936 int src_enc = src->encoding();
4937 if (dst_enc == src_enc) {
4938 if (dst_enc < 16) {
4939 Assembler::punpcklbw(dst, src);
4940 } else {
4941 subptr(rsp, 64);
4942 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4943 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4944 Assembler::punpcklbw(xmm0, xmm0);
4945 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4946 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4947 addptr(rsp, 64);
4948 }
4949 } else {
4950 if ((src_enc < 16) && (dst_enc < 16)) {
4951 Assembler::punpcklbw(dst, src);
4952 } else if (src_enc < 16) {
4953 subptr(rsp, 64);
4954 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4955 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4956 Assembler::punpcklbw(xmm0, src);
4957 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4958 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4959 addptr(rsp, 64);
4960 } else if (dst_enc < 16) {
4961 subptr(rsp, 64);
4962 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4963 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4964 Assembler::punpcklbw(dst, xmm0);
4965 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4966 addptr(rsp, 64);
4967 } else {
4968 subptr(rsp, 64);
4969 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4970 subptr(rsp, 64);
4971 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4972 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4973 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4974 Assembler::punpcklbw(xmm0, xmm1);
4975 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4976 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4977 addptr(rsp, 64);
4978 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4979 addptr(rsp, 64);
4980 }
4981 }
4982 } else {
4983 Assembler::punpcklbw(dst, src);
4984 }
4985 }
4986
4987 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4988 if (VM_Version::supports_avx512vl()) {
4989 Assembler::pshufd(dst, src, mode);
4990 } else {
4991 int dst_enc = dst->encoding();
4992 if (dst_enc < 16) {
4993 Assembler::pshufd(dst, src, mode);
4994 } else {
4995 subptr(rsp, 64);
4996 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4997 Assembler::pshufd(xmm0, src, mode);
4998 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4999 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5000 addptr(rsp, 64);
5001 }
5002 }
5003 }
5004
5005 // This instruction exists within macros, ergo we cannot control its input
5006 // when emitted through those patterns.
5007 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5008 if (VM_Version::supports_avx512nobw()) {
5009 int dst_enc = dst->encoding();
5010 int src_enc = src->encoding();
5011 if (dst_enc == src_enc) {
5012 if (dst_enc < 16) {
5013 Assembler::pshuflw(dst, src, mode);
5014 } else {
5015 subptr(rsp, 64);
5016 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5017 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5018 Assembler::pshuflw(xmm0, xmm0, mode);
5019 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5020 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5021 addptr(rsp, 64);
5022 }
5023 } else {
5024 if ((src_enc < 16) && (dst_enc < 16)) {
5025 Assembler::pshuflw(dst, src, mode);
5026 } else if (src_enc < 16) {
5027 subptr(rsp, 64);
5028 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5029 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5030 Assembler::pshuflw(xmm0, src, mode);
5031 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5032 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5033 addptr(rsp, 64);
5034 } else if (dst_enc < 16) {
5035 subptr(rsp, 64);
5036 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5037 evmovdqul(xmm0, src, Assembler::AVX_512bit);
5038 Assembler::pshuflw(dst, xmm0, mode);
5039 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5040 addptr(rsp, 64);
5041 } else {
5042 subptr(rsp, 64);
5043 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5044 subptr(rsp, 64);
5045 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5046 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5047 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5048 Assembler::pshuflw(xmm0, xmm1, mode);
5049 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5050 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5051 addptr(rsp, 64);
5052 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5053 addptr(rsp, 64);
5054 }
5055 }
5056 } else {
5057 Assembler::pshuflw(dst, src, mode);
5058 }
5059 }
5060
5061 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5062 if (reachable(src)) {
5063 vandpd(dst, nds, as_Address(src), vector_len);
5064 } else {
5065 lea(rscratch1, src);
5066 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5067 }
5068 }
5069
5070 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5071 if (reachable(src)) {
5072 vandps(dst, nds, as_Address(src), vector_len);
5073 } else {
5074 lea(rscratch1, src);
5075 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5076 }
5077 }
5078
5079 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5080 if (reachable(src)) {
5081 vdivsd(dst, nds, as_Address(src));
5082 } else {
5083 lea(rscratch1, src);
5084 vdivsd(dst, nds, Address(rscratch1, 0));
5085 }
5086 }
5087
5088 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5089 if (reachable(src)) {
5090 vdivss(dst, nds, as_Address(src));
5091 } else {
5092 lea(rscratch1, src);
5093 vdivss(dst, nds, Address(rscratch1, 0));
5094 }
5095 }
5096
5097 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5098 if (reachable(src)) {
5099 vmulsd(dst, nds, as_Address(src));
5100 } else {
5101 lea(rscratch1, src);
5102 vmulsd(dst, nds, Address(rscratch1, 0));
5103 }
5104 }
5105
5106 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5107 if (reachable(src)) {
5108 vmulss(dst, nds, as_Address(src));
5109 } else {
5110 lea(rscratch1, src);
5111 vmulss(dst, nds, Address(rscratch1, 0));
5112 }
5113 }
5114
5115 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5116 if (reachable(src)) {
5117 vsubsd(dst, nds, as_Address(src));
5118 } else {
5119 lea(rscratch1, src);
5120 vsubsd(dst, nds, Address(rscratch1, 0));
5121 }
5122 }
5123
5124 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5125 if (reachable(src)) {
5126 vsubss(dst, nds, as_Address(src));
5127 } else {
5128 lea(rscratch1, src);
5129 vsubss(dst, nds, Address(rscratch1, 0));
5130 }
5131 }
5132
5133 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5134 int nds_enc = nds->encoding();
5135 int dst_enc = dst->encoding();
5136 bool dst_upper_bank = (dst_enc > 15);
5137 bool nds_upper_bank = (nds_enc > 15);
5138 if (VM_Version::supports_avx512novl() &&
5139 (nds_upper_bank || dst_upper_bank)) {
5140 if (dst_upper_bank) {
5141 subptr(rsp, 64);
5142 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5143 movflt(xmm0, nds);
5144 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5145 movflt(dst, xmm0);
5146 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5147 addptr(rsp, 64);
5148 } else {
5149 movflt(dst, nds);
5150 vxorps(dst, dst, src, Assembler::AVX_128bit);
5151 }
5152 } else {
5153 vxorps(dst, nds, src, Assembler::AVX_128bit);
5154 }
5155 }
5156
5157 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5158 int nds_enc = nds->encoding();
5159 int dst_enc = dst->encoding();
5160 bool dst_upper_bank = (dst_enc > 15);
5161 bool nds_upper_bank = (nds_enc > 15);
5162 if (VM_Version::supports_avx512novl() &&
5163 (nds_upper_bank || dst_upper_bank)) {
5164 if (dst_upper_bank) {
5165 subptr(rsp, 64);
5166 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5167 movdbl(xmm0, nds);
5168 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5169 movdbl(dst, xmm0);
5170 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5171 addptr(rsp, 64);
5172 } else {
5173 movdbl(dst, nds);
5174 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5175 }
5176 } else {
5177 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5178 }
5179 }
5180
5181 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5182 if (reachable(src)) {
5183 vxorpd(dst, nds, as_Address(src), vector_len);
5184 } else {
5185 lea(rscratch1, src);
5186 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5187 }
5188 }
5189
5190 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5191 if (reachable(src)) {
5192 vxorps(dst, nds, as_Address(src), vector_len);
5193 } else {
5194 lea(rscratch1, src);
5195 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5196 }
5197 }
5198
5199
5200 void MacroAssembler::resolve_jobject(Register value,
5201 Register thread,
5202 Register tmp) {
5203 assert_different_registers(value, thread, tmp);
5204 Label done, not_weak;
5205 testptr(value, value);
5206 jcc(Assembler::zero, done); // Use NULL as-is.
5207 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5208 jcc(Assembler::zero, not_weak);
5209 // Resolve jweak.
5210 movptr(value, Address(value, -JNIHandles::weak_tag_value));
5211 verify_oop(value);
5212 #if INCLUDE_ALL_GCS
5213 if (UseG1GC) {
5214 g1_write_barrier_pre(noreg /* obj */,
5215 value /* pre_val */,
5216 thread /* thread */,
5217 tmp /* tmp */,
5218 true /* tosca_live */,
5219 true /* expand_call */);
5220 }
5221 #endif // INCLUDE_ALL_GCS
5222 jmp(done);
5223 bind(not_weak);
5224 // Resolve (untagged) jobject.
5225 movptr(value, Address(value, 0));
5226 verify_oop(value);
5227 bind(done);
5228 }
5229
5230 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5231 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5232 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5233 // The inverted mask is sign-extended
5234 andptr(possibly_jweak, inverted_jweak_mask);
5235 }
5236
5237 //////////////////////////////////////////////////////////////////////////////////
5238 #if INCLUDE_ALL_GCS
5239
5240 void MacroAssembler::g1_write_barrier_pre(Register obj,
5241 Register pre_val,
5242 Register thread,
5243 Register tmp,
5244 bool tosca_live,
5245 bool expand_call) {
5246
5247 // If expand_call is true then we expand the call_VM_leaf macro
5248 // directly to skip generating the check by
5249 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5250
5251 #ifdef _LP64
5252 assert(thread == r15_thread, "must be");
5253 #endif // _LP64
5254
5255 Label done;
5256 Label runtime;
5257
5258 assert(pre_val != noreg, "check this code");
5259
5260 if (obj != noreg) {
5261 assert_different_registers(obj, pre_val, tmp);
5262 assert(pre_val != rax, "check this code");
5263 }
5264
5265 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5266 SATBMarkQueue::byte_offset_of_active()));
5267 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5268 SATBMarkQueue::byte_offset_of_index()));
5269 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5270 SATBMarkQueue::byte_offset_of_buf()));
5271
5272
5273 // Is marking active?
5274 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5275 cmpl(in_progress, 0);
5276 } else {
5277 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5278 cmpb(in_progress, 0);
5279 }
5280 jcc(Assembler::equal, done);
5281
5282 // Do we need to load the previous value?
5283 if (obj != noreg) {
5284 load_heap_oop(pre_val, Address(obj, 0));
5285 }
5286
5287 // Is the previous value null?
5288 cmpptr(pre_val, (int32_t) NULL_WORD);
5289 jcc(Assembler::equal, done);
5290
5291 // Can we store original value in the thread's buffer?
5292 // Is index == 0?
5293 // (The index field is typed as size_t.)
5294
5295 movptr(tmp, index); // tmp := *index_adr
5296 cmpptr(tmp, 0); // tmp == 0?
5297 jcc(Assembler::equal, runtime); // If yes, goto runtime
5298
5299 subptr(tmp, wordSize); // tmp := tmp - wordSize
5300 movptr(index, tmp); // *index_adr := tmp
5301 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5302
5303 // Record the previous value
5304 movptr(Address(tmp, 0), pre_val);
5305 jmp(done);
5306
5307 bind(runtime);
5308 // save the live input values
5309 if(tosca_live) push(rax);
5310
5311 if (obj != noreg && obj != rax)
5312 push(obj);
5313
5314 if (pre_val != rax)
5315 push(pre_val);
5316
5317 // Calling the runtime using the regular call_VM_leaf mechanism generates
5318 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5319 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5320 //
5321 // If we care generating the pre-barrier without a frame (e.g. in the
5322 // intrinsified Reference.get() routine) then ebp might be pointing to
5323 // the caller frame and so this check will most likely fail at runtime.
5324 //
5325 // Expanding the call directly bypasses the generation of the check.
5326 // So when we do not have have a full interpreter frame on the stack
5327 // expand_call should be passed true.
5328
5329 NOT_LP64( push(thread); )
5330
5331 if (expand_call) {
5332 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5333 pass_arg1(this, thread);
5334 pass_arg0(this, pre_val);
5335 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5336 } else {
5337 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5338 }
5339
5340 NOT_LP64( pop(thread); )
5341
5342 // save the live input values
5343 if (pre_val != rax)
5344 pop(pre_val);
5345
5346 if (obj != noreg && obj != rax)
5347 pop(obj);
5348
5349 if(tosca_live) pop(rax);
5350
5351 bind(done);
5352 }
5353
5354 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5355 Register new_val,
5356 Register thread,
5357 Register tmp,
5358 Register tmp2) {
5359 #ifdef _LP64
5360 assert(thread == r15_thread, "must be");
5361 #endif // _LP64
5362
5363 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5364 DirtyCardQueue::byte_offset_of_index()));
5365 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5366 DirtyCardQueue::byte_offset_of_buf()));
5367
5368 CardTableModRefBS* ct =
5369 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5370 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5371
5372 Label done;
5373 Label runtime;
5374
5375 // Does store cross heap regions?
5376
5377 movptr(tmp, store_addr);
5378 xorptr(tmp, new_val);
5379 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5380 jcc(Assembler::equal, done);
5381
5382 // crosses regions, storing NULL?
5383
5384 cmpptr(new_val, (int32_t) NULL_WORD);
5385 jcc(Assembler::equal, done);
5386
5387 // storing region crossing non-NULL, is card already dirty?
5388
5389 const Register card_addr = tmp;
5390 const Register cardtable = tmp2;
5391
5392 movptr(card_addr, store_addr);
5393 shrptr(card_addr, CardTableModRefBS::card_shift);
5394 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5395 // a valid address and therefore is not properly handled by the relocation code.
5396 movptr(cardtable, (intptr_t)ct->byte_map_base);
5397 addptr(card_addr, cardtable);
5398
5399 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5400 jcc(Assembler::equal, done);
5401
5402 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5403 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5404 jcc(Assembler::equal, done);
5405
5406
5407 // storing a region crossing, non-NULL oop, card is clean.
5408 // dirty card and log.
5409
5410 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5411
5412 cmpl(queue_index, 0);
5413 jcc(Assembler::equal, runtime);
5414 subl(queue_index, wordSize);
5415 movptr(tmp2, buffer);
5416 #ifdef _LP64
5417 movslq(rscratch1, queue_index);
5418 addq(tmp2, rscratch1);
5419 movq(Address(tmp2, 0), card_addr);
5420 #else
5421 addl(tmp2, queue_index);
5422 movl(Address(tmp2, 0), card_addr);
5423 #endif
5424 jmp(done);
5425
5426 bind(runtime);
5427 // save the live input values
5428 push(store_addr);
5429 push(new_val);
5430 #ifdef _LP64
5431 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5432 #else
5433 push(thread);
5434 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5435 pop(thread);
5436 #endif
5437 pop(new_val);
5438 pop(store_addr);
5439
5440 bind(done);
5441 }
5442
5443 #endif // INCLUDE_ALL_GCS
5444 //////////////////////////////////////////////////////////////////////////////////
5445
5446
5447 void MacroAssembler::store_check(Register obj, Address dst) {
5448 store_check(obj);
5449 }
5450
5451 void MacroAssembler::store_check(Register obj) {
5452 // Does a store check for the oop in register obj. The content of
5453 // register obj is destroyed afterwards.
5454 BarrierSet* bs = Universe::heap()->barrier_set();
5455 assert(bs->kind() == BarrierSet::CardTableForRS ||
5456 bs->kind() == BarrierSet::CardTableExtension,
5457 "Wrong barrier set kind");
5458
5459 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5460 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5461
5462 shrptr(obj, CardTableModRefBS::card_shift);
5463
5464 Address card_addr;
5465
5466 // The calculation for byte_map_base is as follows:
5467 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5468 // So this essentially converts an address to a displacement and it will
5469 // never need to be relocated. On 64bit however the value may be too
5470 // large for a 32bit displacement.
5471 intptr_t disp = (intptr_t) ct->byte_map_base;
5472 if (is_simm32(disp)) {
5473 card_addr = Address(noreg, obj, Address::times_1, disp);
5474 } else {
5475 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5476 // displacement and done in a single instruction given favorable mapping and a
5477 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5478 // entry and that entry is not properly handled by the relocation code.
5479 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5480 Address index(noreg, obj, Address::times_1);
5481 card_addr = as_Address(ArrayAddress(cardtable, index));
5482 }
5483
5484 int dirty = CardTableModRefBS::dirty_card_val();
5485 if (UseCondCardMark) {
5486 Label L_already_dirty;
5487 if (UseConcMarkSweepGC) {
5488 membar(Assembler::StoreLoad);
5489 }
5490 cmpb(card_addr, dirty);
5491 jcc(Assembler::equal, L_already_dirty);
5492 movb(card_addr, dirty);
5493 bind(L_already_dirty);
5494 } else {
5495 movb(card_addr, dirty);
5496 }
5497 }
5498
5499 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5500 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5501 }
5502
5503 // Force generation of a 4 byte immediate value even if it fits into 8bit
5504 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5505 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5506 }
5507
5508 void MacroAssembler::subptr(Register dst, Register src) {
5509 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5510 }
5511
5512 // C++ bool manipulation
5513 void MacroAssembler::testbool(Register dst) {
5514 if(sizeof(bool) == 1)
5515 testb(dst, 0xff);
5516 else if(sizeof(bool) == 2) {
5517 // testw implementation needed for two byte bools
5518 ShouldNotReachHere();
5519 } else if(sizeof(bool) == 4)
5520 testl(dst, dst);
5521 else
5522 // unsupported
5523 ShouldNotReachHere();
5524 }
5525
5526 void MacroAssembler::testptr(Register dst, Register src) {
5527 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5528 }
5529
5530 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5531 void MacroAssembler::tlab_allocate(Register obj,
5532 Register var_size_in_bytes,
5533 int con_size_in_bytes,
5534 Register t1,
5535 Register t2,
5536 Label& slow_case) {
5537 assert_different_registers(obj, t1, t2);
5538 assert_different_registers(obj, var_size_in_bytes, t1);
5539 Register end = t2;
5540 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5541
5542 verify_tlab();
5543
5544 NOT_LP64(get_thread(thread));
5545
5546 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5547 if (var_size_in_bytes == noreg) {
5548 lea(end, Address(obj, con_size_in_bytes));
5549 } else {
5550 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5551 }
5552 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5553 jcc(Assembler::above, slow_case);
5554
5555 // update the tlab top pointer
5556 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5557
5558 // recover var_size_in_bytes if necessary
5559 if (var_size_in_bytes == end) {
5560 subptr(var_size_in_bytes, obj);
5561 }
5562 verify_tlab();
5563 }
5564
5565 // Preserves rbx, and rdx.
5566 Register MacroAssembler::tlab_refill(Label& retry,
5567 Label& try_eden,
5568 Label& slow_case) {
5569 Register top = rax;
5570 Register t1 = rcx; // object size
5571 Register t2 = rsi;
5572 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5573 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5574 Label do_refill, discard_tlab;
5575
5576 if (!Universe::heap()->supports_inline_contig_alloc()) {
5577 // No allocation in the shared eden.
5578 jmp(slow_case);
5579 }
5580
5581 NOT_LP64(get_thread(thread_reg));
5582
5583 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5584 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5585
5586 // calculate amount of free space
5587 subptr(t1, top);
5588 shrptr(t1, LogHeapWordSize);
5589
5590 // Retain tlab and allocate object in shared space if
5591 // the amount free in the tlab is too large to discard.
5592 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5593 jcc(Assembler::lessEqual, discard_tlab);
5594
5595 // Retain
5596 // %%% yuck as movptr...
5597 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5598 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5599 if (TLABStats) {
5600 // increment number of slow_allocations
5601 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5602 }
5603 jmp(try_eden);
5604
5605 bind(discard_tlab);
5606 if (TLABStats) {
5607 // increment number of refills
5608 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5609 // accumulate wastage -- t1 is amount free in tlab
5610 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5611 }
5612
5613 // if tlab is currently allocated (top or end != null) then
5614 // fill [top, end + alignment_reserve) with array object
5615 testptr(top, top);
5616 jcc(Assembler::zero, do_refill);
5617
5618 // set up the mark word
5619 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5620 // set the length to the remaining space
5621 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5622 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5623 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5624 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5625 // set klass to intArrayKlass
5626 // dubious reloc why not an oop reloc?
5627 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5628 // store klass last. concurrent gcs assumes klass length is valid if
5629 // klass field is not null.
5630 store_klass(top, t1);
5631
5632 movptr(t1, top);
5633 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5634 incr_allocated_bytes(thread_reg, t1, 0);
5635
5636 // refill the tlab with an eden allocation
5637 bind(do_refill);
5638 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5639 shlptr(t1, LogHeapWordSize);
5640 // allocate new tlab, address returned in top
5641 eden_allocate(top, t1, 0, t2, slow_case);
5642
5643 // Check that t1 was preserved in eden_allocate.
5644 #ifdef ASSERT
5645 if (UseTLAB) {
5646 Label ok;
5647 Register tsize = rsi;
5648 assert_different_registers(tsize, thread_reg, t1);
5649 push(tsize);
5650 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5651 shlptr(tsize, LogHeapWordSize);
5652 cmpptr(t1, tsize);
5653 jcc(Assembler::equal, ok);
5654 STOP("assert(t1 != tlab size)");
5655 should_not_reach_here();
5656
5657 bind(ok);
5658 pop(tsize);
5659 }
5660 #endif
5661 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5662 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5663 addptr(top, t1);
5664 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5665 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5666
5667 if (ZeroTLAB) {
5668 // This is a fast TLAB refill, therefore the GC is not notified of it.
5669 // So compiled code must fill the new TLAB with zeroes.
5670 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5671 zero_memory(top, t1, 0, t2);
5672 }
5673
5674 verify_tlab();
5675 jmp(retry);
5676
5677 return thread_reg; // for use by caller
5678 }
5679
5680 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5681 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5682 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5683 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5684 Label done;
5685
5686 testptr(length_in_bytes, length_in_bytes);
5687 jcc(Assembler::zero, done);
5688
5689 // initialize topmost word, divide index by 2, check if odd and test if zero
5690 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5691 #ifdef ASSERT
5692 {
5693 Label L;
5694 testptr(length_in_bytes, BytesPerWord - 1);
5695 jcc(Assembler::zero, L);
5696 stop("length must be a multiple of BytesPerWord");
5697 bind(L);
5698 }
5699 #endif
5700 Register index = length_in_bytes;
5701 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5702 if (UseIncDec) {
5703 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5704 } else {
5705 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5706 shrptr(index, 1);
5707 }
5708 #ifndef _LP64
5709 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5710 {
5711 Label even;
5712 // note: if index was a multiple of 8, then it cannot
5713 // be 0 now otherwise it must have been 0 before
5714 // => if it is even, we don't need to check for 0 again
5715 jcc(Assembler::carryClear, even);
5716 // clear topmost word (no jump would be needed if conditional assignment worked here)
5717 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5718 // index could be 0 now, must check again
5719 jcc(Assembler::zero, done);
5720 bind(even);
5721 }
5722 #endif // !_LP64
5723 // initialize remaining object fields: index is a multiple of 2 now
5724 {
5725 Label loop;
5726 bind(loop);
5727 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5728 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5729 decrement(index);
5730 jcc(Assembler::notZero, loop);
5731 }
5732
5733 bind(done);
5734 }
5735
5736 void MacroAssembler::incr_allocated_bytes(Register thread,
5737 Register var_size_in_bytes,
5738 int con_size_in_bytes,
5739 Register t1) {
5740 if (!thread->is_valid()) {
5741 #ifdef _LP64
5742 thread = r15_thread;
5743 #else
5744 assert(t1->is_valid(), "need temp reg");
5745 thread = t1;
5746 get_thread(thread);
5747 #endif
5748 }
5749
5750 #ifdef _LP64
5751 if (var_size_in_bytes->is_valid()) {
5752 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5753 } else {
5754 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5755 }
5756 #else
5757 if (var_size_in_bytes->is_valid()) {
5758 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5759 } else {
5760 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5761 }
5762 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5763 #endif
5764 }
5765
5766 // Look up the method for a megamorphic invokeinterface call.
5767 // The target method is determined by <intf_klass, itable_index>.
5768 // The receiver klass is in recv_klass.
5769 // On success, the result will be in method_result, and execution falls through.
5770 // On failure, execution transfers to the given label.
5771 void MacroAssembler::lookup_interface_method(Register recv_klass,
5772 Register intf_klass,
5773 RegisterOrConstant itable_index,
5774 Register method_result,
5775 Register scan_temp,
5776 Label& L_no_such_interface) {
5777 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5778 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5779 "caller must use same register for non-constant itable index as for method");
5780
5781 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5782 int vtable_base = in_bytes(Klass::vtable_start_offset());
5783 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5784 int scan_step = itableOffsetEntry::size() * wordSize;
5785 int vte_size = vtableEntry::size_in_bytes();
5786 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5787 assert(vte_size == wordSize, "else adjust times_vte_scale");
5788
5789 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5790
5791 // %%% Could store the aligned, prescaled offset in the klassoop.
5792 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5793
5794 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5795 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5796 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5797
5798 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5799 // if (scan->interface() == intf) {
5800 // result = (klass + scan->offset() + itable_index);
5801 // }
5802 // }
5803 Label search, found_method;
5804
5805 for (int peel = 1; peel >= 0; peel--) {
5806 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5807 cmpptr(intf_klass, method_result);
5808
5809 if (peel) {
5810 jccb(Assembler::equal, found_method);
5811 } else {
5812 jccb(Assembler::notEqual, search);
5813 // (invert the test to fall through to found_method...)
5814 }
5815
5816 if (!peel) break;
5817
5818 bind(search);
5819
5820 // Check that the previous entry is non-null. A null entry means that
5821 // the receiver class doesn't implement the interface, and wasn't the
5822 // same as when the caller was compiled.
5823 testptr(method_result, method_result);
5824 jcc(Assembler::zero, L_no_such_interface);
5825 addptr(scan_temp, scan_step);
5826 }
5827
5828 bind(found_method);
5829
5830 // Got a hit.
5831 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5832 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5833 }
5834
5835
5836 // virtual method calling
5837 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5838 RegisterOrConstant vtable_index,
5839 Register method_result) {
5840 const int base = in_bytes(Klass::vtable_start_offset());
5841 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5842 Address vtable_entry_addr(recv_klass,
5843 vtable_index, Address::times_ptr,
5844 base + vtableEntry::method_offset_in_bytes());
5845 movptr(method_result, vtable_entry_addr);
5846 }
5847
5848
5849 void MacroAssembler::check_klass_subtype(Register sub_klass,
5850 Register super_klass,
5851 Register temp_reg,
5852 Label& L_success) {
5853 Label L_failure;
5854 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5855 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5856 bind(L_failure);
5857 }
5858
5859
5860 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5861 Register super_klass,
5862 Register temp_reg,
5863 Label* L_success,
5864 Label* L_failure,
5865 Label* L_slow_path,
5866 RegisterOrConstant super_check_offset) {
5867 assert_different_registers(sub_klass, super_klass, temp_reg);
5868 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5869 if (super_check_offset.is_register()) {
5870 assert_different_registers(sub_klass, super_klass,
5871 super_check_offset.as_register());
5872 } else if (must_load_sco) {
5873 assert(temp_reg != noreg, "supply either a temp or a register offset");
5874 }
5875
5876 Label L_fallthrough;
5877 int label_nulls = 0;
5878 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5879 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5880 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5881 assert(label_nulls <= 1, "at most one NULL in the batch");
5882
5883 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5884 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5885 Address super_check_offset_addr(super_klass, sco_offset);
5886
5887 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5888 // range of a jccb. If this routine grows larger, reconsider at
5889 // least some of these.
5890 #define local_jcc(assembler_cond, label) \
5891 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5892 else jcc( assembler_cond, label) /*omit semi*/
5893
5894 // Hacked jmp, which may only be used just before L_fallthrough.
5895 #define final_jmp(label) \
5896 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5897 else jmp(label) /*omit semi*/
5898
5899 // If the pointers are equal, we are done (e.g., String[] elements).
5900 // This self-check enables sharing of secondary supertype arrays among
5901 // non-primary types such as array-of-interface. Otherwise, each such
5902 // type would need its own customized SSA.
5903 // We move this check to the front of the fast path because many
5904 // type checks are in fact trivially successful in this manner,
5905 // so we get a nicely predicted branch right at the start of the check.
5906 cmpptr(sub_klass, super_klass);
5907 local_jcc(Assembler::equal, *L_success);
5908
5909 // Check the supertype display:
5910 if (must_load_sco) {
5911 // Positive movl does right thing on LP64.
5912 movl(temp_reg, super_check_offset_addr);
5913 super_check_offset = RegisterOrConstant(temp_reg);
5914 }
5915 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5916 cmpptr(super_klass, super_check_addr); // load displayed supertype
5917
5918 // This check has worked decisively for primary supers.
5919 // Secondary supers are sought in the super_cache ('super_cache_addr').
5920 // (Secondary supers are interfaces and very deeply nested subtypes.)
5921 // This works in the same check above because of a tricky aliasing
5922 // between the super_cache and the primary super display elements.
5923 // (The 'super_check_addr' can address either, as the case requires.)
5924 // Note that the cache is updated below if it does not help us find
5925 // what we need immediately.
5926 // So if it was a primary super, we can just fail immediately.
5927 // Otherwise, it's the slow path for us (no success at this point).
5928
5929 if (super_check_offset.is_register()) {
5930 local_jcc(Assembler::equal, *L_success);
5931 cmpl(super_check_offset.as_register(), sc_offset);
5932 if (L_failure == &L_fallthrough) {
5933 local_jcc(Assembler::equal, *L_slow_path);
5934 } else {
5935 local_jcc(Assembler::notEqual, *L_failure);
5936 final_jmp(*L_slow_path);
5937 }
5938 } else if (super_check_offset.as_constant() == sc_offset) {
5939 // Need a slow path; fast failure is impossible.
5940 if (L_slow_path == &L_fallthrough) {
5941 local_jcc(Assembler::equal, *L_success);
5942 } else {
5943 local_jcc(Assembler::notEqual, *L_slow_path);
5944 final_jmp(*L_success);
5945 }
5946 } else {
5947 // No slow path; it's a fast decision.
5948 if (L_failure == &L_fallthrough) {
5949 local_jcc(Assembler::equal, *L_success);
5950 } else {
5951 local_jcc(Assembler::notEqual, *L_failure);
5952 final_jmp(*L_success);
5953 }
5954 }
5955
5956 bind(L_fallthrough);
5957
5958 #undef local_jcc
5959 #undef final_jmp
5960 }
5961
5962
5963 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5964 Register super_klass,
5965 Register temp_reg,
5966 Register temp2_reg,
5967 Label* L_success,
5968 Label* L_failure,
5969 bool set_cond_codes) {
5970 assert_different_registers(sub_klass, super_klass, temp_reg);
5971 if (temp2_reg != noreg)
5972 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5973 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5974
5975 Label L_fallthrough;
5976 int label_nulls = 0;
5977 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5978 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5979 assert(label_nulls <= 1, "at most one NULL in the batch");
5980
5981 // a couple of useful fields in sub_klass:
5982 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5983 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5984 Address secondary_supers_addr(sub_klass, ss_offset);
5985 Address super_cache_addr( sub_klass, sc_offset);
5986
5987 // Do a linear scan of the secondary super-klass chain.
5988 // This code is rarely used, so simplicity is a virtue here.
5989 // The repne_scan instruction uses fixed registers, which we must spill.
5990 // Don't worry too much about pre-existing connections with the input regs.
5991
5992 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5993 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5994
5995 // Get super_klass value into rax (even if it was in rdi or rcx).
5996 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5997 if (super_klass != rax || UseCompressedOops) {
5998 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5999 mov(rax, super_klass);
6000 }
6001 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
6002 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
6003
6004 #ifndef PRODUCT
6005 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
6006 ExternalAddress pst_counter_addr((address) pst_counter);
6007 NOT_LP64( incrementl(pst_counter_addr) );
6008 LP64_ONLY( lea(rcx, pst_counter_addr) );
6009 LP64_ONLY( incrementl(Address(rcx, 0)) );
6010 #endif //PRODUCT
6011
6012 // We will consult the secondary-super array.
6013 movptr(rdi, secondary_supers_addr);
6014 // Load the array length. (Positive movl does right thing on LP64.)
6015 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
6016 // Skip to start of data.
6017 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
6018
6019 // Scan RCX words at [RDI] for an occurrence of RAX.
6020 // Set NZ/Z based on last compare.
6021 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
6022 // not change flags (only scas instruction which is repeated sets flags).
6023 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
6024
6025 testptr(rax,rax); // Set Z = 0
6026 repne_scan();
6027
6028 // Unspill the temp. registers:
6029 if (pushed_rdi) pop(rdi);
6030 if (pushed_rcx) pop(rcx);
6031 if (pushed_rax) pop(rax);
6032
6033 if (set_cond_codes) {
6034 // Special hack for the AD files: rdi is guaranteed non-zero.
6035 assert(!pushed_rdi, "rdi must be left non-NULL");
6036 // Also, the condition codes are properly set Z/NZ on succeed/failure.
6037 }
6038
6039 if (L_failure == &L_fallthrough)
6040 jccb(Assembler::notEqual, *L_failure);
6041 else jcc(Assembler::notEqual, *L_failure);
6042
6043 // Success. Cache the super we found and proceed in triumph.
6044 movptr(super_cache_addr, super_klass);
6045
6046 if (L_success != &L_fallthrough) {
6047 jmp(*L_success);
6048 }
6049
6050 #undef IS_A_TEMP
6051
6052 bind(L_fallthrough);
6053 }
6054
6055
6056 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
6057 if (VM_Version::supports_cmov()) {
6058 cmovl(cc, dst, src);
6059 } else {
6060 Label L;
6061 jccb(negate_condition(cc), L);
6062 movl(dst, src);
6063 bind(L);
6064 }
6065 }
6066
6067 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6068 if (VM_Version::supports_cmov()) {
6069 cmovl(cc, dst, src);
6070 } else {
6071 Label L;
6072 jccb(negate_condition(cc), L);
6073 movl(dst, src);
6074 bind(L);
6075 }
6076 }
6077
6078 void MacroAssembler::verify_oop(Register reg, const char* s) {
6079 if (!VerifyOops) return;
6080
6081 // Pass register number to verify_oop_subroutine
6082 const char* b = NULL;
6083 {
6084 ResourceMark rm;
6085 stringStream ss;
6086 ss.print("verify_oop: %s: %s", reg->name(), s);
6087 b = code_string(ss.as_string());
6088 }
6089 BLOCK_COMMENT("verify_oop {");
6090 #ifdef _LP64
6091 push(rscratch1); // save r10, trashed by movptr()
6092 #endif
6093 push(rax); // save rax,
6094 push(reg); // pass register argument
6095 ExternalAddress buffer((address) b);
6096 // avoid using pushptr, as it modifies scratch registers
6097 // and our contract is not to modify anything
6098 movptr(rax, buffer.addr());
6099 push(rax);
6100 // call indirectly to solve generation ordering problem
6101 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6102 call(rax);
6103 // Caller pops the arguments (oop, message) and restores rax, r10
6104 BLOCK_COMMENT("} verify_oop");
6105 }
6106
6107
6108 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6109 Register tmp,
6110 int offset) {
6111 intptr_t value = *delayed_value_addr;
6112 if (value != 0)
6113 return RegisterOrConstant(value + offset);
6114
6115 // load indirectly to solve generation ordering problem
6116 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6117
6118 #ifdef ASSERT
6119 { Label L;
6120 testptr(tmp, tmp);
6121 if (WizardMode) {
6122 const char* buf = NULL;
6123 {
6124 ResourceMark rm;
6125 stringStream ss;
6126 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6127 buf = code_string(ss.as_string());
6128 }
6129 jcc(Assembler::notZero, L);
6130 STOP(buf);
6131 } else {
6132 jccb(Assembler::notZero, L);
6133 hlt();
6134 }
6135 bind(L);
6136 }
6137 #endif
6138
6139 if (offset != 0)
6140 addptr(tmp, offset);
6141
6142 return RegisterOrConstant(tmp);
6143 }
6144
6145
6146 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6147 int extra_slot_offset) {
6148 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6149 int stackElementSize = Interpreter::stackElementSize;
6150 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6151 #ifdef ASSERT
6152 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6153 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6154 #endif
6155 Register scale_reg = noreg;
6156 Address::ScaleFactor scale_factor = Address::no_scale;
6157 if (arg_slot.is_constant()) {
6158 offset += arg_slot.as_constant() * stackElementSize;
6159 } else {
6160 scale_reg = arg_slot.as_register();
6161 scale_factor = Address::times(stackElementSize);
6162 }
6163 offset += wordSize; // return PC is on stack
6164 return Address(rsp, scale_reg, scale_factor, offset);
6165 }
6166
6167
6168 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6169 if (!VerifyOops) return;
6170
6171 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6172 // Pass register number to verify_oop_subroutine
6173 const char* b = NULL;
6174 {
6175 ResourceMark rm;
6176 stringStream ss;
6177 ss.print("verify_oop_addr: %s", s);
6178 b = code_string(ss.as_string());
6179 }
6180 #ifdef _LP64
6181 push(rscratch1); // save r10, trashed by movptr()
6182 #endif
6183 push(rax); // save rax,
6184 // addr may contain rsp so we will have to adjust it based on the push
6185 // we just did (and on 64 bit we do two pushes)
6186 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6187 // stores rax into addr which is backwards of what was intended.
6188 if (addr.uses(rsp)) {
6189 lea(rax, addr);
6190 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6191 } else {
6192 pushptr(addr);
6193 }
6194
6195 ExternalAddress buffer((address) b);
6196 // pass msg argument
6197 // avoid using pushptr, as it modifies scratch registers
6198 // and our contract is not to modify anything
6199 movptr(rax, buffer.addr());
6200 push(rax);
6201
6202 // call indirectly to solve generation ordering problem
6203 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6204 call(rax);
6205 // Caller pops the arguments (addr, message) and restores rax, r10.
6206 }
6207
6208 void MacroAssembler::verify_tlab() {
6209 #ifdef ASSERT
6210 if (UseTLAB && VerifyOops) {
6211 Label next, ok;
6212 Register t1 = rsi;
6213 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6214
6215 push(t1);
6216 NOT_LP64(push(thread_reg));
6217 NOT_LP64(get_thread(thread_reg));
6218
6219 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6220 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6221 jcc(Assembler::aboveEqual, next);
6222 STOP("assert(top >= start)");
6223 should_not_reach_here();
6224
6225 bind(next);
6226 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6227 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6228 jcc(Assembler::aboveEqual, ok);
6229 STOP("assert(top <= end)");
6230 should_not_reach_here();
6231
6232 bind(ok);
6233 NOT_LP64(pop(thread_reg));
6234 pop(t1);
6235 }
6236 #endif
6237 }
6238
6239 class ControlWord {
6240 public:
6241 int32_t _value;
6242
6243 int rounding_control() const { return (_value >> 10) & 3 ; }
6244 int precision_control() const { return (_value >> 8) & 3 ; }
6245 bool precision() const { return ((_value >> 5) & 1) != 0; }
6246 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6247 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6248 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6249 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6250 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6251
6252 void print() const {
6253 // rounding control
6254 const char* rc;
6255 switch (rounding_control()) {
6256 case 0: rc = "round near"; break;
6257 case 1: rc = "round down"; break;
6258 case 2: rc = "round up "; break;
6259 case 3: rc = "chop "; break;
6260 };
6261 // precision control
6262 const char* pc;
6263 switch (precision_control()) {
6264 case 0: pc = "24 bits "; break;
6265 case 1: pc = "reserved"; break;
6266 case 2: pc = "53 bits "; break;
6267 case 3: pc = "64 bits "; break;
6268 };
6269 // flags
6270 char f[9];
6271 f[0] = ' ';
6272 f[1] = ' ';
6273 f[2] = (precision ()) ? 'P' : 'p';
6274 f[3] = (underflow ()) ? 'U' : 'u';
6275 f[4] = (overflow ()) ? 'O' : 'o';
6276 f[5] = (zero_divide ()) ? 'Z' : 'z';
6277 f[6] = (denormalized()) ? 'D' : 'd';
6278 f[7] = (invalid ()) ? 'I' : 'i';
6279 f[8] = '\x0';
6280 // output
6281 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6282 }
6283
6284 };
6285
6286 class StatusWord {
6287 public:
6288 int32_t _value;
6289
6290 bool busy() const { return ((_value >> 15) & 1) != 0; }
6291 bool C3() const { return ((_value >> 14) & 1) != 0; }
6292 bool C2() const { return ((_value >> 10) & 1) != 0; }
6293 bool C1() const { return ((_value >> 9) & 1) != 0; }
6294 bool C0() const { return ((_value >> 8) & 1) != 0; }
6295 int top() const { return (_value >> 11) & 7 ; }
6296 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6297 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6298 bool precision() const { return ((_value >> 5) & 1) != 0; }
6299 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6300 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6301 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6302 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6303 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6304
6305 void print() const {
6306 // condition codes
6307 char c[5];
6308 c[0] = (C3()) ? '3' : '-';
6309 c[1] = (C2()) ? '2' : '-';
6310 c[2] = (C1()) ? '1' : '-';
6311 c[3] = (C0()) ? '0' : '-';
6312 c[4] = '\x0';
6313 // flags
6314 char f[9];
6315 f[0] = (error_status()) ? 'E' : '-';
6316 f[1] = (stack_fault ()) ? 'S' : '-';
6317 f[2] = (precision ()) ? 'P' : '-';
6318 f[3] = (underflow ()) ? 'U' : '-';
6319 f[4] = (overflow ()) ? 'O' : '-';
6320 f[5] = (zero_divide ()) ? 'Z' : '-';
6321 f[6] = (denormalized()) ? 'D' : '-';
6322 f[7] = (invalid ()) ? 'I' : '-';
6323 f[8] = '\x0';
6324 // output
6325 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6326 }
6327
6328 };
6329
6330 class TagWord {
6331 public:
6332 int32_t _value;
6333
6334 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6335
6336 void print() const {
6337 printf("%04x", _value & 0xFFFF);
6338 }
6339
6340 };
6341
6342 class FPU_Register {
6343 public:
6344 int32_t _m0;
6345 int32_t _m1;
6346 int16_t _ex;
6347
6348 bool is_indefinite() const {
6349 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6350 }
6351
6352 void print() const {
6353 char sign = (_ex < 0) ? '-' : '+';
6354 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6355 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6356 };
6357
6358 };
6359
6360 class FPU_State {
6361 public:
6362 enum {
6363 register_size = 10,
6364 number_of_registers = 8,
6365 register_mask = 7
6366 };
6367
6368 ControlWord _control_word;
6369 StatusWord _status_word;
6370 TagWord _tag_word;
6371 int32_t _error_offset;
6372 int32_t _error_selector;
6373 int32_t _data_offset;
6374 int32_t _data_selector;
6375 int8_t _register[register_size * number_of_registers];
6376
6377 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6378 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6379
6380 const char* tag_as_string(int tag) const {
6381 switch (tag) {
6382 case 0: return "valid";
6383 case 1: return "zero";
6384 case 2: return "special";
6385 case 3: return "empty";
6386 }
6387 ShouldNotReachHere();
6388 return NULL;
6389 }
6390
6391 void print() const {
6392 // print computation registers
6393 { int t = _status_word.top();
6394 for (int i = 0; i < number_of_registers; i++) {
6395 int j = (i - t) & register_mask;
6396 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6397 st(j)->print();
6398 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6399 }
6400 }
6401 printf("\n");
6402 // print control registers
6403 printf("ctrl = "); _control_word.print(); printf("\n");
6404 printf("stat = "); _status_word .print(); printf("\n");
6405 printf("tags = "); _tag_word .print(); printf("\n");
6406 }
6407
6408 };
6409
6410 class Flag_Register {
6411 public:
6412 int32_t _value;
6413
6414 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6415 bool direction() const { return ((_value >> 10) & 1) != 0; }
6416 bool sign() const { return ((_value >> 7) & 1) != 0; }
6417 bool zero() const { return ((_value >> 6) & 1) != 0; }
6418 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6419 bool parity() const { return ((_value >> 2) & 1) != 0; }
6420 bool carry() const { return ((_value >> 0) & 1) != 0; }
6421
6422 void print() const {
6423 // flags
6424 char f[8];
6425 f[0] = (overflow ()) ? 'O' : '-';
6426 f[1] = (direction ()) ? 'D' : '-';
6427 f[2] = (sign ()) ? 'S' : '-';
6428 f[3] = (zero ()) ? 'Z' : '-';
6429 f[4] = (auxiliary_carry()) ? 'A' : '-';
6430 f[5] = (parity ()) ? 'P' : '-';
6431 f[6] = (carry ()) ? 'C' : '-';
6432 f[7] = '\x0';
6433 // output
6434 printf("%08x flags = %s", _value, f);
6435 }
6436
6437 };
6438
6439 class IU_Register {
6440 public:
6441 int32_t _value;
6442
6443 void print() const {
6444 printf("%08x %11d", _value, _value);
6445 }
6446
6447 };
6448
6449 class IU_State {
6450 public:
6451 Flag_Register _eflags;
6452 IU_Register _rdi;
6453 IU_Register _rsi;
6454 IU_Register _rbp;
6455 IU_Register _rsp;
6456 IU_Register _rbx;
6457 IU_Register _rdx;
6458 IU_Register _rcx;
6459 IU_Register _rax;
6460
6461 void print() const {
6462 // computation registers
6463 printf("rax, = "); _rax.print(); printf("\n");
6464 printf("rbx, = "); _rbx.print(); printf("\n");
6465 printf("rcx = "); _rcx.print(); printf("\n");
6466 printf("rdx = "); _rdx.print(); printf("\n");
6467 printf("rdi = "); _rdi.print(); printf("\n");
6468 printf("rsi = "); _rsi.print(); printf("\n");
6469 printf("rbp, = "); _rbp.print(); printf("\n");
6470 printf("rsp = "); _rsp.print(); printf("\n");
6471 printf("\n");
6472 // control registers
6473 printf("flgs = "); _eflags.print(); printf("\n");
6474 }
6475 };
6476
6477
6478 class CPU_State {
6479 public:
6480 FPU_State _fpu_state;
6481 IU_State _iu_state;
6482
6483 void print() const {
6484 printf("--------------------------------------------------\n");
6485 _iu_state .print();
6486 printf("\n");
6487 _fpu_state.print();
6488 printf("--------------------------------------------------\n");
6489 }
6490
6491 };
6492
6493
6494 static void _print_CPU_state(CPU_State* state) {
6495 state->print();
6496 };
6497
6498
6499 void MacroAssembler::print_CPU_state() {
6500 push_CPU_state();
6501 push(rsp); // pass CPU state
6502 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6503 addptr(rsp, wordSize); // discard argument
6504 pop_CPU_state();
6505 }
6506
6507
6508 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6509 static int counter = 0;
6510 FPU_State* fs = &state->_fpu_state;
6511 counter++;
6512 // For leaf calls, only verify that the top few elements remain empty.
6513 // We only need 1 empty at the top for C2 code.
6514 if( stack_depth < 0 ) {
6515 if( fs->tag_for_st(7) != 3 ) {
6516 printf("FPR7 not empty\n");
6517 state->print();
6518 assert(false, "error");
6519 return false;
6520 }
6521 return true; // All other stack states do not matter
6522 }
6523
6524 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6525 "bad FPU control word");
6526
6527 // compute stack depth
6528 int i = 0;
6529 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6530 int d = i;
6531 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6532 // verify findings
6533 if (i != FPU_State::number_of_registers) {
6534 // stack not contiguous
6535 printf("%s: stack not contiguous at ST%d\n", s, i);
6536 state->print();
6537 assert(false, "error");
6538 return false;
6539 }
6540 // check if computed stack depth corresponds to expected stack depth
6541 if (stack_depth < 0) {
6542 // expected stack depth is -stack_depth or less
6543 if (d > -stack_depth) {
6544 // too many elements on the stack
6545 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6546 state->print();
6547 assert(false, "error");
6548 return false;
6549 }
6550 } else {
6551 // expected stack depth is stack_depth
6552 if (d != stack_depth) {
6553 // wrong stack depth
6554 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6555 state->print();
6556 assert(false, "error");
6557 return false;
6558 }
6559 }
6560 // everything is cool
6561 return true;
6562 }
6563
6564
6565 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6566 if (!VerifyFPU) return;
6567 push_CPU_state();
6568 push(rsp); // pass CPU state
6569 ExternalAddress msg((address) s);
6570 // pass message string s
6571 pushptr(msg.addr());
6572 push(stack_depth); // pass stack depth
6573 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6574 addptr(rsp, 3 * wordSize); // discard arguments
6575 // check for error
6576 { Label L;
6577 testl(rax, rax);
6578 jcc(Assembler::notZero, L);
6579 int3(); // break if error condition
6580 bind(L);
6581 }
6582 pop_CPU_state();
6583 }
6584
6585 void MacroAssembler::restore_cpu_control_state_after_jni() {
6586 // Either restore the MXCSR register after returning from the JNI Call
6587 // or verify that it wasn't changed (with -Xcheck:jni flag).
6588 if (VM_Version::supports_sse()) {
6589 if (RestoreMXCSROnJNICalls) {
6590 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6591 } else if (CheckJNICalls) {
6592 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6593 }
6594 }
6595 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6596 vzeroupper();
6597
6598 #ifndef _LP64
6599 // Either restore the x87 floating pointer control word after returning
6600 // from the JNI call or verify that it wasn't changed.
6601 if (CheckJNICalls) {
6602 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6603 }
6604 #endif // _LP64
6605 }
6606
6607 void MacroAssembler::load_mirror(Register mirror, Register method) {
6608 // get mirror
6609 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6610 movptr(mirror, Address(method, Method::const_offset()));
6611 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6612 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6613 movptr(mirror, Address(mirror, mirror_offset));
6614 }
6615
6616 void MacroAssembler::load_klass(Register dst, Register src) {
6617 #ifdef _LP64
6618 if (UseCompressedClassPointers) {
6619 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6620 decode_klass_not_null(dst);
6621 } else
6622 #endif
6623 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6624 }
6625
6626 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6627 load_klass(dst, src);
6628 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6629 }
6630
6631 void MacroAssembler::store_klass(Register dst, Register src) {
6632 #ifdef _LP64
6633 if (UseCompressedClassPointers) {
6634 encode_klass_not_null(src);
6635 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6636 } else
6637 #endif
6638 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6639 }
6640
6641 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6642 #ifdef _LP64
6643 // FIXME: Must change all places where we try to load the klass.
6644 if (UseCompressedOops) {
6645 movl(dst, src);
6646 decode_heap_oop(dst);
6647 } else
6648 #endif
6649 movptr(dst, src);
6650 }
6651
6652 // Doesn't do verfication, generates fixed size code
6653 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6654 #ifdef _LP64
6655 if (UseCompressedOops) {
6656 movl(dst, src);
6657 decode_heap_oop_not_null(dst);
6658 } else
6659 #endif
6660 movptr(dst, src);
6661 }
6662
6663 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6664 #ifdef _LP64
6665 if (UseCompressedOops) {
6666 assert(!dst.uses(src), "not enough registers");
6667 encode_heap_oop(src);
6668 movl(dst, src);
6669 } else
6670 #endif
6671 movptr(dst, src);
6672 }
6673
6674 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6675 assert_different_registers(src1, tmp);
6676 #ifdef _LP64
6677 if (UseCompressedOops) {
6678 bool did_push = false;
6679 if (tmp == noreg) {
6680 tmp = rax;
6681 push(tmp);
6682 did_push = true;
6683 assert(!src2.uses(rsp), "can't push");
6684 }
6685 load_heap_oop(tmp, src2);
6686 cmpptr(src1, tmp);
6687 if (did_push) pop(tmp);
6688 } else
6689 #endif
6690 cmpptr(src1, src2);
6691 }
6692
6693 // Used for storing NULLs.
6694 void MacroAssembler::store_heap_oop_null(Address dst) {
6695 #ifdef _LP64
6696 if (UseCompressedOops) {
6697 movl(dst, (int32_t)NULL_WORD);
6698 } else {
6699 movslq(dst, (int32_t)NULL_WORD);
6700 }
6701 #else
6702 movl(dst, (int32_t)NULL_WORD);
6703 #endif
6704 }
6705
6706 #ifdef _LP64
6707 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6708 if (UseCompressedClassPointers) {
6709 // Store to klass gap in destination
6710 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6711 }
6712 }
6713
6714 #ifdef ASSERT
6715 void MacroAssembler::verify_heapbase(const char* msg) {
6716 assert (UseCompressedOops, "should be compressed");
6717 assert (Universe::heap() != NULL, "java heap should be initialized");
6718 if (CheckCompressedOops) {
6719 Label ok;
6720 push(rscratch1); // cmpptr trashes rscratch1
6721 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6722 jcc(Assembler::equal, ok);
6723 STOP(msg);
6724 bind(ok);
6725 pop(rscratch1);
6726 }
6727 }
6728 #endif
6729
6730 // Algorithm must match oop.inline.hpp encode_heap_oop.
6731 void MacroAssembler::encode_heap_oop(Register r) {
6732 #ifdef ASSERT
6733 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6734 #endif
6735 verify_oop(r, "broken oop in encode_heap_oop");
6736 if (Universe::narrow_oop_base() == NULL) {
6737 if (Universe::narrow_oop_shift() != 0) {
6738 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6739 shrq(r, LogMinObjAlignmentInBytes);
6740 }
6741 return;
6742 }
6743 testq(r, r);
6744 cmovq(Assembler::equal, r, r12_heapbase);
6745 subq(r, r12_heapbase);
6746 shrq(r, LogMinObjAlignmentInBytes);
6747 }
6748
6749 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6750 #ifdef ASSERT
6751 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6752 if (CheckCompressedOops) {
6753 Label ok;
6754 testq(r, r);
6755 jcc(Assembler::notEqual, ok);
6756 STOP("null oop passed to encode_heap_oop_not_null");
6757 bind(ok);
6758 }
6759 #endif
6760 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6761 if (Universe::narrow_oop_base() != NULL) {
6762 subq(r, r12_heapbase);
6763 }
6764 if (Universe::narrow_oop_shift() != 0) {
6765 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6766 shrq(r, LogMinObjAlignmentInBytes);
6767 }
6768 }
6769
6770 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6771 #ifdef ASSERT
6772 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6773 if (CheckCompressedOops) {
6774 Label ok;
6775 testq(src, src);
6776 jcc(Assembler::notEqual, ok);
6777 STOP("null oop passed to encode_heap_oop_not_null2");
6778 bind(ok);
6779 }
6780 #endif
6781 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6782 if (dst != src) {
6783 movq(dst, src);
6784 }
6785 if (Universe::narrow_oop_base() != NULL) {
6786 subq(dst, r12_heapbase);
6787 }
6788 if (Universe::narrow_oop_shift() != 0) {
6789 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6790 shrq(dst, LogMinObjAlignmentInBytes);
6791 }
6792 }
6793
6794 void MacroAssembler::decode_heap_oop(Register r) {
6795 #ifdef ASSERT
6796 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6797 #endif
6798 if (Universe::narrow_oop_base() == NULL) {
6799 if (Universe::narrow_oop_shift() != 0) {
6800 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6801 shlq(r, LogMinObjAlignmentInBytes);
6802 }
6803 } else {
6804 Label done;
6805 shlq(r, LogMinObjAlignmentInBytes);
6806 jccb(Assembler::equal, done);
6807 addq(r, r12_heapbase);
6808 bind(done);
6809 }
6810 verify_oop(r, "broken oop in decode_heap_oop");
6811 }
6812
6813 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6814 // Note: it will change flags
6815 assert (UseCompressedOops, "should only be used for compressed headers");
6816 assert (Universe::heap() != NULL, "java heap should be initialized");
6817 // Cannot assert, unverified entry point counts instructions (see .ad file)
6818 // vtableStubs also counts instructions in pd_code_size_limit.
6819 // Also do not verify_oop as this is called by verify_oop.
6820 if (Universe::narrow_oop_shift() != 0) {
6821 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6822 shlq(r, LogMinObjAlignmentInBytes);
6823 if (Universe::narrow_oop_base() != NULL) {
6824 addq(r, r12_heapbase);
6825 }
6826 } else {
6827 assert (Universe::narrow_oop_base() == NULL, "sanity");
6828 }
6829 }
6830
6831 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6832 // Note: it will change flags
6833 assert (UseCompressedOops, "should only be used for compressed headers");
6834 assert (Universe::heap() != NULL, "java heap should be initialized");
6835 // Cannot assert, unverified entry point counts instructions (see .ad file)
6836 // vtableStubs also counts instructions in pd_code_size_limit.
6837 // Also do not verify_oop as this is called by verify_oop.
6838 if (Universe::narrow_oop_shift() != 0) {
6839 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6840 if (LogMinObjAlignmentInBytes == Address::times_8) {
6841 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6842 } else {
6843 if (dst != src) {
6844 movq(dst, src);
6845 }
6846 shlq(dst, LogMinObjAlignmentInBytes);
6847 if (Universe::narrow_oop_base() != NULL) {
6848 addq(dst, r12_heapbase);
6849 }
6850 }
6851 } else {
6852 assert (Universe::narrow_oop_base() == NULL, "sanity");
6853 if (dst != src) {
6854 movq(dst, src);
6855 }
6856 }
6857 }
6858
6859 void MacroAssembler::encode_klass_not_null(Register r) {
6860 if (Universe::narrow_klass_base() != NULL) {
6861 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6862 assert(r != r12_heapbase, "Encoding a klass in r12");
6863 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6864 subq(r, r12_heapbase);
6865 }
6866 if (Universe::narrow_klass_shift() != 0) {
6867 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6868 shrq(r, LogKlassAlignmentInBytes);
6869 }
6870 if (Universe::narrow_klass_base() != NULL) {
6871 reinit_heapbase();
6872 }
6873 }
6874
6875 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6876 if (dst == src) {
6877 encode_klass_not_null(src);
6878 } else {
6879 if (Universe::narrow_klass_base() != NULL) {
6880 mov64(dst, (int64_t)Universe::narrow_klass_base());
6881 negq(dst);
6882 addq(dst, src);
6883 } else {
6884 movptr(dst, src);
6885 }
6886 if (Universe::narrow_klass_shift() != 0) {
6887 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6888 shrq(dst, LogKlassAlignmentInBytes);
6889 }
6890 }
6891 }
6892
6893 // Function instr_size_for_decode_klass_not_null() counts the instructions
6894 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6895 // when (Universe::heap() != NULL). Hence, if the instructions they
6896 // generate change, then this method needs to be updated.
6897 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6898 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6899 if (Universe::narrow_klass_base() != NULL) {
6900 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6901 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6902 } else {
6903 // longest load decode klass function, mov64, leaq
6904 return 16;
6905 }
6906 }
6907
6908 // !!! If the instructions that get generated here change then function
6909 // instr_size_for_decode_klass_not_null() needs to get updated.
6910 void MacroAssembler::decode_klass_not_null(Register r) {
6911 // Note: it will change flags
6912 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6913 assert(r != r12_heapbase, "Decoding a klass in r12");
6914 // Cannot assert, unverified entry point counts instructions (see .ad file)
6915 // vtableStubs also counts instructions in pd_code_size_limit.
6916 // Also do not verify_oop as this is called by verify_oop.
6917 if (Universe::narrow_klass_shift() != 0) {
6918 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6919 shlq(r, LogKlassAlignmentInBytes);
6920 }
6921 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6922 if (Universe::narrow_klass_base() != NULL) {
6923 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6924 addq(r, r12_heapbase);
6925 reinit_heapbase();
6926 }
6927 }
6928
6929 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6930 // Note: it will change flags
6931 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6932 if (dst == src) {
6933 decode_klass_not_null(dst);
6934 } else {
6935 // Cannot assert, unverified entry point counts instructions (see .ad file)
6936 // vtableStubs also counts instructions in pd_code_size_limit.
6937 // Also do not verify_oop as this is called by verify_oop.
6938 mov64(dst, (int64_t)Universe::narrow_klass_base());
6939 if (Universe::narrow_klass_shift() != 0) {
6940 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6941 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6942 leaq(dst, Address(dst, src, Address::times_8, 0));
6943 } else {
6944 addq(dst, src);
6945 }
6946 }
6947 }
6948
6949 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6950 assert (UseCompressedOops, "should only be used for compressed headers");
6951 assert (Universe::heap() != NULL, "java heap should be initialized");
6952 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6953 int oop_index = oop_recorder()->find_index(obj);
6954 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6955 mov_narrow_oop(dst, oop_index, rspec);
6956 }
6957
6958 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6959 assert (UseCompressedOops, "should only be used for compressed headers");
6960 assert (Universe::heap() != NULL, "java heap should be initialized");
6961 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6962 int oop_index = oop_recorder()->find_index(obj);
6963 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6964 mov_narrow_oop(dst, oop_index, rspec);
6965 }
6966
6967 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6968 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6969 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6970 int klass_index = oop_recorder()->find_index(k);
6971 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6972 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6973 }
6974
6975 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6976 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6977 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6978 int klass_index = oop_recorder()->find_index(k);
6979 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6980 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6981 }
6982
6983 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6984 assert (UseCompressedOops, "should only be used for compressed headers");
6985 assert (Universe::heap() != NULL, "java heap should be initialized");
6986 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6987 int oop_index = oop_recorder()->find_index(obj);
6988 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6989 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6990 }
6991
6992 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6993 assert (UseCompressedOops, "should only be used for compressed headers");
6994 assert (Universe::heap() != NULL, "java heap should be initialized");
6995 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6996 int oop_index = oop_recorder()->find_index(obj);
6997 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6998 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6999 }
7000
7001 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
7002 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7003 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7004 int klass_index = oop_recorder()->find_index(k);
7005 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7006 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7007 }
7008
7009 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
7010 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7011 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7012 int klass_index = oop_recorder()->find_index(k);
7013 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7014 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7015 }
7016
7017 void MacroAssembler::reinit_heapbase() {
7018 if (UseCompressedOops || UseCompressedClassPointers) {
7019 if (Universe::heap() != NULL) {
7020 if (Universe::narrow_oop_base() == NULL) {
7021 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
7022 } else {
7023 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
7024 }
7025 } else {
7026 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
7027 }
7028 }
7029 }
7030
7031 #endif // _LP64
7032
7033
7034 // C2 compiled method's prolog code.
7035 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
7036
7037 // WARNING: Initial instruction MUST be 5 bytes or longer so that
7038 // NativeJump::patch_verified_entry will be able to patch out the entry
7039 // code safely. The push to verify stack depth is ok at 5 bytes,
7040 // the frame allocation can be either 3 or 6 bytes. So if we don't do
7041 // stack bang then we must use the 6 byte frame allocation even if
7042 // we have no frame. :-(
7043 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
7044
7045 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7046 // Remove word for return addr
7047 framesize -= wordSize;
7048 stack_bang_size -= wordSize;
7049
7050 // Calls to C2R adapters often do not accept exceptional returns.
7051 // We require that their callers must bang for them. But be careful, because
7052 // some VM calls (such as call site linkage) can use several kilobytes of
7053 // stack. But the stack safety zone should account for that.
7054 // See bugs 4446381, 4468289, 4497237.
7055 if (stack_bang_size > 0) {
7056 generate_stack_overflow_check(stack_bang_size);
7057
7058 // We always push rbp, so that on return to interpreter rbp, will be
7059 // restored correctly and we can correct the stack.
7060 push(rbp);
7061 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7062 if (PreserveFramePointer) {
7063 mov(rbp, rsp);
7064 }
7065 // Remove word for ebp
7066 framesize -= wordSize;
7067
7068 // Create frame
7069 if (framesize) {
7070 subptr(rsp, framesize);
7071 }
7072 } else {
7073 // Create frame (force generation of a 4 byte immediate value)
7074 subptr_imm32(rsp, framesize);
7075
7076 // Save RBP register now.
7077 framesize -= wordSize;
7078 movptr(Address(rsp, framesize), rbp);
7079 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7080 if (PreserveFramePointer) {
7081 movptr(rbp, rsp);
7082 if (framesize > 0) {
7083 addptr(rbp, framesize);
7084 }
7085 }
7086 }
7087
7088 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7089 framesize -= wordSize;
7090 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7091 }
7092
7093 #ifndef _LP64
7094 // If method sets FPU control word do it now
7095 if (fp_mode_24b) {
7096 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7097 }
7098 if (UseSSE >= 2 && VerifyFPU) {
7099 verify_FPU(0, "FPU stack must be clean on entry");
7100 }
7101 #endif
7102
7103 #ifdef ASSERT
7104 if (VerifyStackAtCalls) {
7105 Label L;
7106 push(rax);
7107 mov(rax, rsp);
7108 andptr(rax, StackAlignmentInBytes-1);
7109 cmpptr(rax, StackAlignmentInBytes-wordSize);
7110 pop(rax);
7111 jcc(Assembler::equal, L);
7112 STOP("Stack is not properly aligned!");
7113 bind(L);
7114 }
7115 #endif
7116
7117 }
7118
7119 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7120 // cnt - number of qwords (8-byte words).
7121 // base - start address, qword aligned.
7122 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7123 assert(base==rdi, "base register must be edi for rep stos");
7124 assert(tmp==rax, "tmp register must be eax for rep stos");
7125 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7126 assert(InitArrayShortSize % BytesPerLong == 0,
7127 "InitArrayShortSize should be the multiple of BytesPerLong");
7128
7129 Label DONE;
7130
7131 xorptr(tmp, tmp);
7132
7133 if (!is_large) {
7134 Label LOOP, LONG;
7135 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7136 jccb(Assembler::greater, LONG);
7137
7138 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7139
7140 decrement(cnt);
7141 jccb(Assembler::negative, DONE); // Zero length
7142
7143 // Use individual pointer-sized stores for small counts:
7144 BIND(LOOP);
7145 movptr(Address(base, cnt, Address::times_ptr), tmp);
7146 decrement(cnt);
7147 jccb(Assembler::greaterEqual, LOOP);
7148 jmpb(DONE);
7149
7150 BIND(LONG);
7151 }
7152
7153 // Use longer rep-prefixed ops for non-small counts:
7154 if (UseFastStosb) {
7155 shlptr(cnt, 3); // convert to number of bytes
7156 rep_stosb();
7157 } else {
7158 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7159 rep_stos();
7160 }
7161
7162 BIND(DONE);
7163 }
7164
7165 #ifdef COMPILER2
7166
7167 // IndexOf for constant substrings with size >= 8 chars
7168 // which don't need to be loaded through stack.
7169 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7170 Register cnt1, Register cnt2,
7171 int int_cnt2, Register result,
7172 XMMRegister vec, Register tmp,
7173 int ae) {
7174 ShortBranchVerifier sbv(this);
7175 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7176 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7177
7178 // This method uses the pcmpestri instruction with bound registers
7179 // inputs:
7180 // xmm - substring
7181 // rax - substring length (elements count)
7182 // mem - scanned string
7183 // rdx - string length (elements count)
7184 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7185 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7186 // outputs:
7187 // rcx - matched index in string
7188 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7189 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7190 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7191 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7192 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7193
7194 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7195 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7196 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7197
7198 // Note, inline_string_indexOf() generates checks:
7199 // if (substr.count > string.count) return -1;
7200 // if (substr.count == 0) return 0;
7201 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7202
7203 // Load substring.
7204 if (ae == StrIntrinsicNode::UL) {
7205 pmovzxbw(vec, Address(str2, 0));
7206 } else {
7207 movdqu(vec, Address(str2, 0));
7208 }
7209 movl(cnt2, int_cnt2);
7210 movptr(result, str1); // string addr
7211
7212 if (int_cnt2 > stride) {
7213 jmpb(SCAN_TO_SUBSTR);
7214
7215 // Reload substr for rescan, this code
7216 // is executed only for large substrings (> 8 chars)
7217 bind(RELOAD_SUBSTR);
7218 if (ae == StrIntrinsicNode::UL) {
7219 pmovzxbw(vec, Address(str2, 0));
7220 } else {
7221 movdqu(vec, Address(str2, 0));
7222 }
7223 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7224
7225 bind(RELOAD_STR);
7226 // We came here after the beginning of the substring was
7227 // matched but the rest of it was not so we need to search
7228 // again. Start from the next element after the previous match.
7229
7230 // cnt2 is number of substring reminding elements and
7231 // cnt1 is number of string reminding elements when cmp failed.
7232 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7233 subl(cnt1, cnt2);
7234 addl(cnt1, int_cnt2);
7235 movl(cnt2, int_cnt2); // Now restore cnt2
7236
7237 decrementl(cnt1); // Shift to next element
7238 cmpl(cnt1, cnt2);
7239 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7240
7241 addptr(result, (1<<scale1));
7242
7243 } // (int_cnt2 > 8)
7244
7245 // Scan string for start of substr in 16-byte vectors
7246 bind(SCAN_TO_SUBSTR);
7247 pcmpestri(vec, Address(result, 0), mode);
7248 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7249 subl(cnt1, stride);
7250 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7251 cmpl(cnt1, cnt2);
7252 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7253 addptr(result, 16);
7254 jmpb(SCAN_TO_SUBSTR);
7255
7256 // Found a potential substr
7257 bind(FOUND_CANDIDATE);
7258 // Matched whole vector if first element matched (tmp(rcx) == 0).
7259 if (int_cnt2 == stride) {
7260 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7261 } else { // int_cnt2 > 8
7262 jccb(Assembler::overflow, FOUND_SUBSTR);
7263 }
7264 // After pcmpestri tmp(rcx) contains matched element index
7265 // Compute start addr of substr
7266 lea(result, Address(result, tmp, scale1));
7267
7268 // Make sure string is still long enough
7269 subl(cnt1, tmp);
7270 cmpl(cnt1, cnt2);
7271 if (int_cnt2 == stride) {
7272 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7273 } else { // int_cnt2 > 8
7274 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7275 }
7276 // Left less then substring.
7277
7278 bind(RET_NOT_FOUND);
7279 movl(result, -1);
7280 jmp(EXIT);
7281
7282 if (int_cnt2 > stride) {
7283 // This code is optimized for the case when whole substring
7284 // is matched if its head is matched.
7285 bind(MATCH_SUBSTR_HEAD);
7286 pcmpestri(vec, Address(result, 0), mode);
7287 // Reload only string if does not match
7288 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7289
7290 Label CONT_SCAN_SUBSTR;
7291 // Compare the rest of substring (> 8 chars).
7292 bind(FOUND_SUBSTR);
7293 // First 8 chars are already matched.
7294 negptr(cnt2);
7295 addptr(cnt2, stride);
7296
7297 bind(SCAN_SUBSTR);
7298 subl(cnt1, stride);
7299 cmpl(cnt2, -stride); // Do not read beyond substring
7300 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7301 // Back-up strings to avoid reading beyond substring:
7302 // cnt1 = cnt1 - cnt2 + 8
7303 addl(cnt1, cnt2); // cnt2 is negative
7304 addl(cnt1, stride);
7305 movl(cnt2, stride); negptr(cnt2);
7306 bind(CONT_SCAN_SUBSTR);
7307 if (int_cnt2 < (int)G) {
7308 int tail_off1 = int_cnt2<<scale1;
7309 int tail_off2 = int_cnt2<<scale2;
7310 if (ae == StrIntrinsicNode::UL) {
7311 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7312 } else {
7313 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7314 }
7315 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7316 } else {
7317 // calculate index in register to avoid integer overflow (int_cnt2*2)
7318 movl(tmp, int_cnt2);
7319 addptr(tmp, cnt2);
7320 if (ae == StrIntrinsicNode::UL) {
7321 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7322 } else {
7323 movdqu(vec, Address(str2, tmp, scale2, 0));
7324 }
7325 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7326 }
7327 // Need to reload strings pointers if not matched whole vector
7328 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7329 addptr(cnt2, stride);
7330 jcc(Assembler::negative, SCAN_SUBSTR);
7331 // Fall through if found full substring
7332
7333 } // (int_cnt2 > 8)
7334
7335 bind(RET_FOUND);
7336 // Found result if we matched full small substring.
7337 // Compute substr offset
7338 subptr(result, str1);
7339 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7340 shrl(result, 1); // index
7341 }
7342 bind(EXIT);
7343
7344 } // string_indexofC8
7345
7346 // Small strings are loaded through stack if they cross page boundary.
7347 void MacroAssembler::string_indexof(Register str1, Register str2,
7348 Register cnt1, Register cnt2,
7349 int int_cnt2, Register result,
7350 XMMRegister vec, Register tmp,
7351 int ae) {
7352 ShortBranchVerifier sbv(this);
7353 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7354 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7355
7356 //
7357 // int_cnt2 is length of small (< 8 chars) constant substring
7358 // or (-1) for non constant substring in which case its length
7359 // is in cnt2 register.
7360 //
7361 // Note, inline_string_indexOf() generates checks:
7362 // if (substr.count > string.count) return -1;
7363 // if (substr.count == 0) return 0;
7364 //
7365 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7366 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7367 // This method uses the pcmpestri instruction with bound registers
7368 // inputs:
7369 // xmm - substring
7370 // rax - substring length (elements count)
7371 // mem - scanned string
7372 // rdx - string length (elements count)
7373 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7374 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7375 // outputs:
7376 // rcx - matched index in string
7377 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7378 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7379 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7380 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7381
7382 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7383 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7384 FOUND_CANDIDATE;
7385
7386 { //========================================================
7387 // We don't know where these strings are located
7388 // and we can't read beyond them. Load them through stack.
7389 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7390
7391 movptr(tmp, rsp); // save old SP
7392
7393 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7394 if (int_cnt2 == (1>>scale2)) { // One byte
7395 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7396 load_unsigned_byte(result, Address(str2, 0));
7397 movdl(vec, result); // move 32 bits
7398 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7399 // Not enough header space in 32-bit VM: 12+3 = 15.
7400 movl(result, Address(str2, -1));
7401 shrl(result, 8);
7402 movdl(vec, result); // move 32 bits
7403 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7404 load_unsigned_short(result, Address(str2, 0));
7405 movdl(vec, result); // move 32 bits
7406 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7407 movdl(vec, Address(str2, 0)); // move 32 bits
7408 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7409 movq(vec, Address(str2, 0)); // move 64 bits
7410 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7411 // Array header size is 12 bytes in 32-bit VM
7412 // + 6 bytes for 3 chars == 18 bytes,
7413 // enough space to load vec and shift.
7414 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7415 if (ae == StrIntrinsicNode::UL) {
7416 int tail_off = int_cnt2-8;
7417 pmovzxbw(vec, Address(str2, tail_off));
7418 psrldq(vec, -2*tail_off);
7419 }
7420 else {
7421 int tail_off = int_cnt2*(1<<scale2);
7422 movdqu(vec, Address(str2, tail_off-16));
7423 psrldq(vec, 16-tail_off);
7424 }
7425 }
7426 } else { // not constant substring
7427 cmpl(cnt2, stride);
7428 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7429
7430 // We can read beyond string if srt+16 does not cross page boundary
7431 // since heaps are aligned and mapped by pages.
7432 assert(os::vm_page_size() < (int)G, "default page should be small");
7433 movl(result, str2); // We need only low 32 bits
7434 andl(result, (os::vm_page_size()-1));
7435 cmpl(result, (os::vm_page_size()-16));
7436 jccb(Assembler::belowEqual, CHECK_STR);
7437
7438 // Move small strings to stack to allow load 16 bytes into vec.
7439 subptr(rsp, 16);
7440 int stk_offset = wordSize-(1<<scale2);
7441 push(cnt2);
7442
7443 bind(COPY_SUBSTR);
7444 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7445 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7446 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7447 } else if (ae == StrIntrinsicNode::UU) {
7448 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7449 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7450 }
7451 decrement(cnt2);
7452 jccb(Assembler::notZero, COPY_SUBSTR);
7453
7454 pop(cnt2);
7455 movptr(str2, rsp); // New substring address
7456 } // non constant
7457
7458 bind(CHECK_STR);
7459 cmpl(cnt1, stride);
7460 jccb(Assembler::aboveEqual, BIG_STRINGS);
7461
7462 // Check cross page boundary.
7463 movl(result, str1); // We need only low 32 bits
7464 andl(result, (os::vm_page_size()-1));
7465 cmpl(result, (os::vm_page_size()-16));
7466 jccb(Assembler::belowEqual, BIG_STRINGS);
7467
7468 subptr(rsp, 16);
7469 int stk_offset = -(1<<scale1);
7470 if (int_cnt2 < 0) { // not constant
7471 push(cnt2);
7472 stk_offset += wordSize;
7473 }
7474 movl(cnt2, cnt1);
7475
7476 bind(COPY_STR);
7477 if (ae == StrIntrinsicNode::LL) {
7478 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7479 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7480 } else {
7481 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7482 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7483 }
7484 decrement(cnt2);
7485 jccb(Assembler::notZero, COPY_STR);
7486
7487 if (int_cnt2 < 0) { // not constant
7488 pop(cnt2);
7489 }
7490 movptr(str1, rsp); // New string address
7491
7492 bind(BIG_STRINGS);
7493 // Load substring.
7494 if (int_cnt2 < 0) { // -1
7495 if (ae == StrIntrinsicNode::UL) {
7496 pmovzxbw(vec, Address(str2, 0));
7497 } else {
7498 movdqu(vec, Address(str2, 0));
7499 }
7500 push(cnt2); // substr count
7501 push(str2); // substr addr
7502 push(str1); // string addr
7503 } else {
7504 // Small (< 8 chars) constant substrings are loaded already.
7505 movl(cnt2, int_cnt2);
7506 }
7507 push(tmp); // original SP
7508
7509 } // Finished loading
7510
7511 //========================================================
7512 // Start search
7513 //
7514
7515 movptr(result, str1); // string addr
7516
7517 if (int_cnt2 < 0) { // Only for non constant substring
7518 jmpb(SCAN_TO_SUBSTR);
7519
7520 // SP saved at sp+0
7521 // String saved at sp+1*wordSize
7522 // Substr saved at sp+2*wordSize
7523 // Substr count saved at sp+3*wordSize
7524
7525 // Reload substr for rescan, this code
7526 // is executed only for large substrings (> 8 chars)
7527 bind(RELOAD_SUBSTR);
7528 movptr(str2, Address(rsp, 2*wordSize));
7529 movl(cnt2, Address(rsp, 3*wordSize));
7530 if (ae == StrIntrinsicNode::UL) {
7531 pmovzxbw(vec, Address(str2, 0));
7532 } else {
7533 movdqu(vec, Address(str2, 0));
7534 }
7535 // We came here after the beginning of the substring was
7536 // matched but the rest of it was not so we need to search
7537 // again. Start from the next element after the previous match.
7538 subptr(str1, result); // Restore counter
7539 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7540 shrl(str1, 1);
7541 }
7542 addl(cnt1, str1);
7543 decrementl(cnt1); // Shift to next element
7544 cmpl(cnt1, cnt2);
7545 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7546
7547 addptr(result, (1<<scale1));
7548 } // non constant
7549
7550 // Scan string for start of substr in 16-byte vectors
7551 bind(SCAN_TO_SUBSTR);
7552 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7553 pcmpestri(vec, Address(result, 0), mode);
7554 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7555 subl(cnt1, stride);
7556 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7557 cmpl(cnt1, cnt2);
7558 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7559 addptr(result, 16);
7560
7561 bind(ADJUST_STR);
7562 cmpl(cnt1, stride); // Do not read beyond string
7563 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7564 // Back-up string to avoid reading beyond string.
7565 lea(result, Address(result, cnt1, scale1, -16));
7566 movl(cnt1, stride);
7567 jmpb(SCAN_TO_SUBSTR);
7568
7569 // Found a potential substr
7570 bind(FOUND_CANDIDATE);
7571 // After pcmpestri tmp(rcx) contains matched element index
7572
7573 // Make sure string is still long enough
7574 subl(cnt1, tmp);
7575 cmpl(cnt1, cnt2);
7576 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7577 // Left less then substring.
7578
7579 bind(RET_NOT_FOUND);
7580 movl(result, -1);
7581 jmpb(CLEANUP);
7582
7583 bind(FOUND_SUBSTR);
7584 // Compute start addr of substr
7585 lea(result, Address(result, tmp, scale1));
7586 if (int_cnt2 > 0) { // Constant substring
7587 // Repeat search for small substring (< 8 chars)
7588 // from new point without reloading substring.
7589 // Have to check that we don't read beyond string.
7590 cmpl(tmp, stride-int_cnt2);
7591 jccb(Assembler::greater, ADJUST_STR);
7592 // Fall through if matched whole substring.
7593 } else { // non constant
7594 assert(int_cnt2 == -1, "should be != 0");
7595
7596 addl(tmp, cnt2);
7597 // Found result if we matched whole substring.
7598 cmpl(tmp, stride);
7599 jccb(Assembler::lessEqual, RET_FOUND);
7600
7601 // Repeat search for small substring (<= 8 chars)
7602 // from new point 'str1' without reloading substring.
7603 cmpl(cnt2, stride);
7604 // Have to check that we don't read beyond string.
7605 jccb(Assembler::lessEqual, ADJUST_STR);
7606
7607 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7608 // Compare the rest of substring (> 8 chars).
7609 movptr(str1, result);
7610
7611 cmpl(tmp, cnt2);
7612 // First 8 chars are already matched.
7613 jccb(Assembler::equal, CHECK_NEXT);
7614
7615 bind(SCAN_SUBSTR);
7616 pcmpestri(vec, Address(str1, 0), mode);
7617 // Need to reload strings pointers if not matched whole vector
7618 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7619
7620 bind(CHECK_NEXT);
7621 subl(cnt2, stride);
7622 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7623 addptr(str1, 16);
7624 if (ae == StrIntrinsicNode::UL) {
7625 addptr(str2, 8);
7626 } else {
7627 addptr(str2, 16);
7628 }
7629 subl(cnt1, stride);
7630 cmpl(cnt2, stride); // Do not read beyond substring
7631 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7632 // Back-up strings to avoid reading beyond substring.
7633
7634 if (ae == StrIntrinsicNode::UL) {
7635 lea(str2, Address(str2, cnt2, scale2, -8));
7636 lea(str1, Address(str1, cnt2, scale1, -16));
7637 } else {
7638 lea(str2, Address(str2, cnt2, scale2, -16));
7639 lea(str1, Address(str1, cnt2, scale1, -16));
7640 }
7641 subl(cnt1, cnt2);
7642 movl(cnt2, stride);
7643 addl(cnt1, stride);
7644 bind(CONT_SCAN_SUBSTR);
7645 if (ae == StrIntrinsicNode::UL) {
7646 pmovzxbw(vec, Address(str2, 0));
7647 } else {
7648 movdqu(vec, Address(str2, 0));
7649 }
7650 jmp(SCAN_SUBSTR);
7651
7652 bind(RET_FOUND_LONG);
7653 movptr(str1, Address(rsp, wordSize));
7654 } // non constant
7655
7656 bind(RET_FOUND);
7657 // Compute substr offset
7658 subptr(result, str1);
7659 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7660 shrl(result, 1); // index
7661 }
7662 bind(CLEANUP);
7663 pop(rsp); // restore SP
7664
7665 } // string_indexof
7666
7667 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7668 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7669 ShortBranchVerifier sbv(this);
7670 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7671
7672 int stride = 8;
7673
7674 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7675 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7676 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7677 FOUND_SEQ_CHAR, DONE_LABEL;
7678
7679 movptr(result, str1);
7680 if (UseAVX >= 2) {
7681 cmpl(cnt1, stride);
7682 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7683 cmpl(cnt1, 2*stride);
7684 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7685 movdl(vec1, ch);
7686 vpbroadcastw(vec1, vec1);
7687 vpxor(vec2, vec2);
7688 movl(tmp, cnt1);
7689 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7690 andl(cnt1,0x0000000F); //tail count (in chars)
7691
7692 bind(SCAN_TO_16_CHAR_LOOP);
7693 vmovdqu(vec3, Address(result, 0));
7694 vpcmpeqw(vec3, vec3, vec1, 1);
7695 vptest(vec2, vec3);
7696 jcc(Assembler::carryClear, FOUND_CHAR);
7697 addptr(result, 32);
7698 subl(tmp, 2*stride);
7699 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7700 jmp(SCAN_TO_8_CHAR);
7701 bind(SCAN_TO_8_CHAR_INIT);
7702 movdl(vec1, ch);
7703 pshuflw(vec1, vec1, 0x00);
7704 pshufd(vec1, vec1, 0);
7705 pxor(vec2, vec2);
7706 }
7707 bind(SCAN_TO_8_CHAR);
7708 cmpl(cnt1, stride);
7709 if (UseAVX >= 2) {
7710 jcc(Assembler::less, SCAN_TO_CHAR);
7711 } else {
7712 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7713 movdl(vec1, ch);
7714 pshuflw(vec1, vec1, 0x00);
7715 pshufd(vec1, vec1, 0);
7716 pxor(vec2, vec2);
7717 }
7718 movl(tmp, cnt1);
7719 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7720 andl(cnt1,0x00000007); //tail count (in chars)
7721
7722 bind(SCAN_TO_8_CHAR_LOOP);
7723 movdqu(vec3, Address(result, 0));
7724 pcmpeqw(vec3, vec1);
7725 ptest(vec2, vec3);
7726 jcc(Assembler::carryClear, FOUND_CHAR);
7727 addptr(result, 16);
7728 subl(tmp, stride);
7729 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7730 bind(SCAN_TO_CHAR);
7731 testl(cnt1, cnt1);
7732 jcc(Assembler::zero, RET_NOT_FOUND);
7733 bind(SCAN_TO_CHAR_LOOP);
7734 load_unsigned_short(tmp, Address(result, 0));
7735 cmpl(ch, tmp);
7736 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7737 addptr(result, 2);
7738 subl(cnt1, 1);
7739 jccb(Assembler::zero, RET_NOT_FOUND);
7740 jmp(SCAN_TO_CHAR_LOOP);
7741
7742 bind(RET_NOT_FOUND);
7743 movl(result, -1);
7744 jmpb(DONE_LABEL);
7745
7746 bind(FOUND_CHAR);
7747 if (UseAVX >= 2) {
7748 vpmovmskb(tmp, vec3);
7749 } else {
7750 pmovmskb(tmp, vec3);
7751 }
7752 bsfl(ch, tmp);
7753 addl(result, ch);
7754
7755 bind(FOUND_SEQ_CHAR);
7756 subptr(result, str1);
7757 shrl(result, 1);
7758
7759 bind(DONE_LABEL);
7760 } // string_indexof_char
7761
7762 // helper function for string_compare
7763 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7764 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7765 Address::ScaleFactor scale2, Register index, int ae) {
7766 if (ae == StrIntrinsicNode::LL) {
7767 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7768 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7769 } else if (ae == StrIntrinsicNode::UU) {
7770 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7771 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7772 } else {
7773 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7774 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7775 }
7776 }
7777
7778 // Compare strings, used for char[] and byte[].
7779 void MacroAssembler::string_compare(Register str1, Register str2,
7780 Register cnt1, Register cnt2, Register result,
7781 XMMRegister vec1, int ae) {
7782 ShortBranchVerifier sbv(this);
7783 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7784 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7785 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7786 int stride2x2 = 0x40;
7787 Address::ScaleFactor scale = Address::no_scale;
7788 Address::ScaleFactor scale1 = Address::no_scale;
7789 Address::ScaleFactor scale2 = Address::no_scale;
7790
7791 if (ae != StrIntrinsicNode::LL) {
7792 stride2x2 = 0x20;
7793 }
7794
7795 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7796 shrl(cnt2, 1);
7797 }
7798 // Compute the minimum of the string lengths and the
7799 // difference of the string lengths (stack).
7800 // Do the conditional move stuff
7801 movl(result, cnt1);
7802 subl(cnt1, cnt2);
7803 push(cnt1);
7804 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7805
7806 // Is the minimum length zero?
7807 testl(cnt2, cnt2);
7808 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7809 if (ae == StrIntrinsicNode::LL) {
7810 // Load first bytes
7811 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7812 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7813 } else if (ae == StrIntrinsicNode::UU) {
7814 // Load first characters
7815 load_unsigned_short(result, Address(str1, 0));
7816 load_unsigned_short(cnt1, Address(str2, 0));
7817 } else {
7818 load_unsigned_byte(result, Address(str1, 0));
7819 load_unsigned_short(cnt1, Address(str2, 0));
7820 }
7821 subl(result, cnt1);
7822 jcc(Assembler::notZero, POP_LABEL);
7823
7824 if (ae == StrIntrinsicNode::UU) {
7825 // Divide length by 2 to get number of chars
7826 shrl(cnt2, 1);
7827 }
7828 cmpl(cnt2, 1);
7829 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7830
7831 // Check if the strings start at the same location and setup scale and stride
7832 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7833 cmpptr(str1, str2);
7834 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7835 if (ae == StrIntrinsicNode::LL) {
7836 scale = Address::times_1;
7837 stride = 16;
7838 } else {
7839 scale = Address::times_2;
7840 stride = 8;
7841 }
7842 } else {
7843 scale1 = Address::times_1;
7844 scale2 = Address::times_2;
7845 // scale not used
7846 stride = 8;
7847 }
7848
7849 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7850 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7851 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7852 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7853 Label COMPARE_TAIL_LONG;
7854 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7855
7856 int pcmpmask = 0x19;
7857 if (ae == StrIntrinsicNode::LL) {
7858 pcmpmask &= ~0x01;
7859 }
7860
7861 // Setup to compare 16-chars (32-bytes) vectors,
7862 // start from first character again because it has aligned address.
7863 if (ae == StrIntrinsicNode::LL) {
7864 stride2 = 32;
7865 } else {
7866 stride2 = 16;
7867 }
7868 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7869 adr_stride = stride << scale;
7870 } else {
7871 adr_stride1 = 8; //stride << scale1;
7872 adr_stride2 = 16; //stride << scale2;
7873 }
7874
7875 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7876 // rax and rdx are used by pcmpestri as elements counters
7877 movl(result, cnt2);
7878 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7879 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7880
7881 // fast path : compare first 2 8-char vectors.
7882 bind(COMPARE_16_CHARS);
7883 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7884 movdqu(vec1, Address(str1, 0));
7885 } else {
7886 pmovzxbw(vec1, Address(str1, 0));
7887 }
7888 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7889 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7890
7891 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7892 movdqu(vec1, Address(str1, adr_stride));
7893 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7894 } else {
7895 pmovzxbw(vec1, Address(str1, adr_stride1));
7896 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7897 }
7898 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7899 addl(cnt1, stride);
7900
7901 // Compare the characters at index in cnt1
7902 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7903 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7904 subl(result, cnt2);
7905 jmp(POP_LABEL);
7906
7907 // Setup the registers to start vector comparison loop
7908 bind(COMPARE_WIDE_VECTORS);
7909 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7910 lea(str1, Address(str1, result, scale));
7911 lea(str2, Address(str2, result, scale));
7912 } else {
7913 lea(str1, Address(str1, result, scale1));
7914 lea(str2, Address(str2, result, scale2));
7915 }
7916 subl(result, stride2);
7917 subl(cnt2, stride2);
7918 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7919 negptr(result);
7920
7921 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7922 bind(COMPARE_WIDE_VECTORS_LOOP);
7923
7924 #ifdef _LP64
7925 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7926 cmpl(cnt2, stride2x2);
7927 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7928 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7929 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7930
7931 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7932 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7933 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7934 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7935 } else {
7936 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7937 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7938 }
7939 kortestql(k7, k7);
7940 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7941 addptr(result, stride2x2); // update since we already compared at this addr
7942 subl(cnt2, stride2x2); // and sub the size too
7943 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7944
7945 vpxor(vec1, vec1);
7946 jmpb(COMPARE_WIDE_TAIL);
7947 }//if (VM_Version::supports_avx512vlbw())
7948 #endif // _LP64
7949
7950
7951 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7952 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7953 vmovdqu(vec1, Address(str1, result, scale));
7954 vpxor(vec1, Address(str2, result, scale));
7955 } else {
7956 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7957 vpxor(vec1, Address(str2, result, scale2));
7958 }
7959 vptest(vec1, vec1);
7960 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7961 addptr(result, stride2);
7962 subl(cnt2, stride2);
7963 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7964 // clean upper bits of YMM registers
7965 vpxor(vec1, vec1);
7966
7967 // compare wide vectors tail
7968 bind(COMPARE_WIDE_TAIL);
7969 testptr(result, result);
7970 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7971
7972 movl(result, stride2);
7973 movl(cnt2, result);
7974 negptr(result);
7975 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7976
7977 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7978 bind(VECTOR_NOT_EQUAL);
7979 // clean upper bits of YMM registers
7980 vpxor(vec1, vec1);
7981 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7982 lea(str1, Address(str1, result, scale));
7983 lea(str2, Address(str2, result, scale));
7984 } else {
7985 lea(str1, Address(str1, result, scale1));
7986 lea(str2, Address(str2, result, scale2));
7987 }
7988 jmp(COMPARE_16_CHARS);
7989
7990 // Compare tail chars, length between 1 to 15 chars
7991 bind(COMPARE_TAIL_LONG);
7992 movl(cnt2, result);
7993 cmpl(cnt2, stride);
7994 jcc(Assembler::less, COMPARE_SMALL_STR);
7995
7996 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7997 movdqu(vec1, Address(str1, 0));
7998 } else {
7999 pmovzxbw(vec1, Address(str1, 0));
8000 }
8001 pcmpestri(vec1, Address(str2, 0), pcmpmask);
8002 jcc(Assembler::below, COMPARE_INDEX_CHAR);
8003 subptr(cnt2, stride);
8004 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8005 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8006 lea(str1, Address(str1, result, scale));
8007 lea(str2, Address(str2, result, scale));
8008 } else {
8009 lea(str1, Address(str1, result, scale1));
8010 lea(str2, Address(str2, result, scale2));
8011 }
8012 negptr(cnt2);
8013 jmpb(WHILE_HEAD_LABEL);
8014
8015 bind(COMPARE_SMALL_STR);
8016 } else if (UseSSE42Intrinsics) {
8017 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8018 int pcmpmask = 0x19;
8019 // Setup to compare 8-char (16-byte) vectors,
8020 // start from first character again because it has aligned address.
8021 movl(result, cnt2);
8022 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
8023 if (ae == StrIntrinsicNode::LL) {
8024 pcmpmask &= ~0x01;
8025 }
8026 jcc(Assembler::zero, COMPARE_TAIL);
8027 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8028 lea(str1, Address(str1, result, scale));
8029 lea(str2, Address(str2, result, scale));
8030 } else {
8031 lea(str1, Address(str1, result, scale1));
8032 lea(str2, Address(str2, result, scale2));
8033 }
8034 negptr(result);
8035
8036 // pcmpestri
8037 // inputs:
8038 // vec1- substring
8039 // rax - negative string length (elements count)
8040 // mem - scanned string
8041 // rdx - string length (elements count)
8042 // pcmpmask - cmp mode: 11000 (string compare with negated result)
8043 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
8044 // outputs:
8045 // rcx - first mismatched element index
8046 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
8047
8048 bind(COMPARE_WIDE_VECTORS);
8049 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8050 movdqu(vec1, Address(str1, result, scale));
8051 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8052 } else {
8053 pmovzxbw(vec1, Address(str1, result, scale1));
8054 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8055 }
8056 // After pcmpestri cnt1(rcx) contains mismatched element index
8057
8058 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8059 addptr(result, stride);
8060 subptr(cnt2, stride);
8061 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8062
8063 // compare wide vectors tail
8064 testptr(result, result);
8065 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8066
8067 movl(cnt2, stride);
8068 movl(result, stride);
8069 negptr(result);
8070 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8071 movdqu(vec1, Address(str1, result, scale));
8072 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8073 } else {
8074 pmovzxbw(vec1, Address(str1, result, scale1));
8075 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8076 }
8077 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8078
8079 // Mismatched characters in the vectors
8080 bind(VECTOR_NOT_EQUAL);
8081 addptr(cnt1, result);
8082 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8083 subl(result, cnt2);
8084 jmpb(POP_LABEL);
8085
8086 bind(COMPARE_TAIL); // limit is zero
8087 movl(cnt2, result);
8088 // Fallthru to tail compare
8089 }
8090 // Shift str2 and str1 to the end of the arrays, negate min
8091 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8092 lea(str1, Address(str1, cnt2, scale));
8093 lea(str2, Address(str2, cnt2, scale));
8094 } else {
8095 lea(str1, Address(str1, cnt2, scale1));
8096 lea(str2, Address(str2, cnt2, scale2));
8097 }
8098 decrementl(cnt2); // first character was compared already
8099 negptr(cnt2);
8100
8101 // Compare the rest of the elements
8102 bind(WHILE_HEAD_LABEL);
8103 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8104 subl(result, cnt1);
8105 jccb(Assembler::notZero, POP_LABEL);
8106 increment(cnt2);
8107 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8108
8109 // Strings are equal up to min length. Return the length difference.
8110 bind(LENGTH_DIFF_LABEL);
8111 pop(result);
8112 if (ae == StrIntrinsicNode::UU) {
8113 // Divide diff by 2 to get number of chars
8114 sarl(result, 1);
8115 }
8116 jmpb(DONE_LABEL);
8117
8118 #ifdef _LP64
8119 if (VM_Version::supports_avx512vlbw()) {
8120
8121 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8122
8123 kmovql(cnt1, k7);
8124 notq(cnt1);
8125 bsfq(cnt2, cnt1);
8126 if (ae != StrIntrinsicNode::LL) {
8127 // Divide diff by 2 to get number of chars
8128 sarl(cnt2, 1);
8129 }
8130 addq(result, cnt2);
8131 if (ae == StrIntrinsicNode::LL) {
8132 load_unsigned_byte(cnt1, Address(str2, result));
8133 load_unsigned_byte(result, Address(str1, result));
8134 } else if (ae == StrIntrinsicNode::UU) {
8135 load_unsigned_short(cnt1, Address(str2, result, scale));
8136 load_unsigned_short(result, Address(str1, result, scale));
8137 } else {
8138 load_unsigned_short(cnt1, Address(str2, result, scale2));
8139 load_unsigned_byte(result, Address(str1, result, scale1));
8140 }
8141 subl(result, cnt1);
8142 jmpb(POP_LABEL);
8143 }//if (VM_Version::supports_avx512vlbw())
8144 #endif // _LP64
8145
8146 // Discard the stored length difference
8147 bind(POP_LABEL);
8148 pop(cnt1);
8149
8150 // That's it
8151 bind(DONE_LABEL);
8152 if(ae == StrIntrinsicNode::UL) {
8153 negl(result);
8154 }
8155
8156 }
8157
8158 // Search for Non-ASCII character (Negative byte value) in a byte array,
8159 // return true if it has any and false otherwise.
8160 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8161 // @HotSpotIntrinsicCandidate
8162 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8163 // for (int i = off; i < off + len; i++) {
8164 // if (ba[i] < 0) {
8165 // return true;
8166 // }
8167 // }
8168 // return false;
8169 // }
8170 void MacroAssembler::has_negatives(Register ary1, Register len,
8171 Register result, Register tmp1,
8172 XMMRegister vec1, XMMRegister vec2) {
8173 // rsi: byte array
8174 // rcx: len
8175 // rax: result
8176 ShortBranchVerifier sbv(this);
8177 assert_different_registers(ary1, len, result, tmp1);
8178 assert_different_registers(vec1, vec2);
8179 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8180
8181 // len == 0
8182 testl(len, len);
8183 jcc(Assembler::zero, FALSE_LABEL);
8184
8185 if ((UseAVX > 2) && // AVX512
8186 VM_Version::supports_avx512vlbw() &&
8187 VM_Version::supports_bmi2()) {
8188
8189 set_vector_masking(); // opening of the stub context for programming mask registers
8190
8191 Label test_64_loop, test_tail;
8192 Register tmp3_aliased = len;
8193
8194 movl(tmp1, len);
8195 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8196
8197 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8198 andl(len, ~(64 - 1)); // vector count (in chars)
8199 jccb(Assembler::zero, test_tail);
8200
8201 lea(ary1, Address(ary1, len, Address::times_1));
8202 negptr(len);
8203
8204 bind(test_64_loop);
8205 // Check whether our 64 elements of size byte contain negatives
8206 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8207 kortestql(k2, k2);
8208 jcc(Assembler::notZero, TRUE_LABEL);
8209
8210 addptr(len, 64);
8211 jccb(Assembler::notZero, test_64_loop);
8212
8213
8214 bind(test_tail);
8215 // bail out when there is nothing to be done
8216 testl(tmp1, -1);
8217 jcc(Assembler::zero, FALSE_LABEL);
8218
8219 // Save k1
8220 kmovql(k3, k1);
8221
8222 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8223 #ifdef _LP64
8224 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8225 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8226 notq(tmp3_aliased);
8227 kmovql(k1, tmp3_aliased);
8228 #else
8229 Label k_init;
8230 jmp(k_init);
8231
8232 // We could not read 64-bits from a general purpose register thus we move
8233 // data required to compose 64 1's to the instruction stream
8234 // We emit 64 byte wide series of elements from 0..63 which later on would
8235 // be used as a compare targets with tail count contained in tmp1 register.
8236 // Result would be a k1 register having tmp1 consecutive number or 1
8237 // counting from least significant bit.
8238 address tmp = pc();
8239 emit_int64(0x0706050403020100);
8240 emit_int64(0x0F0E0D0C0B0A0908);
8241 emit_int64(0x1716151413121110);
8242 emit_int64(0x1F1E1D1C1B1A1918);
8243 emit_int64(0x2726252423222120);
8244 emit_int64(0x2F2E2D2C2B2A2928);
8245 emit_int64(0x3736353433323130);
8246 emit_int64(0x3F3E3D3C3B3A3938);
8247
8248 bind(k_init);
8249 lea(len, InternalAddress(tmp));
8250 // create mask to test for negative byte inside a vector
8251 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8252 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8253
8254 #endif
8255 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8256 ktestq(k2, k1);
8257 // Restore k1
8258 kmovql(k1, k3);
8259 jcc(Assembler::notZero, TRUE_LABEL);
8260
8261 jmp(FALSE_LABEL);
8262
8263 clear_vector_masking(); // closing of the stub context for programming mask registers
8264 } else {
8265 movl(result, len); // copy
8266
8267 if (UseAVX == 2 && UseSSE >= 2) {
8268 // With AVX2, use 32-byte vector compare
8269 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8270
8271 // Compare 32-byte vectors
8272 andl(result, 0x0000001f); // tail count (in bytes)
8273 andl(len, 0xffffffe0); // vector count (in bytes)
8274 jccb(Assembler::zero, COMPARE_TAIL);
8275
8276 lea(ary1, Address(ary1, len, Address::times_1));
8277 negptr(len);
8278
8279 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8280 movdl(vec2, tmp1);
8281 vpbroadcastd(vec2, vec2);
8282
8283 bind(COMPARE_WIDE_VECTORS);
8284 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8285 vptest(vec1, vec2);
8286 jccb(Assembler::notZero, TRUE_LABEL);
8287 addptr(len, 32);
8288 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8289
8290 testl(result, result);
8291 jccb(Assembler::zero, FALSE_LABEL);
8292
8293 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8294 vptest(vec1, vec2);
8295 jccb(Assembler::notZero, TRUE_LABEL);
8296 jmpb(FALSE_LABEL);
8297
8298 bind(COMPARE_TAIL); // len is zero
8299 movl(len, result);
8300 // Fallthru to tail compare
8301 } else if (UseSSE42Intrinsics) {
8302 // With SSE4.2, use double quad vector compare
8303 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8304
8305 // Compare 16-byte vectors
8306 andl(result, 0x0000000f); // tail count (in bytes)
8307 andl(len, 0xfffffff0); // vector count (in bytes)
8308 jccb(Assembler::zero, COMPARE_TAIL);
8309
8310 lea(ary1, Address(ary1, len, Address::times_1));
8311 negptr(len);
8312
8313 movl(tmp1, 0x80808080);
8314 movdl(vec2, tmp1);
8315 pshufd(vec2, vec2, 0);
8316
8317 bind(COMPARE_WIDE_VECTORS);
8318 movdqu(vec1, Address(ary1, len, Address::times_1));
8319 ptest(vec1, vec2);
8320 jccb(Assembler::notZero, TRUE_LABEL);
8321 addptr(len, 16);
8322 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8323
8324 testl(result, result);
8325 jccb(Assembler::zero, FALSE_LABEL);
8326
8327 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8328 ptest(vec1, vec2);
8329 jccb(Assembler::notZero, TRUE_LABEL);
8330 jmpb(FALSE_LABEL);
8331
8332 bind(COMPARE_TAIL); // len is zero
8333 movl(len, result);
8334 // Fallthru to tail compare
8335 }
8336 }
8337 // Compare 4-byte vectors
8338 andl(len, 0xfffffffc); // vector count (in bytes)
8339 jccb(Assembler::zero, COMPARE_CHAR);
8340
8341 lea(ary1, Address(ary1, len, Address::times_1));
8342 negptr(len);
8343
8344 bind(COMPARE_VECTORS);
8345 movl(tmp1, Address(ary1, len, Address::times_1));
8346 andl(tmp1, 0x80808080);
8347 jccb(Assembler::notZero, TRUE_LABEL);
8348 addptr(len, 4);
8349 jcc(Assembler::notZero, COMPARE_VECTORS);
8350
8351 // Compare trailing char (final 2 bytes), if any
8352 bind(COMPARE_CHAR);
8353 testl(result, 0x2); // tail char
8354 jccb(Assembler::zero, COMPARE_BYTE);
8355 load_unsigned_short(tmp1, Address(ary1, 0));
8356 andl(tmp1, 0x00008080);
8357 jccb(Assembler::notZero, TRUE_LABEL);
8358 subptr(result, 2);
8359 lea(ary1, Address(ary1, 2));
8360
8361 bind(COMPARE_BYTE);
8362 testl(result, 0x1); // tail byte
8363 jccb(Assembler::zero, FALSE_LABEL);
8364 load_unsigned_byte(tmp1, Address(ary1, 0));
8365 andl(tmp1, 0x00000080);
8366 jccb(Assembler::notEqual, TRUE_LABEL);
8367 jmpb(FALSE_LABEL);
8368
8369 bind(TRUE_LABEL);
8370 movl(result, 1); // return true
8371 jmpb(DONE);
8372
8373 bind(FALSE_LABEL);
8374 xorl(result, result); // return false
8375
8376 // That's it
8377 bind(DONE);
8378 if (UseAVX >= 2 && UseSSE >= 2) {
8379 // clean upper bits of YMM registers
8380 vpxor(vec1, vec1);
8381 vpxor(vec2, vec2);
8382 }
8383 }
8384 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8385 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8386 Register limit, Register result, Register chr,
8387 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8388 ShortBranchVerifier sbv(this);
8389 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8390
8391 int length_offset = arrayOopDesc::length_offset_in_bytes();
8392 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8393
8394 if (is_array_equ) {
8395 // Check the input args
8396 cmpptr(ary1, ary2);
8397 jcc(Assembler::equal, TRUE_LABEL);
8398
8399 // Need additional checks for arrays_equals.
8400 testptr(ary1, ary1);
8401 jcc(Assembler::zero, FALSE_LABEL);
8402 testptr(ary2, ary2);
8403 jcc(Assembler::zero, FALSE_LABEL);
8404
8405 // Check the lengths
8406 movl(limit, Address(ary1, length_offset));
8407 cmpl(limit, Address(ary2, length_offset));
8408 jcc(Assembler::notEqual, FALSE_LABEL);
8409 }
8410
8411 // count == 0
8412 testl(limit, limit);
8413 jcc(Assembler::zero, TRUE_LABEL);
8414
8415 if (is_array_equ) {
8416 // Load array address
8417 lea(ary1, Address(ary1, base_offset));
8418 lea(ary2, Address(ary2, base_offset));
8419 }
8420
8421 if (is_array_equ && is_char) {
8422 // arrays_equals when used for char[].
8423 shll(limit, 1); // byte count != 0
8424 }
8425 movl(result, limit); // copy
8426
8427 if (UseAVX >= 2) {
8428 // With AVX2, use 32-byte vector compare
8429 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8430
8431 // Compare 32-byte vectors
8432 andl(result, 0x0000001f); // tail count (in bytes)
8433 andl(limit, 0xffffffe0); // vector count (in bytes)
8434 jcc(Assembler::zero, COMPARE_TAIL);
8435
8436 lea(ary1, Address(ary1, limit, Address::times_1));
8437 lea(ary2, Address(ary2, limit, Address::times_1));
8438 negptr(limit);
8439
8440 bind(COMPARE_WIDE_VECTORS);
8441
8442 #ifdef _LP64
8443 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8444 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8445
8446 cmpl(limit, -64);
8447 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8448
8449 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8450
8451 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8452 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8453 kortestql(k7, k7);
8454 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8455 addptr(limit, 64); // update since we already compared at this addr
8456 cmpl(limit, -64);
8457 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8458
8459 // At this point we may still need to compare -limit+result bytes.
8460 // We could execute the next two instruction and just continue via non-wide path:
8461 // cmpl(limit, 0);
8462 // jcc(Assembler::equal, COMPARE_TAIL); // true
8463 // But since we stopped at the points ary{1,2}+limit which are
8464 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8465 // (|limit| <= 32 and result < 32),
8466 // we may just compare the last 64 bytes.
8467 //
8468 addptr(result, -64); // it is safe, bc we just came from this area
8469 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8470 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8471 kortestql(k7, k7);
8472 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8473
8474 jmp(TRUE_LABEL);
8475
8476 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8477
8478 }//if (VM_Version::supports_avx512vlbw())
8479 #endif //_LP64
8480
8481 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8482 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8483 vpxor(vec1, vec2);
8484
8485 vptest(vec1, vec1);
8486 jcc(Assembler::notZero, FALSE_LABEL);
8487 addptr(limit, 32);
8488 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8489
8490 testl(result, result);
8491 jcc(Assembler::zero, TRUE_LABEL);
8492
8493 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8494 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8495 vpxor(vec1, vec2);
8496
8497 vptest(vec1, vec1);
8498 jccb(Assembler::notZero, FALSE_LABEL);
8499 jmpb(TRUE_LABEL);
8500
8501 bind(COMPARE_TAIL); // limit is zero
8502 movl(limit, result);
8503 // Fallthru to tail compare
8504 } else if (UseSSE42Intrinsics) {
8505 // With SSE4.2, use double quad vector compare
8506 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8507
8508 // Compare 16-byte vectors
8509 andl(result, 0x0000000f); // tail count (in bytes)
8510 andl(limit, 0xfffffff0); // vector count (in bytes)
8511 jcc(Assembler::zero, COMPARE_TAIL);
8512
8513 lea(ary1, Address(ary1, limit, Address::times_1));
8514 lea(ary2, Address(ary2, limit, Address::times_1));
8515 negptr(limit);
8516
8517 bind(COMPARE_WIDE_VECTORS);
8518 movdqu(vec1, Address(ary1, limit, Address::times_1));
8519 movdqu(vec2, Address(ary2, limit, Address::times_1));
8520 pxor(vec1, vec2);
8521
8522 ptest(vec1, vec1);
8523 jcc(Assembler::notZero, FALSE_LABEL);
8524 addptr(limit, 16);
8525 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8526
8527 testl(result, result);
8528 jcc(Assembler::zero, TRUE_LABEL);
8529
8530 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8531 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8532 pxor(vec1, vec2);
8533
8534 ptest(vec1, vec1);
8535 jccb(Assembler::notZero, FALSE_LABEL);
8536 jmpb(TRUE_LABEL);
8537
8538 bind(COMPARE_TAIL); // limit is zero
8539 movl(limit, result);
8540 // Fallthru to tail compare
8541 }
8542
8543 // Compare 4-byte vectors
8544 andl(limit, 0xfffffffc); // vector count (in bytes)
8545 jccb(Assembler::zero, COMPARE_CHAR);
8546
8547 lea(ary1, Address(ary1, limit, Address::times_1));
8548 lea(ary2, Address(ary2, limit, Address::times_1));
8549 negptr(limit);
8550
8551 bind(COMPARE_VECTORS);
8552 movl(chr, Address(ary1, limit, Address::times_1));
8553 cmpl(chr, Address(ary2, limit, Address::times_1));
8554 jccb(Assembler::notEqual, FALSE_LABEL);
8555 addptr(limit, 4);
8556 jcc(Assembler::notZero, COMPARE_VECTORS);
8557
8558 // Compare trailing char (final 2 bytes), if any
8559 bind(COMPARE_CHAR);
8560 testl(result, 0x2); // tail char
8561 jccb(Assembler::zero, COMPARE_BYTE);
8562 load_unsigned_short(chr, Address(ary1, 0));
8563 load_unsigned_short(limit, Address(ary2, 0));
8564 cmpl(chr, limit);
8565 jccb(Assembler::notEqual, FALSE_LABEL);
8566
8567 if (is_array_equ && is_char) {
8568 bind(COMPARE_BYTE);
8569 } else {
8570 lea(ary1, Address(ary1, 2));
8571 lea(ary2, Address(ary2, 2));
8572
8573 bind(COMPARE_BYTE);
8574 testl(result, 0x1); // tail byte
8575 jccb(Assembler::zero, TRUE_LABEL);
8576 load_unsigned_byte(chr, Address(ary1, 0));
8577 load_unsigned_byte(limit, Address(ary2, 0));
8578 cmpl(chr, limit);
8579 jccb(Assembler::notEqual, FALSE_LABEL);
8580 }
8581 bind(TRUE_LABEL);
8582 movl(result, 1); // return true
8583 jmpb(DONE);
8584
8585 bind(FALSE_LABEL);
8586 xorl(result, result); // return false
8587
8588 // That's it
8589 bind(DONE);
8590 if (UseAVX >= 2) {
8591 // clean upper bits of YMM registers
8592 vpxor(vec1, vec1);
8593 vpxor(vec2, vec2);
8594 }
8595 }
8596
8597 #endif
8598
8599 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8600 Register to, Register value, Register count,
8601 Register rtmp, XMMRegister xtmp) {
8602 ShortBranchVerifier sbv(this);
8603 assert_different_registers(to, value, count, rtmp);
8604 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8605 Label L_fill_2_bytes, L_fill_4_bytes;
8606
8607 int shift = -1;
8608 switch (t) {
8609 case T_BYTE:
8610 shift = 2;
8611 break;
8612 case T_SHORT:
8613 shift = 1;
8614 break;
8615 case T_INT:
8616 shift = 0;
8617 break;
8618 default: ShouldNotReachHere();
8619 }
8620
8621 if (t == T_BYTE) {
8622 andl(value, 0xff);
8623 movl(rtmp, value);
8624 shll(rtmp, 8);
8625 orl(value, rtmp);
8626 }
8627 if (t == T_SHORT) {
8628 andl(value, 0xffff);
8629 }
8630 if (t == T_BYTE || t == T_SHORT) {
8631 movl(rtmp, value);
8632 shll(rtmp, 16);
8633 orl(value, rtmp);
8634 }
8635
8636 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8637 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8638 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8639 // align source address at 4 bytes address boundary
8640 if (t == T_BYTE) {
8641 // One byte misalignment happens only for byte arrays
8642 testptr(to, 1);
8643 jccb(Assembler::zero, L_skip_align1);
8644 movb(Address(to, 0), value);
8645 increment(to);
8646 decrement(count);
8647 BIND(L_skip_align1);
8648 }
8649 // Two bytes misalignment happens only for byte and short (char) arrays
8650 testptr(to, 2);
8651 jccb(Assembler::zero, L_skip_align2);
8652 movw(Address(to, 0), value);
8653 addptr(to, 2);
8654 subl(count, 1<<(shift-1));
8655 BIND(L_skip_align2);
8656 }
8657 if (UseSSE < 2) {
8658 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8659 // Fill 32-byte chunks
8660 subl(count, 8 << shift);
8661 jcc(Assembler::less, L_check_fill_8_bytes);
8662 align(16);
8663
8664 BIND(L_fill_32_bytes_loop);
8665
8666 for (int i = 0; i < 32; i += 4) {
8667 movl(Address(to, i), value);
8668 }
8669
8670 addptr(to, 32);
8671 subl(count, 8 << shift);
8672 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8673 BIND(L_check_fill_8_bytes);
8674 addl(count, 8 << shift);
8675 jccb(Assembler::zero, L_exit);
8676 jmpb(L_fill_8_bytes);
8677
8678 //
8679 // length is too short, just fill qwords
8680 //
8681 BIND(L_fill_8_bytes_loop);
8682 movl(Address(to, 0), value);
8683 movl(Address(to, 4), value);
8684 addptr(to, 8);
8685 BIND(L_fill_8_bytes);
8686 subl(count, 1 << (shift + 1));
8687 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8688 // fall through to fill 4 bytes
8689 } else {
8690 Label L_fill_32_bytes;
8691 if (!UseUnalignedLoadStores) {
8692 // align to 8 bytes, we know we are 4 byte aligned to start
8693 testptr(to, 4);
8694 jccb(Assembler::zero, L_fill_32_bytes);
8695 movl(Address(to, 0), value);
8696 addptr(to, 4);
8697 subl(count, 1<<shift);
8698 }
8699 BIND(L_fill_32_bytes);
8700 {
8701 assert( UseSSE >= 2, "supported cpu only" );
8702 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8703 if (UseAVX > 2) {
8704 movl(rtmp, 0xffff);
8705 kmovwl(k1, rtmp);
8706 }
8707 movdl(xtmp, value);
8708 if (UseAVX > 2 && UseUnalignedLoadStores) {
8709 // Fill 64-byte chunks
8710 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8711 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8712
8713 subl(count, 16 << shift);
8714 jcc(Assembler::less, L_check_fill_32_bytes);
8715 align(16);
8716
8717 BIND(L_fill_64_bytes_loop);
8718 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8719 addptr(to, 64);
8720 subl(count, 16 << shift);
8721 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8722
8723 BIND(L_check_fill_32_bytes);
8724 addl(count, 8 << shift);
8725 jccb(Assembler::less, L_check_fill_8_bytes);
8726 vmovdqu(Address(to, 0), xtmp);
8727 addptr(to, 32);
8728 subl(count, 8 << shift);
8729
8730 BIND(L_check_fill_8_bytes);
8731 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8732 // Fill 64-byte chunks
8733 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8734 vpbroadcastd(xtmp, xtmp);
8735
8736 subl(count, 16 << shift);
8737 jcc(Assembler::less, L_check_fill_32_bytes);
8738 align(16);
8739
8740 BIND(L_fill_64_bytes_loop);
8741 vmovdqu(Address(to, 0), xtmp);
8742 vmovdqu(Address(to, 32), xtmp);
8743 addptr(to, 64);
8744 subl(count, 16 << shift);
8745 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8746
8747 BIND(L_check_fill_32_bytes);
8748 addl(count, 8 << shift);
8749 jccb(Assembler::less, L_check_fill_8_bytes);
8750 vmovdqu(Address(to, 0), xtmp);
8751 addptr(to, 32);
8752 subl(count, 8 << shift);
8753
8754 BIND(L_check_fill_8_bytes);
8755 // clean upper bits of YMM registers
8756 movdl(xtmp, value);
8757 pshufd(xtmp, xtmp, 0);
8758 } else {
8759 // Fill 32-byte chunks
8760 pshufd(xtmp, xtmp, 0);
8761
8762 subl(count, 8 << shift);
8763 jcc(Assembler::less, L_check_fill_8_bytes);
8764 align(16);
8765
8766 BIND(L_fill_32_bytes_loop);
8767
8768 if (UseUnalignedLoadStores) {
8769 movdqu(Address(to, 0), xtmp);
8770 movdqu(Address(to, 16), xtmp);
8771 } else {
8772 movq(Address(to, 0), xtmp);
8773 movq(Address(to, 8), xtmp);
8774 movq(Address(to, 16), xtmp);
8775 movq(Address(to, 24), xtmp);
8776 }
8777
8778 addptr(to, 32);
8779 subl(count, 8 << shift);
8780 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8781
8782 BIND(L_check_fill_8_bytes);
8783 }
8784 addl(count, 8 << shift);
8785 jccb(Assembler::zero, L_exit);
8786 jmpb(L_fill_8_bytes);
8787
8788 //
8789 // length is too short, just fill qwords
8790 //
8791 BIND(L_fill_8_bytes_loop);
8792 movq(Address(to, 0), xtmp);
8793 addptr(to, 8);
8794 BIND(L_fill_8_bytes);
8795 subl(count, 1 << (shift + 1));
8796 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8797 }
8798 }
8799 // fill trailing 4 bytes
8800 BIND(L_fill_4_bytes);
8801 testl(count, 1<<shift);
8802 jccb(Assembler::zero, L_fill_2_bytes);
8803 movl(Address(to, 0), value);
8804 if (t == T_BYTE || t == T_SHORT) {
8805 addptr(to, 4);
8806 BIND(L_fill_2_bytes);
8807 // fill trailing 2 bytes
8808 testl(count, 1<<(shift-1));
8809 jccb(Assembler::zero, L_fill_byte);
8810 movw(Address(to, 0), value);
8811 if (t == T_BYTE) {
8812 addptr(to, 2);
8813 BIND(L_fill_byte);
8814 // fill trailing byte
8815 testl(count, 1);
8816 jccb(Assembler::zero, L_exit);
8817 movb(Address(to, 0), value);
8818 } else {
8819 BIND(L_fill_byte);
8820 }
8821 } else {
8822 BIND(L_fill_2_bytes);
8823 }
8824 BIND(L_exit);
8825 }
8826
8827 // encode char[] to byte[] in ISO_8859_1
8828 //@HotSpotIntrinsicCandidate
8829 //private static int implEncodeISOArray(byte[] sa, int sp,
8830 //byte[] da, int dp, int len) {
8831 // int i = 0;
8832 // for (; i < len; i++) {
8833 // char c = StringUTF16.getChar(sa, sp++);
8834 // if (c > '\u00FF')
8835 // break;
8836 // da[dp++] = (byte)c;
8837 // }
8838 // return i;
8839 //}
8840 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8841 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8842 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8843 Register tmp5, Register result) {
8844
8845 // rsi: src
8846 // rdi: dst
8847 // rdx: len
8848 // rcx: tmp5
8849 // rax: result
8850 ShortBranchVerifier sbv(this);
8851 assert_different_registers(src, dst, len, tmp5, result);
8852 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8853
8854 // set result
8855 xorl(result, result);
8856 // check for zero length
8857 testl(len, len);
8858 jcc(Assembler::zero, L_done);
8859
8860 movl(result, len);
8861
8862 // Setup pointers
8863 lea(src, Address(src, len, Address::times_2)); // char[]
8864 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8865 negptr(len);
8866
8867 if (UseSSE42Intrinsics || UseAVX >= 2) {
8868 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8869 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8870
8871 if (UseAVX >= 2) {
8872 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8873 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8874 movdl(tmp1Reg, tmp5);
8875 vpbroadcastd(tmp1Reg, tmp1Reg);
8876 jmp(L_chars_32_check);
8877
8878 bind(L_copy_32_chars);
8879 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8880 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8881 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8882 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8883 jccb(Assembler::notZero, L_copy_32_chars_exit);
8884 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8885 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8886 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8887
8888 bind(L_chars_32_check);
8889 addptr(len, 32);
8890 jcc(Assembler::lessEqual, L_copy_32_chars);
8891
8892 bind(L_copy_32_chars_exit);
8893 subptr(len, 16);
8894 jccb(Assembler::greater, L_copy_16_chars_exit);
8895
8896 } else if (UseSSE42Intrinsics) {
8897 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8898 movdl(tmp1Reg, tmp5);
8899 pshufd(tmp1Reg, tmp1Reg, 0);
8900 jmpb(L_chars_16_check);
8901 }
8902
8903 bind(L_copy_16_chars);
8904 if (UseAVX >= 2) {
8905 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8906 vptest(tmp2Reg, tmp1Reg);
8907 jcc(Assembler::notZero, L_copy_16_chars_exit);
8908 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8909 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8910 } else {
8911 if (UseAVX > 0) {
8912 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8913 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8914 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8915 } else {
8916 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8917 por(tmp2Reg, tmp3Reg);
8918 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8919 por(tmp2Reg, tmp4Reg);
8920 }
8921 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8922 jccb(Assembler::notZero, L_copy_16_chars_exit);
8923 packuswb(tmp3Reg, tmp4Reg);
8924 }
8925 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8926
8927 bind(L_chars_16_check);
8928 addptr(len, 16);
8929 jcc(Assembler::lessEqual, L_copy_16_chars);
8930
8931 bind(L_copy_16_chars_exit);
8932 if (UseAVX >= 2) {
8933 // clean upper bits of YMM registers
8934 vpxor(tmp2Reg, tmp2Reg);
8935 vpxor(tmp3Reg, tmp3Reg);
8936 vpxor(tmp4Reg, tmp4Reg);
8937 movdl(tmp1Reg, tmp5);
8938 pshufd(tmp1Reg, tmp1Reg, 0);
8939 }
8940 subptr(len, 8);
8941 jccb(Assembler::greater, L_copy_8_chars_exit);
8942
8943 bind(L_copy_8_chars);
8944 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8945 ptest(tmp3Reg, tmp1Reg);
8946 jccb(Assembler::notZero, L_copy_8_chars_exit);
8947 packuswb(tmp3Reg, tmp1Reg);
8948 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8949 addptr(len, 8);
8950 jccb(Assembler::lessEqual, L_copy_8_chars);
8951
8952 bind(L_copy_8_chars_exit);
8953 subptr(len, 8);
8954 jccb(Assembler::zero, L_done);
8955 }
8956
8957 bind(L_copy_1_char);
8958 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8959 testl(tmp5, 0xff00); // check if Unicode char
8960 jccb(Assembler::notZero, L_copy_1_char_exit);
8961 movb(Address(dst, len, Address::times_1, 0), tmp5);
8962 addptr(len, 1);
8963 jccb(Assembler::less, L_copy_1_char);
8964
8965 bind(L_copy_1_char_exit);
8966 addptr(result, len); // len is negative count of not processed elements
8967
8968 bind(L_done);
8969 }
8970
8971 #ifdef _LP64
8972 /**
8973 * Helper for multiply_to_len().
8974 */
8975 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8976 addq(dest_lo, src1);
8977 adcq(dest_hi, 0);
8978 addq(dest_lo, src2);
8979 adcq(dest_hi, 0);
8980 }
8981
8982 /**
8983 * Multiply 64 bit by 64 bit first loop.
8984 */
8985 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8986 Register y, Register y_idx, Register z,
8987 Register carry, Register product,
8988 Register idx, Register kdx) {
8989 //
8990 // jlong carry, x[], y[], z[];
8991 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8992 // huge_128 product = y[idx] * x[xstart] + carry;
8993 // z[kdx] = (jlong)product;
8994 // carry = (jlong)(product >>> 64);
8995 // }
8996 // z[xstart] = carry;
8997 //
8998
8999 Label L_first_loop, L_first_loop_exit;
9000 Label L_one_x, L_one_y, L_multiply;
9001
9002 decrementl(xstart);
9003 jcc(Assembler::negative, L_one_x);
9004
9005 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9006 rorq(x_xstart, 32); // convert big-endian to little-endian
9007
9008 bind(L_first_loop);
9009 decrementl(idx);
9010 jcc(Assembler::negative, L_first_loop_exit);
9011 decrementl(idx);
9012 jcc(Assembler::negative, L_one_y);
9013 movq(y_idx, Address(y, idx, Address::times_4, 0));
9014 rorq(y_idx, 32); // convert big-endian to little-endian
9015 bind(L_multiply);
9016 movq(product, x_xstart);
9017 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
9018 addq(product, carry);
9019 adcq(rdx, 0);
9020 subl(kdx, 2);
9021 movl(Address(z, kdx, Address::times_4, 4), product);
9022 shrq(product, 32);
9023 movl(Address(z, kdx, Address::times_4, 0), product);
9024 movq(carry, rdx);
9025 jmp(L_first_loop);
9026
9027 bind(L_one_y);
9028 movl(y_idx, Address(y, 0));
9029 jmp(L_multiply);
9030
9031 bind(L_one_x);
9032 movl(x_xstart, Address(x, 0));
9033 jmp(L_first_loop);
9034
9035 bind(L_first_loop_exit);
9036 }
9037
9038 /**
9039 * Multiply 64 bit by 64 bit and add 128 bit.
9040 */
9041 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
9042 Register yz_idx, Register idx,
9043 Register carry, Register product, int offset) {
9044 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
9045 // z[kdx] = (jlong)product;
9046
9047 movq(yz_idx, Address(y, idx, Address::times_4, offset));
9048 rorq(yz_idx, 32); // convert big-endian to little-endian
9049 movq(product, x_xstart);
9050 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9051 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9052 rorq(yz_idx, 32); // convert big-endian to little-endian
9053
9054 add2_with_carry(rdx, product, carry, yz_idx);
9055
9056 movl(Address(z, idx, Address::times_4, offset+4), product);
9057 shrq(product, 32);
9058 movl(Address(z, idx, Address::times_4, offset), product);
9059
9060 }
9061
9062 /**
9063 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9064 */
9065 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9066 Register yz_idx, Register idx, Register jdx,
9067 Register carry, Register product,
9068 Register carry2) {
9069 // jlong carry, x[], y[], z[];
9070 // int kdx = ystart+1;
9071 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9072 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9073 // z[kdx+idx+1] = (jlong)product;
9074 // jlong carry2 = (jlong)(product >>> 64);
9075 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9076 // z[kdx+idx] = (jlong)product;
9077 // carry = (jlong)(product >>> 64);
9078 // }
9079 // idx += 2;
9080 // if (idx > 0) {
9081 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9082 // z[kdx+idx] = (jlong)product;
9083 // carry = (jlong)(product >>> 64);
9084 // }
9085 //
9086
9087 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9088
9089 movl(jdx, idx);
9090 andl(jdx, 0xFFFFFFFC);
9091 shrl(jdx, 2);
9092
9093 bind(L_third_loop);
9094 subl(jdx, 1);
9095 jcc(Assembler::negative, L_third_loop_exit);
9096 subl(idx, 4);
9097
9098 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9099 movq(carry2, rdx);
9100
9101 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9102 movq(carry, rdx);
9103 jmp(L_third_loop);
9104
9105 bind (L_third_loop_exit);
9106
9107 andl (idx, 0x3);
9108 jcc(Assembler::zero, L_post_third_loop_done);
9109
9110 Label L_check_1;
9111 subl(idx, 2);
9112 jcc(Assembler::negative, L_check_1);
9113
9114 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9115 movq(carry, rdx);
9116
9117 bind (L_check_1);
9118 addl (idx, 0x2);
9119 andl (idx, 0x1);
9120 subl(idx, 1);
9121 jcc(Assembler::negative, L_post_third_loop_done);
9122
9123 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9124 movq(product, x_xstart);
9125 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9126 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9127
9128 add2_with_carry(rdx, product, yz_idx, carry);
9129
9130 movl(Address(z, idx, Address::times_4, 0), product);
9131 shrq(product, 32);
9132
9133 shlq(rdx, 32);
9134 orq(product, rdx);
9135 movq(carry, product);
9136
9137 bind(L_post_third_loop_done);
9138 }
9139
9140 /**
9141 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9142 *
9143 */
9144 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9145 Register carry, Register carry2,
9146 Register idx, Register jdx,
9147 Register yz_idx1, Register yz_idx2,
9148 Register tmp, Register tmp3, Register tmp4) {
9149 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9150
9151 // jlong carry, x[], y[], z[];
9152 // int kdx = ystart+1;
9153 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9154 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9155 // jlong carry2 = (jlong)(tmp3 >>> 64);
9156 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9157 // carry = (jlong)(tmp4 >>> 64);
9158 // z[kdx+idx+1] = (jlong)tmp3;
9159 // z[kdx+idx] = (jlong)tmp4;
9160 // }
9161 // idx += 2;
9162 // if (idx > 0) {
9163 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9164 // z[kdx+idx] = (jlong)yz_idx1;
9165 // carry = (jlong)(yz_idx1 >>> 64);
9166 // }
9167 //
9168
9169 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9170
9171 movl(jdx, idx);
9172 andl(jdx, 0xFFFFFFFC);
9173 shrl(jdx, 2);
9174
9175 bind(L_third_loop);
9176 subl(jdx, 1);
9177 jcc(Assembler::negative, L_third_loop_exit);
9178 subl(idx, 4);
9179
9180 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9181 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9182 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9183 rorxq(yz_idx2, yz_idx2, 32);
9184
9185 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9186 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9187
9188 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9189 rorxq(yz_idx1, yz_idx1, 32);
9190 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9191 rorxq(yz_idx2, yz_idx2, 32);
9192
9193 if (VM_Version::supports_adx()) {
9194 adcxq(tmp3, carry);
9195 adoxq(tmp3, yz_idx1);
9196
9197 adcxq(tmp4, tmp);
9198 adoxq(tmp4, yz_idx2);
9199
9200 movl(carry, 0); // does not affect flags
9201 adcxq(carry2, carry);
9202 adoxq(carry2, carry);
9203 } else {
9204 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9205 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9206 }
9207 movq(carry, carry2);
9208
9209 movl(Address(z, idx, Address::times_4, 12), tmp3);
9210 shrq(tmp3, 32);
9211 movl(Address(z, idx, Address::times_4, 8), tmp3);
9212
9213 movl(Address(z, idx, Address::times_4, 4), tmp4);
9214 shrq(tmp4, 32);
9215 movl(Address(z, idx, Address::times_4, 0), tmp4);
9216
9217 jmp(L_third_loop);
9218
9219 bind (L_third_loop_exit);
9220
9221 andl (idx, 0x3);
9222 jcc(Assembler::zero, L_post_third_loop_done);
9223
9224 Label L_check_1;
9225 subl(idx, 2);
9226 jcc(Assembler::negative, L_check_1);
9227
9228 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9229 rorxq(yz_idx1, yz_idx1, 32);
9230 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9231 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9232 rorxq(yz_idx2, yz_idx2, 32);
9233
9234 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9235
9236 movl(Address(z, idx, Address::times_4, 4), tmp3);
9237 shrq(tmp3, 32);
9238 movl(Address(z, idx, Address::times_4, 0), tmp3);
9239 movq(carry, tmp4);
9240
9241 bind (L_check_1);
9242 addl (idx, 0x2);
9243 andl (idx, 0x1);
9244 subl(idx, 1);
9245 jcc(Assembler::negative, L_post_third_loop_done);
9246 movl(tmp4, Address(y, idx, Address::times_4, 0));
9247 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9248 movl(tmp4, Address(z, idx, Address::times_4, 0));
9249
9250 add2_with_carry(carry2, tmp3, tmp4, carry);
9251
9252 movl(Address(z, idx, Address::times_4, 0), tmp3);
9253 shrq(tmp3, 32);
9254
9255 shlq(carry2, 32);
9256 orq(tmp3, carry2);
9257 movq(carry, tmp3);
9258
9259 bind(L_post_third_loop_done);
9260 }
9261
9262 /**
9263 * Code for BigInteger::multiplyToLen() instrinsic.
9264 *
9265 * rdi: x
9266 * rax: xlen
9267 * rsi: y
9268 * rcx: ylen
9269 * r8: z
9270 * r11: zlen
9271 * r12: tmp1
9272 * r13: tmp2
9273 * r14: tmp3
9274 * r15: tmp4
9275 * rbx: tmp5
9276 *
9277 */
9278 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9279 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9280 ShortBranchVerifier sbv(this);
9281 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9282
9283 push(tmp1);
9284 push(tmp2);
9285 push(tmp3);
9286 push(tmp4);
9287 push(tmp5);
9288
9289 push(xlen);
9290 push(zlen);
9291
9292 const Register idx = tmp1;
9293 const Register kdx = tmp2;
9294 const Register xstart = tmp3;
9295
9296 const Register y_idx = tmp4;
9297 const Register carry = tmp5;
9298 const Register product = xlen;
9299 const Register x_xstart = zlen; // reuse register
9300
9301 // First Loop.
9302 //
9303 // final static long LONG_MASK = 0xffffffffL;
9304 // int xstart = xlen - 1;
9305 // int ystart = ylen - 1;
9306 // long carry = 0;
9307 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9308 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9309 // z[kdx] = (int)product;
9310 // carry = product >>> 32;
9311 // }
9312 // z[xstart] = (int)carry;
9313 //
9314
9315 movl(idx, ylen); // idx = ylen;
9316 movl(kdx, zlen); // kdx = xlen+ylen;
9317 xorq(carry, carry); // carry = 0;
9318
9319 Label L_done;
9320
9321 movl(xstart, xlen);
9322 decrementl(xstart);
9323 jcc(Assembler::negative, L_done);
9324
9325 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9326
9327 Label L_second_loop;
9328 testl(kdx, kdx);
9329 jcc(Assembler::zero, L_second_loop);
9330
9331 Label L_carry;
9332 subl(kdx, 1);
9333 jcc(Assembler::zero, L_carry);
9334
9335 movl(Address(z, kdx, Address::times_4, 0), carry);
9336 shrq(carry, 32);
9337 subl(kdx, 1);
9338
9339 bind(L_carry);
9340 movl(Address(z, kdx, Address::times_4, 0), carry);
9341
9342 // Second and third (nested) loops.
9343 //
9344 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9345 // carry = 0;
9346 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9347 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9348 // (z[k] & LONG_MASK) + carry;
9349 // z[k] = (int)product;
9350 // carry = product >>> 32;
9351 // }
9352 // z[i] = (int)carry;
9353 // }
9354 //
9355 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9356
9357 const Register jdx = tmp1;
9358
9359 bind(L_second_loop);
9360 xorl(carry, carry); // carry = 0;
9361 movl(jdx, ylen); // j = ystart+1
9362
9363 subl(xstart, 1); // i = xstart-1;
9364 jcc(Assembler::negative, L_done);
9365
9366 push (z);
9367
9368 Label L_last_x;
9369 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9370 subl(xstart, 1); // i = xstart-1;
9371 jcc(Assembler::negative, L_last_x);
9372
9373 if (UseBMI2Instructions) {
9374 movq(rdx, Address(x, xstart, Address::times_4, 0));
9375 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9376 } else {
9377 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9378 rorq(x_xstart, 32); // convert big-endian to little-endian
9379 }
9380
9381 Label L_third_loop_prologue;
9382 bind(L_third_loop_prologue);
9383
9384 push (x);
9385 push (xstart);
9386 push (ylen);
9387
9388
9389 if (UseBMI2Instructions) {
9390 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9391 } else { // !UseBMI2Instructions
9392 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9393 }
9394
9395 pop(ylen);
9396 pop(xlen);
9397 pop(x);
9398 pop(z);
9399
9400 movl(tmp3, xlen);
9401 addl(tmp3, 1);
9402 movl(Address(z, tmp3, Address::times_4, 0), carry);
9403 subl(tmp3, 1);
9404 jccb(Assembler::negative, L_done);
9405
9406 shrq(carry, 32);
9407 movl(Address(z, tmp3, Address::times_4, 0), carry);
9408 jmp(L_second_loop);
9409
9410 // Next infrequent code is moved outside loops.
9411 bind(L_last_x);
9412 if (UseBMI2Instructions) {
9413 movl(rdx, Address(x, 0));
9414 } else {
9415 movl(x_xstart, Address(x, 0));
9416 }
9417 jmp(L_third_loop_prologue);
9418
9419 bind(L_done);
9420
9421 pop(zlen);
9422 pop(xlen);
9423
9424 pop(tmp5);
9425 pop(tmp4);
9426 pop(tmp3);
9427 pop(tmp2);
9428 pop(tmp1);
9429 }
9430
9431 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9432 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9433 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9434 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9435 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9436 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9437 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9438 Label SAME_TILL_END, DONE;
9439 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9440
9441 //scale is in rcx in both Win64 and Unix
9442 ShortBranchVerifier sbv(this);
9443
9444 shlq(length);
9445 xorq(result, result);
9446
9447 if ((UseAVX > 2) &&
9448 VM_Version::supports_avx512vlbw()) {
9449 set_vector_masking(); // opening of the stub context for programming mask registers
9450 cmpq(length, 64);
9451 jcc(Assembler::less, VECTOR32_TAIL);
9452 movq(tmp1, length);
9453 andq(tmp1, 0x3F); // tail count
9454 andq(length, ~(0x3F)); //vector count
9455
9456 bind(VECTOR64_LOOP);
9457 // AVX512 code to compare 64 byte vectors.
9458 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9459 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9460 kortestql(k7, k7);
9461 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9462 addq(result, 64);
9463 subq(length, 64);
9464 jccb(Assembler::notZero, VECTOR64_LOOP);
9465
9466 //bind(VECTOR64_TAIL);
9467 testq(tmp1, tmp1);
9468 jcc(Assembler::zero, SAME_TILL_END);
9469
9470 bind(VECTOR64_TAIL);
9471 // AVX512 code to compare upto 63 byte vectors.
9472 // Save k1
9473 kmovql(k3, k1);
9474 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9475 shlxq(tmp2, tmp2, tmp1);
9476 notq(tmp2);
9477 kmovql(k1, tmp2);
9478
9479 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9480 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9481
9482 ktestql(k7, k1);
9483 // Restore k1
9484 kmovql(k1, k3);
9485 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9486
9487 bind(VECTOR64_NOT_EQUAL);
9488 kmovql(tmp1, k7);
9489 notq(tmp1);
9490 tzcntq(tmp1, tmp1);
9491 addq(result, tmp1);
9492 shrq(result);
9493 jmp(DONE);
9494 bind(VECTOR32_TAIL);
9495 clear_vector_masking(); // closing of the stub context for programming mask registers
9496 }
9497
9498 cmpq(length, 8);
9499 jcc(Assembler::equal, VECTOR8_LOOP);
9500 jcc(Assembler::less, VECTOR4_TAIL);
9501
9502 if (UseAVX >= 2) {
9503
9504 cmpq(length, 16);
9505 jcc(Assembler::equal, VECTOR16_LOOP);
9506 jcc(Assembler::less, VECTOR8_LOOP);
9507
9508 cmpq(length, 32);
9509 jccb(Assembler::less, VECTOR16_TAIL);
9510
9511 subq(length, 32);
9512 bind(VECTOR32_LOOP);
9513 vmovdqu(rymm0, Address(obja, result));
9514 vmovdqu(rymm1, Address(objb, result));
9515 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9516 vptest(rymm2, rymm2);
9517 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9518 addq(result, 32);
9519 subq(length, 32);
9520 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9521 addq(length, 32);
9522 jcc(Assembler::equal, SAME_TILL_END);
9523 //falling through if less than 32 bytes left //close the branch here.
9524
9525 bind(VECTOR16_TAIL);
9526 cmpq(length, 16);
9527 jccb(Assembler::less, VECTOR8_TAIL);
9528 bind(VECTOR16_LOOP);
9529 movdqu(rymm0, Address(obja, result));
9530 movdqu(rymm1, Address(objb, result));
9531 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9532 ptest(rymm2, rymm2);
9533 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9534 addq(result, 16);
9535 subq(length, 16);
9536 jcc(Assembler::equal, SAME_TILL_END);
9537 //falling through if less than 16 bytes left
9538 } else {//regular intrinsics
9539
9540 cmpq(length, 16);
9541 jccb(Assembler::less, VECTOR8_TAIL);
9542
9543 subq(length, 16);
9544 bind(VECTOR16_LOOP);
9545 movdqu(rymm0, Address(obja, result));
9546 movdqu(rymm1, Address(objb, result));
9547 pxor(rymm0, rymm1);
9548 ptest(rymm0, rymm0);
9549 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9550 addq(result, 16);
9551 subq(length, 16);
9552 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9553 addq(length, 16);
9554 jcc(Assembler::equal, SAME_TILL_END);
9555 //falling through if less than 16 bytes left
9556 }
9557
9558 bind(VECTOR8_TAIL);
9559 cmpq(length, 8);
9560 jccb(Assembler::less, VECTOR4_TAIL);
9561 bind(VECTOR8_LOOP);
9562 movq(tmp1, Address(obja, result));
9563 movq(tmp2, Address(objb, result));
9564 xorq(tmp1, tmp2);
9565 testq(tmp1, tmp1);
9566 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9567 addq(result, 8);
9568 subq(length, 8);
9569 jcc(Assembler::equal, SAME_TILL_END);
9570 //falling through if less than 8 bytes left
9571
9572 bind(VECTOR4_TAIL);
9573 cmpq(length, 4);
9574 jccb(Assembler::less, BYTES_TAIL);
9575 bind(VECTOR4_LOOP);
9576 movl(tmp1, Address(obja, result));
9577 xorl(tmp1, Address(objb, result));
9578 testl(tmp1, tmp1);
9579 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9580 addq(result, 4);
9581 subq(length, 4);
9582 jcc(Assembler::equal, SAME_TILL_END);
9583 //falling through if less than 4 bytes left
9584
9585 bind(BYTES_TAIL);
9586 bind(BYTES_LOOP);
9587 load_unsigned_byte(tmp1, Address(obja, result));
9588 load_unsigned_byte(tmp2, Address(objb, result));
9589 xorl(tmp1, tmp2);
9590 testl(tmp1, tmp1);
9591 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9592 decq(length);
9593 jccb(Assembler::zero, SAME_TILL_END);
9594 incq(result);
9595 load_unsigned_byte(tmp1, Address(obja, result));
9596 load_unsigned_byte(tmp2, Address(objb, result));
9597 xorl(tmp1, tmp2);
9598 testl(tmp1, tmp1);
9599 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9600 decq(length);
9601 jccb(Assembler::zero, SAME_TILL_END);
9602 incq(result);
9603 load_unsigned_byte(tmp1, Address(obja, result));
9604 load_unsigned_byte(tmp2, Address(objb, result));
9605 xorl(tmp1, tmp2);
9606 testl(tmp1, tmp1);
9607 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9608 jmpb(SAME_TILL_END);
9609
9610 if (UseAVX >= 2) {
9611 bind(VECTOR32_NOT_EQUAL);
9612 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9613 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9614 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9615 vpmovmskb(tmp1, rymm0);
9616 bsfq(tmp1, tmp1);
9617 addq(result, tmp1);
9618 shrq(result);
9619 jmpb(DONE);
9620 }
9621
9622 bind(VECTOR16_NOT_EQUAL);
9623 if (UseAVX >= 2) {
9624 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9625 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9626 pxor(rymm0, rymm2);
9627 } else {
9628 pcmpeqb(rymm2, rymm2);
9629 pxor(rymm0, rymm1);
9630 pcmpeqb(rymm0, rymm1);
9631 pxor(rymm0, rymm2);
9632 }
9633 pmovmskb(tmp1, rymm0);
9634 bsfq(tmp1, tmp1);
9635 addq(result, tmp1);
9636 shrq(result);
9637 jmpb(DONE);
9638
9639 bind(VECTOR8_NOT_EQUAL);
9640 bind(VECTOR4_NOT_EQUAL);
9641 bsfq(tmp1, tmp1);
9642 shrq(tmp1, 3);
9643 addq(result, tmp1);
9644 bind(BYTES_NOT_EQUAL);
9645 shrq(result);
9646 jmpb(DONE);
9647
9648 bind(SAME_TILL_END);
9649 mov64(result, -1);
9650
9651 bind(DONE);
9652 }
9653
9654 //Helper functions for square_to_len()
9655
9656 /**
9657 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9658 * Preserves x and z and modifies rest of the registers.
9659 */
9660 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9661 // Perform square and right shift by 1
9662 // Handle odd xlen case first, then for even xlen do the following
9663 // jlong carry = 0;
9664 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9665 // huge_128 product = x[j:j+1] * x[j:j+1];
9666 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9667 // z[i+2:i+3] = (jlong)(product >>> 1);
9668 // carry = (jlong)product;
9669 // }
9670
9671 xorq(tmp5, tmp5); // carry
9672 xorq(rdxReg, rdxReg);
9673 xorl(tmp1, tmp1); // index for x
9674 xorl(tmp4, tmp4); // index for z
9675
9676 Label L_first_loop, L_first_loop_exit;
9677
9678 testl(xlen, 1);
9679 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9680
9681 // Square and right shift by 1 the odd element using 32 bit multiply
9682 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9683 imulq(raxReg, raxReg);
9684 shrq(raxReg, 1);
9685 adcq(tmp5, 0);
9686 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9687 incrementl(tmp1);
9688 addl(tmp4, 2);
9689
9690 // Square and right shift by 1 the rest using 64 bit multiply
9691 bind(L_first_loop);
9692 cmpptr(tmp1, xlen);
9693 jccb(Assembler::equal, L_first_loop_exit);
9694
9695 // Square
9696 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9697 rorq(raxReg, 32); // convert big-endian to little-endian
9698 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9699
9700 // Right shift by 1 and save carry
9701 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9702 rcrq(rdxReg, 1);
9703 rcrq(raxReg, 1);
9704 adcq(tmp5, 0);
9705
9706 // Store result in z
9707 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9708 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9709
9710 // Update indices for x and z
9711 addl(tmp1, 2);
9712 addl(tmp4, 4);
9713 jmp(L_first_loop);
9714
9715 bind(L_first_loop_exit);
9716 }
9717
9718
9719 /**
9720 * Perform the following multiply add operation using BMI2 instructions
9721 * carry:sum = sum + op1*op2 + carry
9722 * op2 should be in rdx
9723 * op2 is preserved, all other registers are modified
9724 */
9725 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9726 // assert op2 is rdx
9727 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9728 addq(sum, carry);
9729 adcq(tmp2, 0);
9730 addq(sum, op1);
9731 adcq(tmp2, 0);
9732 movq(carry, tmp2);
9733 }
9734
9735 /**
9736 * Perform the following multiply add operation:
9737 * carry:sum = sum + op1*op2 + carry
9738 * Preserves op1, op2 and modifies rest of registers
9739 */
9740 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9741 // rdx:rax = op1 * op2
9742 movq(raxReg, op2);
9743 mulq(op1);
9744
9745 // rdx:rax = sum + carry + rdx:rax
9746 addq(sum, carry);
9747 adcq(rdxReg, 0);
9748 addq(sum, raxReg);
9749 adcq(rdxReg, 0);
9750
9751 // carry:sum = rdx:sum
9752 movq(carry, rdxReg);
9753 }
9754
9755 /**
9756 * Add 64 bit long carry into z[] with carry propogation.
9757 * Preserves z and carry register values and modifies rest of registers.
9758 *
9759 */
9760 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9761 Label L_fourth_loop, L_fourth_loop_exit;
9762
9763 movl(tmp1, 1);
9764 subl(zlen, 2);
9765 addq(Address(z, zlen, Address::times_4, 0), carry);
9766
9767 bind(L_fourth_loop);
9768 jccb(Assembler::carryClear, L_fourth_loop_exit);
9769 subl(zlen, 2);
9770 jccb(Assembler::negative, L_fourth_loop_exit);
9771 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9772 jmp(L_fourth_loop);
9773 bind(L_fourth_loop_exit);
9774 }
9775
9776 /**
9777 * Shift z[] left by 1 bit.
9778 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9779 *
9780 */
9781 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9782
9783 Label L_fifth_loop, L_fifth_loop_exit;
9784
9785 // Fifth loop
9786 // Perform primitiveLeftShift(z, zlen, 1)
9787
9788 const Register prev_carry = tmp1;
9789 const Register new_carry = tmp4;
9790 const Register value = tmp2;
9791 const Register zidx = tmp3;
9792
9793 // int zidx, carry;
9794 // long value;
9795 // carry = 0;
9796 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9797 // (carry:value) = (z[i] << 1) | carry ;
9798 // z[i] = value;
9799 // }
9800
9801 movl(zidx, zlen);
9802 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9803
9804 bind(L_fifth_loop);
9805 decl(zidx); // Use decl to preserve carry flag
9806 decl(zidx);
9807 jccb(Assembler::negative, L_fifth_loop_exit);
9808
9809 if (UseBMI2Instructions) {
9810 movq(value, Address(z, zidx, Address::times_4, 0));
9811 rclq(value, 1);
9812 rorxq(value, value, 32);
9813 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9814 }
9815 else {
9816 // clear new_carry
9817 xorl(new_carry, new_carry);
9818
9819 // Shift z[i] by 1, or in previous carry and save new carry
9820 movq(value, Address(z, zidx, Address::times_4, 0));
9821 shlq(value, 1);
9822 adcl(new_carry, 0);
9823
9824 orq(value, prev_carry);
9825 rorq(value, 0x20);
9826 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9827
9828 // Set previous carry = new carry
9829 movl(prev_carry, new_carry);
9830 }
9831 jmp(L_fifth_loop);
9832
9833 bind(L_fifth_loop_exit);
9834 }
9835
9836
9837 /**
9838 * Code for BigInteger::squareToLen() intrinsic
9839 *
9840 * rdi: x
9841 * rsi: len
9842 * r8: z
9843 * rcx: zlen
9844 * r12: tmp1
9845 * r13: tmp2
9846 * r14: tmp3
9847 * r15: tmp4
9848 * rbx: tmp5
9849 *
9850 */
9851 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9852
9853 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9854 push(tmp1);
9855 push(tmp2);
9856 push(tmp3);
9857 push(tmp4);
9858 push(tmp5);
9859
9860 // First loop
9861 // Store the squares, right shifted one bit (i.e., divided by 2).
9862 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9863
9864 // Add in off-diagonal sums.
9865 //
9866 // Second, third (nested) and fourth loops.
9867 // zlen +=2;
9868 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9869 // carry = 0;
9870 // long op2 = x[xidx:xidx+1];
9871 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9872 // k -= 2;
9873 // long op1 = x[j:j+1];
9874 // long sum = z[k:k+1];
9875 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9876 // z[k:k+1] = sum;
9877 // }
9878 // add_one_64(z, k, carry, tmp_regs);
9879 // }
9880
9881 const Register carry = tmp5;
9882 const Register sum = tmp3;
9883 const Register op1 = tmp4;
9884 Register op2 = tmp2;
9885
9886 push(zlen);
9887 push(len);
9888 addl(zlen,2);
9889 bind(L_second_loop);
9890 xorq(carry, carry);
9891 subl(zlen, 4);
9892 subl(len, 2);
9893 push(zlen);
9894 push(len);
9895 cmpl(len, 0);
9896 jccb(Assembler::lessEqual, L_second_loop_exit);
9897
9898 // Multiply an array by one 64 bit long.
9899 if (UseBMI2Instructions) {
9900 op2 = rdxReg;
9901 movq(op2, Address(x, len, Address::times_4, 0));
9902 rorxq(op2, op2, 32);
9903 }
9904 else {
9905 movq(op2, Address(x, len, Address::times_4, 0));
9906 rorq(op2, 32);
9907 }
9908
9909 bind(L_third_loop);
9910 decrementl(len);
9911 jccb(Assembler::negative, L_third_loop_exit);
9912 decrementl(len);
9913 jccb(Assembler::negative, L_last_x);
9914
9915 movq(op1, Address(x, len, Address::times_4, 0));
9916 rorq(op1, 32);
9917
9918 bind(L_multiply);
9919 subl(zlen, 2);
9920 movq(sum, Address(z, zlen, Address::times_4, 0));
9921
9922 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9923 if (UseBMI2Instructions) {
9924 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9925 }
9926 else {
9927 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9928 }
9929
9930 movq(Address(z, zlen, Address::times_4, 0), sum);
9931
9932 jmp(L_third_loop);
9933 bind(L_third_loop_exit);
9934
9935 // Fourth loop
9936 // Add 64 bit long carry into z with carry propogation.
9937 // Uses offsetted zlen.
9938 add_one_64(z, zlen, carry, tmp1);
9939
9940 pop(len);
9941 pop(zlen);
9942 jmp(L_second_loop);
9943
9944 // Next infrequent code is moved outside loops.
9945 bind(L_last_x);
9946 movl(op1, Address(x, 0));
9947 jmp(L_multiply);
9948
9949 bind(L_second_loop_exit);
9950 pop(len);
9951 pop(zlen);
9952 pop(len);
9953 pop(zlen);
9954
9955 // Fifth loop
9956 // Shift z left 1 bit.
9957 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9958
9959 // z[zlen-1] |= x[len-1] & 1;
9960 movl(tmp3, Address(x, len, Address::times_4, -4));
9961 andl(tmp3, 1);
9962 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9963
9964 pop(tmp5);
9965 pop(tmp4);
9966 pop(tmp3);
9967 pop(tmp2);
9968 pop(tmp1);
9969 }
9970
9971 /**
9972 * Helper function for mul_add()
9973 * Multiply the in[] by int k and add to out[] starting at offset offs using
9974 * 128 bit by 32 bit multiply and return the carry in tmp5.
9975 * Only quad int aligned length of in[] is operated on in this function.
9976 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9977 * This function preserves out, in and k registers.
9978 * len and offset point to the appropriate index in "in" & "out" correspondingly
9979 * tmp5 has the carry.
9980 * other registers are temporary and are modified.
9981 *
9982 */
9983 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9984 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9985 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9986
9987 Label L_first_loop, L_first_loop_exit;
9988
9989 movl(tmp1, len);
9990 shrl(tmp1, 2);
9991
9992 bind(L_first_loop);
9993 subl(tmp1, 1);
9994 jccb(Assembler::negative, L_first_loop_exit);
9995
9996 subl(len, 4);
9997 subl(offset, 4);
9998
9999 Register op2 = tmp2;
10000 const Register sum = tmp3;
10001 const Register op1 = tmp4;
10002 const Register carry = tmp5;
10003
10004 if (UseBMI2Instructions) {
10005 op2 = rdxReg;
10006 }
10007
10008 movq(op1, Address(in, len, Address::times_4, 8));
10009 rorq(op1, 32);
10010 movq(sum, Address(out, offset, Address::times_4, 8));
10011 rorq(sum, 32);
10012 if (UseBMI2Instructions) {
10013 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10014 }
10015 else {
10016 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10017 }
10018 // Store back in big endian from little endian
10019 rorq(sum, 0x20);
10020 movq(Address(out, offset, Address::times_4, 8), sum);
10021
10022 movq(op1, Address(in, len, Address::times_4, 0));
10023 rorq(op1, 32);
10024 movq(sum, Address(out, offset, Address::times_4, 0));
10025 rorq(sum, 32);
10026 if (UseBMI2Instructions) {
10027 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10028 }
10029 else {
10030 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10031 }
10032 // Store back in big endian from little endian
10033 rorq(sum, 0x20);
10034 movq(Address(out, offset, Address::times_4, 0), sum);
10035
10036 jmp(L_first_loop);
10037 bind(L_first_loop_exit);
10038 }
10039
10040 /**
10041 * Code for BigInteger::mulAdd() intrinsic
10042 *
10043 * rdi: out
10044 * rsi: in
10045 * r11: offs (out.length - offset)
10046 * rcx: len
10047 * r8: k
10048 * r12: tmp1
10049 * r13: tmp2
10050 * r14: tmp3
10051 * r15: tmp4
10052 * rbx: tmp5
10053 * Multiply the in[] by word k and add to out[], return the carry in rax
10054 */
10055 void MacroAssembler::mul_add(Register out, Register in, Register offs,
10056 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
10057 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10058
10059 Label L_carry, L_last_in, L_done;
10060
10061 // carry = 0;
10062 // for (int j=len-1; j >= 0; j--) {
10063 // long product = (in[j] & LONG_MASK) * kLong +
10064 // (out[offs] & LONG_MASK) + carry;
10065 // out[offs--] = (int)product;
10066 // carry = product >>> 32;
10067 // }
10068 //
10069 push(tmp1);
10070 push(tmp2);
10071 push(tmp3);
10072 push(tmp4);
10073 push(tmp5);
10074
10075 Register op2 = tmp2;
10076 const Register sum = tmp3;
10077 const Register op1 = tmp4;
10078 const Register carry = tmp5;
10079
10080 if (UseBMI2Instructions) {
10081 op2 = rdxReg;
10082 movl(op2, k);
10083 }
10084 else {
10085 movl(op2, k);
10086 }
10087
10088 xorq(carry, carry);
10089
10090 //First loop
10091
10092 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10093 //The carry is in tmp5
10094 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10095
10096 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10097 decrementl(len);
10098 jccb(Assembler::negative, L_carry);
10099 decrementl(len);
10100 jccb(Assembler::negative, L_last_in);
10101
10102 movq(op1, Address(in, len, Address::times_4, 0));
10103 rorq(op1, 32);
10104
10105 subl(offs, 2);
10106 movq(sum, Address(out, offs, Address::times_4, 0));
10107 rorq(sum, 32);
10108
10109 if (UseBMI2Instructions) {
10110 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10111 }
10112 else {
10113 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10114 }
10115
10116 // Store back in big endian from little endian
10117 rorq(sum, 0x20);
10118 movq(Address(out, offs, Address::times_4, 0), sum);
10119
10120 testl(len, len);
10121 jccb(Assembler::zero, L_carry);
10122
10123 //Multiply the last in[] entry, if any
10124 bind(L_last_in);
10125 movl(op1, Address(in, 0));
10126 movl(sum, Address(out, offs, Address::times_4, -4));
10127
10128 movl(raxReg, k);
10129 mull(op1); //tmp4 * eax -> edx:eax
10130 addl(sum, carry);
10131 adcl(rdxReg, 0);
10132 addl(sum, raxReg);
10133 adcl(rdxReg, 0);
10134 movl(carry, rdxReg);
10135
10136 movl(Address(out, offs, Address::times_4, -4), sum);
10137
10138 bind(L_carry);
10139 //return tmp5/carry as carry in rax
10140 movl(rax, carry);
10141
10142 bind(L_done);
10143 pop(tmp5);
10144 pop(tmp4);
10145 pop(tmp3);
10146 pop(tmp2);
10147 pop(tmp1);
10148 }
10149 #endif
10150
10151 /**
10152 * Emits code to update CRC-32 with a byte value according to constants in table
10153 *
10154 * @param [in,out]crc Register containing the crc.
10155 * @param [in]val Register containing the byte to fold into the CRC.
10156 * @param [in]table Register containing the table of crc constants.
10157 *
10158 * uint32_t crc;
10159 * val = crc_table[(val ^ crc) & 0xFF];
10160 * crc = val ^ (crc >> 8);
10161 *
10162 */
10163 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10164 xorl(val, crc);
10165 andl(val, 0xFF);
10166 shrl(crc, 8); // unsigned shift
10167 xorl(crc, Address(table, val, Address::times_4, 0));
10168 }
10169
10170 /**
10171 * Fold 128-bit data chunk
10172 */
10173 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10174 if (UseAVX > 0) {
10175 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10176 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10177 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10178 pxor(xcrc, xtmp);
10179 } else {
10180 movdqa(xtmp, xcrc);
10181 pclmulhdq(xtmp, xK); // [123:64]
10182 pclmulldq(xcrc, xK); // [63:0]
10183 pxor(xcrc, xtmp);
10184 movdqu(xtmp, Address(buf, offset));
10185 pxor(xcrc, xtmp);
10186 }
10187 }
10188
10189 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10190 if (UseAVX > 0) {
10191 vpclmulhdq(xtmp, xK, xcrc);
10192 vpclmulldq(xcrc, xK, xcrc);
10193 pxor(xcrc, xbuf);
10194 pxor(xcrc, xtmp);
10195 } else {
10196 movdqa(xtmp, xcrc);
10197 pclmulhdq(xtmp, xK);
10198 pclmulldq(xcrc, xK);
10199 pxor(xcrc, xbuf);
10200 pxor(xcrc, xtmp);
10201 }
10202 }
10203
10204 /**
10205 * 8-bit folds to compute 32-bit CRC
10206 *
10207 * uint64_t xcrc;
10208 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10209 */
10210 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10211 movdl(tmp, xcrc);
10212 andl(tmp, 0xFF);
10213 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10214 psrldq(xcrc, 1); // unsigned shift one byte
10215 pxor(xcrc, xtmp);
10216 }
10217
10218 /**
10219 * uint32_t crc;
10220 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10221 */
10222 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10223 movl(tmp, crc);
10224 andl(tmp, 0xFF);
10225 shrl(crc, 8);
10226 xorl(crc, Address(table, tmp, Address::times_4, 0));
10227 }
10228
10229 /**
10230 * @param crc register containing existing CRC (32-bit)
10231 * @param buf register pointing to input byte buffer (byte*)
10232 * @param len register containing number of bytes
10233 * @param table register that will contain address of CRC table
10234 * @param tmp scratch register
10235 */
10236 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10237 assert_different_registers(crc, buf, len, table, tmp, rax);
10238
10239 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10240 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10241
10242 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10243 // context for the registers used, where all instructions below are using 128-bit mode
10244 // On EVEX without VL and BW, these instructions will all be AVX.
10245 if (VM_Version::supports_avx512vlbw()) {
10246 movl(tmp, 0xffff);
10247 kmovwl(k1, tmp);
10248 }
10249
10250 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10251 notl(crc); // ~crc
10252 cmpl(len, 16);
10253 jcc(Assembler::less, L_tail);
10254
10255 // Align buffer to 16 bytes
10256 movl(tmp, buf);
10257 andl(tmp, 0xF);
10258 jccb(Assembler::zero, L_aligned);
10259 subl(tmp, 16);
10260 addl(len, tmp);
10261
10262 align(4);
10263 BIND(L_align_loop);
10264 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10265 update_byte_crc32(crc, rax, table);
10266 increment(buf);
10267 incrementl(tmp);
10268 jccb(Assembler::less, L_align_loop);
10269
10270 BIND(L_aligned);
10271 movl(tmp, len); // save
10272 shrl(len, 4);
10273 jcc(Assembler::zero, L_tail_restore);
10274
10275 // Fold crc into first bytes of vector
10276 movdqa(xmm1, Address(buf, 0));
10277 movdl(rax, xmm1);
10278 xorl(crc, rax);
10279 if (VM_Version::supports_sse4_1()) {
10280 pinsrd(xmm1, crc, 0);
10281 } else {
10282 pinsrw(xmm1, crc, 0);
10283 shrl(crc, 16);
10284 pinsrw(xmm1, crc, 1);
10285 }
10286 addptr(buf, 16);
10287 subl(len, 4); // len > 0
10288 jcc(Assembler::less, L_fold_tail);
10289
10290 movdqa(xmm2, Address(buf, 0));
10291 movdqa(xmm3, Address(buf, 16));
10292 movdqa(xmm4, Address(buf, 32));
10293 addptr(buf, 48);
10294 subl(len, 3);
10295 jcc(Assembler::lessEqual, L_fold_512b);
10296
10297 // Fold total 512 bits of polynomial on each iteration,
10298 // 128 bits per each of 4 parallel streams.
10299 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10300
10301 align(32);
10302 BIND(L_fold_512b_loop);
10303 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10304 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10305 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10306 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10307 addptr(buf, 64);
10308 subl(len, 4);
10309 jcc(Assembler::greater, L_fold_512b_loop);
10310
10311 // Fold 512 bits to 128 bits.
10312 BIND(L_fold_512b);
10313 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10314 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10315 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10316 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10317
10318 // Fold the rest of 128 bits data chunks
10319 BIND(L_fold_tail);
10320 addl(len, 3);
10321 jccb(Assembler::lessEqual, L_fold_128b);
10322 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10323
10324 BIND(L_fold_tail_loop);
10325 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10326 addptr(buf, 16);
10327 decrementl(len);
10328 jccb(Assembler::greater, L_fold_tail_loop);
10329
10330 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10331 BIND(L_fold_128b);
10332 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10333 if (UseAVX > 0) {
10334 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10335 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10336 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10337 } else {
10338 movdqa(xmm2, xmm0);
10339 pclmulqdq(xmm2, xmm1, 0x1);
10340 movdqa(xmm3, xmm0);
10341 pand(xmm3, xmm2);
10342 pclmulqdq(xmm0, xmm3, 0x1);
10343 }
10344 psrldq(xmm1, 8);
10345 psrldq(xmm2, 4);
10346 pxor(xmm0, xmm1);
10347 pxor(xmm0, xmm2);
10348
10349 // 8 8-bit folds to compute 32-bit CRC.
10350 for (int j = 0; j < 4; j++) {
10351 fold_8bit_crc32(xmm0, table, xmm1, rax);
10352 }
10353 movdl(crc, xmm0); // mov 32 bits to general register
10354 for (int j = 0; j < 4; j++) {
10355 fold_8bit_crc32(crc, table, rax);
10356 }
10357
10358 BIND(L_tail_restore);
10359 movl(len, tmp); // restore
10360 BIND(L_tail);
10361 andl(len, 0xf);
10362 jccb(Assembler::zero, L_exit);
10363
10364 // Fold the rest of bytes
10365 align(4);
10366 BIND(L_tail_loop);
10367 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10368 update_byte_crc32(crc, rax, table);
10369 increment(buf);
10370 decrementl(len);
10371 jccb(Assembler::greater, L_tail_loop);
10372
10373 BIND(L_exit);
10374 notl(crc); // ~c
10375 }
10376
10377 #ifdef _LP64
10378 // S. Gueron / Information Processing Letters 112 (2012) 184
10379 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10380 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10381 // Output: the 64-bit carry-less product of B * CONST
10382 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10383 Register tmp1, Register tmp2, Register tmp3) {
10384 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10385 if (n > 0) {
10386 addq(tmp3, n * 256 * 8);
10387 }
10388 // Q1 = TABLEExt[n][B & 0xFF];
10389 movl(tmp1, in);
10390 andl(tmp1, 0x000000FF);
10391 shll(tmp1, 3);
10392 addq(tmp1, tmp3);
10393 movq(tmp1, Address(tmp1, 0));
10394
10395 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10396 movl(tmp2, in);
10397 shrl(tmp2, 8);
10398 andl(tmp2, 0x000000FF);
10399 shll(tmp2, 3);
10400 addq(tmp2, tmp3);
10401 movq(tmp2, Address(tmp2, 0));
10402
10403 shlq(tmp2, 8);
10404 xorq(tmp1, tmp2);
10405
10406 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10407 movl(tmp2, in);
10408 shrl(tmp2, 16);
10409 andl(tmp2, 0x000000FF);
10410 shll(tmp2, 3);
10411 addq(tmp2, tmp3);
10412 movq(tmp2, Address(tmp2, 0));
10413
10414 shlq(tmp2, 16);
10415 xorq(tmp1, tmp2);
10416
10417 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10418 shrl(in, 24);
10419 andl(in, 0x000000FF);
10420 shll(in, 3);
10421 addq(in, tmp3);
10422 movq(in, Address(in, 0));
10423
10424 shlq(in, 24);
10425 xorq(in, tmp1);
10426 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10427 }
10428
10429 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10430 Register in_out,
10431 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10432 XMMRegister w_xtmp2,
10433 Register tmp1,
10434 Register n_tmp2, Register n_tmp3) {
10435 if (is_pclmulqdq_supported) {
10436 movdl(w_xtmp1, in_out); // modified blindly
10437
10438 movl(tmp1, const_or_pre_comp_const_index);
10439 movdl(w_xtmp2, tmp1);
10440 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10441
10442 movdq(in_out, w_xtmp1);
10443 } else {
10444 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10445 }
10446 }
10447
10448 // Recombination Alternative 2: No bit-reflections
10449 // T1 = (CRC_A * U1) << 1
10450 // T2 = (CRC_B * U2) << 1
10451 // C1 = T1 >> 32
10452 // C2 = T2 >> 32
10453 // T1 = T1 & 0xFFFFFFFF
10454 // T2 = T2 & 0xFFFFFFFF
10455 // T1 = CRC32(0, T1)
10456 // T2 = CRC32(0, T2)
10457 // C1 = C1 ^ T1
10458 // C2 = C2 ^ T2
10459 // CRC = C1 ^ C2 ^ CRC_C
10460 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10461 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10462 Register tmp1, Register tmp2,
10463 Register n_tmp3) {
10464 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10465 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10466 shlq(in_out, 1);
10467 movl(tmp1, in_out);
10468 shrq(in_out, 32);
10469 xorl(tmp2, tmp2);
10470 crc32(tmp2, tmp1, 4);
10471 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10472 shlq(in1, 1);
10473 movl(tmp1, in1);
10474 shrq(in1, 32);
10475 xorl(tmp2, tmp2);
10476 crc32(tmp2, tmp1, 4);
10477 xorl(in1, tmp2);
10478 xorl(in_out, in1);
10479 xorl(in_out, in2);
10480 }
10481
10482 // Set N to predefined value
10483 // Subtract from a lenght of a buffer
10484 // execute in a loop:
10485 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10486 // for i = 1 to N do
10487 // CRC_A = CRC32(CRC_A, A[i])
10488 // CRC_B = CRC32(CRC_B, B[i])
10489 // CRC_C = CRC32(CRC_C, C[i])
10490 // end for
10491 // Recombine
10492 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10493 Register in_out1, Register in_out2, Register in_out3,
10494 Register tmp1, Register tmp2, Register tmp3,
10495 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10496 Register tmp4, Register tmp5,
10497 Register n_tmp6) {
10498 Label L_processPartitions;
10499 Label L_processPartition;
10500 Label L_exit;
10501
10502 bind(L_processPartitions);
10503 cmpl(in_out1, 3 * size);
10504 jcc(Assembler::less, L_exit);
10505 xorl(tmp1, tmp1);
10506 xorl(tmp2, tmp2);
10507 movq(tmp3, in_out2);
10508 addq(tmp3, size);
10509
10510 bind(L_processPartition);
10511 crc32(in_out3, Address(in_out2, 0), 8);
10512 crc32(tmp1, Address(in_out2, size), 8);
10513 crc32(tmp2, Address(in_out2, size * 2), 8);
10514 addq(in_out2, 8);
10515 cmpq(in_out2, tmp3);
10516 jcc(Assembler::less, L_processPartition);
10517 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10518 w_xtmp1, w_xtmp2, w_xtmp3,
10519 tmp4, tmp5,
10520 n_tmp6);
10521 addq(in_out2, 2 * size);
10522 subl(in_out1, 3 * size);
10523 jmp(L_processPartitions);
10524
10525 bind(L_exit);
10526 }
10527 #else
10528 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10529 Register tmp1, Register tmp2, Register tmp3,
10530 XMMRegister xtmp1, XMMRegister xtmp2) {
10531 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10532 if (n > 0) {
10533 addl(tmp3, n * 256 * 8);
10534 }
10535 // Q1 = TABLEExt[n][B & 0xFF];
10536 movl(tmp1, in_out);
10537 andl(tmp1, 0x000000FF);
10538 shll(tmp1, 3);
10539 addl(tmp1, tmp3);
10540 movq(xtmp1, Address(tmp1, 0));
10541
10542 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10543 movl(tmp2, in_out);
10544 shrl(tmp2, 8);
10545 andl(tmp2, 0x000000FF);
10546 shll(tmp2, 3);
10547 addl(tmp2, tmp3);
10548 movq(xtmp2, Address(tmp2, 0));
10549
10550 psllq(xtmp2, 8);
10551 pxor(xtmp1, xtmp2);
10552
10553 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10554 movl(tmp2, in_out);
10555 shrl(tmp2, 16);
10556 andl(tmp2, 0x000000FF);
10557 shll(tmp2, 3);
10558 addl(tmp2, tmp3);
10559 movq(xtmp2, Address(tmp2, 0));
10560
10561 psllq(xtmp2, 16);
10562 pxor(xtmp1, xtmp2);
10563
10564 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10565 shrl(in_out, 24);
10566 andl(in_out, 0x000000FF);
10567 shll(in_out, 3);
10568 addl(in_out, tmp3);
10569 movq(xtmp2, Address(in_out, 0));
10570
10571 psllq(xtmp2, 24);
10572 pxor(xtmp1, xtmp2); // Result in CXMM
10573 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10574 }
10575
10576 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10577 Register in_out,
10578 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10579 XMMRegister w_xtmp2,
10580 Register tmp1,
10581 Register n_tmp2, Register n_tmp3) {
10582 if (is_pclmulqdq_supported) {
10583 movdl(w_xtmp1, in_out);
10584
10585 movl(tmp1, const_or_pre_comp_const_index);
10586 movdl(w_xtmp2, tmp1);
10587 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10588 // Keep result in XMM since GPR is 32 bit in length
10589 } else {
10590 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10591 }
10592 }
10593
10594 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10595 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10596 Register tmp1, Register tmp2,
10597 Register n_tmp3) {
10598 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10599 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10600
10601 psllq(w_xtmp1, 1);
10602 movdl(tmp1, w_xtmp1);
10603 psrlq(w_xtmp1, 32);
10604 movdl(in_out, w_xtmp1);
10605
10606 xorl(tmp2, tmp2);
10607 crc32(tmp2, tmp1, 4);
10608 xorl(in_out, tmp2);
10609
10610 psllq(w_xtmp2, 1);
10611 movdl(tmp1, w_xtmp2);
10612 psrlq(w_xtmp2, 32);
10613 movdl(in1, w_xtmp2);
10614
10615 xorl(tmp2, tmp2);
10616 crc32(tmp2, tmp1, 4);
10617 xorl(in1, tmp2);
10618 xorl(in_out, in1);
10619 xorl(in_out, in2);
10620 }
10621
10622 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10623 Register in_out1, Register in_out2, Register in_out3,
10624 Register tmp1, Register tmp2, Register tmp3,
10625 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10626 Register tmp4, Register tmp5,
10627 Register n_tmp6) {
10628 Label L_processPartitions;
10629 Label L_processPartition;
10630 Label L_exit;
10631
10632 bind(L_processPartitions);
10633 cmpl(in_out1, 3 * size);
10634 jcc(Assembler::less, L_exit);
10635 xorl(tmp1, tmp1);
10636 xorl(tmp2, tmp2);
10637 movl(tmp3, in_out2);
10638 addl(tmp3, size);
10639
10640 bind(L_processPartition);
10641 crc32(in_out3, Address(in_out2, 0), 4);
10642 crc32(tmp1, Address(in_out2, size), 4);
10643 crc32(tmp2, Address(in_out2, size*2), 4);
10644 crc32(in_out3, Address(in_out2, 0+4), 4);
10645 crc32(tmp1, Address(in_out2, size+4), 4);
10646 crc32(tmp2, Address(in_out2, size*2+4), 4);
10647 addl(in_out2, 8);
10648 cmpl(in_out2, tmp3);
10649 jcc(Assembler::less, L_processPartition);
10650
10651 push(tmp3);
10652 push(in_out1);
10653 push(in_out2);
10654 tmp4 = tmp3;
10655 tmp5 = in_out1;
10656 n_tmp6 = in_out2;
10657
10658 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10659 w_xtmp1, w_xtmp2, w_xtmp3,
10660 tmp4, tmp5,
10661 n_tmp6);
10662
10663 pop(in_out2);
10664 pop(in_out1);
10665 pop(tmp3);
10666
10667 addl(in_out2, 2 * size);
10668 subl(in_out1, 3 * size);
10669 jmp(L_processPartitions);
10670
10671 bind(L_exit);
10672 }
10673 #endif //LP64
10674
10675 #ifdef _LP64
10676 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10677 // Input: A buffer I of L bytes.
10678 // Output: the CRC32C value of the buffer.
10679 // Notations:
10680 // Write L = 24N + r, with N = floor (L/24).
10681 // r = L mod 24 (0 <= r < 24).
10682 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10683 // N quadwords, and R consists of r bytes.
10684 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10685 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10686 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10687 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10688 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10689 Register tmp1, Register tmp2, Register tmp3,
10690 Register tmp4, Register tmp5, Register tmp6,
10691 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10692 bool is_pclmulqdq_supported) {
10693 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10694 Label L_wordByWord;
10695 Label L_byteByByteProlog;
10696 Label L_byteByByte;
10697 Label L_exit;
10698
10699 if (is_pclmulqdq_supported ) {
10700 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10701 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10702
10703 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10704 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10705
10706 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10707 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10708 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10709 } else {
10710 const_or_pre_comp_const_index[0] = 1;
10711 const_or_pre_comp_const_index[1] = 0;
10712
10713 const_or_pre_comp_const_index[2] = 3;
10714 const_or_pre_comp_const_index[3] = 2;
10715
10716 const_or_pre_comp_const_index[4] = 5;
10717 const_or_pre_comp_const_index[5] = 4;
10718 }
10719 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10720 in2, in1, in_out,
10721 tmp1, tmp2, tmp3,
10722 w_xtmp1, w_xtmp2, w_xtmp3,
10723 tmp4, tmp5,
10724 tmp6);
10725 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10726 in2, in1, in_out,
10727 tmp1, tmp2, tmp3,
10728 w_xtmp1, w_xtmp2, w_xtmp3,
10729 tmp4, tmp5,
10730 tmp6);
10731 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10732 in2, in1, in_out,
10733 tmp1, tmp2, tmp3,
10734 w_xtmp1, w_xtmp2, w_xtmp3,
10735 tmp4, tmp5,
10736 tmp6);
10737 movl(tmp1, in2);
10738 andl(tmp1, 0x00000007);
10739 negl(tmp1);
10740 addl(tmp1, in2);
10741 addq(tmp1, in1);
10742
10743 BIND(L_wordByWord);
10744 cmpq(in1, tmp1);
10745 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10746 crc32(in_out, Address(in1, 0), 4);
10747 addq(in1, 4);
10748 jmp(L_wordByWord);
10749
10750 BIND(L_byteByByteProlog);
10751 andl(in2, 0x00000007);
10752 movl(tmp2, 1);
10753
10754 BIND(L_byteByByte);
10755 cmpl(tmp2, in2);
10756 jccb(Assembler::greater, L_exit);
10757 crc32(in_out, Address(in1, 0), 1);
10758 incq(in1);
10759 incl(tmp2);
10760 jmp(L_byteByByte);
10761
10762 BIND(L_exit);
10763 }
10764 #else
10765 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10766 Register tmp1, Register tmp2, Register tmp3,
10767 Register tmp4, Register tmp5, Register tmp6,
10768 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10769 bool is_pclmulqdq_supported) {
10770 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10771 Label L_wordByWord;
10772 Label L_byteByByteProlog;
10773 Label L_byteByByte;
10774 Label L_exit;
10775
10776 if (is_pclmulqdq_supported) {
10777 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10778 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10779
10780 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10781 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10782
10783 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10784 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10785 } else {
10786 const_or_pre_comp_const_index[0] = 1;
10787 const_or_pre_comp_const_index[1] = 0;
10788
10789 const_or_pre_comp_const_index[2] = 3;
10790 const_or_pre_comp_const_index[3] = 2;
10791
10792 const_or_pre_comp_const_index[4] = 5;
10793 const_or_pre_comp_const_index[5] = 4;
10794 }
10795 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10796 in2, in1, in_out,
10797 tmp1, tmp2, tmp3,
10798 w_xtmp1, w_xtmp2, w_xtmp3,
10799 tmp4, tmp5,
10800 tmp6);
10801 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10802 in2, in1, in_out,
10803 tmp1, tmp2, tmp3,
10804 w_xtmp1, w_xtmp2, w_xtmp3,
10805 tmp4, tmp5,
10806 tmp6);
10807 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10808 in2, in1, in_out,
10809 tmp1, tmp2, tmp3,
10810 w_xtmp1, w_xtmp2, w_xtmp3,
10811 tmp4, tmp5,
10812 tmp6);
10813 movl(tmp1, in2);
10814 andl(tmp1, 0x00000007);
10815 negl(tmp1);
10816 addl(tmp1, in2);
10817 addl(tmp1, in1);
10818
10819 BIND(L_wordByWord);
10820 cmpl(in1, tmp1);
10821 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10822 crc32(in_out, Address(in1,0), 4);
10823 addl(in1, 4);
10824 jmp(L_wordByWord);
10825
10826 BIND(L_byteByByteProlog);
10827 andl(in2, 0x00000007);
10828 movl(tmp2, 1);
10829
10830 BIND(L_byteByByte);
10831 cmpl(tmp2, in2);
10832 jccb(Assembler::greater, L_exit);
10833 movb(tmp1, Address(in1, 0));
10834 crc32(in_out, tmp1, 1);
10835 incl(in1);
10836 incl(tmp2);
10837 jmp(L_byteByByte);
10838
10839 BIND(L_exit);
10840 }
10841 #endif // LP64
10842 #undef BIND
10843 #undef BLOCK_COMMENT
10844
10845 // Compress char[] array to byte[].
10846 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10847 // @HotSpotIntrinsicCandidate
10848 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10849 // for (int i = 0; i < len; i++) {
10850 // int c = src[srcOff++];
10851 // if (c >>> 8 != 0) {
10852 // return 0;
10853 // }
10854 // dst[dstOff++] = (byte)c;
10855 // }
10856 // return len;
10857 // }
10858 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10859 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10860 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10861 Register tmp5, Register result) {
10862 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10863
10864 // rsi: src
10865 // rdi: dst
10866 // rdx: len
10867 // rcx: tmp5
10868 // rax: result
10869
10870 // rsi holds start addr of source char[] to be compressed
10871 // rdi holds start addr of destination byte[]
10872 // rdx holds length
10873
10874 assert(len != result, "");
10875
10876 // save length for return
10877 push(len);
10878
10879 if ((UseAVX > 2) && // AVX512
10880 VM_Version::supports_avx512vlbw() &&
10881 VM_Version::supports_bmi2()) {
10882
10883 set_vector_masking(); // opening of the stub context for programming mask registers
10884
10885 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10886
10887 // alignement
10888 Label post_alignement;
10889
10890 // if length of the string is less than 16, handle it in an old fashioned
10891 // way
10892 testl(len, -32);
10893 jcc(Assembler::zero, below_threshold);
10894
10895 // First check whether a character is compressable ( <= 0xFF).
10896 // Create mask to test for Unicode chars inside zmm vector
10897 movl(result, 0x00FF);
10898 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10899
10900 // Save k1
10901 kmovql(k3, k1);
10902
10903 testl(len, -64);
10904 jcc(Assembler::zero, post_alignement);
10905
10906 movl(tmp5, dst);
10907 andl(tmp5, (32 - 1));
10908 negl(tmp5);
10909 andl(tmp5, (32 - 1));
10910
10911 // bail out when there is nothing to be done
10912 testl(tmp5, 0xFFFFFFFF);
10913 jcc(Assembler::zero, post_alignement);
10914
10915 // ~(~0 << len), where len is the # of remaining elements to process
10916 movl(result, 0xFFFFFFFF);
10917 shlxl(result, result, tmp5);
10918 notl(result);
10919 kmovdl(k1, result);
10920
10921 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10922 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10923 ktestd(k2, k1);
10924 jcc(Assembler::carryClear, restore_k1_return_zero);
10925
10926 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10927
10928 addptr(src, tmp5);
10929 addptr(src, tmp5);
10930 addptr(dst, tmp5);
10931 subl(len, tmp5);
10932
10933 bind(post_alignement);
10934 // end of alignement
10935
10936 movl(tmp5, len);
10937 andl(tmp5, (32 - 1)); // tail count (in chars)
10938 andl(len, ~(32 - 1)); // vector count (in chars)
10939 jcc(Assembler::zero, copy_loop_tail);
10940
10941 lea(src, Address(src, len, Address::times_2));
10942 lea(dst, Address(dst, len, Address::times_1));
10943 negptr(len);
10944
10945 bind(copy_32_loop);
10946 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10947 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10948 kortestdl(k2, k2);
10949 jcc(Assembler::carryClear, restore_k1_return_zero);
10950
10951 // All elements in current processed chunk are valid candidates for
10952 // compression. Write a truncated byte elements to the memory.
10953 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10954 addptr(len, 32);
10955 jcc(Assembler::notZero, copy_32_loop);
10956
10957 bind(copy_loop_tail);
10958 // bail out when there is nothing to be done
10959 testl(tmp5, 0xFFFFFFFF);
10960 // Restore k1
10961 kmovql(k1, k3);
10962 jcc(Assembler::zero, return_length);
10963
10964 movl(len, tmp5);
10965
10966 // ~(~0 << len), where len is the # of remaining elements to process
10967 movl(result, 0xFFFFFFFF);
10968 shlxl(result, result, len);
10969 notl(result);
10970
10971 kmovdl(k1, result);
10972
10973 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10974 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10975 ktestd(k2, k1);
10976 jcc(Assembler::carryClear, restore_k1_return_zero);
10977
10978 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10979 // Restore k1
10980 kmovql(k1, k3);
10981 jmp(return_length);
10982
10983 bind(restore_k1_return_zero);
10984 // Restore k1
10985 kmovql(k1, k3);
10986 jmp(return_zero);
10987
10988 clear_vector_masking(); // closing of the stub context for programming mask registers
10989 }
10990 if (UseSSE42Intrinsics) {
10991 Label copy_32_loop, copy_16, copy_tail;
10992
10993 bind(below_threshold);
10994
10995 movl(result, len);
10996
10997 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10998
10999 // vectored compression
11000 andl(len, 0xfffffff0); // vector count (in chars)
11001 andl(result, 0x0000000f); // tail count (in chars)
11002 testl(len, len);
11003 jccb(Assembler::zero, copy_16);
11004
11005 // compress 16 chars per iter
11006 movdl(tmp1Reg, tmp5);
11007 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
11008 pxor(tmp4Reg, tmp4Reg);
11009
11010 lea(src, Address(src, len, Address::times_2));
11011 lea(dst, Address(dst, len, Address::times_1));
11012 negptr(len);
11013
11014 bind(copy_32_loop);
11015 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
11016 por(tmp4Reg, tmp2Reg);
11017 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
11018 por(tmp4Reg, tmp3Reg);
11019 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
11020 jcc(Assembler::notZero, return_zero);
11021 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
11022 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
11023 addptr(len, 16);
11024 jcc(Assembler::notZero, copy_32_loop);
11025
11026 // compress next vector of 8 chars (if any)
11027 bind(copy_16);
11028 movl(len, result);
11029 andl(len, 0xfffffff8); // vector count (in chars)
11030 andl(result, 0x00000007); // tail count (in chars)
11031 testl(len, len);
11032 jccb(Assembler::zero, copy_tail);
11033
11034 movdl(tmp1Reg, tmp5);
11035 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
11036 pxor(tmp3Reg, tmp3Reg);
11037
11038 movdqu(tmp2Reg, Address(src, 0));
11039 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
11040 jccb(Assembler::notZero, return_zero);
11041 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
11042 movq(Address(dst, 0), tmp2Reg);
11043 addptr(src, 16);
11044 addptr(dst, 8);
11045
11046 bind(copy_tail);
11047 movl(len, result);
11048 }
11049 // compress 1 char per iter
11050 testl(len, len);
11051 jccb(Assembler::zero, return_length);
11052 lea(src, Address(src, len, Address::times_2));
11053 lea(dst, Address(dst, len, Address::times_1));
11054 negptr(len);
11055
11056 bind(copy_chars_loop);
11057 load_unsigned_short(result, Address(src, len, Address::times_2));
11058 testl(result, 0xff00); // check if Unicode char
11059 jccb(Assembler::notZero, return_zero);
11060 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
11061 increment(len);
11062 jcc(Assembler::notZero, copy_chars_loop);
11063
11064 // if compression succeeded, return length
11065 bind(return_length);
11066 pop(result);
11067 jmpb(done);
11068
11069 // if compression failed, return 0
11070 bind(return_zero);
11071 xorl(result, result);
11072 addptr(rsp, wordSize);
11073
11074 bind(done);
11075 }
11076
11077 // Inflate byte[] array to char[].
11078 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11079 // @HotSpotIntrinsicCandidate
11080 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11081 // for (int i = 0; i < len; i++) {
11082 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11083 // }
11084 // }
11085 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11086 XMMRegister tmp1, Register tmp2) {
11087 Label copy_chars_loop, done, below_threshold;
11088 // rsi: src
11089 // rdi: dst
11090 // rdx: len
11091 // rcx: tmp2
11092
11093 // rsi holds start addr of source byte[] to be inflated
11094 // rdi holds start addr of destination char[]
11095 // rdx holds length
11096 assert_different_registers(src, dst, len, tmp2);
11097
11098 if ((UseAVX > 2) && // AVX512
11099 VM_Version::supports_avx512vlbw() &&
11100 VM_Version::supports_bmi2()) {
11101
11102 set_vector_masking(); // opening of the stub context for programming mask registers
11103
11104 Label copy_32_loop, copy_tail;
11105 Register tmp3_aliased = len;
11106
11107 // if length of the string is less than 16, handle it in an old fashioned
11108 // way
11109 testl(len, -16);
11110 jcc(Assembler::zero, below_threshold);
11111
11112 // In order to use only one arithmetic operation for the main loop we use
11113 // this pre-calculation
11114 movl(tmp2, len);
11115 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11116 andl(len, -32); // vector count
11117 jccb(Assembler::zero, copy_tail);
11118
11119 lea(src, Address(src, len, Address::times_1));
11120 lea(dst, Address(dst, len, Address::times_2));
11121 negptr(len);
11122
11123
11124 // inflate 32 chars per iter
11125 bind(copy_32_loop);
11126 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11127 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11128 addptr(len, 32);
11129 jcc(Assembler::notZero, copy_32_loop);
11130
11131 bind(copy_tail);
11132 // bail out when there is nothing to be done
11133 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11134 jcc(Assembler::zero, done);
11135
11136 // Save k1
11137 kmovql(k2, k1);
11138
11139 // ~(~0 << length), where length is the # of remaining elements to process
11140 movl(tmp3_aliased, -1);
11141 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11142 notl(tmp3_aliased);
11143 kmovdl(k1, tmp3_aliased);
11144 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11145 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11146
11147 // Restore k1
11148 kmovql(k1, k2);
11149 jmp(done);
11150
11151 clear_vector_masking(); // closing of the stub context for programming mask registers
11152 }
11153 if (UseSSE42Intrinsics) {
11154 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11155
11156 movl(tmp2, len);
11157
11158 if (UseAVX > 1) {
11159 andl(tmp2, (16 - 1));
11160 andl(len, -16);
11161 jccb(Assembler::zero, copy_new_tail);
11162 } else {
11163 andl(tmp2, 0x00000007); // tail count (in chars)
11164 andl(len, 0xfffffff8); // vector count (in chars)
11165 jccb(Assembler::zero, copy_tail);
11166 }
11167
11168 // vectored inflation
11169 lea(src, Address(src, len, Address::times_1));
11170 lea(dst, Address(dst, len, Address::times_2));
11171 negptr(len);
11172
11173 if (UseAVX > 1) {
11174 bind(copy_16_loop);
11175 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11176 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11177 addptr(len, 16);
11178 jcc(Assembler::notZero, copy_16_loop);
11179
11180 bind(below_threshold);
11181 bind(copy_new_tail);
11182 if ((UseAVX > 2) &&
11183 VM_Version::supports_avx512vlbw() &&
11184 VM_Version::supports_bmi2()) {
11185 movl(tmp2, len);
11186 } else {
11187 movl(len, tmp2);
11188 }
11189 andl(tmp2, 0x00000007);
11190 andl(len, 0xFFFFFFF8);
11191 jccb(Assembler::zero, copy_tail);
11192
11193 pmovzxbw(tmp1, Address(src, 0));
11194 movdqu(Address(dst, 0), tmp1);
11195 addptr(src, 8);
11196 addptr(dst, 2 * 8);
11197
11198 jmp(copy_tail, true);
11199 }
11200
11201 // inflate 8 chars per iter
11202 bind(copy_8_loop);
11203 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11204 movdqu(Address(dst, len, Address::times_2), tmp1);
11205 addptr(len, 8);
11206 jcc(Assembler::notZero, copy_8_loop);
11207
11208 bind(copy_tail);
11209 movl(len, tmp2);
11210
11211 cmpl(len, 4);
11212 jccb(Assembler::less, copy_bytes);
11213
11214 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11215 pmovzxbw(tmp1, tmp1);
11216 movq(Address(dst, 0), tmp1);
11217 subptr(len, 4);
11218 addptr(src, 4);
11219 addptr(dst, 8);
11220
11221 bind(copy_bytes);
11222 }
11223 testl(len, len);
11224 jccb(Assembler::zero, done);
11225 lea(src, Address(src, len, Address::times_1));
11226 lea(dst, Address(dst, len, Address::times_2));
11227 negptr(len);
11228
11229 // inflate 1 char per iter
11230 bind(copy_chars_loop);
11231 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11232 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11233 increment(len);
11234 jcc(Assembler::notZero, copy_chars_loop);
11235
11236 bind(done);
11237 }
11238
11239 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11240 switch (cond) {
11241 // Note some conditions are synonyms for others
11242 case Assembler::zero: return Assembler::notZero;
11243 case Assembler::notZero: return Assembler::zero;
11244 case Assembler::less: return Assembler::greaterEqual;
11245 case Assembler::lessEqual: return Assembler::greater;
11246 case Assembler::greater: return Assembler::lessEqual;
11247 case Assembler::greaterEqual: return Assembler::less;
11248 case Assembler::below: return Assembler::aboveEqual;
11249 case Assembler::belowEqual: return Assembler::above;
11250 case Assembler::above: return Assembler::belowEqual;
11251 case Assembler::aboveEqual: return Assembler::below;
11252 case Assembler::overflow: return Assembler::noOverflow;
11253 case Assembler::noOverflow: return Assembler::overflow;
11254 case Assembler::negative: return Assembler::positive;
11255 case Assembler::positive: return Assembler::negative;
11256 case Assembler::parity: return Assembler::noParity;
11257 case Assembler::noParity: return Assembler::parity;
11258 }
11259 ShouldNotReachHere(); return Assembler::overflow;
11260 }
11261
11262 SkipIfEqual::SkipIfEqual(
11263 MacroAssembler* masm, const bool* flag_addr, bool value) {
11264 _masm = masm;
11265 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11266 _masm->jcc(Assembler::equal, _label);
11267 }
11268
11269 SkipIfEqual::~SkipIfEqual() {
11270 _masm->bind(_label);
11271 }
11272
11273 // 32-bit Windows has its own fast-path implementation
11274 // of get_thread
11275 #if !defined(WIN32) || defined(_LP64)
11276
11277 // This is simply a call to Thread::current()
11278 void MacroAssembler::get_thread(Register thread) {
11279 if (thread != rax) {
11280 push(rax);
11281 }
11282 LP64_ONLY(push(rdi);)
11283 LP64_ONLY(push(rsi);)
11284 push(rdx);
11285 push(rcx);
11286 #ifdef _LP64
11287 push(r8);
11288 push(r9);
11289 push(r10);
11290 push(r11);
11291 #endif
11292
11293 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11294
11295 #ifdef _LP64
11296 pop(r11);
11297 pop(r10);
11298 pop(r9);
11299 pop(r8);
11300 #endif
11301 pop(rcx);
11302 pop(rdx);
11303 LP64_ONLY(pop(rsi);)
11304 LP64_ONLY(pop(rdi);)
11305 if (thread != rax) {
11306 mov(thread, rax);
11307 pop(rax);
11308 }
11309 }
11310
11311 #endif