src/hotspot/cpu/arm/templateTable_arm.cpp

*** 2961,2970 ****
--- 2961,2971 ----
    if (is_static) {
      __ ldr(Robj, Address(Rtemp,
               cp_base_offset + ConstantPoolCacheEntry::f1_offset()));
      const int mirror_offset = in_bytes(Klass::java_mirror_offset());
      __ ldr(Robj, Address(Robj, mirror_offset));
+     __ resolve_oop_handle(Robj);
    }
  }
  
  
  // Blows all volatile registers: R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR.