1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/jvm.h"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "utilities/align.hpp"
36 #include "utilities/defaultStream.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "vm_version_ppc.hpp"
39
40 # include <sys/sysinfo.h>
41
42 bool VM_Version::_is_determine_features_test_running = false;
43 uint64_t VM_Version::_dscr_val = 0;
44
45 #define MSG(flag) \
46 if (flag && !FLAG_IS_DEFAULT(flag)) \
47 jio_fprintf(defaultStream::error_stream(), \
48 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
49 " -XX:+" #flag " will be disabled!\n");
50
51 void VM_Version::initialize() {
52
53 // Test which instructions are supported and measure cache line size.
54 determine_features();
55
56 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
57 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
58 if (VM_Version::has_lqarx()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
60 } else if (VM_Version::has_popcntw()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
62 } else if (VM_Version::has_cmpb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
64 } else if (VM_Version::has_popcntb()) {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
66 } else {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
68 }
69 }
70
71 bool PowerArchitecturePPC64_ok = false;
72 switch (PowerArchitecturePPC64) {
73 case 8: if (!VM_Version::has_lqarx() ) break;
74 case 7: if (!VM_Version::has_popcntw()) break;
75 case 6: if (!VM_Version::has_cmpb() ) break;
76 case 5: if (!VM_Version::has_popcntb()) break;
77 case 0: PowerArchitecturePPC64_ok = true; break;
78 default: break;
79 }
80 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
81 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
82
83 // Power 8: Configure Data Stream Control Register.
84 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
85 config_dscr();
86 }
87
88 if (!UseSIGTRAP) {
89 MSG(TrapBasedICMissChecks);
90 MSG(TrapBasedNotEntrantChecks);
91 MSG(TrapBasedNullChecks);
92 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
94 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
95 }
96
97 #ifdef COMPILER2
98 if (!UseSIGTRAP) {
99 MSG(TrapBasedRangeChecks);
100 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
101 }
102
103 // On Power6 test for section size.
104 if (PowerArchitecturePPC64 == 6) {
105 determine_section_size();
106 // TODO: PPC port } else {
107 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
108 }
109
110 if (PowerArchitecturePPC64 >= 8) {
111 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
112 FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
113 }
114 } else {
115 if (SuperwordUseVSX) {
116 warning("SuperwordUseVSX specified, but needs at least Power8.");
117 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
118 }
119 }
120 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
121 #endif
122
123 // Create and print feature-string.
124 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
125 jio_snprintf(buf, sizeof(buf),
126 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
127 (has_fsqrt() ? " fsqrt" : ""),
128 (has_isel() ? " isel" : ""),
129 (has_lxarxeh() ? " lxarxeh" : ""),
130 (has_cmpb() ? " cmpb" : ""),
131 //(has_mftgpr()? " mftgpr" : ""),
132 (has_popcntb() ? " popcntb" : ""),
133 (has_popcntw() ? " popcntw" : ""),
134 (has_fcfids() ? " fcfids" : ""),
135 (has_vand() ? " vand" : ""),
136 (has_lqarx() ? " lqarx" : ""),
137 (has_vcipher() ? " aes" : ""),
138 (has_vpmsumb() ? " vpmsumb" : ""),
139 (has_tcheck() ? " tcheck" : ""),
140 (has_mfdscr() ? " mfdscr" : ""),
141 (has_vsx() ? " vsx" : ""),
142 (has_ldbrx() ? " ldbrx" : ""),
143 (has_stdbrx() ? " stdbrx" : ""),
144 (has_vshasig() ? " sha" : "")
145 // Make sure number of %s matches num_features!
146 );
147 _features_string = os::strdup(buf);
148 if (Verbose) {
149 print_features();
150 }
151
152 // PPC64 supports 8-byte compare-exchange operations (see
153 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
154 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
155 _supports_cx8 = true;
156
157 // Used by C1.
158 _supports_atomic_getset4 = true;
159 _supports_atomic_getadd4 = true;
160 _supports_atomic_getset8 = true;
161 _supports_atomic_getadd8 = true;
162
163 UseSSE = 0; // Only on x86 and x64
164
165 intx cache_line_size = L1_data_cache_line_size();
166
167 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
168
169 if (AllocatePrefetchStyle == 4) {
170 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
171 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
172 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
173 } else {
174 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
175 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
176 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
177 }
178
179 assert(AllocatePrefetchLines > 0, "invalid value");
180 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
181 AllocatePrefetchLines = 1; // Conservative value.
182 }
183
184 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
185 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
186 }
187
188 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
189
190 // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware,
191 // the implementation uses the vector instructions available with Power8.
192 // In all other cases, the implementation uses only generally available instructions.
193 if (!UseCRC32Intrinsics) {
194 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
195 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
196 }
197 }
198
199 // Implementation does not use any of the vector instructions available with Power8.
200 // Their exploitation is still pending (aka "work in progress").
201 if (!UseCRC32CIntrinsics) {
202 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
203 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
204 }
205 }
206
207 // TODO: Provide implementation.
208 if (UseAdler32Intrinsics) {
209 warning("Adler32Intrinsics not available on this CPU.");
210 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
211 }
212
213 // The AES intrinsic stubs require AES instruction support.
214 if (has_vcipher()) {
215 if (FLAG_IS_DEFAULT(UseAES)) {
216 UseAES = true;
217 }
218 } else if (UseAES) {
219 if (!FLAG_IS_DEFAULT(UseAES))
220 warning("AES instructions are not available on this CPU");
221 FLAG_SET_DEFAULT(UseAES, false);
222 }
223
224 if (UseAES && has_vcipher()) {
225 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
226 UseAESIntrinsics = true;
227 }
228 } else if (UseAESIntrinsics) {
229 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
230 warning("AES intrinsics are not available on this CPU");
231 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
232 }
233
234 if (UseAESCTRIntrinsics) {
235 warning("AES/CTR intrinsics are not available on this CPU");
236 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
237 }
238
239 if (UseGHASHIntrinsics) {
240 warning("GHASH intrinsics are not available on this CPU");
241 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
242 }
243
244 if (FLAG_IS_DEFAULT(UseFMA)) {
245 FLAG_SET_DEFAULT(UseFMA, true);
246 }
247
248 if (has_vshasig()) {
249 if (FLAG_IS_DEFAULT(UseSHA)) {
250 UseSHA = true;
251 }
252 } else if (UseSHA) {
253 if (!FLAG_IS_DEFAULT(UseSHA))
254 warning("SHA instructions are not available on this CPU");
255 FLAG_SET_DEFAULT(UseSHA, false);
256 }
257
258 if (UseSHA1Intrinsics) {
259 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
260 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
261 }
262
263 if (UseSHA && has_vshasig()) {
264 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
265 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
266 }
267 } else if (UseSHA256Intrinsics) {
268 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
269 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
270 }
271
272 if (UseSHA && has_vshasig()) {
273 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
274 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
275 }
276 } else if (UseSHA512Intrinsics) {
277 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
278 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
279 }
280
281 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
282 FLAG_SET_DEFAULT(UseSHA, false);
283 }
284
285 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
286 UseSquareToLenIntrinsic = true;
287 }
288 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
289 UseMulAddIntrinsic = true;
290 }
291 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
292 UseMultiplyToLenIntrinsic = true;
293 }
294 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
295 UseMontgomeryMultiplyIntrinsic = true;
296 }
297 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
298 UseMontgomerySquareIntrinsic = true;
299 }
300
301 if (UseVectorizedMismatchIntrinsic) {
302 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
303 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
304 }
305
306
307 // Adjust RTM (Restricted Transactional Memory) flags.
308 if (UseRTMLocking) {
309 // If CPU or OS are too old:
310 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
311 // setting during arguments processing. See use_biased_locking().
312 // VM_Version_init() is executed after UseBiasedLocking is used
313 // in Thread::allocate().
314 if (!has_tcheck()) {
315 vm_exit_during_initialization("RTM instructions are not available on this CPU");
316 }
317 bool os_too_old = true;
318 #ifdef AIX
319 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
320 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
321 // The Java property os.version, which is used in RTM tests to decide
322 // whether the feature is available, only knows major and minor versions.
323 // We don't want to change this property, as user code might depend on it.
324 // So the tests can not check on subversion 3.30, and we only enable RTM
325 // with AIX 7.2.
326 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
327 os_too_old = false;
328 }
329 #endif
330 #ifdef LINUX
331 // At least Linux kernel 4.2, as the problematic behavior of syscalls
332 // being called in the middle of a transaction has been addressed.
333 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
334 // in Linux kernel source tree: https://goo.gl/Kc5i7A
335 if (os::Linux::os_version_is_known()) {
336 if (os::Linux::os_version() >= 0x040200)
337 os_too_old = false;
338 } else {
339 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
340 }
341 #endif
342 if (os_too_old) {
343 vm_exit_during_initialization("RTM is not supported on this OS version.");
344 }
345 }
346
347 if (UseRTMLocking) {
348 #if INCLUDE_RTM_OPT
349 if (!UnlockExperimentalVMOptions) {
350 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
351 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
352 } else {
353 warning("UseRTMLocking is only available as experimental option on this platform.");
354 }
355 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
356 // RTM locking should be used only for applications with
357 // high lock contention. For now we do not use it by default.
358 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
359 }
360 #else
361 // Only C2 does RTM locking optimization.
362 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
363 // setting during arguments processing. See use_biased_locking().
364 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
365 #endif
366 } else { // !UseRTMLocking
367 if (UseRTMForStackLocks) {
368 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
369 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
370 }
371 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
372 }
373 if (UseRTMDeopt) {
374 FLAG_SET_DEFAULT(UseRTMDeopt, false);
375 }
376 if (PrintPreciseRTMLockingStatistics) {
377 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
378 }
379 }
380
381 // This machine allows unaligned memory accesses
382 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
383 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
384 }
385 }
386
387 bool VM_Version::use_biased_locking() {
388 #if INCLUDE_RTM_OPT
389 // RTM locking is most useful when there is high lock contention and
390 // low data contention. With high lock contention the lock is usually
391 // inflated and biased locking is not suitable for that case.
392 // RTM locking code requires that biased locking is off.
393 // Note: we can't switch off UseBiasedLocking in get_processor_features()
394 // because it is used by Thread::allocate() which is called before
395 // VM_Version::initialize().
396 if (UseRTMLocking && UseBiasedLocking) {
397 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
398 FLAG_SET_DEFAULT(UseBiasedLocking, false);
399 } else {
400 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
401 UseBiasedLocking = false;
402 }
403 }
404 #endif
405 return UseBiasedLocking;
406 }
407
408 void VM_Version::print_features() {
409 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
410 }
411
412 #ifdef COMPILER2
413 // Determine section size on power6: If section size is 8 instructions,
414 // there should be a difference between the two testloops of ~15 %. If
415 // no difference is detected the section is assumed to be 32 instructions.
416 void VM_Version::determine_section_size() {
417
418 int unroll = 80;
419
420 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
421
422 // Allocate space for the code.
423 ResourceMark rm;
424 CodeBuffer cb("detect_section_size", code_size, 0);
425 MacroAssembler* a = new MacroAssembler(&cb);
426
427 uint32_t *code = (uint32_t *)a->pc();
428 // Emit code.
429 void (*test1)() = (void(*)())(void *)a->function_entry();
430
431 Label l1;
432
433 a->li(R4, 1);
434 a->sldi(R4, R4, 28);
435 a->b(l1);
436 a->align(CodeEntryAlignment);
437
438 a->bind(l1);
439
440 for (int i = 0; i < unroll; i++) {
441 // Schleife 1
442 // ------- sector 0 ------------
443 // ;; 0
444 a->nop(); // 1
445 a->fpnop0(); // 2
446 a->fpnop1(); // 3
447 a->addi(R4,R4, -1); // 4
448
449 // ;; 1
450 a->nop(); // 5
451 a->fmr(F6, F6); // 6
452 a->fmr(F7, F7); // 7
453 a->endgroup(); // 8
454 // ------- sector 8 ------------
455
456 // ;; 2
457 a->nop(); // 9
458 a->nop(); // 10
459 a->fmr(F8, F8); // 11
460 a->fmr(F9, F9); // 12
461
462 // ;; 3
463 a->nop(); // 13
464 a->fmr(F10, F10); // 14
465 a->fmr(F11, F11); // 15
466 a->endgroup(); // 16
467 // -------- sector 16 -------------
468
469 // ;; 4
470 a->nop(); // 17
471 a->nop(); // 18
472 a->fmr(F15, F15); // 19
473 a->fmr(F16, F16); // 20
474
475 // ;; 5
476 a->nop(); // 21
477 a->fmr(F17, F17); // 22
478 a->fmr(F18, F18); // 23
479 a->endgroup(); // 24
480 // ------- sector 24 ------------
481
482 // ;; 6
483 a->nop(); // 25
484 a->nop(); // 26
485 a->fmr(F19, F19); // 27
486 a->fmr(F20, F20); // 28
487
488 // ;; 7
489 a->nop(); // 29
490 a->fmr(F21, F21); // 30
491 a->fmr(F22, F22); // 31
492 a->brnop0(); // 32
493
494 // ------- sector 32 ------------
495 }
496
497 // ;; 8
498 a->cmpdi(CCR0, R4, unroll); // 33
499 a->bge(CCR0, l1); // 34
500 a->blr();
501
502 // Emit code.
503 void (*test2)() = (void(*)())(void *)a->function_entry();
504 // uint32_t *code = (uint32_t *)a->pc();
505
506 Label l2;
507
508 a->li(R4, 1);
509 a->sldi(R4, R4, 28);
510 a->b(l2);
511 a->align(CodeEntryAlignment);
512
513 a->bind(l2);
514
515 for (int i = 0; i < unroll; i++) {
516 // Schleife 2
517 // ------- sector 0 ------------
518 // ;; 0
519 a->brnop0(); // 1
520 a->nop(); // 2
521 //a->cmpdi(CCR0, R4, unroll);
522 a->fpnop0(); // 3
523 a->fpnop1(); // 4
524 a->addi(R4,R4, -1); // 5
525
526 // ;; 1
527
528 a->nop(); // 6
529 a->fmr(F6, F6); // 7
530 a->fmr(F7, F7); // 8
531 // ------- sector 8 ---------------
532
533 // ;; 2
534 a->endgroup(); // 9
535
536 // ;; 3
537 a->nop(); // 10
538 a->nop(); // 11
539 a->fmr(F8, F8); // 12
540
541 // ;; 4
542 a->fmr(F9, F9); // 13
543 a->nop(); // 14
544 a->fmr(F10, F10); // 15
545
546 // ;; 5
547 a->fmr(F11, F11); // 16
548 // -------- sector 16 -------------
549
550 // ;; 6
551 a->endgroup(); // 17
552
553 // ;; 7
554 a->nop(); // 18
555 a->nop(); // 19
556 a->fmr(F15, F15); // 20
557
558 // ;; 8
559 a->fmr(F16, F16); // 21
560 a->nop(); // 22
561 a->fmr(F17, F17); // 23
562
563 // ;; 9
564 a->fmr(F18, F18); // 24
565 // -------- sector 24 -------------
566
567 // ;; 10
568 a->endgroup(); // 25
569
570 // ;; 11
571 a->nop(); // 26
572 a->nop(); // 27
573 a->fmr(F19, F19); // 28
574
575 // ;; 12
576 a->fmr(F20, F20); // 29
577 a->nop(); // 30
578 a->fmr(F21, F21); // 31
579
580 // ;; 13
581 a->fmr(F22, F22); // 32
582 }
583
584 // -------- sector 32 -------------
585 // ;; 14
586 a->cmpdi(CCR0, R4, unroll); // 33
587 a->bge(CCR0, l2); // 34
588
589 a->blr();
590 uint32_t *code_end = (uint32_t *)a->pc();
591 a->flush();
592
593 double loop1_seconds,loop2_seconds, rel_diff;
594 uint64_t start1, stop1;
595
596 start1 = os::current_thread_cpu_time(false);
597 (*test1)();
598 stop1 = os::current_thread_cpu_time(false);
599 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
600
601
602 start1 = os::current_thread_cpu_time(false);
603 (*test2)();
604 stop1 = os::current_thread_cpu_time(false);
605
606 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
607
608 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
609
610 if (PrintAssembly) {
611 ttyLocker ttyl;
612 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
613 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
614 tty->print_cr("Time loop1 :%f", loop1_seconds);
615 tty->print_cr("Time loop2 :%f", loop2_seconds);
616 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
617
618 if (rel_diff > 12.0) {
619 tty->print_cr("Section Size 8 Instructions");
620 } else{
621 tty->print_cr("Section Size 32 Instructions or Power5");
622 }
623 }
624
625 #if 0 // TODO: PPC port
626 // Set sector size (if not set explicitly).
627 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
628 if (rel_diff > 12.0) {
629 PdScheduling::power6SectorSize = 0x20;
630 } else {
631 PdScheduling::power6SectorSize = 0x80;
632 }
633 } else if (Power6SectorSize128PPC64) {
634 PdScheduling::power6SectorSize = 0x80;
635 } else {
636 PdScheduling::power6SectorSize = 0x20;
637 }
638 #endif
639 if (UsePower6SchedulerPPC64) Unimplemented();
640 }
641 #endif // COMPILER2
642
643 void VM_Version::determine_features() {
644 #if defined(ABI_ELFv2)
645 // 1 InstWord per call for the blr instruction.
646 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
647 #else
648 // 7 InstWords for each call (function descriptor + blr instruction).
649 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
650 #endif
651 int features = 0;
652
653 // create test area
654 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
655 char test_area[BUFFER_SIZE];
656 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
657
658 // Allocate space for the code.
659 ResourceMark rm;
660 CodeBuffer cb("detect_cpu_features", code_size, 0);
661 MacroAssembler* a = new MacroAssembler(&cb);
662
663 // Must be set to true so we can generate the test code.
664 _features = VM_Version::all_features_m;
665
666 // Emit code.
667 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
668 uint32_t *code = (uint32_t *)a->pc();
669 // Don't use R0 in ldarx.
670 // Keep R3_ARG1 unmodified, it contains &field (see below).
671 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
672 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
673 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
674 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
675 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
676 a->cmpb(R7, R5, R6); // code[4] -> cmpb
677 a->popcntb(R7, R5); // code[5] -> popcntb
678 a->popcntw(R7, R5); // code[6] -> popcntw
679 a->fcfids(F3, F4); // code[7] -> fcfids
680 a->vand(VR0, VR0, VR0); // code[8] -> vand
681 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
682 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
683 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
684 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
685 a->tcheck(0); // code[12] -> tcheck
686 a->mfdscr(R0); // code[13] -> mfdscr
687 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
688 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> ldbrx
689 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[16] -> stdbrx
690 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[17] -> vshasig
691 a->blr();
692
693 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
694 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
695 a->dcbz(R3_ARG1); // R3_ARG1 = addr
696 a->blr();
697
698 uint32_t *code_end = (uint32_t *)a->pc();
699 a->flush();
700 _features = VM_Version::unknown_m;
701
702 // Print the detection code.
703 if (PrintAssembly) {
704 ttyLocker ttyl;
705 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
706 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
707 }
708
709 // Measure cache line size.
710 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
711 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
712 int count = 0; // count zeroed bytes
713 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
714 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
715 _L1_data_cache_line_size = count;
716
717 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
718 VM_Version::_is_determine_features_test_running = true;
719 // We must align the first argument to 16 bytes because of the lqarx check.
720 (*test)(align_up((address)mid_of_test_area, 16), 0);
721 VM_Version::_is_determine_features_test_running = false;
722
723 // determine which instructions are legal.
724 int feature_cntr = 0;
725 if (code[feature_cntr++]) features |= fsqrt_m;
726 if (code[feature_cntr++]) features |= fsqrts_m;
727 if (code[feature_cntr++]) features |= isel_m;
728 if (code[feature_cntr++]) features |= lxarxeh_m;
729 if (code[feature_cntr++]) features |= cmpb_m;
730 if (code[feature_cntr++]) features |= popcntb_m;
731 if (code[feature_cntr++]) features |= popcntw_m;
732 if (code[feature_cntr++]) features |= fcfids_m;
733 if (code[feature_cntr++]) features |= vand_m;
734 if (code[feature_cntr++]) features |= lqarx_m;
735 if (code[feature_cntr++]) features |= vcipher_m;
736 if (code[feature_cntr++]) features |= vpmsumb_m;
737 if (code[feature_cntr++]) features |= tcheck_m;
738 if (code[feature_cntr++]) features |= mfdscr_m;
739 if (code[feature_cntr++]) features |= vsx_m;
740 if (code[feature_cntr++]) features |= ldbrx_m;
741 if (code[feature_cntr++]) features |= stdbrx_m;
742 if (code[feature_cntr++]) features |= vshasig_m;
743
744 // Print the detection code.
745 if (PrintAssembly) {
746 ttyLocker ttyl;
747 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
748 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
749 }
750
751 _features = features;
752 }
753
754 // Power 8: Configure Data Stream Control Register.
755 void VM_Version::config_dscr() {
756 // 7 InstWords for each call (function descriptor + blr instruction).
757 const int code_size = (2+2*7)*BytesPerInstWord;
758
759 // Allocate space for the code.
760 ResourceMark rm;
761 CodeBuffer cb("config_dscr", code_size, 0);
762 MacroAssembler* a = new MacroAssembler(&cb);
763
764 // Emit code.
765 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
766 uint32_t *code = (uint32_t *)a->pc();
767 a->mfdscr(R3);
768 a->blr();
769
770 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
771 a->mtdscr(R3);
772 a->blr();
773
774 uint32_t *code_end = (uint32_t *)a->pc();
775 a->flush();
776
777 // Print the detection code.
778 if (PrintAssembly) {
779 ttyLocker ttyl;
780 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
781 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
782 }
783
784 // Apply the configuration if needed.
785 _dscr_val = (*get_dscr)();
786 if (Verbose) {
787 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
788 }
789 bool change_requested = false;
790 if (DSCR_PPC64 != (uintx)-1) {
791 _dscr_val = DSCR_PPC64;
792 change_requested = true;
793 }
794 if (DSCR_DPFD_PPC64 <= 7) {
795 uint64_t mask = 0x7;
796 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
797 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
798 change_requested = true;
799 }
800 }
801 if (DSCR_URG_PPC64 <= 7) {
802 uint64_t mask = 0x7 << 6;
803 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
804 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
805 change_requested = true;
806 }
807 }
808 if (change_requested) {
809 (*set_dscr)(_dscr_val);
810 if (Verbose) {
811 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
812 }
813 }
814 }
815
816 static uint64_t saved_features = 0;
817
818 void VM_Version::allow_all() {
819 saved_features = _features;
820 _features = all_features_m;
821 }
822
823 void VM_Version::revert() {
824 _features = saved_features;
825 }