1 /*
2 * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "prims/jvm.h"
29 #include "runtime/java.hpp"
30 #include "runtime/os.inline.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_arm.hpp"
33
34 int VM_Version::_stored_pc_adjustment = 4;
35 int VM_Version::_arm_arch = 5;
36 bool VM_Version::_is_initialized = false;
37 int VM_Version::_kuser_helper_version = 0;
38
39 extern "C" {
40 typedef int (*get_cpu_info_t)();
41 typedef bool (*check_vfp_t)(double *d);
42 typedef bool (*check_simd_t)();
43 }
44
45 #define __ _masm->
46
47 class VM_Version_StubGenerator: public StubCodeGenerator {
48 public:
49
50 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
51
52 address generate_get_cpu_info() {
53 StubCodeMark mark(this, "VM_Version", "get_cpu_info");
54 address start = __ pc();
55
56 __ mov(R0, PC);
57 __ push(PC);
58 __ pop(R1);
59 __ sub(R0, R1, R0);
60 // return the result in R0
61 __ bx(LR);
62
63 return start;
64 };
65
66 address generate_check_vfp() {
67 StubCodeMark mark(this, "VM_Version", "check_vfp");
68 address start = __ pc();
69
70 __ fstd(D0, Address(R0));
71 __ mov(R0, 1);
72 __ bx(LR);
73
74 return start;
75 };
76
77 address generate_check_vfp3_32() {
78 StubCodeMark mark(this, "VM_Version", "check_vfp3_32");
79 address start = __ pc();
80
81 __ fstd(D16, Address(R0));
82 __ mov(R0, 1);
83 __ bx(LR);
84
85 return start;
86 };
87
88 address generate_check_simd() {
89 StubCodeMark mark(this, "VM_Version", "check_simd");
90 address start = __ pc();
91
92 __ vcnt(Stemp, Stemp);
93 __ mov(R0, 1);
94 __ bx(LR);
95
96 return start;
97 };
98 };
99
100 #undef __
101
102
103 extern "C" address check_vfp3_32_fault_instr;
104 extern "C" address check_vfp_fault_instr;
105 extern "C" address check_simd_fault_instr;
106
107 void VM_Version::initialize() {
108 ResourceMark rm;
109
110 // Making this stub must be FIRST use of assembler
111 const int stub_size = 128;
112 BufferBlob* stub_blob = BufferBlob::create("get_cpu_info", stub_size);
113 if (stub_blob == NULL) {
114 vm_exit_during_initialization("Unable to allocate get_cpu_info stub");
115 }
116
117 CodeBuffer c(stub_blob);
118 VM_Version_StubGenerator g(&c);
119 address get_cpu_info_pc = g.generate_get_cpu_info();
120 get_cpu_info_t get_cpu_info = CAST_TO_FN_PTR(get_cpu_info_t, get_cpu_info_pc);
121
122 int pc_adjustment = get_cpu_info();
123
124 VM_Version::_stored_pc_adjustment = pc_adjustment;
125
126 #ifndef __SOFTFP__
127 address check_vfp_pc = g.generate_check_vfp();
128 check_vfp_t check_vfp = CAST_TO_FN_PTR(check_vfp_t, check_vfp_pc);
129
130 check_vfp_fault_instr = (address)check_vfp;
131 double dummy;
132 if (check_vfp(&dummy)) {
133 _features |= vfp_m;
134 }
135
136 #ifdef COMPILER2
137 if (has_vfp()) {
138 address check_vfp3_32_pc = g.generate_check_vfp3_32();
139 check_vfp_t check_vfp3_32 = CAST_TO_FN_PTR(check_vfp_t, check_vfp3_32_pc);
140 check_vfp3_32_fault_instr = (address)check_vfp3_32;
141 double dummy;
142 if (check_vfp3_32(&dummy)) {
143 _features |= vfp3_32_m;
144 }
145
146 address check_simd_pc =g.generate_check_simd();
147 check_simd_t check_simd = CAST_TO_FN_PTR(check_simd_t, check_simd_pc);
148 check_simd_fault_instr = (address)check_simd;
149 if (check_simd()) {
150 _features |= simd_m;
151 }
152 }
153 #endif
154 #endif
155
156
157 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
158 warning("AES intrinsics are not available on this CPU");
159 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
160 }
161
162 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
163 warning("AES instructions are not available on this CPU");
164 FLAG_SET_DEFAULT(UseAES, false);
165 }
166
167 if (UseAESCTRIntrinsics) {
168 warning("AES/CTR intrinsics are not available on this CPU");
169 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
170 }
171
172 if (UseFMA) {
173 warning("FMA instructions are not available on this CPU");
174 FLAG_SET_DEFAULT(UseFMA, false);
175 }
176
177 if (UseSHA) {
178 warning("SHA instructions are not available on this CPU");
179 FLAG_SET_DEFAULT(UseSHA, false);
180 }
181
182 if (UseSHA1Intrinsics) {
183 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
184 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
185 }
186
187 if (UseSHA256Intrinsics) {
188 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
189 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
190 }
191
192 if (UseSHA512Intrinsics) {
193 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
194 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
195 }
196
197 if (UseCRC32Intrinsics) {
198 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
199 warning("CRC32 intrinsics are not available on this CPU");
200 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
201 }
202
203 if (UseCRC32CIntrinsics) {
204 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
205 warning("CRC32C intrinsics are not available on this CPU");
206 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
207 }
208
209 if (UseAdler32Intrinsics) {
210 warning("Adler32 intrinsics are not available on this CPU");
211 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
212 }
213
214 if (UseVectorizedMismatchIntrinsic) {
215 warning("vectorizedMismatch intrinsic is not available on this CPU.");
216 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
217 }
218
219 get_os_cpu_info();
220
221 _kuser_helper_version = *(int*)KUSER_HELPER_VERSION_ADDR;
222
223 #ifdef COMPILER2
224 // C2 is only supported on v7+ VFP at this time
225 if (_arm_arch < 7 || !has_vfp()) {
226 vm_exit_during_initialization("Server VM is only supported on ARMv7+ VFP");
227 }
228 #endif
229
230 // armv7 has the ldrexd instruction that can be used to implement cx8
231 // armv5 with linux >= 3.1 can use kernel helper routine
232 _supports_cx8 = (supports_ldrexd() || supports_kuser_cmpxchg64());
233 // ARM doesn't have special instructions for these but ldrex/ldrexd
234 // enable shorter instruction sequences that the ones based on cas.
235 _supports_atomic_getset4 = supports_ldrex();
236 _supports_atomic_getadd4 = supports_ldrex();
237 _supports_atomic_getset8 = supports_ldrexd();
238 _supports_atomic_getadd8 = supports_ldrexd();
239
240 #ifdef COMPILER2
241 assert(_supports_cx8 && _supports_atomic_getset4 && _supports_atomic_getadd4
242 && _supports_atomic_getset8 && _supports_atomic_getadd8, "C2: atomic operations must be supported");
243 #endif
244 char buf[512];
245 jio_snprintf(buf, sizeof(buf), "(ARMv%d)%s%s%s",
246 _arm_arch,
247 (has_vfp() ? ", vfp" : ""),
248 (has_vfp3_32() ? ", vfp3-32" : ""),
249 (has_simd() ? ", simd" : ""));
250
251 // buf is started with ", " or is empty
252 _features_string = os::strdup(buf);
253
254 if (has_simd()) {
255 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
256 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
257 }
258 }
259
260 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
261 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 128);
262 }
263
264 #ifdef COMPILER2
265 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
266
267 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
268 // FLAG_SET_DEFAULT(MaxVectorSize, has_simd() ? 16 : 8);
269 // SIMD/NEON can use 16, but default is 8 because currently
270 // larger than 8 will disable instruction scheduling
271 FLAG_SET_DEFAULT(MaxVectorSize, 8);
272 }
273
274 if (MaxVectorSize > 16) {
275 FLAG_SET_DEFAULT(MaxVectorSize, 8);
276 }
277 #endif
278
279 if (FLAG_IS_DEFAULT(Tier4CompileThreshold)) {
280 Tier4CompileThreshold = 10000;
281 }
282 if (FLAG_IS_DEFAULT(Tier3InvocationThreshold)) {
283 Tier3InvocationThreshold = 1000;
284 }
285 if (FLAG_IS_DEFAULT(Tier3CompileThreshold)) {
286 Tier3CompileThreshold = 5000;
287 }
288 if (FLAG_IS_DEFAULT(Tier3MinInvocationThreshold)) {
289 Tier3MinInvocationThreshold = 500;
290 }
291
292 FLAG_SET_DEFAULT(TypeProfileLevel, 0); // unsupported
293
294 // This machine does not allow unaligned memory accesses
295 if (UseUnalignedAccesses) {
296 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
297 warning("Unaligned memory access is not available on this CPU");
298 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
299 }
300
301 _is_initialized = true;
302 }
303
304 bool VM_Version::use_biased_locking() {
305 get_os_cpu_info();
306 // The cost of CAS on uniprocessor ARM v6 and later is low compared to the
307 // overhead related to slightly longer Biased Locking execution path.
308 // Testing shows no improvement when running with Biased Locking enabled
309 // on an ARMv6 and higher uniprocessor systems. The situation is different on
310 // ARMv5 and MP systems.
311 //
312 // Therefore the Biased Locking is enabled on ARMv5 and ARM MP only.
313 //
314 return (!os::is_MP() && (arm_arch() > 5)) ? false : true;
315 }
316
317 #define EXP
318
319 // Temporary override for experimental features
320 // Copied from Abstract_VM_Version
321 const char* VM_Version::vm_info_string() {
322 switch (Arguments::mode()) {
323 case Arguments::_int:
324 return UseSharedSpaces ? "interpreted mode, sharing" EXP : "interpreted mode" EXP;
325 case Arguments::_mixed:
326 return UseSharedSpaces ? "mixed mode, sharing" EXP : "mixed mode" EXP;
327 case Arguments::_comp:
328 return UseSharedSpaces ? "compiled mode, sharing" EXP : "compiled mode" EXP;
329 };
330 ShouldNotReachHere();
331 return "";
332 }