1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/cardTableModRefBS.hpp"
31 #include "gc/shared/collectedHeap.inline.hpp"
32 #include "interpreter/interpreter.hpp"
33 #include "memory/resourceArea.hpp"
34 #include "memory/universe.hpp"
35 #include "oops/klass.inline.hpp"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "runtime/thread.hpp"
44 #include "utilities/macros.hpp"
45 #if INCLUDE_ALL_GCS
46 #include "gc/g1/g1CollectedHeap.inline.hpp"
47 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
48 #include "gc/g1/heapRegion.hpp"
49 #endif // INCLUDE_ALL_GCS
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::extend_sign(Register hi, Register lo) {
130 // According to Intel Doc. AP-526, "Integer Divide", p.18.
131 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
132 cdql();
133 } else {
134 movl(hi, lo);
135 sarl(hi, 31);
136 }
137 }
138
139 void MacroAssembler::jC2(Register tmp, Label& L) {
140 // set parity bit if FPU flag C2 is set (via rax)
141 save_rax(tmp);
142 fwait(); fnstsw_ax();
143 sahf();
144 restore_rax(tmp);
145 // branch
146 jcc(Assembler::parity, L);
147 }
148
149 void MacroAssembler::jnC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::noParity, L);
157 }
158
159 // 32bit can do a case table jump in one instruction but we no longer allow the base
160 // to be installed in the Address class
161 void MacroAssembler::jump(ArrayAddress entry) {
162 jmp(as_Address(entry));
163 }
164
165 // Note: y_lo will be destroyed
166 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
167 // Long compare for Java (semantics as described in JVM spec.)
168 Label high, low, done;
169
170 cmpl(x_hi, y_hi);
171 jcc(Assembler::less, low);
172 jcc(Assembler::greater, high);
173 // x_hi is the return register
174 xorl(x_hi, x_hi);
175 cmpl(x_lo, y_lo);
176 jcc(Assembler::below, low);
177 jcc(Assembler::equal, done);
178
179 bind(high);
180 xorl(x_hi, x_hi);
181 increment(x_hi);
182 jmp(done);
183
184 bind(low);
185 xorl(x_hi, x_hi);
186 decrementl(x_hi);
187
188 bind(done);
189 }
190
191 void MacroAssembler::lea(Register dst, AddressLiteral src) {
192 mov_literal32(dst, (int32_t)src.target(), src.rspec());
193 }
194
195 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
196 // leal(dst, as_Address(adr));
197 // see note in movl as to why we must use a move
198 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
199 }
200
201 void MacroAssembler::leave() {
202 mov(rsp, rbp);
203 pop(rbp);
204 }
205
206 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
207 // Multiplication of two Java long values stored on the stack
208 // as illustrated below. Result is in rdx:rax.
209 //
210 // rsp ---> [ ?? ] \ \
211 // .... | y_rsp_offset |
212 // [ y_lo ] / (in bytes) | x_rsp_offset
213 // [ y_hi ] | (in bytes)
214 // .... |
215 // [ x_lo ] /
216 // [ x_hi ]
217 // ....
218 //
219 // Basic idea: lo(result) = lo(x_lo * y_lo)
220 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
221 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
222 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
223 Label quick;
224 // load x_hi, y_hi and check if quick
225 // multiplication is possible
226 movl(rbx, x_hi);
227 movl(rcx, y_hi);
228 movl(rax, rbx);
229 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
230 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
231 // do full multiplication
232 // 1st step
233 mull(y_lo); // x_hi * y_lo
234 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
235 // 2nd step
236 movl(rax, x_lo);
237 mull(rcx); // x_lo * y_hi
238 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
239 // 3rd step
240 bind(quick); // note: rbx, = 0 if quick multiply!
241 movl(rax, x_lo);
242 mull(y_lo); // x_lo * y_lo
243 addl(rdx, rbx); // correct hi(x_lo * y_lo)
244 }
245
246 void MacroAssembler::lneg(Register hi, Register lo) {
247 negl(lo);
248 adcl(hi, 0);
249 negl(hi);
250 }
251
252 void MacroAssembler::lshl(Register hi, Register lo) {
253 // Java shift left long support (semantics as described in JVM spec., p.305)
254 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
255 // shift value is in rcx !
256 assert(hi != rcx, "must not use rcx");
257 assert(lo != rcx, "must not use rcx");
258 const Register s = rcx; // shift count
259 const int n = BitsPerWord;
260 Label L;
261 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
262 cmpl(s, n); // if (s < n)
263 jcc(Assembler::less, L); // else (s >= n)
264 movl(hi, lo); // x := x << n
265 xorl(lo, lo);
266 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
267 bind(L); // s (mod n) < n
268 shldl(hi, lo); // x := x << s
269 shll(lo);
270 }
271
272
273 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
274 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
275 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
276 assert(hi != rcx, "must not use rcx");
277 assert(lo != rcx, "must not use rcx");
278 const Register s = rcx; // shift count
279 const int n = BitsPerWord;
280 Label L;
281 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
282 cmpl(s, n); // if (s < n)
283 jcc(Assembler::less, L); // else (s >= n)
284 movl(lo, hi); // x := x >> n
285 if (sign_extension) sarl(hi, 31);
286 else xorl(hi, hi);
287 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
288 bind(L); // s (mod n) < n
289 shrdl(lo, hi); // x := x >> s
290 if (sign_extension) sarl(hi);
291 else shrl(hi);
292 }
293
294 void MacroAssembler::movoop(Register dst, jobject obj) {
295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
296 }
297
298 void MacroAssembler::movoop(Address dst, jobject obj) {
299 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
300 }
301
302 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
304 }
305
306 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
307 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
308 }
309
310 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
311 // scratch register is not used,
312 // it is defined to match parameters of 64-bit version of this method.
313 if (src.is_lval()) {
314 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
315 } else {
316 movl(dst, as_Address(src));
317 }
318 }
319
320 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
321 movl(as_Address(dst), src);
322 }
323
324 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
325 movl(dst, as_Address(src));
326 }
327
328 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
329 void MacroAssembler::movptr(Address dst, intptr_t src) {
330 movl(dst, src);
331 }
332
333
334 void MacroAssembler::pop_callee_saved_registers() {
335 pop(rcx);
336 pop(rdx);
337 pop(rdi);
338 pop(rsi);
339 }
340
341 void MacroAssembler::pop_fTOS() {
342 fld_d(Address(rsp, 0));
343 addl(rsp, 2 * wordSize);
344 }
345
346 void MacroAssembler::push_callee_saved_registers() {
347 push(rsi);
348 push(rdi);
349 push(rdx);
350 push(rcx);
351 }
352
353 void MacroAssembler::push_fTOS() {
354 subl(rsp, 2 * wordSize);
355 fstp_d(Address(rsp, 0));
356 }
357
358
359 void MacroAssembler::pushoop(jobject obj) {
360 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
361 }
362
363 void MacroAssembler::pushklass(Metadata* obj) {
364 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
365 }
366
367 void MacroAssembler::pushptr(AddressLiteral src) {
368 if (src.is_lval()) {
369 push_literal32((int32_t)src.target(), src.rspec());
370 } else {
371 pushl(as_Address(src));
372 }
373 }
374
375 void MacroAssembler::set_word_if_not_zero(Register dst) {
376 xorl(dst, dst);
377 set_byte_if_not_zero(dst);
378 }
379
380 static void pass_arg0(MacroAssembler* masm, Register arg) {
381 masm->push(arg);
382 }
383
384 static void pass_arg1(MacroAssembler* masm, Register arg) {
385 masm->push(arg);
386 }
387
388 static void pass_arg2(MacroAssembler* masm, Register arg) {
389 masm->push(arg);
390 }
391
392 static void pass_arg3(MacroAssembler* masm, Register arg) {
393 masm->push(arg);
394 }
395
396 #ifndef PRODUCT
397 extern "C" void findpc(intptr_t x);
398 #endif
399
400 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
401 // In order to get locks to work, we need to fake a in_VM state
402 JavaThread* thread = JavaThread::current();
403 JavaThreadState saved_state = thread->thread_state();
404 thread->set_thread_state(_thread_in_vm);
405 if (ShowMessageBoxOnError) {
406 JavaThread* thread = JavaThread::current();
407 JavaThreadState saved_state = thread->thread_state();
408 thread->set_thread_state(_thread_in_vm);
409 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
410 ttyLocker ttyl;
411 BytecodeCounter::print();
412 }
413 // To see where a verify_oop failed, get $ebx+40/X for this frame.
414 // This is the value of eip which points to where verify_oop will return.
415 if (os::message_box(msg, "Execution stopped, print registers?")) {
416 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
417 BREAKPOINT;
418 }
419 } else {
420 ttyLocker ttyl;
421 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
422 }
423 // Don't assert holding the ttyLock
424 assert(false, "DEBUG MESSAGE: %s", msg);
425 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
426 }
427
428 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
429 ttyLocker ttyl;
430 FlagSetting fs(Debugging, true);
431 tty->print_cr("eip = 0x%08x", eip);
432 #ifndef PRODUCT
433 if ((WizardMode || Verbose) && PrintMiscellaneous) {
434 tty->cr();
435 findpc(eip);
436 tty->cr();
437 }
438 #endif
439 #define PRINT_REG(rax) \
440 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
441 PRINT_REG(rax);
442 PRINT_REG(rbx);
443 PRINT_REG(rcx);
444 PRINT_REG(rdx);
445 PRINT_REG(rdi);
446 PRINT_REG(rsi);
447 PRINT_REG(rbp);
448 PRINT_REG(rsp);
449 #undef PRINT_REG
450 // Print some words near top of staack.
451 int* dump_sp = (int*) rsp;
452 for (int col1 = 0; col1 < 8; col1++) {
453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
454 os::print_location(tty, *dump_sp++);
455 }
456 for (int row = 0; row < 16; row++) {
457 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
458 for (int col = 0; col < 8; col++) {
459 tty->print(" 0x%08x", *dump_sp++);
460 }
461 tty->cr();
462 }
463 // Print some instructions around pc:
464 Disassembler::decode((address)eip-64, (address)eip);
465 tty->print_cr("--------");
466 Disassembler::decode((address)eip, (address)eip+32);
467 }
468
469 void MacroAssembler::stop(const char* msg) {
470 ExternalAddress message((address)msg);
471 // push address of message
472 pushptr(message.addr());
473 { Label L; call(L, relocInfo::none); bind(L); } // push eip
474 pusha(); // push registers
475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
476 hlt();
477 }
478
479 void MacroAssembler::warn(const char* msg) {
480 push_CPU_state();
481
482 ExternalAddress message((address) msg);
483 // push address of message
484 pushptr(message.addr());
485
486 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
487 addl(rsp, wordSize); // discard argument
488 pop_CPU_state();
489 }
490
491 void MacroAssembler::print_state() {
492 { Label L; call(L, relocInfo::none); bind(L); } // push eip
493 pusha(); // push registers
494
495 push_CPU_state();
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
497 pop_CPU_state();
498
499 popa();
500 addl(rsp, wordSize);
501 }
502
503 #else // _LP64
504
505 // 64 bit versions
506
507 Address MacroAssembler::as_Address(AddressLiteral adr) {
508 // amd64 always does this as a pc-rel
509 // we can be absolute or disp based on the instruction type
510 // jmp/call are displacements others are absolute
511 assert(!adr.is_lval(), "must be rval");
512 assert(reachable(adr), "must be");
513 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
514
515 }
516
517 Address MacroAssembler::as_Address(ArrayAddress adr) {
518 AddressLiteral base = adr.base();
519 lea(rscratch1, base);
520 Address index = adr.index();
521 assert(index._disp == 0, "must not have disp"); // maybe it can?
522 Address array(rscratch1, index._index, index._scale, index._disp);
523 return array;
524 }
525
526 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
527 Label L, E;
528
529 #ifdef _WIN64
530 // Windows always allocates space for it's register args
531 assert(num_args <= 4, "only register arguments supported");
532 subq(rsp, frame::arg_reg_save_area_bytes);
533 #endif
534
535 // Align stack if necessary
536 testl(rsp, 15);
537 jcc(Assembler::zero, L);
538
539 subq(rsp, 8);
540 {
541 call(RuntimeAddress(entry_point));
542 }
543 addq(rsp, 8);
544 jmp(E);
545
546 bind(L);
547 {
548 call(RuntimeAddress(entry_point));
549 }
550
551 bind(E);
552
553 #ifdef _WIN64
554 // restore stack pointer
555 addq(rsp, frame::arg_reg_save_area_bytes);
556 #endif
557
558 }
559
560 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
561 assert(!src2.is_lval(), "should use cmpptr");
562
563 if (reachable(src2)) {
564 cmpq(src1, as_Address(src2));
565 } else {
566 lea(rscratch1, src2);
567 Assembler::cmpq(src1, Address(rscratch1, 0));
568 }
569 }
570
571 int MacroAssembler::corrected_idivq(Register reg) {
572 // Full implementation of Java ldiv and lrem; checks for special
573 // case as described in JVM spec., p.243 & p.271. The function
574 // returns the (pc) offset of the idivl instruction - may be needed
575 // for implicit exceptions.
576 //
577 // normal case special case
578 //
579 // input : rax: dividend min_long
580 // reg: divisor (may not be eax/edx) -1
581 //
582 // output: rax: quotient (= rax idiv reg) min_long
583 // rdx: remainder (= rax irem reg) 0
584 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
585 static const int64_t min_long = 0x8000000000000000;
586 Label normal_case, special_case;
587
588 // check for special case
589 cmp64(rax, ExternalAddress((address) &min_long));
590 jcc(Assembler::notEqual, normal_case);
591 xorl(rdx, rdx); // prepare rdx for possible special case (where
592 // remainder = 0)
593 cmpq(reg, -1);
594 jcc(Assembler::equal, special_case);
595
596 // handle normal case
597 bind(normal_case);
598 cdqq();
599 int idivq_offset = offset();
600 idivq(reg);
601
602 // normal and special case exit
603 bind(special_case);
604
605 return idivq_offset;
606 }
607
608 void MacroAssembler::decrementq(Register reg, int value) {
609 if (value == min_jint) { subq(reg, value); return; }
610 if (value < 0) { incrementq(reg, -value); return; }
611 if (value == 0) { ; return; }
612 if (value == 1 && UseIncDec) { decq(reg) ; return; }
613 /* else */ { subq(reg, value) ; return; }
614 }
615
616 void MacroAssembler::decrementq(Address dst, int value) {
617 if (value == min_jint) { subq(dst, value); return; }
618 if (value < 0) { incrementq(dst, -value); return; }
619 if (value == 0) { ; return; }
620 if (value == 1 && UseIncDec) { decq(dst) ; return; }
621 /* else */ { subq(dst, value) ; return; }
622 }
623
624 void MacroAssembler::incrementq(AddressLiteral dst) {
625 if (reachable(dst)) {
626 incrementq(as_Address(dst));
627 } else {
628 lea(rscratch1, dst);
629 incrementq(Address(rscratch1, 0));
630 }
631 }
632
633 void MacroAssembler::incrementq(Register reg, int value) {
634 if (value == min_jint) { addq(reg, value); return; }
635 if (value < 0) { decrementq(reg, -value); return; }
636 if (value == 0) { ; return; }
637 if (value == 1 && UseIncDec) { incq(reg) ; return; }
638 /* else */ { addq(reg, value) ; return; }
639 }
640
641 void MacroAssembler::incrementq(Address dst, int value) {
642 if (value == min_jint) { addq(dst, value); return; }
643 if (value < 0) { decrementq(dst, -value); return; }
644 if (value == 0) { ; return; }
645 if (value == 1 && UseIncDec) { incq(dst) ; return; }
646 /* else */ { addq(dst, value) ; return; }
647 }
648
649 // 32bit can do a case table jump in one instruction but we no longer allow the base
650 // to be installed in the Address class
651 void MacroAssembler::jump(ArrayAddress entry) {
652 lea(rscratch1, entry.base());
653 Address dispatch = entry.index();
654 assert(dispatch._base == noreg, "must be");
655 dispatch._base = rscratch1;
656 jmp(dispatch);
657 }
658
659 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
660 ShouldNotReachHere(); // 64bit doesn't use two regs
661 cmpq(x_lo, y_lo);
662 }
663
664 void MacroAssembler::lea(Register dst, AddressLiteral src) {
665 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
666 }
667
668 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
669 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
670 movptr(dst, rscratch1);
671 }
672
673 void MacroAssembler::leave() {
674 // %%% is this really better? Why not on 32bit too?
675 emit_int8((unsigned char)0xC9); // LEAVE
676 }
677
678 void MacroAssembler::lneg(Register hi, Register lo) {
679 ShouldNotReachHere(); // 64bit doesn't use two regs
680 negq(lo);
681 }
682
683 void MacroAssembler::movoop(Register dst, jobject obj) {
684 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
685 }
686
687 void MacroAssembler::movoop(Address dst, jobject obj) {
688 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
689 movq(dst, rscratch1);
690 }
691
692 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
693 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
694 }
695
696 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
697 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
698 movq(dst, rscratch1);
699 }
700
701 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
702 if (src.is_lval()) {
703 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
704 } else {
705 if (reachable(src)) {
706 movq(dst, as_Address(src));
707 } else {
708 lea(scratch, src);
709 movq(dst, Address(scratch, 0));
710 }
711 }
712 }
713
714 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
715 movq(as_Address(dst), src);
716 }
717
718 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
719 movq(dst, as_Address(src));
720 }
721
722 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
723 void MacroAssembler::movptr(Address dst, intptr_t src) {
724 mov64(rscratch1, src);
725 movq(dst, rscratch1);
726 }
727
728 // These are mostly for initializing NULL
729 void MacroAssembler::movptr(Address dst, int32_t src) {
730 movslq(dst, src);
731 }
732
733 void MacroAssembler::movptr(Register dst, int32_t src) {
734 mov64(dst, (intptr_t)src);
735 }
736
737 void MacroAssembler::pushoop(jobject obj) {
738 movoop(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushklass(Metadata* obj) {
743 mov_metadata(rscratch1, obj);
744 push(rscratch1);
745 }
746
747 void MacroAssembler::pushptr(AddressLiteral src) {
748 lea(rscratch1, src);
749 if (src.is_lval()) {
750 push(rscratch1);
751 } else {
752 pushq(Address(rscratch1, 0));
753 }
754 }
755
756 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
757 // we must set sp to zero to clear frame
758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
759 // must clear fp, so that compiled frames are not confused; it is
760 // possible that we need it only for debugging
761 if (clear_fp) {
762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
763 }
764
765 // Always clear the pc because it could have been set by make_walkable()
766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
767 vzeroupper();
768 }
769
770 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
771 Register last_java_fp,
772 address last_java_pc) {
773 vzeroupper();
774 // determine last_java_sp register
775 if (!last_java_sp->is_valid()) {
776 last_java_sp = rsp;
777 }
778
779 // last_java_fp is optional
780 if (last_java_fp->is_valid()) {
781 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
782 last_java_fp);
783 }
784
785 // last_java_pc is optional
786 if (last_java_pc != NULL) {
787 Address java_pc(r15_thread,
788 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
789 lea(rscratch1, InternalAddress(last_java_pc));
790 movptr(java_pc, rscratch1);
791 }
792
793 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
794 }
795
796 static void pass_arg0(MacroAssembler* masm, Register arg) {
797 if (c_rarg0 != arg ) {
798 masm->mov(c_rarg0, arg);
799 }
800 }
801
802 static void pass_arg1(MacroAssembler* masm, Register arg) {
803 if (c_rarg1 != arg ) {
804 masm->mov(c_rarg1, arg);
805 }
806 }
807
808 static void pass_arg2(MacroAssembler* masm, Register arg) {
809 if (c_rarg2 != arg ) {
810 masm->mov(c_rarg2, arg);
811 }
812 }
813
814 static void pass_arg3(MacroAssembler* masm, Register arg) {
815 if (c_rarg3 != arg ) {
816 masm->mov(c_rarg3, arg);
817 }
818 }
819
820 void MacroAssembler::stop(const char* msg) {
821 address rip = pc();
822 pusha(); // get regs on stack
823 lea(c_rarg0, ExternalAddress((address) msg));
824 lea(c_rarg1, InternalAddress(rip));
825 movq(c_rarg2, rsp); // pass pointer to regs array
826 andq(rsp, -16); // align stack as required by ABI
827 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
828 hlt();
829 }
830
831 void MacroAssembler::warn(const char* msg) {
832 push(rbp);
833 movq(rbp, rsp);
834 andq(rsp, -16); // align stack as required by push_CPU_state and call
835 push_CPU_state(); // keeps alignment at 16 bytes
836 lea(c_rarg0, ExternalAddress((address) msg));
837 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
838 pop_CPU_state();
839 mov(rsp, rbp);
840 pop(rbp);
841 }
842
843 void MacroAssembler::print_state() {
844 address rip = pc();
845 pusha(); // get regs on stack
846 push(rbp);
847 movq(rbp, rsp);
848 andq(rsp, -16); // align stack as required by push_CPU_state and call
849 push_CPU_state(); // keeps alignment at 16 bytes
850
851 lea(c_rarg0, InternalAddress(rip));
852 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
853 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
854
855 pop_CPU_state();
856 mov(rsp, rbp);
857 pop(rbp);
858 popa();
859 }
860
861 #ifndef PRODUCT
862 extern "C" void findpc(intptr_t x);
863 #endif
864
865 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
866 // In order to get locks to work, we need to fake a in_VM state
867 if (ShowMessageBoxOnError) {
868 JavaThread* thread = JavaThread::current();
869 JavaThreadState saved_state = thread->thread_state();
870 thread->set_thread_state(_thread_in_vm);
871 #ifndef PRODUCT
872 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
873 ttyLocker ttyl;
874 BytecodeCounter::print();
875 }
876 #endif
877 // To see where a verify_oop failed, get $ebx+40/X for this frame.
878 // XXX correct this offset for amd64
879 // This is the value of eip which points to where verify_oop will return.
880 if (os::message_box(msg, "Execution stopped, print registers?")) {
881 print_state64(pc, regs);
882 BREAKPOINT;
883 assert(false, "start up GDB");
884 }
885 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
886 } else {
887 ttyLocker ttyl;
888 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
889 msg);
890 assert(false, "DEBUG MESSAGE: %s", msg);
891 }
892 }
893
894 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
895 ttyLocker ttyl;
896 FlagSetting fs(Debugging, true);
897 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
898 #ifndef PRODUCT
899 tty->cr();
900 findpc(pc);
901 tty->cr();
902 #endif
903 #define PRINT_REG(rax, value) \
904 { tty->print("%s = ", #rax); os::print_location(tty, value); }
905 PRINT_REG(rax, regs[15]);
906 PRINT_REG(rbx, regs[12]);
907 PRINT_REG(rcx, regs[14]);
908 PRINT_REG(rdx, regs[13]);
909 PRINT_REG(rdi, regs[8]);
910 PRINT_REG(rsi, regs[9]);
911 PRINT_REG(rbp, regs[10]);
912 PRINT_REG(rsp, regs[11]);
913 PRINT_REG(r8 , regs[7]);
914 PRINT_REG(r9 , regs[6]);
915 PRINT_REG(r10, regs[5]);
916 PRINT_REG(r11, regs[4]);
917 PRINT_REG(r12, regs[3]);
918 PRINT_REG(r13, regs[2]);
919 PRINT_REG(r14, regs[1]);
920 PRINT_REG(r15, regs[0]);
921 #undef PRINT_REG
922 // Print some words near top of staack.
923 int64_t* rsp = (int64_t*) regs[11];
924 int64_t* dump_sp = rsp;
925 for (int col1 = 0; col1 < 8; col1++) {
926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
927 os::print_location(tty, *dump_sp++);
928 }
929 for (int row = 0; row < 25; row++) {
930 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
931 for (int col = 0; col < 4; col++) {
932 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
933 }
934 tty->cr();
935 }
936 // Print some instructions around pc:
937 Disassembler::decode((address)pc-64, (address)pc);
938 tty->print_cr("--------");
939 Disassembler::decode((address)pc, (address)pc+32);
940 }
941
942 #endif // _LP64
943
944 // Now versions that are common to 32/64 bit
945
946 void MacroAssembler::addptr(Register dst, int32_t imm32) {
947 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
948 }
949
950 void MacroAssembler::addptr(Register dst, Register src) {
951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
952 }
953
954 void MacroAssembler::addptr(Address dst, Register src) {
955 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
956 }
957
958 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
959 if (reachable(src)) {
960 Assembler::addsd(dst, as_Address(src));
961 } else {
962 lea(rscratch1, src);
963 Assembler::addsd(dst, Address(rscratch1, 0));
964 }
965 }
966
967 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
968 if (reachable(src)) {
969 addss(dst, as_Address(src));
970 } else {
971 lea(rscratch1, src);
972 addss(dst, Address(rscratch1, 0));
973 }
974 }
975
976 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
977 if (reachable(src)) {
978 Assembler::addpd(dst, as_Address(src));
979 } else {
980 lea(rscratch1, src);
981 Assembler::addpd(dst, Address(rscratch1, 0));
982 }
983 }
984
985 void MacroAssembler::align(int modulus) {
986 align(modulus, offset());
987 }
988
989 void MacroAssembler::align(int modulus, int target) {
990 if (target % modulus != 0) {
991 nop(modulus - (target % modulus));
992 }
993 }
994
995 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
996 // Used in sign-masking with aligned address.
997 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
998 if (reachable(src)) {
999 Assembler::andpd(dst, as_Address(src));
1000 } else {
1001 lea(rscratch1, src);
1002 Assembler::andpd(dst, Address(rscratch1, 0));
1003 }
1004 }
1005
1006 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andps(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andps(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1018 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1019 }
1020
1021 void MacroAssembler::atomic_incl(Address counter_addr) {
1022 if (os::is_MP())
1023 lock();
1024 incrementl(counter_addr);
1025 }
1026
1027 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1028 if (reachable(counter_addr)) {
1029 atomic_incl(as_Address(counter_addr));
1030 } else {
1031 lea(scr, counter_addr);
1032 atomic_incl(Address(scr, 0));
1033 }
1034 }
1035
1036 #ifdef _LP64
1037 void MacroAssembler::atomic_incq(Address counter_addr) {
1038 if (os::is_MP())
1039 lock();
1040 incrementq(counter_addr);
1041 }
1042
1043 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1044 if (reachable(counter_addr)) {
1045 atomic_incq(as_Address(counter_addr));
1046 } else {
1047 lea(scr, counter_addr);
1048 atomic_incq(Address(scr, 0));
1049 }
1050 }
1051 #endif
1052
1053 // Writes to stack successive pages until offset reached to check for
1054 // stack overflow + shadow pages. This clobbers tmp.
1055 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1056 movptr(tmp, rsp);
1057 // Bang stack for total size given plus shadow page size.
1058 // Bang one page at a time because large size can bang beyond yellow and
1059 // red zones.
1060 Label loop;
1061 bind(loop);
1062 movl(Address(tmp, (-os::vm_page_size())), size );
1063 subptr(tmp, os::vm_page_size());
1064 subl(size, os::vm_page_size());
1065 jcc(Assembler::greater, loop);
1066
1067 // Bang down shadow pages too.
1068 // At this point, (tmp-0) is the last address touched, so don't
1069 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1070 // was post-decremented.) Skip this address by starting at i=1, and
1071 // touch a few more pages below. N.B. It is important to touch all
1072 // the way down including all pages in the shadow zone.
1073 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1074 // this could be any sized move but this is can be a debugging crumb
1075 // so the bigger the better.
1076 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1077 }
1078 }
1079
1080 void MacroAssembler::reserved_stack_check() {
1081 // testing if reserved zone needs to be enabled
1082 Label no_reserved_zone_enabling;
1083 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1084 NOT_LP64(get_thread(rsi);)
1085
1086 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1087 jcc(Assembler::below, no_reserved_zone_enabling);
1088
1089 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1090 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1091 should_not_reach_here();
1092
1093 bind(no_reserved_zone_enabling);
1094 }
1095
1096 int MacroAssembler::biased_locking_enter(Register lock_reg,
1097 Register obj_reg,
1098 Register swap_reg,
1099 Register tmp_reg,
1100 bool swap_reg_contains_mark,
1101 Label& done,
1102 Label* slow_case,
1103 BiasedLockingCounters* counters) {
1104 assert(UseBiasedLocking, "why call this otherwise?");
1105 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1106 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1107 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1108 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1109 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1110 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1111
1112 if (PrintBiasedLockingStatistics && counters == NULL) {
1113 counters = BiasedLocking::counters();
1114 }
1115 // Biased locking
1116 // See whether the lock is currently biased toward our thread and
1117 // whether the epoch is still valid
1118 // Note that the runtime guarantees sufficient alignment of JavaThread
1119 // pointers to allow age to be placed into low bits
1120 // First check to see whether biasing is even enabled for this object
1121 Label cas_label;
1122 int null_check_offset = -1;
1123 if (!swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 movptr(swap_reg, mark_addr);
1126 }
1127 movptr(tmp_reg, swap_reg);
1128 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1129 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1130 jcc(Assembler::notEqual, cas_label);
1131 // The bias pattern is present in the object's header. Need to check
1132 // whether the bias owner and the epoch are both still current.
1133 #ifndef _LP64
1134 // Note that because there is no current thread register on x86_32 we
1135 // need to store off the mark word we read out of the object to
1136 // avoid reloading it and needing to recheck invariants below. This
1137 // store is unfortunate but it makes the overall code shorter and
1138 // simpler.
1139 movptr(saved_mark_addr, swap_reg);
1140 #endif
1141 if (swap_reg_contains_mark) {
1142 null_check_offset = offset();
1143 }
1144 load_prototype_header(tmp_reg, obj_reg);
1145 #ifdef _LP64
1146 orptr(tmp_reg, r15_thread);
1147 xorptr(tmp_reg, swap_reg);
1148 Register header_reg = tmp_reg;
1149 #else
1150 xorptr(tmp_reg, swap_reg);
1151 get_thread(swap_reg);
1152 xorptr(swap_reg, tmp_reg);
1153 Register header_reg = swap_reg;
1154 #endif
1155 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1156 if (counters != NULL) {
1157 cond_inc32(Assembler::zero,
1158 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1159 }
1160 jcc(Assembler::equal, done);
1161
1162 Label try_revoke_bias;
1163 Label try_rebias;
1164
1165 // At this point we know that the header has the bias pattern and
1166 // that we are not the bias owner in the current epoch. We need to
1167 // figure out more details about the state of the header in order to
1168 // know what operations can be legally performed on the object's
1169 // header.
1170
1171 // If the low three bits in the xor result aren't clear, that means
1172 // the prototype header is no longer biased and we have to revoke
1173 // the bias on this object.
1174 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1175 jccb(Assembler::notZero, try_revoke_bias);
1176
1177 // Biasing is still enabled for this data type. See whether the
1178 // epoch of the current bias is still valid, meaning that the epoch
1179 // bits of the mark word are equal to the epoch bits of the
1180 // prototype header. (Note that the prototype header's epoch bits
1181 // only change at a safepoint.) If not, attempt to rebias the object
1182 // toward the current thread. Note that we must be absolutely sure
1183 // that the current epoch is invalid in order to do this because
1184 // otherwise the manipulations it performs on the mark word are
1185 // illegal.
1186 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1187 jccb(Assembler::notZero, try_rebias);
1188
1189 // The epoch of the current bias is still valid but we know nothing
1190 // about the owner; it might be set or it might be clear. Try to
1191 // acquire the bias of the object using an atomic operation. If this
1192 // fails we will go in to the runtime to revoke the object's bias.
1193 // Note that we first construct the presumed unbiased header so we
1194 // don't accidentally blow away another thread's valid bias.
1195 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1196 andptr(swap_reg,
1197 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1198 #ifdef _LP64
1199 movptr(tmp_reg, swap_reg);
1200 orptr(tmp_reg, r15_thread);
1201 #else
1202 get_thread(tmp_reg);
1203 orptr(tmp_reg, swap_reg);
1204 #endif
1205 if (os::is_MP()) {
1206 lock();
1207 }
1208 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1209 // If the biasing toward our thread failed, this means that
1210 // another thread succeeded in biasing it toward itself and we
1211 // need to revoke that bias. The revocation will occur in the
1212 // interpreter runtime in the slow case.
1213 if (counters != NULL) {
1214 cond_inc32(Assembler::zero,
1215 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1216 }
1217 if (slow_case != NULL) {
1218 jcc(Assembler::notZero, *slow_case);
1219 }
1220 jmp(done);
1221
1222 bind(try_rebias);
1223 // At this point we know the epoch has expired, meaning that the
1224 // current "bias owner", if any, is actually invalid. Under these
1225 // circumstances _only_, we are allowed to use the current header's
1226 // value as the comparison value when doing the cas to acquire the
1227 // bias in the current epoch. In other words, we allow transfer of
1228 // the bias from one thread to another directly in this situation.
1229 //
1230 // FIXME: due to a lack of registers we currently blow away the age
1231 // bits in this situation. Should attempt to preserve them.
1232 load_prototype_header(tmp_reg, obj_reg);
1233 #ifdef _LP64
1234 orptr(tmp_reg, r15_thread);
1235 #else
1236 get_thread(swap_reg);
1237 orptr(tmp_reg, swap_reg);
1238 movptr(swap_reg, saved_mark_addr);
1239 #endif
1240 if (os::is_MP()) {
1241 lock();
1242 }
1243 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1244 // If the biasing toward our thread failed, then another thread
1245 // succeeded in biasing it toward itself and we need to revoke that
1246 // bias. The revocation will occur in the runtime in the slow case.
1247 if (counters != NULL) {
1248 cond_inc32(Assembler::zero,
1249 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1250 }
1251 if (slow_case != NULL) {
1252 jcc(Assembler::notZero, *slow_case);
1253 }
1254 jmp(done);
1255
1256 bind(try_revoke_bias);
1257 // The prototype mark in the klass doesn't have the bias bit set any
1258 // more, indicating that objects of this data type are not supposed
1259 // to be biased any more. We are going to try to reset the mark of
1260 // this object to the prototype value and fall through to the
1261 // CAS-based locking scheme. Note that if our CAS fails, it means
1262 // that another thread raced us for the privilege of revoking the
1263 // bias of this particular object, so it's okay to continue in the
1264 // normal locking code.
1265 //
1266 // FIXME: due to a lack of registers we currently blow away the age
1267 // bits in this situation. Should attempt to preserve them.
1268 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 // Fall through to the normal CAS-based lock, because no matter what
1275 // the result of the above CAS, some thread must have succeeded in
1276 // removing the bias bit from the object's header.
1277 if (counters != NULL) {
1278 cond_inc32(Assembler::zero,
1279 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1280 }
1281
1282 bind(cas_label);
1283
1284 return null_check_offset;
1285 }
1286
1287 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1288 assert(UseBiasedLocking, "why call this otherwise?");
1289
1290 // Check for biased locking unlock case, which is a no-op
1291 // Note: we do not have to check the thread ID for two reasons.
1292 // First, the interpreter checks for IllegalMonitorStateException at
1293 // a higher level. Second, if the bias was revoked while we held the
1294 // lock, the object could not be rebiased toward another thread, so
1295 // the bias bit would be clear.
1296 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1297 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1298 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1299 jcc(Assembler::equal, done);
1300 }
1301
1302 #ifdef COMPILER2
1303
1304 #if INCLUDE_RTM_OPT
1305
1306 // Update rtm_counters based on abort status
1307 // input: abort_status
1308 // rtm_counters (RTMLockingCounters*)
1309 // flags are killed
1310 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1311
1312 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1313 if (PrintPreciseRTMLockingStatistics) {
1314 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1315 Label check_abort;
1316 testl(abort_status, (1<<i));
1317 jccb(Assembler::equal, check_abort);
1318 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1319 bind(check_abort);
1320 }
1321 }
1322 }
1323
1324 // Branch if (random & (count-1) != 0), count is 2^n
1325 // tmp, scr and flags are killed
1326 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1327 assert(tmp == rax, "");
1328 assert(scr == rdx, "");
1329 rdtsc(); // modifies EDX:EAX
1330 andptr(tmp, count-1);
1331 jccb(Assembler::notZero, brLabel);
1332 }
1333
1334 // Perform abort ratio calculation, set no_rtm bit if high ratio
1335 // input: rtm_counters_Reg (RTMLockingCounters* address)
1336 // tmpReg, rtm_counters_Reg and flags are killed
1337 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1338 Register rtm_counters_Reg,
1339 RTMLockingCounters* rtm_counters,
1340 Metadata* method_data) {
1341 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1342
1343 if (RTMLockingCalculationDelay > 0) {
1344 // Delay calculation
1345 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1346 testptr(tmpReg, tmpReg);
1347 jccb(Assembler::equal, L_done);
1348 }
1349 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1350 // Aborted transactions = abort_count * 100
1351 // All transactions = total_count * RTMTotalCountIncrRate
1352 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1353
1354 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1355 cmpptr(tmpReg, RTMAbortThreshold);
1356 jccb(Assembler::below, L_check_always_rtm2);
1357 imulptr(tmpReg, tmpReg, 100);
1358
1359 Register scrReg = rtm_counters_Reg;
1360 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1361 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1362 imulptr(scrReg, scrReg, RTMAbortRatio);
1363 cmpptr(tmpReg, scrReg);
1364 jccb(Assembler::below, L_check_always_rtm1);
1365 if (method_data != NULL) {
1366 // set rtm_state to "no rtm" in MDO
1367 mov_metadata(tmpReg, method_data);
1368 if (os::is_MP()) {
1369 lock();
1370 }
1371 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1372 }
1373 jmpb(L_done);
1374 bind(L_check_always_rtm1);
1375 // Reload RTMLockingCounters* address
1376 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1377 bind(L_check_always_rtm2);
1378 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1379 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1380 jccb(Assembler::below, L_done);
1381 if (method_data != NULL) {
1382 // set rtm_state to "always rtm" in MDO
1383 mov_metadata(tmpReg, method_data);
1384 if (os::is_MP()) {
1385 lock();
1386 }
1387 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1388 }
1389 bind(L_done);
1390 }
1391
1392 // Update counters and perform abort ratio calculation
1393 // input: abort_status_Reg
1394 // rtm_counters_Reg, flags are killed
1395 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1396 Register rtm_counters_Reg,
1397 RTMLockingCounters* rtm_counters,
1398 Metadata* method_data,
1399 bool profile_rtm) {
1400
1401 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1402 // update rtm counters based on rax value at abort
1403 // reads abort_status_Reg, updates flags
1404 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1405 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1406 if (profile_rtm) {
1407 // Save abort status because abort_status_Reg is used by following code.
1408 if (RTMRetryCount > 0) {
1409 push(abort_status_Reg);
1410 }
1411 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1412 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1413 // restore abort status
1414 if (RTMRetryCount > 0) {
1415 pop(abort_status_Reg);
1416 }
1417 }
1418 }
1419
1420 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1421 // inputs: retry_count_Reg
1422 // : abort_status_Reg
1423 // output: retry_count_Reg decremented by 1
1424 // flags are killed
1425 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1426 Label doneRetry;
1427 assert(abort_status_Reg == rax, "");
1428 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1429 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1430 // if reason is in 0x6 and retry count != 0 then retry
1431 andptr(abort_status_Reg, 0x6);
1432 jccb(Assembler::zero, doneRetry);
1433 testl(retry_count_Reg, retry_count_Reg);
1434 jccb(Assembler::zero, doneRetry);
1435 pause();
1436 decrementl(retry_count_Reg);
1437 jmp(retryLabel);
1438 bind(doneRetry);
1439 }
1440
1441 // Spin and retry if lock is busy,
1442 // inputs: box_Reg (monitor address)
1443 // : retry_count_Reg
1444 // output: retry_count_Reg decremented by 1
1445 // : clear z flag if retry count exceeded
1446 // tmp_Reg, scr_Reg, flags are killed
1447 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1448 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1449 Label SpinLoop, SpinExit, doneRetry;
1450 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1451
1452 testl(retry_count_Reg, retry_count_Reg);
1453 jccb(Assembler::zero, doneRetry);
1454 decrementl(retry_count_Reg);
1455 movptr(scr_Reg, RTMSpinLoopCount);
1456
1457 bind(SpinLoop);
1458 pause();
1459 decrementl(scr_Reg);
1460 jccb(Assembler::lessEqual, SpinExit);
1461 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1462 testptr(tmp_Reg, tmp_Reg);
1463 jccb(Assembler::notZero, SpinLoop);
1464
1465 bind(SpinExit);
1466 jmp(retryLabel);
1467 bind(doneRetry);
1468 incrementl(retry_count_Reg); // clear z flag
1469 }
1470
1471 // Use RTM for normal stack locks
1472 // Input: objReg (object to lock)
1473 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1474 Register retry_on_abort_count_Reg,
1475 RTMLockingCounters* stack_rtm_counters,
1476 Metadata* method_data, bool profile_rtm,
1477 Label& DONE_LABEL, Label& IsInflated) {
1478 assert(UseRTMForStackLocks, "why call this otherwise?");
1479 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1480 assert(tmpReg == rax, "");
1481 assert(scrReg == rdx, "");
1482 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1483
1484 if (RTMRetryCount > 0) {
1485 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1486 bind(L_rtm_retry);
1487 }
1488 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1489 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1490 jcc(Assembler::notZero, IsInflated);
1491
1492 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1493 Label L_noincrement;
1494 if (RTMTotalCountIncrRate > 1) {
1495 // tmpReg, scrReg and flags are killed
1496 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1497 }
1498 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1499 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1500 bind(L_noincrement);
1501 }
1502 xbegin(L_on_abort);
1503 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1504 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1505 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1506 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1507
1508 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1509 if (UseRTMXendForLockBusy) {
1510 xend();
1511 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1512 jmp(L_decrement_retry);
1513 }
1514 else {
1515 xabort(0);
1516 }
1517 bind(L_on_abort);
1518 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1519 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1520 }
1521 bind(L_decrement_retry);
1522 if (RTMRetryCount > 0) {
1523 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1524 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1525 }
1526 }
1527
1528 // Use RTM for inflating locks
1529 // inputs: objReg (object to lock)
1530 // boxReg (on-stack box address (displaced header location) - KILLED)
1531 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1532 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1533 Register scrReg, Register retry_on_busy_count_Reg,
1534 Register retry_on_abort_count_Reg,
1535 RTMLockingCounters* rtm_counters,
1536 Metadata* method_data, bool profile_rtm,
1537 Label& DONE_LABEL) {
1538 assert(UseRTMLocking, "why call this otherwise?");
1539 assert(tmpReg == rax, "");
1540 assert(scrReg == rdx, "");
1541 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1542 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1543
1544 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1545 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1546 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1547
1548 if (RTMRetryCount > 0) {
1549 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1550 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1551 bind(L_rtm_retry);
1552 }
1553 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1554 Label L_noincrement;
1555 if (RTMTotalCountIncrRate > 1) {
1556 // tmpReg, scrReg and flags are killed
1557 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1558 }
1559 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1560 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1561 bind(L_noincrement);
1562 }
1563 xbegin(L_on_abort);
1564 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1565 movptr(tmpReg, Address(tmpReg, owner_offset));
1566 testptr(tmpReg, tmpReg);
1567 jcc(Assembler::zero, DONE_LABEL);
1568 if (UseRTMXendForLockBusy) {
1569 xend();
1570 jmp(L_decrement_retry);
1571 }
1572 else {
1573 xabort(0);
1574 }
1575 bind(L_on_abort);
1576 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1577 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1578 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1579 }
1580 if (RTMRetryCount > 0) {
1581 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1582 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1583 }
1584
1585 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1586 testptr(tmpReg, tmpReg) ;
1587 jccb(Assembler::notZero, L_decrement_retry) ;
1588
1589 // Appears unlocked - try to swing _owner from null to non-null.
1590 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1591 #ifdef _LP64
1592 Register threadReg = r15_thread;
1593 #else
1594 get_thread(scrReg);
1595 Register threadReg = scrReg;
1596 #endif
1597 if (os::is_MP()) {
1598 lock();
1599 }
1600 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1601
1602 if (RTMRetryCount > 0) {
1603 // success done else retry
1604 jccb(Assembler::equal, DONE_LABEL) ;
1605 bind(L_decrement_retry);
1606 // Spin and retry if lock is busy.
1607 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1608 }
1609 else {
1610 bind(L_decrement_retry);
1611 }
1612 }
1613
1614 #endif // INCLUDE_RTM_OPT
1615
1616 // Fast_Lock and Fast_Unlock used by C2
1617
1618 // Because the transitions from emitted code to the runtime
1619 // monitorenter/exit helper stubs are so slow it's critical that
1620 // we inline both the stack-locking fast-path and the inflated fast path.
1621 //
1622 // See also: cmpFastLock and cmpFastUnlock.
1623 //
1624 // What follows is a specialized inline transliteration of the code
1625 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1626 // another option would be to emit TrySlowEnter and TrySlowExit methods
1627 // at startup-time. These methods would accept arguments as
1628 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1629 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1630 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1631 // In practice, however, the # of lock sites is bounded and is usually small.
1632 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1633 // if the processor uses simple bimodal branch predictors keyed by EIP
1634 // Since the helper routines would be called from multiple synchronization
1635 // sites.
1636 //
1637 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1638 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1639 // to those specialized methods. That'd give us a mostly platform-independent
1640 // implementation that the JITs could optimize and inline at their pleasure.
1641 // Done correctly, the only time we'd need to cross to native could would be
1642 // to park() or unpark() threads. We'd also need a few more unsafe operators
1643 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1644 // (b) explicit barriers or fence operations.
1645 //
1646 // TODO:
1647 //
1648 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1649 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1650 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1651 // the lock operators would typically be faster than reifying Self.
1652 //
1653 // * Ideally I'd define the primitives as:
1654 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1655 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1656 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1657 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1658 // Furthermore the register assignments are overconstrained, possibly resulting in
1659 // sub-optimal code near the synchronization site.
1660 //
1661 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1662 // Alternately, use a better sp-proximity test.
1663 //
1664 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1665 // Either one is sufficient to uniquely identify a thread.
1666 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1667 //
1668 // * Intrinsify notify() and notifyAll() for the common cases where the
1669 // object is locked by the calling thread but the waitlist is empty.
1670 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1671 //
1672 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1673 // But beware of excessive branch density on AMD Opterons.
1674 //
1675 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1676 // or failure of the fast-path. If the fast-path fails then we pass
1677 // control to the slow-path, typically in C. In Fast_Lock and
1678 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1679 // will emit a conditional branch immediately after the node.
1680 // So we have branches to branches and lots of ICC.ZF games.
1681 // Instead, it might be better to have C2 pass a "FailureLabel"
1682 // into Fast_Lock and Fast_Unlock. In the case of success, control
1683 // will drop through the node. ICC.ZF is undefined at exit.
1684 // In the case of failure, the node will branch directly to the
1685 // FailureLabel
1686
1687
1688 // obj: object to lock
1689 // box: on-stack box address (displaced header location) - KILLED
1690 // rax,: tmp -- KILLED
1691 // scr: tmp -- KILLED
1692 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1693 Register scrReg, Register cx1Reg, Register cx2Reg,
1694 BiasedLockingCounters* counters,
1695 RTMLockingCounters* rtm_counters,
1696 RTMLockingCounters* stack_rtm_counters,
1697 Metadata* method_data,
1698 bool use_rtm, bool profile_rtm) {
1699 // Ensure the register assignments are disjoint
1700 assert(tmpReg == rax, "");
1701
1702 if (use_rtm) {
1703 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1704 } else {
1705 assert(cx1Reg == noreg, "");
1706 assert(cx2Reg == noreg, "");
1707 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1708 }
1709
1710 if (counters != NULL) {
1711 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1712 }
1713 if (EmitSync & 1) {
1714 // set box->dhw = markOopDesc::unused_mark()
1715 // Force all sync thru slow-path: slow_enter() and slow_exit()
1716 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1717 cmpptr (rsp, (int32_t)NULL_WORD);
1718 } else {
1719 // Possible cases that we'll encounter in fast_lock
1720 // ------------------------------------------------
1721 // * Inflated
1722 // -- unlocked
1723 // -- Locked
1724 // = by self
1725 // = by other
1726 // * biased
1727 // -- by Self
1728 // -- by other
1729 // * neutral
1730 // * stack-locked
1731 // -- by self
1732 // = sp-proximity test hits
1733 // = sp-proximity test generates false-negative
1734 // -- by other
1735 //
1736
1737 Label IsInflated, DONE_LABEL;
1738
1739 // it's stack-locked, biased or neutral
1740 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1741 // order to reduce the number of conditional branches in the most common cases.
1742 // Beware -- there's a subtle invariant that fetch of the markword
1743 // at [FETCH], below, will never observe a biased encoding (*101b).
1744 // If this invariant is not held we risk exclusion (safety) failure.
1745 if (UseBiasedLocking && !UseOptoBiasInlining) {
1746 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1747 }
1748
1749 #if INCLUDE_RTM_OPT
1750 if (UseRTMForStackLocks && use_rtm) {
1751 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1752 stack_rtm_counters, method_data, profile_rtm,
1753 DONE_LABEL, IsInflated);
1754 }
1755 #endif // INCLUDE_RTM_OPT
1756
1757 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1758 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1759 jccb(Assembler::notZero, IsInflated);
1760
1761 // Attempt stack-locking ...
1762 orptr (tmpReg, markOopDesc::unlocked_value);
1763 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1764 if (os::is_MP()) {
1765 lock();
1766 }
1767 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1768 if (counters != NULL) {
1769 cond_inc32(Assembler::equal,
1770 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1771 }
1772 jcc(Assembler::equal, DONE_LABEL); // Success
1773
1774 // Recursive locking.
1775 // The object is stack-locked: markword contains stack pointer to BasicLock.
1776 // Locked by current thread if difference with current SP is less than one page.
1777 subptr(tmpReg, rsp);
1778 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1779 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1780 movptr(Address(boxReg, 0), tmpReg);
1781 if (counters != NULL) {
1782 cond_inc32(Assembler::equal,
1783 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1784 }
1785 jmp(DONE_LABEL);
1786
1787 bind(IsInflated);
1788 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1789
1790 #if INCLUDE_RTM_OPT
1791 // Use the same RTM locking code in 32- and 64-bit VM.
1792 if (use_rtm) {
1793 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1794 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1795 } else {
1796 #endif // INCLUDE_RTM_OPT
1797
1798 #ifndef _LP64
1799 // The object is inflated.
1800
1801 // boxReg refers to the on-stack BasicLock in the current frame.
1802 // We'd like to write:
1803 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1804 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1805 // additional latency as we have another ST in the store buffer that must drain.
1806
1807 if (EmitSync & 8192) {
1808 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1809 get_thread (scrReg);
1810 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1811 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1812 if (os::is_MP()) {
1813 lock();
1814 }
1815 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1816 } else
1817 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1818 // register juggle because we need tmpReg for cmpxchgptr below
1819 movptr(scrReg, boxReg);
1820 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1821
1822 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1823 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1824 // prefetchw [eax + Offset(_owner)-2]
1825 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1826 }
1827
1828 if ((EmitSync & 64) == 0) {
1829 // Optimistic form: consider XORL tmpReg,tmpReg
1830 movptr(tmpReg, NULL_WORD);
1831 } else {
1832 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1833 // Test-And-CAS instead of CAS
1834 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1835 testptr(tmpReg, tmpReg); // Locked ?
1836 jccb (Assembler::notZero, DONE_LABEL);
1837 }
1838
1839 // Appears unlocked - try to swing _owner from null to non-null.
1840 // Ideally, I'd manifest "Self" with get_thread and then attempt
1841 // to CAS the register containing Self into m->Owner.
1842 // But we don't have enough registers, so instead we can either try to CAS
1843 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1844 // we later store "Self" into m->Owner. Transiently storing a stack address
1845 // (rsp or the address of the box) into m->owner is harmless.
1846 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1847 if (os::is_MP()) {
1848 lock();
1849 }
1850 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1851 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1852 // If we weren't able to swing _owner from NULL to the BasicLock
1853 // then take the slow path.
1854 jccb (Assembler::notZero, DONE_LABEL);
1855 // update _owner from BasicLock to thread
1856 get_thread (scrReg); // beware: clobbers ICCs
1857 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1858 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1859
1860 // If the CAS fails we can either retry or pass control to the slow-path.
1861 // We use the latter tactic.
1862 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1863 // If the CAS was successful ...
1864 // Self has acquired the lock
1865 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1866 // Intentional fall-through into DONE_LABEL ...
1867 } else {
1868 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1869 movptr(boxReg, tmpReg);
1870
1871 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1872 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1873 // prefetchw [eax + Offset(_owner)-2]
1874 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1875 }
1876
1877 if ((EmitSync & 64) == 0) {
1878 // Optimistic form
1879 xorptr (tmpReg, tmpReg);
1880 } else {
1881 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1882 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1883 testptr(tmpReg, tmpReg); // Locked ?
1884 jccb (Assembler::notZero, DONE_LABEL);
1885 }
1886
1887 // Appears unlocked - try to swing _owner from null to non-null.
1888 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1889 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1890 get_thread (scrReg);
1891 if (os::is_MP()) {
1892 lock();
1893 }
1894 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1895
1896 // If the CAS fails we can either retry or pass control to the slow-path.
1897 // We use the latter tactic.
1898 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1899 // If the CAS was successful ...
1900 // Self has acquired the lock
1901 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1902 // Intentional fall-through into DONE_LABEL ...
1903 }
1904 #else // _LP64
1905 // It's inflated
1906 movq(scrReg, tmpReg);
1907 xorq(tmpReg, tmpReg);
1908
1909 if (os::is_MP()) {
1910 lock();
1911 }
1912 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1913 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1914 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1915 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1916 // Intentional fall-through into DONE_LABEL ...
1917 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1918 #endif // _LP64
1919 #if INCLUDE_RTM_OPT
1920 } // use_rtm()
1921 #endif
1922 // DONE_LABEL is a hot target - we'd really like to place it at the
1923 // start of cache line by padding with NOPs.
1924 // See the AMD and Intel software optimization manuals for the
1925 // most efficient "long" NOP encodings.
1926 // Unfortunately none of our alignment mechanisms suffice.
1927 bind(DONE_LABEL);
1928
1929 // At DONE_LABEL the icc ZFlag is set as follows ...
1930 // Fast_Unlock uses the same protocol.
1931 // ZFlag == 1 -> Success
1932 // ZFlag == 0 -> Failure - force control through the slow-path
1933 }
1934 }
1935
1936 // obj: object to unlock
1937 // box: box address (displaced header location), killed. Must be EAX.
1938 // tmp: killed, cannot be obj nor box.
1939 //
1940 // Some commentary on balanced locking:
1941 //
1942 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1943 // Methods that don't have provably balanced locking are forced to run in the
1944 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1945 // The interpreter provides two properties:
1946 // I1: At return-time the interpreter automatically and quietly unlocks any
1947 // objects acquired the current activation (frame). Recall that the
1948 // interpreter maintains an on-stack list of locks currently held by
1949 // a frame.
1950 // I2: If a method attempts to unlock an object that is not held by the
1951 // the frame the interpreter throws IMSX.
1952 //
1953 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1954 // B() doesn't have provably balanced locking so it runs in the interpreter.
1955 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1956 // is still locked by A().
1957 //
1958 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1959 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1960 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1961 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1962 // Arguably given that the spec legislates the JNI case as undefined our implementation
1963 // could reasonably *avoid* checking owner in Fast_Unlock().
1964 // In the interest of performance we elide m->Owner==Self check in unlock.
1965 // A perfectly viable alternative is to elide the owner check except when
1966 // Xcheck:jni is enabled.
1967
1968 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1969 assert(boxReg == rax, "");
1970 assert_different_registers(objReg, boxReg, tmpReg);
1971
1972 if (EmitSync & 4) {
1973 // Disable - inhibit all inlining. Force control through the slow-path
1974 cmpptr (rsp, 0);
1975 } else {
1976 Label DONE_LABEL, Stacked, CheckSucc;
1977
1978 // Critically, the biased locking test must have precedence over
1979 // and appear before the (box->dhw == 0) recursive stack-lock test.
1980 if (UseBiasedLocking && !UseOptoBiasInlining) {
1981 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1982 }
1983
1984 #if INCLUDE_RTM_OPT
1985 if (UseRTMForStackLocks && use_rtm) {
1986 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1987 Label L_regular_unlock;
1988 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1989 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1990 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1991 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1992 xend(); // otherwise end...
1993 jmp(DONE_LABEL); // ... and we're done
1994 bind(L_regular_unlock);
1995 }
1996 #endif
1997
1998 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1999 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2000 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2001 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2002 jccb (Assembler::zero, Stacked);
2003
2004 // It's inflated.
2005 #if INCLUDE_RTM_OPT
2006 if (use_rtm) {
2007 Label L_regular_inflated_unlock;
2008 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2009 movptr(boxReg, Address(tmpReg, owner_offset));
2010 testptr(boxReg, boxReg);
2011 jccb(Assembler::notZero, L_regular_inflated_unlock);
2012 xend();
2013 jmpb(DONE_LABEL);
2014 bind(L_regular_inflated_unlock);
2015 }
2016 #endif
2017
2018 // Despite our balanced locking property we still check that m->_owner == Self
2019 // as java routines or native JNI code called by this thread might
2020 // have released the lock.
2021 // Refer to the comments in synchronizer.cpp for how we might encode extra
2022 // state in _succ so we can avoid fetching EntryList|cxq.
2023 //
2024 // I'd like to add more cases in fast_lock() and fast_unlock() --
2025 // such as recursive enter and exit -- but we have to be wary of
2026 // I$ bloat, T$ effects and BP$ effects.
2027 //
2028 // If there's no contention try a 1-0 exit. That is, exit without
2029 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2030 // we detect and recover from the race that the 1-0 exit admits.
2031 //
2032 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2033 // before it STs null into _owner, releasing the lock. Updates
2034 // to data protected by the critical section must be visible before
2035 // we drop the lock (and thus before any other thread could acquire
2036 // the lock and observe the fields protected by the lock).
2037 // IA32's memory-model is SPO, so STs are ordered with respect to
2038 // each other and there's no need for an explicit barrier (fence).
2039 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2040 #ifndef _LP64
2041 get_thread (boxReg);
2042 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2043 // prefetchw [ebx + Offset(_owner)-2]
2044 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2045 }
2046
2047 // Note that we could employ various encoding schemes to reduce
2048 // the number of loads below (currently 4) to just 2 or 3.
2049 // Refer to the comments in synchronizer.cpp.
2050 // In practice the chain of fetches doesn't seem to impact performance, however.
2051 xorptr(boxReg, boxReg);
2052 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2053 // Attempt to reduce branch density - AMD's branch predictor.
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2056 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2057 jccb (Assembler::notZero, DONE_LABEL);
2058 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2059 jmpb (DONE_LABEL);
2060 } else {
2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2062 jccb (Assembler::notZero, DONE_LABEL);
2063 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2064 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2065 jccb (Assembler::notZero, CheckSucc);
2066 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2067 jmpb (DONE_LABEL);
2068 }
2069
2070 // The Following code fragment (EmitSync & 65536) improves the performance of
2071 // contended applications and contended synchronization microbenchmarks.
2072 // Unfortunately the emission of the code - even though not executed - causes regressions
2073 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2074 // with an equal number of never-executed NOPs results in the same regression.
2075 // We leave it off by default.
2076
2077 if ((EmitSync & 65536) != 0) {
2078 Label LSuccess, LGoSlowPath ;
2079
2080 bind (CheckSucc);
2081
2082 // Optional pre-test ... it's safe to elide this
2083 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2084 jccb(Assembler::zero, LGoSlowPath);
2085
2086 // We have a classic Dekker-style idiom:
2087 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2088 // There are a number of ways to implement the barrier:
2089 // (1) lock:andl &m->_owner, 0
2090 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2091 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2092 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2093 // (2) If supported, an explicit MFENCE is appealing.
2094 // In older IA32 processors MFENCE is slower than lock:add or xchg
2095 // particularly if the write-buffer is full as might be the case if
2096 // if stores closely precede the fence or fence-equivalent instruction.
2097 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2098 // as the situation has changed with Nehalem and Shanghai.
2099 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2100 // The $lines underlying the top-of-stack should be in M-state.
2101 // The locked add instruction is serializing, of course.
2102 // (4) Use xchg, which is serializing
2103 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2104 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2105 // The integer condition codes will tell us if succ was 0.
2106 // Since _succ and _owner should reside in the same $line and
2107 // we just stored into _owner, it's likely that the $line
2108 // remains in M-state for the lock:orl.
2109 //
2110 // We currently use (3), although it's likely that switching to (2)
2111 // is correct for the future.
2112
2113 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2114 if (os::is_MP()) {
2115 lock(); addptr(Address(rsp, 0), 0);
2116 }
2117 // Ratify _succ remains non-null
2118 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2119 jccb (Assembler::notZero, LSuccess);
2120
2121 xorptr(boxReg, boxReg); // box is really EAX
2122 if (os::is_MP()) { lock(); }
2123 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2124 // There's no successor so we tried to regrab the lock with the
2125 // placeholder value. If that didn't work, then another thread
2126 // grabbed the lock so we're done (and exit was a success).
2127 jccb (Assembler::notEqual, LSuccess);
2128 // Since we're low on registers we installed rsp as a placeholding in _owner.
2129 // Now install Self over rsp. This is safe as we're transitioning from
2130 // non-null to non=null
2131 get_thread (boxReg);
2132 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2133 // Intentional fall-through into LGoSlowPath ...
2134
2135 bind (LGoSlowPath);
2136 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2137 jmpb (DONE_LABEL);
2138
2139 bind (LSuccess);
2140 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2141 jmpb (DONE_LABEL);
2142 }
2143
2144 bind (Stacked);
2145 // It's not inflated and it's not recursively stack-locked and it's not biased.
2146 // It must be stack-locked.
2147 // Try to reset the header to displaced header.
2148 // The "box" value on the stack is stable, so we can reload
2149 // and be assured we observe the same value as above.
2150 movptr(tmpReg, Address(boxReg, 0));
2151 if (os::is_MP()) {
2152 lock();
2153 }
2154 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2155 // Intention fall-thru into DONE_LABEL
2156
2157 // DONE_LABEL is a hot target - we'd really like to place it at the
2158 // start of cache line by padding with NOPs.
2159 // See the AMD and Intel software optimization manuals for the
2160 // most efficient "long" NOP encodings.
2161 // Unfortunately none of our alignment mechanisms suffice.
2162 if ((EmitSync & 65536) == 0) {
2163 bind (CheckSucc);
2164 }
2165 #else // _LP64
2166 // It's inflated
2167 if (EmitSync & 1024) {
2168 // Emit code to check that _owner == Self
2169 // We could fold the _owner test into subsequent code more efficiently
2170 // than using a stand-alone check, but since _owner checking is off by
2171 // default we don't bother. We also might consider predicating the
2172 // _owner==Self check on Xcheck:jni or running on a debug build.
2173 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2174 xorptr(boxReg, r15_thread);
2175 } else {
2176 xorptr(boxReg, boxReg);
2177 }
2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2179 jccb (Assembler::notZero, DONE_LABEL);
2180 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2181 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2182 jccb (Assembler::notZero, CheckSucc);
2183 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2184 jmpb (DONE_LABEL);
2185
2186 if ((EmitSync & 65536) == 0) {
2187 // Try to avoid passing control into the slow_path ...
2188 Label LSuccess, LGoSlowPath ;
2189 bind (CheckSucc);
2190
2191 // The following optional optimization can be elided if necessary
2192 // Effectively: if (succ == null) goto SlowPath
2193 // The code reduces the window for a race, however,
2194 // and thus benefits performance.
2195 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2196 jccb (Assembler::zero, LGoSlowPath);
2197
2198 xorptr(boxReg, boxReg);
2199 if ((EmitSync & 16) && os::is_MP()) {
2200 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2201 } else {
2202 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2203 if (os::is_MP()) {
2204 // Memory barrier/fence
2205 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2206 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2207 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2208 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2209 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2210 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2211 lock(); addl(Address(rsp, 0), 0);
2212 }
2213 }
2214 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2215 jccb (Assembler::notZero, LSuccess);
2216
2217 // Rare inopportune interleaving - race.
2218 // The successor vanished in the small window above.
2219 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2220 // We need to ensure progress and succession.
2221 // Try to reacquire the lock.
2222 // If that fails then the new owner is responsible for succession and this
2223 // thread needs to take no further action and can exit via the fast path (success).
2224 // If the re-acquire succeeds then pass control into the slow path.
2225 // As implemented, this latter mode is horrible because we generated more
2226 // coherence traffic on the lock *and* artifically extended the critical section
2227 // length while by virtue of passing control into the slow path.
2228
2229 // box is really RAX -- the following CMPXCHG depends on that binding
2230 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2231 if (os::is_MP()) { lock(); }
2232 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2233 // There's no successor so we tried to regrab the lock.
2234 // If that didn't work, then another thread grabbed the
2235 // lock so we're done (and exit was a success).
2236 jccb (Assembler::notEqual, LSuccess);
2237 // Intentional fall-through into slow-path
2238
2239 bind (LGoSlowPath);
2240 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2241 jmpb (DONE_LABEL);
2242
2243 bind (LSuccess);
2244 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2245 jmpb (DONE_LABEL);
2246 }
2247
2248 bind (Stacked);
2249 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2250 if (os::is_MP()) { lock(); }
2251 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2252
2253 if (EmitSync & 65536) {
2254 bind (CheckSucc);
2255 }
2256 #endif
2257 bind(DONE_LABEL);
2258 }
2259 }
2260 #endif // COMPILER2
2261
2262 void MacroAssembler::c2bool(Register x) {
2263 // implements x == 0 ? 0 : 1
2264 // note: must only look at least-significant byte of x
2265 // since C-style booleans are stored in one byte
2266 // only! (was bug)
2267 andl(x, 0xFF);
2268 setb(Assembler::notZero, x);
2269 }
2270
2271 // Wouldn't need if AddressLiteral version had new name
2272 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2273 Assembler::call(L, rtype);
2274 }
2275
2276 void MacroAssembler::call(Register entry) {
2277 Assembler::call(entry);
2278 }
2279
2280 void MacroAssembler::call(AddressLiteral entry) {
2281 if (reachable(entry)) {
2282 Assembler::call_literal(entry.target(), entry.rspec());
2283 } else {
2284 lea(rscratch1, entry);
2285 Assembler::call(rscratch1);
2286 }
2287 }
2288
2289 void MacroAssembler::ic_call(address entry, jint method_index) {
2290 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2291 movptr(rax, (intptr_t)Universe::non_oop_word());
2292 call(AddressLiteral(entry, rh));
2293 }
2294
2295 // Implementation of call_VM versions
2296
2297 void MacroAssembler::call_VM(Register oop_result,
2298 address entry_point,
2299 bool check_exceptions) {
2300 Label C, E;
2301 call(C, relocInfo::none);
2302 jmp(E);
2303
2304 bind(C);
2305 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2306 ret(0);
2307
2308 bind(E);
2309 }
2310
2311 void MacroAssembler::call_VM(Register oop_result,
2312 address entry_point,
2313 Register arg_1,
2314 bool check_exceptions) {
2315 Label C, E;
2316 call(C, relocInfo::none);
2317 jmp(E);
2318
2319 bind(C);
2320 pass_arg1(this, arg_1);
2321 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2322 ret(0);
2323
2324 bind(E);
2325 }
2326
2327 void MacroAssembler::call_VM(Register oop_result,
2328 address entry_point,
2329 Register arg_1,
2330 Register arg_2,
2331 bool check_exceptions) {
2332 Label C, E;
2333 call(C, relocInfo::none);
2334 jmp(E);
2335
2336 bind(C);
2337
2338 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2339
2340 pass_arg2(this, arg_2);
2341 pass_arg1(this, arg_1);
2342 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2343 ret(0);
2344
2345 bind(E);
2346 }
2347
2348 void MacroAssembler::call_VM(Register oop_result,
2349 address entry_point,
2350 Register arg_1,
2351 Register arg_2,
2352 Register arg_3,
2353 bool check_exceptions) {
2354 Label C, E;
2355 call(C, relocInfo::none);
2356 jmp(E);
2357
2358 bind(C);
2359
2360 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2361 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2362 pass_arg3(this, arg_3);
2363
2364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2365 pass_arg2(this, arg_2);
2366
2367 pass_arg1(this, arg_1);
2368 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2369 ret(0);
2370
2371 bind(E);
2372 }
2373
2374 void MacroAssembler::call_VM(Register oop_result,
2375 Register last_java_sp,
2376 address entry_point,
2377 int number_of_arguments,
2378 bool check_exceptions) {
2379 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2380 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2381 }
2382
2383 void MacroAssembler::call_VM(Register oop_result,
2384 Register last_java_sp,
2385 address entry_point,
2386 Register arg_1,
2387 bool check_exceptions) {
2388 pass_arg1(this, arg_1);
2389 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2390 }
2391
2392 void MacroAssembler::call_VM(Register oop_result,
2393 Register last_java_sp,
2394 address entry_point,
2395 Register arg_1,
2396 Register arg_2,
2397 bool check_exceptions) {
2398
2399 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2400 pass_arg2(this, arg_2);
2401 pass_arg1(this, arg_1);
2402 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2403 }
2404
2405 void MacroAssembler::call_VM(Register oop_result,
2406 Register last_java_sp,
2407 address entry_point,
2408 Register arg_1,
2409 Register arg_2,
2410 Register arg_3,
2411 bool check_exceptions) {
2412 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2413 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2414 pass_arg3(this, arg_3);
2415 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2416 pass_arg2(this, arg_2);
2417 pass_arg1(this, arg_1);
2418 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2419 }
2420
2421 void MacroAssembler::super_call_VM(Register oop_result,
2422 Register last_java_sp,
2423 address entry_point,
2424 int number_of_arguments,
2425 bool check_exceptions) {
2426 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2427 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2428 }
2429
2430 void MacroAssembler::super_call_VM(Register oop_result,
2431 Register last_java_sp,
2432 address entry_point,
2433 Register arg_1,
2434 bool check_exceptions) {
2435 pass_arg1(this, arg_1);
2436 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2437 }
2438
2439 void MacroAssembler::super_call_VM(Register oop_result,
2440 Register last_java_sp,
2441 address entry_point,
2442 Register arg_1,
2443 Register arg_2,
2444 bool check_exceptions) {
2445
2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2447 pass_arg2(this, arg_2);
2448 pass_arg1(this, arg_1);
2449 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2450 }
2451
2452 void MacroAssembler::super_call_VM(Register oop_result,
2453 Register last_java_sp,
2454 address entry_point,
2455 Register arg_1,
2456 Register arg_2,
2457 Register arg_3,
2458 bool check_exceptions) {
2459 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2460 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2461 pass_arg3(this, arg_3);
2462 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2463 pass_arg2(this, arg_2);
2464 pass_arg1(this, arg_1);
2465 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2466 }
2467
2468 void MacroAssembler::call_VM_base(Register oop_result,
2469 Register java_thread,
2470 Register last_java_sp,
2471 address entry_point,
2472 int number_of_arguments,
2473 bool check_exceptions) {
2474 // determine java_thread register
2475 if (!java_thread->is_valid()) {
2476 #ifdef _LP64
2477 java_thread = r15_thread;
2478 #else
2479 java_thread = rdi;
2480 get_thread(java_thread);
2481 #endif // LP64
2482 }
2483 // determine last_java_sp register
2484 if (!last_java_sp->is_valid()) {
2485 last_java_sp = rsp;
2486 }
2487 // debugging support
2488 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2489 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2490 #ifdef ASSERT
2491 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2492 // r12 is the heapbase.
2493 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2494 #endif // ASSERT
2495
2496 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2497 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2498
2499 // push java thread (becomes first argument of C function)
2500
2501 NOT_LP64(push(java_thread); number_of_arguments++);
2502 LP64_ONLY(mov(c_rarg0, r15_thread));
2503
2504 // set last Java frame before call
2505 assert(last_java_sp != rbp, "can't use ebp/rbp");
2506
2507 // Only interpreter should have to set fp
2508 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2509
2510 // do the call, remove parameters
2511 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2512
2513 // restore the thread (cannot use the pushed argument since arguments
2514 // may be overwritten by C code generated by an optimizing compiler);
2515 // however can use the register value directly if it is callee saved.
2516 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2517 // rdi & rsi (also r15) are callee saved -> nothing to do
2518 #ifdef ASSERT
2519 guarantee(java_thread != rax, "change this code");
2520 push(rax);
2521 { Label L;
2522 get_thread(rax);
2523 cmpptr(java_thread, rax);
2524 jcc(Assembler::equal, L);
2525 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2526 bind(L);
2527 }
2528 pop(rax);
2529 #endif
2530 } else {
2531 get_thread(java_thread);
2532 }
2533 // reset last Java frame
2534 // Only interpreter should have to clear fp
2535 reset_last_Java_frame(java_thread, true);
2536
2537 // C++ interp handles this in the interpreter
2538 check_and_handle_popframe(java_thread);
2539 check_and_handle_earlyret(java_thread);
2540
2541 if (check_exceptions) {
2542 // check for pending exceptions (java_thread is set upon return)
2543 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2544 #ifndef _LP64
2545 jump_cc(Assembler::notEqual,
2546 RuntimeAddress(StubRoutines::forward_exception_entry()));
2547 #else
2548 // This used to conditionally jump to forward_exception however it is
2549 // possible if we relocate that the branch will not reach. So we must jump
2550 // around so we can always reach
2551
2552 Label ok;
2553 jcc(Assembler::equal, ok);
2554 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2555 bind(ok);
2556 #endif // LP64
2557 }
2558
2559 // get oop result if there is one and reset the value in the thread
2560 if (oop_result->is_valid()) {
2561 get_vm_result(oop_result, java_thread);
2562 }
2563 }
2564
2565 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2566
2567 // Calculate the value for last_Java_sp
2568 // somewhat subtle. call_VM does an intermediate call
2569 // which places a return address on the stack just under the
2570 // stack pointer as the user finsihed with it. This allows
2571 // use to retrieve last_Java_pc from last_Java_sp[-1].
2572 // On 32bit we then have to push additional args on the stack to accomplish
2573 // the actual requested call. On 64bit call_VM only can use register args
2574 // so the only extra space is the return address that call_VM created.
2575 // This hopefully explains the calculations here.
2576
2577 #ifdef _LP64
2578 // We've pushed one address, correct last_Java_sp
2579 lea(rax, Address(rsp, wordSize));
2580 #else
2581 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2582 #endif // LP64
2583
2584 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2585
2586 }
2587
2588 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2589 void MacroAssembler::call_VM_leaf0(address entry_point) {
2590 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2591 }
2592
2593 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2594 call_VM_leaf_base(entry_point, number_of_arguments);
2595 }
2596
2597 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2598 pass_arg0(this, arg_0);
2599 call_VM_leaf(entry_point, 1);
2600 }
2601
2602 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2603
2604 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2605 pass_arg1(this, arg_1);
2606 pass_arg0(this, arg_0);
2607 call_VM_leaf(entry_point, 2);
2608 }
2609
2610 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2611 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2612 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2613 pass_arg2(this, arg_2);
2614 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2615 pass_arg1(this, arg_1);
2616 pass_arg0(this, arg_0);
2617 call_VM_leaf(entry_point, 3);
2618 }
2619
2620 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2621 pass_arg0(this, arg_0);
2622 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2623 }
2624
2625 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2626
2627 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2628 pass_arg1(this, arg_1);
2629 pass_arg0(this, arg_0);
2630 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2631 }
2632
2633 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2634 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2635 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2636 pass_arg2(this, arg_2);
2637 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2638 pass_arg1(this, arg_1);
2639 pass_arg0(this, arg_0);
2640 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2641 }
2642
2643 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2644 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2645 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2646 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2647 pass_arg3(this, arg_3);
2648 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2649 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2650 pass_arg2(this, arg_2);
2651 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2652 pass_arg1(this, arg_1);
2653 pass_arg0(this, arg_0);
2654 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2655 }
2656
2657 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2658 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2659 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2660 verify_oop(oop_result, "broken oop in call_VM_base");
2661 }
2662
2663 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2664 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2665 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2666 }
2667
2668 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2669 }
2670
2671 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2672 }
2673
2674 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2675 if (reachable(src1)) {
2676 cmpl(as_Address(src1), imm);
2677 } else {
2678 lea(rscratch1, src1);
2679 cmpl(Address(rscratch1, 0), imm);
2680 }
2681 }
2682
2683 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2684 assert(!src2.is_lval(), "use cmpptr");
2685 if (reachable(src2)) {
2686 cmpl(src1, as_Address(src2));
2687 } else {
2688 lea(rscratch1, src2);
2689 cmpl(src1, Address(rscratch1, 0));
2690 }
2691 }
2692
2693 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2694 Assembler::cmpl(src1, imm);
2695 }
2696
2697 void MacroAssembler::cmp32(Register src1, Address src2) {
2698 Assembler::cmpl(src1, src2);
2699 }
2700
2701 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2702 ucomisd(opr1, opr2);
2703
2704 Label L;
2705 if (unordered_is_less) {
2706 movl(dst, -1);
2707 jcc(Assembler::parity, L);
2708 jcc(Assembler::below , L);
2709 movl(dst, 0);
2710 jcc(Assembler::equal , L);
2711 increment(dst);
2712 } else { // unordered is greater
2713 movl(dst, 1);
2714 jcc(Assembler::parity, L);
2715 jcc(Assembler::above , L);
2716 movl(dst, 0);
2717 jcc(Assembler::equal , L);
2718 decrementl(dst);
2719 }
2720 bind(L);
2721 }
2722
2723 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2724 ucomiss(opr1, opr2);
2725
2726 Label L;
2727 if (unordered_is_less) {
2728 movl(dst, -1);
2729 jcc(Assembler::parity, L);
2730 jcc(Assembler::below , L);
2731 movl(dst, 0);
2732 jcc(Assembler::equal , L);
2733 increment(dst);
2734 } else { // unordered is greater
2735 movl(dst, 1);
2736 jcc(Assembler::parity, L);
2737 jcc(Assembler::above , L);
2738 movl(dst, 0);
2739 jcc(Assembler::equal , L);
2740 decrementl(dst);
2741 }
2742 bind(L);
2743 }
2744
2745
2746 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2747 if (reachable(src1)) {
2748 cmpb(as_Address(src1), imm);
2749 } else {
2750 lea(rscratch1, src1);
2751 cmpb(Address(rscratch1, 0), imm);
2752 }
2753 }
2754
2755 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2756 #ifdef _LP64
2757 if (src2.is_lval()) {
2758 movptr(rscratch1, src2);
2759 Assembler::cmpq(src1, rscratch1);
2760 } else if (reachable(src2)) {
2761 cmpq(src1, as_Address(src2));
2762 } else {
2763 lea(rscratch1, src2);
2764 Assembler::cmpq(src1, Address(rscratch1, 0));
2765 }
2766 #else
2767 if (src2.is_lval()) {
2768 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2769 } else {
2770 cmpl(src1, as_Address(src2));
2771 }
2772 #endif // _LP64
2773 }
2774
2775 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2776 assert(src2.is_lval(), "not a mem-mem compare");
2777 #ifdef _LP64
2778 // moves src2's literal address
2779 movptr(rscratch1, src2);
2780 Assembler::cmpq(src1, rscratch1);
2781 #else
2782 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2783 #endif // _LP64
2784 }
2785
2786 void MacroAssembler::cmpoop(Register src1, Register src2) {
2787 cmpptr(src1, src2);
2788 }
2789
2790 void MacroAssembler::cmpoop(Register src1, Address src2) {
2791 cmpptr(src1, src2);
2792 }
2793
2794 #ifdef _LP64
2795 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2796 movoop(rscratch1, src2);
2797 cmpptr(src1, rscratch1);
2798 }
2799 #endif
2800
2801 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2802 if (reachable(adr)) {
2803 if (os::is_MP())
2804 lock();
2805 cmpxchgptr(reg, as_Address(adr));
2806 } else {
2807 lea(rscratch1, adr);
2808 if (os::is_MP())
2809 lock();
2810 cmpxchgptr(reg, Address(rscratch1, 0));
2811 }
2812 }
2813
2814 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2815 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2816 }
2817
2818 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2819 if (reachable(src)) {
2820 Assembler::comisd(dst, as_Address(src));
2821 } else {
2822 lea(rscratch1, src);
2823 Assembler::comisd(dst, Address(rscratch1, 0));
2824 }
2825 }
2826
2827 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2828 if (reachable(src)) {
2829 Assembler::comiss(dst, as_Address(src));
2830 } else {
2831 lea(rscratch1, src);
2832 Assembler::comiss(dst, Address(rscratch1, 0));
2833 }
2834 }
2835
2836
2837 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2838 Condition negated_cond = negate_condition(cond);
2839 Label L;
2840 jcc(negated_cond, L);
2841 pushf(); // Preserve flags
2842 atomic_incl(counter_addr);
2843 popf();
2844 bind(L);
2845 }
2846
2847 int MacroAssembler::corrected_idivl(Register reg) {
2848 // Full implementation of Java idiv and irem; checks for
2849 // special case as described in JVM spec., p.243 & p.271.
2850 // The function returns the (pc) offset of the idivl
2851 // instruction - may be needed for implicit exceptions.
2852 //
2853 // normal case special case
2854 //
2855 // input : rax,: dividend min_int
2856 // reg: divisor (may not be rax,/rdx) -1
2857 //
2858 // output: rax,: quotient (= rax, idiv reg) min_int
2859 // rdx: remainder (= rax, irem reg) 0
2860 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2861 const int min_int = 0x80000000;
2862 Label normal_case, special_case;
2863
2864 // check for special case
2865 cmpl(rax, min_int);
2866 jcc(Assembler::notEqual, normal_case);
2867 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2868 cmpl(reg, -1);
2869 jcc(Assembler::equal, special_case);
2870
2871 // handle normal case
2872 bind(normal_case);
2873 cdql();
2874 int idivl_offset = offset();
2875 idivl(reg);
2876
2877 // normal and special case exit
2878 bind(special_case);
2879
2880 return idivl_offset;
2881 }
2882
2883
2884
2885 void MacroAssembler::decrementl(Register reg, int value) {
2886 if (value == min_jint) {subl(reg, value) ; return; }
2887 if (value < 0) { incrementl(reg, -value); return; }
2888 if (value == 0) { ; return; }
2889 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2890 /* else */ { subl(reg, value) ; return; }
2891 }
2892
2893 void MacroAssembler::decrementl(Address dst, int value) {
2894 if (value == min_jint) {subl(dst, value) ; return; }
2895 if (value < 0) { incrementl(dst, -value); return; }
2896 if (value == 0) { ; return; }
2897 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2898 /* else */ { subl(dst, value) ; return; }
2899 }
2900
2901 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2902 assert (shift_value > 0, "illegal shift value");
2903 Label _is_positive;
2904 testl (reg, reg);
2905 jcc (Assembler::positive, _is_positive);
2906 int offset = (1 << shift_value) - 1 ;
2907
2908 if (offset == 1) {
2909 incrementl(reg);
2910 } else {
2911 addl(reg, offset);
2912 }
2913
2914 bind (_is_positive);
2915 sarl(reg, shift_value);
2916 }
2917
2918 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2919 if (reachable(src)) {
2920 Assembler::divsd(dst, as_Address(src));
2921 } else {
2922 lea(rscratch1, src);
2923 Assembler::divsd(dst, Address(rscratch1, 0));
2924 }
2925 }
2926
2927 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2928 if (reachable(src)) {
2929 Assembler::divss(dst, as_Address(src));
2930 } else {
2931 lea(rscratch1, src);
2932 Assembler::divss(dst, Address(rscratch1, 0));
2933 }
2934 }
2935
2936 // !defined(COMPILER2) is because of stupid core builds
2937 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2938 void MacroAssembler::empty_FPU_stack() {
2939 if (VM_Version::supports_mmx()) {
2940 emms();
2941 } else {
2942 for (int i = 8; i-- > 0; ) ffree(i);
2943 }
2944 }
2945 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2946
2947
2948 // Defines obj, preserves var_size_in_bytes
2949 void MacroAssembler::eden_allocate(Register obj,
2950 Register var_size_in_bytes,
2951 int con_size_in_bytes,
2952 Register t1,
2953 Label& slow_case) {
2954 assert(obj == rax, "obj must be in rax, for cmpxchg");
2955 assert_different_registers(obj, var_size_in_bytes, t1);
2956 if (!Universe::heap()->supports_inline_contig_alloc()) {
2957 jmp(slow_case);
2958 } else {
2959 Register end = t1;
2960 Label retry;
2961 bind(retry);
2962 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2963 movptr(obj, heap_top);
2964 if (var_size_in_bytes == noreg) {
2965 lea(end, Address(obj, con_size_in_bytes));
2966 } else {
2967 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2968 }
2969 // if end < obj then we wrapped around => object too long => slow case
2970 cmpptr(end, obj);
2971 jcc(Assembler::below, slow_case);
2972 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2973 jcc(Assembler::above, slow_case);
2974 // Compare obj with the top addr, and if still equal, store the new top addr in
2975 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2976 // it otherwise. Use lock prefix for atomicity on MPs.
2977 locked_cmpxchgptr(end, heap_top);
2978 jcc(Assembler::notEqual, retry);
2979 }
2980 }
2981
2982 void MacroAssembler::enter() {
2983 push(rbp);
2984 mov(rbp, rsp);
2985 }
2986
2987 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2988 void MacroAssembler::fat_nop() {
2989 if (UseAddressNop) {
2990 addr_nop_5();
2991 } else {
2992 emit_int8(0x26); // es:
2993 emit_int8(0x2e); // cs:
2994 emit_int8(0x64); // fs:
2995 emit_int8(0x65); // gs:
2996 emit_int8((unsigned char)0x90);
2997 }
2998 }
2999
3000 void MacroAssembler::fcmp(Register tmp) {
3001 fcmp(tmp, 1, true, true);
3002 }
3003
3004 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3005 assert(!pop_right || pop_left, "usage error");
3006 if (VM_Version::supports_cmov()) {
3007 assert(tmp == noreg, "unneeded temp");
3008 if (pop_left) {
3009 fucomip(index);
3010 } else {
3011 fucomi(index);
3012 }
3013 if (pop_right) {
3014 fpop();
3015 }
3016 } else {
3017 assert(tmp != noreg, "need temp");
3018 if (pop_left) {
3019 if (pop_right) {
3020 fcompp();
3021 } else {
3022 fcomp(index);
3023 }
3024 } else {
3025 fcom(index);
3026 }
3027 // convert FPU condition into eflags condition via rax,
3028 save_rax(tmp);
3029 fwait(); fnstsw_ax();
3030 sahf();
3031 restore_rax(tmp);
3032 }
3033 // condition codes set as follows:
3034 //
3035 // CF (corresponds to C0) if x < y
3036 // PF (corresponds to C2) if unordered
3037 // ZF (corresponds to C3) if x = y
3038 }
3039
3040 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3041 fcmp2int(dst, unordered_is_less, 1, true, true);
3042 }
3043
3044 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3045 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3046 Label L;
3047 if (unordered_is_less) {
3048 movl(dst, -1);
3049 jcc(Assembler::parity, L);
3050 jcc(Assembler::below , L);
3051 movl(dst, 0);
3052 jcc(Assembler::equal , L);
3053 increment(dst);
3054 } else { // unordered is greater
3055 movl(dst, 1);
3056 jcc(Assembler::parity, L);
3057 jcc(Assembler::above , L);
3058 movl(dst, 0);
3059 jcc(Assembler::equal , L);
3060 decrementl(dst);
3061 }
3062 bind(L);
3063 }
3064
3065 void MacroAssembler::fld_d(AddressLiteral src) {
3066 fld_d(as_Address(src));
3067 }
3068
3069 void MacroAssembler::fld_s(AddressLiteral src) {
3070 fld_s(as_Address(src));
3071 }
3072
3073 void MacroAssembler::fld_x(AddressLiteral src) {
3074 Assembler::fld_x(as_Address(src));
3075 }
3076
3077 void MacroAssembler::fldcw(AddressLiteral src) {
3078 Assembler::fldcw(as_Address(src));
3079 }
3080
3081 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3082 if (reachable(src)) {
3083 Assembler::mulpd(dst, as_Address(src));
3084 } else {
3085 lea(rscratch1, src);
3086 Assembler::mulpd(dst, Address(rscratch1, 0));
3087 }
3088 }
3089
3090 void MacroAssembler::increase_precision() {
3091 subptr(rsp, BytesPerWord);
3092 fnstcw(Address(rsp, 0));
3093 movl(rax, Address(rsp, 0));
3094 orl(rax, 0x300);
3095 push(rax);
3096 fldcw(Address(rsp, 0));
3097 pop(rax);
3098 }
3099
3100 void MacroAssembler::restore_precision() {
3101 fldcw(Address(rsp, 0));
3102 addptr(rsp, BytesPerWord);
3103 }
3104
3105 void MacroAssembler::fpop() {
3106 ffree();
3107 fincstp();
3108 }
3109
3110 void MacroAssembler::load_float(Address src) {
3111 if (UseSSE >= 1) {
3112 movflt(xmm0, src);
3113 } else {
3114 LP64_ONLY(ShouldNotReachHere());
3115 NOT_LP64(fld_s(src));
3116 }
3117 }
3118
3119 void MacroAssembler::store_float(Address dst) {
3120 if (UseSSE >= 1) {
3121 movflt(dst, xmm0);
3122 } else {
3123 LP64_ONLY(ShouldNotReachHere());
3124 NOT_LP64(fstp_s(dst));
3125 }
3126 }
3127
3128 void MacroAssembler::load_double(Address src) {
3129 if (UseSSE >= 2) {
3130 movdbl(xmm0, src);
3131 } else {
3132 LP64_ONLY(ShouldNotReachHere());
3133 NOT_LP64(fld_d(src));
3134 }
3135 }
3136
3137 void MacroAssembler::store_double(Address dst) {
3138 if (UseSSE >= 2) {
3139 movdbl(dst, xmm0);
3140 } else {
3141 LP64_ONLY(ShouldNotReachHere());
3142 NOT_LP64(fstp_d(dst));
3143 }
3144 }
3145
3146 void MacroAssembler::fremr(Register tmp) {
3147 save_rax(tmp);
3148 { Label L;
3149 bind(L);
3150 fprem();
3151 fwait(); fnstsw_ax();
3152 #ifdef _LP64
3153 testl(rax, 0x400);
3154 jcc(Assembler::notEqual, L);
3155 #else
3156 sahf();
3157 jcc(Assembler::parity, L);
3158 #endif // _LP64
3159 }
3160 restore_rax(tmp);
3161 // Result is in ST0.
3162 // Note: fxch & fpop to get rid of ST1
3163 // (otherwise FPU stack could overflow eventually)
3164 fxch(1);
3165 fpop();
3166 }
3167
3168 // dst = c = a * b + c
3169 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3170 Assembler::vfmadd231sd(c, a, b);
3171 if (dst != c) {
3172 movdbl(dst, c);
3173 }
3174 }
3175
3176 // dst = c = a * b + c
3177 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3178 Assembler::vfmadd231ss(c, a, b);
3179 if (dst != c) {
3180 movflt(dst, c);
3181 }
3182 }
3183
3184 // dst = c = a * b + c
3185 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3186 Assembler::vfmadd231pd(c, a, b, vector_len);
3187 if (dst != c) {
3188 vmovdqu(dst, c);
3189 }
3190 }
3191
3192 // dst = c = a * b + c
3193 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3194 Assembler::vfmadd231ps(c, a, b, vector_len);
3195 if (dst != c) {
3196 vmovdqu(dst, c);
3197 }
3198 }
3199
3200 // dst = c = a * b + c
3201 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3202 Assembler::vfmadd231pd(c, a, b, vector_len);
3203 if (dst != c) {
3204 vmovdqu(dst, c);
3205 }
3206 }
3207
3208 // dst = c = a * b + c
3209 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3210 Assembler::vfmadd231ps(c, a, b, vector_len);
3211 if (dst != c) {
3212 vmovdqu(dst, c);
3213 }
3214 }
3215
3216 void MacroAssembler::incrementl(AddressLiteral dst) {
3217 if (reachable(dst)) {
3218 incrementl(as_Address(dst));
3219 } else {
3220 lea(rscratch1, dst);
3221 incrementl(Address(rscratch1, 0));
3222 }
3223 }
3224
3225 void MacroAssembler::incrementl(ArrayAddress dst) {
3226 incrementl(as_Address(dst));
3227 }
3228
3229 void MacroAssembler::incrementl(Register reg, int value) {
3230 if (value == min_jint) {addl(reg, value) ; return; }
3231 if (value < 0) { decrementl(reg, -value); return; }
3232 if (value == 0) { ; return; }
3233 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3234 /* else */ { addl(reg, value) ; return; }
3235 }
3236
3237 void MacroAssembler::incrementl(Address dst, int value) {
3238 if (value == min_jint) {addl(dst, value) ; return; }
3239 if (value < 0) { decrementl(dst, -value); return; }
3240 if (value == 0) { ; return; }
3241 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3242 /* else */ { addl(dst, value) ; return; }
3243 }
3244
3245 void MacroAssembler::jump(AddressLiteral dst) {
3246 if (reachable(dst)) {
3247 jmp_literal(dst.target(), dst.rspec());
3248 } else {
3249 lea(rscratch1, dst);
3250 jmp(rscratch1);
3251 }
3252 }
3253
3254 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3255 if (reachable(dst)) {
3256 InstructionMark im(this);
3257 relocate(dst.reloc());
3258 const int short_size = 2;
3259 const int long_size = 6;
3260 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3261 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3262 // 0111 tttn #8-bit disp
3263 emit_int8(0x70 | cc);
3264 emit_int8((offs - short_size) & 0xFF);
3265 } else {
3266 // 0000 1111 1000 tttn #32-bit disp
3267 emit_int8(0x0F);
3268 emit_int8((unsigned char)(0x80 | cc));
3269 emit_int32(offs - long_size);
3270 }
3271 } else {
3272 #ifdef ASSERT
3273 warning("reversing conditional branch");
3274 #endif /* ASSERT */
3275 Label skip;
3276 jccb(reverse[cc], skip);
3277 lea(rscratch1, dst);
3278 Assembler::jmp(rscratch1);
3279 bind(skip);
3280 }
3281 }
3282
3283 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3284 if (reachable(src)) {
3285 Assembler::ldmxcsr(as_Address(src));
3286 } else {
3287 lea(rscratch1, src);
3288 Assembler::ldmxcsr(Address(rscratch1, 0));
3289 }
3290 }
3291
3292 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3293 int off;
3294 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3295 off = offset();
3296 movsbl(dst, src); // movsxb
3297 } else {
3298 off = load_unsigned_byte(dst, src);
3299 shll(dst, 24);
3300 sarl(dst, 24);
3301 }
3302 return off;
3303 }
3304
3305 // Note: load_signed_short used to be called load_signed_word.
3306 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3307 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3308 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3309 int MacroAssembler::load_signed_short(Register dst, Address src) {
3310 int off;
3311 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3312 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3313 // version but this is what 64bit has always done. This seems to imply
3314 // that users are only using 32bits worth.
3315 off = offset();
3316 movswl(dst, src); // movsxw
3317 } else {
3318 off = load_unsigned_short(dst, src);
3319 shll(dst, 16);
3320 sarl(dst, 16);
3321 }
3322 return off;
3323 }
3324
3325 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3326 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3327 // and "3.9 Partial Register Penalties", p. 22).
3328 int off;
3329 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3330 off = offset();
3331 movzbl(dst, src); // movzxb
3332 } else {
3333 xorl(dst, dst);
3334 off = offset();
3335 movb(dst, src);
3336 }
3337 return off;
3338 }
3339
3340 // Note: load_unsigned_short used to be called load_unsigned_word.
3341 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3342 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3343 // and "3.9 Partial Register Penalties", p. 22).
3344 int off;
3345 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3346 off = offset();
3347 movzwl(dst, src); // movzxw
3348 } else {
3349 xorl(dst, dst);
3350 off = offset();
3351 movw(dst, src);
3352 }
3353 return off;
3354 }
3355
3356 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3357 switch (size_in_bytes) {
3358 #ifndef _LP64
3359 case 8:
3360 assert(dst2 != noreg, "second dest register required");
3361 movl(dst, src);
3362 movl(dst2, src.plus_disp(BytesPerInt));
3363 break;
3364 #else
3365 case 8: movq(dst, src); break;
3366 #endif
3367 case 4: movl(dst, src); break;
3368 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3369 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3370 default: ShouldNotReachHere();
3371 }
3372 }
3373
3374 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3375 switch (size_in_bytes) {
3376 #ifndef _LP64
3377 case 8:
3378 assert(src2 != noreg, "second source register required");
3379 movl(dst, src);
3380 movl(dst.plus_disp(BytesPerInt), src2);
3381 break;
3382 #else
3383 case 8: movq(dst, src); break;
3384 #endif
3385 case 4: movl(dst, src); break;
3386 case 2: movw(dst, src); break;
3387 case 1: movb(dst, src); break;
3388 default: ShouldNotReachHere();
3389 }
3390 }
3391
3392 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3393 if (reachable(dst)) {
3394 movl(as_Address(dst), src);
3395 } else {
3396 lea(rscratch1, dst);
3397 movl(Address(rscratch1, 0), src);
3398 }
3399 }
3400
3401 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3402 if (reachable(src)) {
3403 movl(dst, as_Address(src));
3404 } else {
3405 lea(rscratch1, src);
3406 movl(dst, Address(rscratch1, 0));
3407 }
3408 }
3409
3410 // C++ bool manipulation
3411
3412 void MacroAssembler::movbool(Register dst, Address src) {
3413 if(sizeof(bool) == 1)
3414 movb(dst, src);
3415 else if(sizeof(bool) == 2)
3416 movw(dst, src);
3417 else if(sizeof(bool) == 4)
3418 movl(dst, src);
3419 else
3420 // unsupported
3421 ShouldNotReachHere();
3422 }
3423
3424 void MacroAssembler::movbool(Address dst, bool boolconst) {
3425 if(sizeof(bool) == 1)
3426 movb(dst, (int) boolconst);
3427 else if(sizeof(bool) == 2)
3428 movw(dst, (int) boolconst);
3429 else if(sizeof(bool) == 4)
3430 movl(dst, (int) boolconst);
3431 else
3432 // unsupported
3433 ShouldNotReachHere();
3434 }
3435
3436 void MacroAssembler::movbool(Address dst, Register src) {
3437 if(sizeof(bool) == 1)
3438 movb(dst, src);
3439 else if(sizeof(bool) == 2)
3440 movw(dst, src);
3441 else if(sizeof(bool) == 4)
3442 movl(dst, src);
3443 else
3444 // unsupported
3445 ShouldNotReachHere();
3446 }
3447
3448 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3449 movb(as_Address(dst), src);
3450 }
3451
3452 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3453 if (reachable(src)) {
3454 movdl(dst, as_Address(src));
3455 } else {
3456 lea(rscratch1, src);
3457 movdl(dst, Address(rscratch1, 0));
3458 }
3459 }
3460
3461 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3462 if (reachable(src)) {
3463 movq(dst, as_Address(src));
3464 } else {
3465 lea(rscratch1, src);
3466 movq(dst, Address(rscratch1, 0));
3467 }
3468 }
3469
3470 void MacroAssembler::setvectmask(Register dst, Register src) {
3471 Assembler::movl(dst, 1);
3472 Assembler::shlxl(dst, dst, src);
3473 Assembler::decl(dst);
3474 Assembler::kmovdl(k1, dst);
3475 Assembler::movl(dst, src);
3476 }
3477
3478 void MacroAssembler::restorevectmask() {
3479 Assembler::knotwl(k1, k0);
3480 }
3481
3482 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3483 if (reachable(src)) {
3484 if (UseXmmLoadAndClearUpper) {
3485 movsd (dst, as_Address(src));
3486 } else {
3487 movlpd(dst, as_Address(src));
3488 }
3489 } else {
3490 lea(rscratch1, src);
3491 if (UseXmmLoadAndClearUpper) {
3492 movsd (dst, Address(rscratch1, 0));
3493 } else {
3494 movlpd(dst, Address(rscratch1, 0));
3495 }
3496 }
3497 }
3498
3499 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3500 if (reachable(src)) {
3501 movss(dst, as_Address(src));
3502 } else {
3503 lea(rscratch1, src);
3504 movss(dst, Address(rscratch1, 0));
3505 }
3506 }
3507
3508 void MacroAssembler::movptr(Register dst, Register src) {
3509 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3510 }
3511
3512 void MacroAssembler::movptr(Register dst, Address src) {
3513 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3514 }
3515
3516 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3517 void MacroAssembler::movptr(Register dst, intptr_t src) {
3518 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3519 }
3520
3521 void MacroAssembler::movptr(Address dst, Register src) {
3522 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3523 }
3524
3525 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3526 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3527 Assembler::vextractf32x4(dst, src, 0);
3528 } else {
3529 Assembler::movdqu(dst, src);
3530 }
3531 }
3532
3533 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3534 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3535 Assembler::vinsertf32x4(dst, dst, src, 0);
3536 } else {
3537 Assembler::movdqu(dst, src);
3538 }
3539 }
3540
3541 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3542 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3543 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3544 } else {
3545 Assembler::movdqu(dst, src);
3546 }
3547 }
3548
3549 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3550 if (reachable(src)) {
3551 movdqu(dst, as_Address(src));
3552 } else {
3553 lea(scratchReg, src);
3554 movdqu(dst, Address(scratchReg, 0));
3555 }
3556 }
3557
3558 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3559 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3560 vextractf64x4_low(dst, src);
3561 } else {
3562 Assembler::vmovdqu(dst, src);
3563 }
3564 }
3565
3566 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3567 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3568 vinsertf64x4_low(dst, src);
3569 } else {
3570 Assembler::vmovdqu(dst, src);
3571 }
3572 }
3573
3574 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3575 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3576 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3577 }
3578 else {
3579 Assembler::vmovdqu(dst, src);
3580 }
3581 }
3582
3583 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3584 if (reachable(src)) {
3585 vmovdqu(dst, as_Address(src));
3586 }
3587 else {
3588 lea(rscratch1, src);
3589 vmovdqu(dst, Address(rscratch1, 0));
3590 }
3591 }
3592
3593 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3594 if (reachable(src)) {
3595 Assembler::movdqa(dst, as_Address(src));
3596 } else {
3597 lea(rscratch1, src);
3598 Assembler::movdqa(dst, Address(rscratch1, 0));
3599 }
3600 }
3601
3602 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3603 if (reachable(src)) {
3604 Assembler::movsd(dst, as_Address(src));
3605 } else {
3606 lea(rscratch1, src);
3607 Assembler::movsd(dst, Address(rscratch1, 0));
3608 }
3609 }
3610
3611 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3612 if (reachable(src)) {
3613 Assembler::movss(dst, as_Address(src));
3614 } else {
3615 lea(rscratch1, src);
3616 Assembler::movss(dst, Address(rscratch1, 0));
3617 }
3618 }
3619
3620 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3621 if (reachable(src)) {
3622 Assembler::mulsd(dst, as_Address(src));
3623 } else {
3624 lea(rscratch1, src);
3625 Assembler::mulsd(dst, Address(rscratch1, 0));
3626 }
3627 }
3628
3629 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3630 if (reachable(src)) {
3631 Assembler::mulss(dst, as_Address(src));
3632 } else {
3633 lea(rscratch1, src);
3634 Assembler::mulss(dst, Address(rscratch1, 0));
3635 }
3636 }
3637
3638 void MacroAssembler::null_check(Register reg, int offset) {
3639 if (needs_explicit_null_check(offset)) {
3640 // provoke OS NULL exception if reg = NULL by
3641 // accessing M[reg] w/o changing any (non-CC) registers
3642 // NOTE: cmpl is plenty here to provoke a segv
3643 cmpptr(rax, Address(reg, 0));
3644 // Note: should probably use testl(rax, Address(reg, 0));
3645 // may be shorter code (however, this version of
3646 // testl needs to be implemented first)
3647 } else {
3648 // nothing to do, (later) access of M[reg + offset]
3649 // will provoke OS NULL exception if reg = NULL
3650 }
3651 }
3652
3653 void MacroAssembler::os_breakpoint() {
3654 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3655 // (e.g., MSVC can't call ps() otherwise)
3656 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3657 }
3658
3659 void MacroAssembler::unimplemented(const char* what) {
3660 char* b = new char[1024];
3661 jio_snprintf(b, 1024, "unimplemented: %s", what);
3662 stop(b);
3663 }
3664
3665 #ifdef _LP64
3666 #define XSTATE_BV 0x200
3667 #endif
3668
3669 void MacroAssembler::pop_CPU_state() {
3670 pop_FPU_state();
3671 pop_IU_state();
3672 }
3673
3674 void MacroAssembler::pop_FPU_state() {
3675 #ifndef _LP64
3676 frstor(Address(rsp, 0));
3677 #else
3678 fxrstor(Address(rsp, 0));
3679 #endif
3680 addptr(rsp, FPUStateSizeInWords * wordSize);
3681 }
3682
3683 void MacroAssembler::pop_IU_state() {
3684 popa();
3685 LP64_ONLY(addq(rsp, 8));
3686 popf();
3687 }
3688
3689 // Save Integer and Float state
3690 // Warning: Stack must be 16 byte aligned (64bit)
3691 void MacroAssembler::push_CPU_state() {
3692 push_IU_state();
3693 push_FPU_state();
3694 }
3695
3696 void MacroAssembler::push_FPU_state() {
3697 subptr(rsp, FPUStateSizeInWords * wordSize);
3698 #ifndef _LP64
3699 fnsave(Address(rsp, 0));
3700 fwait();
3701 #else
3702 fxsave(Address(rsp, 0));
3703 #endif // LP64
3704 }
3705
3706 void MacroAssembler::push_IU_state() {
3707 // Push flags first because pusha kills them
3708 pushf();
3709 // Make sure rsp stays 16-byte aligned
3710 LP64_ONLY(subq(rsp, 8));
3711 pusha();
3712 }
3713
3714 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3715 if (!java_thread->is_valid()) {
3716 java_thread = rdi;
3717 get_thread(java_thread);
3718 }
3719 // we must set sp to zero to clear frame
3720 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3721 if (clear_fp) {
3722 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3723 }
3724
3725 // Always clear the pc because it could have been set by make_walkable()
3726 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3727
3728 vzeroupper();
3729 }
3730
3731 void MacroAssembler::restore_rax(Register tmp) {
3732 if (tmp == noreg) pop(rax);
3733 else if (tmp != rax) mov(rax, tmp);
3734 }
3735
3736 void MacroAssembler::round_to(Register reg, int modulus) {
3737 addptr(reg, modulus - 1);
3738 andptr(reg, -modulus);
3739 }
3740
3741 void MacroAssembler::save_rax(Register tmp) {
3742 if (tmp == noreg) push(rax);
3743 else if (tmp != rax) mov(tmp, rax);
3744 }
3745
3746 // Write serialization page so VM thread can do a pseudo remote membar.
3747 // We use the current thread pointer to calculate a thread specific
3748 // offset to write to within the page. This minimizes bus traffic
3749 // due to cache line collision.
3750 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3751 movl(tmp, thread);
3752 shrl(tmp, os::get_serialize_page_shift_count());
3753 andl(tmp, (os::vm_page_size() - sizeof(int)));
3754
3755 Address index(noreg, tmp, Address::times_1);
3756 ExternalAddress page(os::get_memory_serialize_page());
3757
3758 // Size of store must match masking code above
3759 movl(as_Address(ArrayAddress(page, index)), tmp);
3760 }
3761
3762 // Calls to C land
3763 //
3764 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3765 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3766 // has to be reset to 0. This is required to allow proper stack traversal.
3767 void MacroAssembler::set_last_Java_frame(Register java_thread,
3768 Register last_java_sp,
3769 Register last_java_fp,
3770 address last_java_pc) {
3771 vzeroupper();
3772 // determine java_thread register
3773 if (!java_thread->is_valid()) {
3774 java_thread = rdi;
3775 get_thread(java_thread);
3776 }
3777 // determine last_java_sp register
3778 if (!last_java_sp->is_valid()) {
3779 last_java_sp = rsp;
3780 }
3781
3782 // last_java_fp is optional
3783
3784 if (last_java_fp->is_valid()) {
3785 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3786 }
3787
3788 // last_java_pc is optional
3789
3790 if (last_java_pc != NULL) {
3791 lea(Address(java_thread,
3792 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3793 InternalAddress(last_java_pc));
3794
3795 }
3796 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3797 }
3798
3799 void MacroAssembler::shlptr(Register dst, int imm8) {
3800 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3801 }
3802
3803 void MacroAssembler::shrptr(Register dst, int imm8) {
3804 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3805 }
3806
3807 void MacroAssembler::sign_extend_byte(Register reg) {
3808 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3809 movsbl(reg, reg); // movsxb
3810 } else {
3811 shll(reg, 24);
3812 sarl(reg, 24);
3813 }
3814 }
3815
3816 void MacroAssembler::sign_extend_short(Register reg) {
3817 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3818 movswl(reg, reg); // movsxw
3819 } else {
3820 shll(reg, 16);
3821 sarl(reg, 16);
3822 }
3823 }
3824
3825 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3826 assert(reachable(src), "Address should be reachable");
3827 testl(dst, as_Address(src));
3828 }
3829
3830 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3831 int dst_enc = dst->encoding();
3832 int src_enc = src->encoding();
3833 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3834 Assembler::pcmpeqb(dst, src);
3835 } else if ((dst_enc < 16) && (src_enc < 16)) {
3836 Assembler::pcmpeqb(dst, src);
3837 } else if (src_enc < 16) {
3838 subptr(rsp, 64);
3839 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3840 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3841 Assembler::pcmpeqb(xmm0, src);
3842 movdqu(dst, xmm0);
3843 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3844 addptr(rsp, 64);
3845 } else if (dst_enc < 16) {
3846 subptr(rsp, 64);
3847 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3848 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3849 Assembler::pcmpeqb(dst, xmm0);
3850 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3851 addptr(rsp, 64);
3852 } else {
3853 subptr(rsp, 64);
3854 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3855 subptr(rsp, 64);
3856 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3857 movdqu(xmm0, src);
3858 movdqu(xmm1, dst);
3859 Assembler::pcmpeqb(xmm1, xmm0);
3860 movdqu(dst, xmm1);
3861 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3862 addptr(rsp, 64);
3863 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3864 addptr(rsp, 64);
3865 }
3866 }
3867
3868 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3869 int dst_enc = dst->encoding();
3870 int src_enc = src->encoding();
3871 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3872 Assembler::pcmpeqw(dst, src);
3873 } else if ((dst_enc < 16) && (src_enc < 16)) {
3874 Assembler::pcmpeqw(dst, src);
3875 } else if (src_enc < 16) {
3876 subptr(rsp, 64);
3877 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3878 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3879 Assembler::pcmpeqw(xmm0, src);
3880 movdqu(dst, xmm0);
3881 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3882 addptr(rsp, 64);
3883 } else if (dst_enc < 16) {
3884 subptr(rsp, 64);
3885 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3886 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3887 Assembler::pcmpeqw(dst, xmm0);
3888 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3889 addptr(rsp, 64);
3890 } else {
3891 subptr(rsp, 64);
3892 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3893 subptr(rsp, 64);
3894 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3895 movdqu(xmm0, src);
3896 movdqu(xmm1, dst);
3897 Assembler::pcmpeqw(xmm1, xmm0);
3898 movdqu(dst, xmm1);
3899 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3900 addptr(rsp, 64);
3901 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3902 addptr(rsp, 64);
3903 }
3904 }
3905
3906 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3907 int dst_enc = dst->encoding();
3908 if (dst_enc < 16) {
3909 Assembler::pcmpestri(dst, src, imm8);
3910 } else {
3911 subptr(rsp, 64);
3912 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3913 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3914 Assembler::pcmpestri(xmm0, src, imm8);
3915 movdqu(dst, xmm0);
3916 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3917 addptr(rsp, 64);
3918 }
3919 }
3920
3921 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3922 int dst_enc = dst->encoding();
3923 int src_enc = src->encoding();
3924 if ((dst_enc < 16) && (src_enc < 16)) {
3925 Assembler::pcmpestri(dst, src, imm8);
3926 } else if (src_enc < 16) {
3927 subptr(rsp, 64);
3928 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3929 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3930 Assembler::pcmpestri(xmm0, src, imm8);
3931 movdqu(dst, xmm0);
3932 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3933 addptr(rsp, 64);
3934 } else if (dst_enc < 16) {
3935 subptr(rsp, 64);
3936 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3937 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3938 Assembler::pcmpestri(dst, xmm0, imm8);
3939 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3940 addptr(rsp, 64);
3941 } else {
3942 subptr(rsp, 64);
3943 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3944 subptr(rsp, 64);
3945 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3946 movdqu(xmm0, src);
3947 movdqu(xmm1, dst);
3948 Assembler::pcmpestri(xmm1, xmm0, imm8);
3949 movdqu(dst, xmm1);
3950 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3951 addptr(rsp, 64);
3952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3953 addptr(rsp, 64);
3954 }
3955 }
3956
3957 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3958 int dst_enc = dst->encoding();
3959 int src_enc = src->encoding();
3960 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3961 Assembler::pmovzxbw(dst, src);
3962 } else if ((dst_enc < 16) && (src_enc < 16)) {
3963 Assembler::pmovzxbw(dst, src);
3964 } else if (src_enc < 16) {
3965 subptr(rsp, 64);
3966 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3967 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3968 Assembler::pmovzxbw(xmm0, src);
3969 movdqu(dst, xmm0);
3970 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3971 addptr(rsp, 64);
3972 } else if (dst_enc < 16) {
3973 subptr(rsp, 64);
3974 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3975 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3976 Assembler::pmovzxbw(dst, xmm0);
3977 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3978 addptr(rsp, 64);
3979 } else {
3980 subptr(rsp, 64);
3981 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3982 subptr(rsp, 64);
3983 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3984 movdqu(xmm0, src);
3985 movdqu(xmm1, dst);
3986 Assembler::pmovzxbw(xmm1, xmm0);
3987 movdqu(dst, xmm1);
3988 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3989 addptr(rsp, 64);
3990 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3991 addptr(rsp, 64);
3992 }
3993 }
3994
3995 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3996 int dst_enc = dst->encoding();
3997 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3998 Assembler::pmovzxbw(dst, src);
3999 } else if (dst_enc < 16) {
4000 Assembler::pmovzxbw(dst, src);
4001 } else {
4002 subptr(rsp, 64);
4003 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4004 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4005 Assembler::pmovzxbw(xmm0, src);
4006 movdqu(dst, xmm0);
4007 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4008 addptr(rsp, 64);
4009 }
4010 }
4011
4012 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
4013 int src_enc = src->encoding();
4014 if (src_enc < 16) {
4015 Assembler::pmovmskb(dst, src);
4016 } else {
4017 subptr(rsp, 64);
4018 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4019 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4020 Assembler::pmovmskb(dst, xmm0);
4021 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4022 addptr(rsp, 64);
4023 }
4024 }
4025
4026 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4027 int dst_enc = dst->encoding();
4028 int src_enc = src->encoding();
4029 if ((dst_enc < 16) && (src_enc < 16)) {
4030 Assembler::ptest(dst, src);
4031 } else if (src_enc < 16) {
4032 subptr(rsp, 64);
4033 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4034 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4035 Assembler::ptest(xmm0, src);
4036 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4037 addptr(rsp, 64);
4038 } else if (dst_enc < 16) {
4039 subptr(rsp, 64);
4040 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4041 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4042 Assembler::ptest(dst, xmm0);
4043 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4044 addptr(rsp, 64);
4045 } else {
4046 subptr(rsp, 64);
4047 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4048 subptr(rsp, 64);
4049 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4050 movdqu(xmm0, src);
4051 movdqu(xmm1, dst);
4052 Assembler::ptest(xmm1, xmm0);
4053 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4054 addptr(rsp, 64);
4055 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4056 addptr(rsp, 64);
4057 }
4058 }
4059
4060 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4061 if (reachable(src)) {
4062 Assembler::sqrtsd(dst, as_Address(src));
4063 } else {
4064 lea(rscratch1, src);
4065 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4066 }
4067 }
4068
4069 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4070 if (reachable(src)) {
4071 Assembler::sqrtss(dst, as_Address(src));
4072 } else {
4073 lea(rscratch1, src);
4074 Assembler::sqrtss(dst, Address(rscratch1, 0));
4075 }
4076 }
4077
4078 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4079 if (reachable(src)) {
4080 Assembler::subsd(dst, as_Address(src));
4081 } else {
4082 lea(rscratch1, src);
4083 Assembler::subsd(dst, Address(rscratch1, 0));
4084 }
4085 }
4086
4087 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4088 if (reachable(src)) {
4089 Assembler::subss(dst, as_Address(src));
4090 } else {
4091 lea(rscratch1, src);
4092 Assembler::subss(dst, Address(rscratch1, 0));
4093 }
4094 }
4095
4096 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4097 if (reachable(src)) {
4098 Assembler::ucomisd(dst, as_Address(src));
4099 } else {
4100 lea(rscratch1, src);
4101 Assembler::ucomisd(dst, Address(rscratch1, 0));
4102 }
4103 }
4104
4105 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4106 if (reachable(src)) {
4107 Assembler::ucomiss(dst, as_Address(src));
4108 } else {
4109 lea(rscratch1, src);
4110 Assembler::ucomiss(dst, Address(rscratch1, 0));
4111 }
4112 }
4113
4114 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4115 // Used in sign-bit flipping with aligned address.
4116 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4117 if (reachable(src)) {
4118 Assembler::xorpd(dst, as_Address(src));
4119 } else {
4120 lea(rscratch1, src);
4121 Assembler::xorpd(dst, Address(rscratch1, 0));
4122 }
4123 }
4124
4125 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4126 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4127 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4128 }
4129 else {
4130 Assembler::xorpd(dst, src);
4131 }
4132 }
4133
4134 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4135 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4136 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4137 } else {
4138 Assembler::xorps(dst, src);
4139 }
4140 }
4141
4142 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4143 // Used in sign-bit flipping with aligned address.
4144 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4145 if (reachable(src)) {
4146 Assembler::xorps(dst, as_Address(src));
4147 } else {
4148 lea(rscratch1, src);
4149 Assembler::xorps(dst, Address(rscratch1, 0));
4150 }
4151 }
4152
4153 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4154 // Used in sign-bit flipping with aligned address.
4155 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4156 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4157 if (reachable(src)) {
4158 Assembler::pshufb(dst, as_Address(src));
4159 } else {
4160 lea(rscratch1, src);
4161 Assembler::pshufb(dst, Address(rscratch1, 0));
4162 }
4163 }
4164
4165 // AVX 3-operands instructions
4166
4167 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4168 if (reachable(src)) {
4169 vaddsd(dst, nds, as_Address(src));
4170 } else {
4171 lea(rscratch1, src);
4172 vaddsd(dst, nds, Address(rscratch1, 0));
4173 }
4174 }
4175
4176 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4177 if (reachable(src)) {
4178 vaddss(dst, nds, as_Address(src));
4179 } else {
4180 lea(rscratch1, src);
4181 vaddss(dst, nds, Address(rscratch1, 0));
4182 }
4183 }
4184
4185 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4186 int dst_enc = dst->encoding();
4187 int nds_enc = nds->encoding();
4188 int src_enc = src->encoding();
4189 if ((dst_enc < 16) && (nds_enc < 16)) {
4190 vandps(dst, nds, negate_field, vector_len);
4191 } else if ((src_enc < 16) && (dst_enc < 16)) {
4192 evmovdqul(src, nds, Assembler::AVX_512bit);
4193 vandps(dst, src, negate_field, vector_len);
4194 } else if (src_enc < 16) {
4195 evmovdqul(src, nds, Assembler::AVX_512bit);
4196 vandps(src, src, negate_field, vector_len);
4197 evmovdqul(dst, src, Assembler::AVX_512bit);
4198 } else if (dst_enc < 16) {
4199 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4200 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4201 vandps(dst, xmm0, negate_field, vector_len);
4202 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4203 } else {
4204 if (src_enc != dst_enc) {
4205 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4206 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4207 vandps(xmm0, xmm0, negate_field, vector_len);
4208 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4209 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4210 } else {
4211 subptr(rsp, 64);
4212 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4213 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4214 vandps(xmm0, xmm0, negate_field, vector_len);
4215 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4216 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4217 addptr(rsp, 64);
4218 }
4219 }
4220 }
4221
4222 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4223 int dst_enc = dst->encoding();
4224 int nds_enc = nds->encoding();
4225 int src_enc = src->encoding();
4226 if ((dst_enc < 16) && (nds_enc < 16)) {
4227 vandpd(dst, nds, negate_field, vector_len);
4228 } else if ((src_enc < 16) && (dst_enc < 16)) {
4229 evmovdqul(src, nds, Assembler::AVX_512bit);
4230 vandpd(dst, src, negate_field, vector_len);
4231 } else if (src_enc < 16) {
4232 evmovdqul(src, nds, Assembler::AVX_512bit);
4233 vandpd(src, src, negate_field, vector_len);
4234 evmovdqul(dst, src, Assembler::AVX_512bit);
4235 } else if (dst_enc < 16) {
4236 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4237 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4238 vandpd(dst, xmm0, negate_field, vector_len);
4239 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4240 } else {
4241 if (src_enc != dst_enc) {
4242 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4243 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4244 vandpd(xmm0, xmm0, negate_field, vector_len);
4245 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4246 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4247 } else {
4248 subptr(rsp, 64);
4249 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4250 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4251 vandpd(xmm0, xmm0, negate_field, vector_len);
4252 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4253 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4254 addptr(rsp, 64);
4255 }
4256 }
4257 }
4258
4259 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4260 int dst_enc = dst->encoding();
4261 int nds_enc = nds->encoding();
4262 int src_enc = src->encoding();
4263 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4264 Assembler::vpaddb(dst, nds, src, vector_len);
4265 } else if ((dst_enc < 16) && (src_enc < 16)) {
4266 Assembler::vpaddb(dst, dst, src, vector_len);
4267 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4268 // use nds as scratch for src
4269 evmovdqul(nds, src, Assembler::AVX_512bit);
4270 Assembler::vpaddb(dst, dst, nds, vector_len);
4271 } else if ((src_enc < 16) && (nds_enc < 16)) {
4272 // use nds as scratch for dst
4273 evmovdqul(nds, dst, Assembler::AVX_512bit);
4274 Assembler::vpaddb(nds, nds, src, vector_len);
4275 evmovdqul(dst, nds, Assembler::AVX_512bit);
4276 } else if (dst_enc < 16) {
4277 // use nds as scatch for xmm0 to hold src
4278 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4279 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4280 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4281 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4282 } else {
4283 // worse case scenario, all regs are in the upper bank
4284 subptr(rsp, 64);
4285 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4286 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4287 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4288 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4289 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4290 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4291 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4292 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4293 addptr(rsp, 64);
4294 }
4295 }
4296
4297 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4298 int dst_enc = dst->encoding();
4299 int nds_enc = nds->encoding();
4300 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4301 Assembler::vpaddb(dst, nds, src, vector_len);
4302 } else if (dst_enc < 16) {
4303 Assembler::vpaddb(dst, dst, src, vector_len);
4304 } else if (nds_enc < 16) {
4305 // implies dst_enc in upper bank with src as scratch
4306 evmovdqul(nds, dst, Assembler::AVX_512bit);
4307 Assembler::vpaddb(nds, nds, src, vector_len);
4308 evmovdqul(dst, nds, Assembler::AVX_512bit);
4309 } else {
4310 // worse case scenario, all regs in upper bank
4311 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4312 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4313 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4314 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4315 }
4316 }
4317
4318 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4319 int dst_enc = dst->encoding();
4320 int nds_enc = nds->encoding();
4321 int src_enc = src->encoding();
4322 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4323 Assembler::vpaddw(dst, nds, src, vector_len);
4324 } else if ((dst_enc < 16) && (src_enc < 16)) {
4325 Assembler::vpaddw(dst, dst, src, vector_len);
4326 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4327 // use nds as scratch for src
4328 evmovdqul(nds, src, Assembler::AVX_512bit);
4329 Assembler::vpaddw(dst, dst, nds, vector_len);
4330 } else if ((src_enc < 16) && (nds_enc < 16)) {
4331 // use nds as scratch for dst
4332 evmovdqul(nds, dst, Assembler::AVX_512bit);
4333 Assembler::vpaddw(nds, nds, src, vector_len);
4334 evmovdqul(dst, nds, Assembler::AVX_512bit);
4335 } else if (dst_enc < 16) {
4336 // use nds as scatch for xmm0 to hold src
4337 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4338 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4339 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4340 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4341 } else {
4342 // worse case scenario, all regs are in the upper bank
4343 subptr(rsp, 64);
4344 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4345 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4346 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4347 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4348 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4349 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4350 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4351 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4352 addptr(rsp, 64);
4353 }
4354 }
4355
4356 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4357 int dst_enc = dst->encoding();
4358 int nds_enc = nds->encoding();
4359 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4360 Assembler::vpaddw(dst, nds, src, vector_len);
4361 } else if (dst_enc < 16) {
4362 Assembler::vpaddw(dst, dst, src, vector_len);
4363 } else if (nds_enc < 16) {
4364 // implies dst_enc in upper bank with src as scratch
4365 evmovdqul(nds, dst, Assembler::AVX_512bit);
4366 Assembler::vpaddw(nds, nds, src, vector_len);
4367 evmovdqul(dst, nds, Assembler::AVX_512bit);
4368 } else {
4369 // worse case scenario, all regs in upper bank
4370 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4371 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4372 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4373 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4374 }
4375 }
4376
4377 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4378 if (reachable(src)) {
4379 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4380 } else {
4381 lea(rscratch1, src);
4382 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4383 }
4384 }
4385
4386 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4387 int dst_enc = dst->encoding();
4388 int src_enc = src->encoding();
4389 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4390 Assembler::vpbroadcastw(dst, src);
4391 } else if ((dst_enc < 16) && (src_enc < 16)) {
4392 Assembler::vpbroadcastw(dst, src);
4393 } else if (src_enc < 16) {
4394 subptr(rsp, 64);
4395 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4396 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4397 Assembler::vpbroadcastw(xmm0, src);
4398 movdqu(dst, xmm0);
4399 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4400 addptr(rsp, 64);
4401 } else if (dst_enc < 16) {
4402 subptr(rsp, 64);
4403 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4404 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4405 Assembler::vpbroadcastw(dst, xmm0);
4406 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4407 addptr(rsp, 64);
4408 } else {
4409 subptr(rsp, 64);
4410 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4411 subptr(rsp, 64);
4412 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4413 movdqu(xmm0, src);
4414 movdqu(xmm1, dst);
4415 Assembler::vpbroadcastw(xmm1, xmm0);
4416 movdqu(dst, xmm1);
4417 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4418 addptr(rsp, 64);
4419 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4420 addptr(rsp, 64);
4421 }
4422 }
4423
4424 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4425 int dst_enc = dst->encoding();
4426 int nds_enc = nds->encoding();
4427 int src_enc = src->encoding();
4428 assert(dst_enc == nds_enc, "");
4429 if ((dst_enc < 16) && (src_enc < 16)) {
4430 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4431 } else if (src_enc < 16) {
4432 subptr(rsp, 64);
4433 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4434 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4435 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4436 movdqu(dst, xmm0);
4437 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4438 addptr(rsp, 64);
4439 } else if (dst_enc < 16) {
4440 subptr(rsp, 64);
4441 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4442 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4443 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4444 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4445 addptr(rsp, 64);
4446 } else {
4447 subptr(rsp, 64);
4448 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4449 subptr(rsp, 64);
4450 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4451 movdqu(xmm0, src);
4452 movdqu(xmm1, dst);
4453 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4454 movdqu(dst, xmm1);
4455 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4456 addptr(rsp, 64);
4457 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4458 addptr(rsp, 64);
4459 }
4460 }
4461
4462 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4463 int dst_enc = dst->encoding();
4464 int nds_enc = nds->encoding();
4465 int src_enc = src->encoding();
4466 assert(dst_enc == nds_enc, "");
4467 if ((dst_enc < 16) && (src_enc < 16)) {
4468 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4469 } else if (src_enc < 16) {
4470 subptr(rsp, 64);
4471 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4472 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4473 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4474 movdqu(dst, xmm0);
4475 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4476 addptr(rsp, 64);
4477 } else if (dst_enc < 16) {
4478 subptr(rsp, 64);
4479 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4480 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4481 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4482 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4483 addptr(rsp, 64);
4484 } else {
4485 subptr(rsp, 64);
4486 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4487 subptr(rsp, 64);
4488 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4489 movdqu(xmm0, src);
4490 movdqu(xmm1, dst);
4491 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4492 movdqu(dst, xmm1);
4493 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4494 addptr(rsp, 64);
4495 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4496 addptr(rsp, 64);
4497 }
4498 }
4499
4500 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4501 int dst_enc = dst->encoding();
4502 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4503 Assembler::vpmovzxbw(dst, src, vector_len);
4504 } else if (dst_enc < 16) {
4505 Assembler::vpmovzxbw(dst, src, vector_len);
4506 } else {
4507 subptr(rsp, 64);
4508 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4509 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4510 Assembler::vpmovzxbw(xmm0, src, vector_len);
4511 movdqu(dst, xmm0);
4512 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4513 addptr(rsp, 64);
4514 }
4515 }
4516
4517 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4518 int src_enc = src->encoding();
4519 if (src_enc < 16) {
4520 Assembler::vpmovmskb(dst, src);
4521 } else {
4522 subptr(rsp, 64);
4523 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4524 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4525 Assembler::vpmovmskb(dst, xmm0);
4526 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4527 addptr(rsp, 64);
4528 }
4529 }
4530
4531 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4532 int dst_enc = dst->encoding();
4533 int nds_enc = nds->encoding();
4534 int src_enc = src->encoding();
4535 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4536 Assembler::vpmullw(dst, nds, src, vector_len);
4537 } else if ((dst_enc < 16) && (src_enc < 16)) {
4538 Assembler::vpmullw(dst, dst, src, vector_len);
4539 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4540 // use nds as scratch for src
4541 evmovdqul(nds, src, Assembler::AVX_512bit);
4542 Assembler::vpmullw(dst, dst, nds, vector_len);
4543 } else if ((src_enc < 16) && (nds_enc < 16)) {
4544 // use nds as scratch for dst
4545 evmovdqul(nds, dst, Assembler::AVX_512bit);
4546 Assembler::vpmullw(nds, nds, src, vector_len);
4547 evmovdqul(dst, nds, Assembler::AVX_512bit);
4548 } else if (dst_enc < 16) {
4549 // use nds as scatch for xmm0 to hold src
4550 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4551 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4552 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4553 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4554 } else {
4555 // worse case scenario, all regs are in the upper bank
4556 subptr(rsp, 64);
4557 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4558 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4559 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4560 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4561 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4562 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4563 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4564 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4565 addptr(rsp, 64);
4566 }
4567 }
4568
4569 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4570 int dst_enc = dst->encoding();
4571 int nds_enc = nds->encoding();
4572 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4573 Assembler::vpmullw(dst, nds, src, vector_len);
4574 } else if (dst_enc < 16) {
4575 Assembler::vpmullw(dst, dst, src, vector_len);
4576 } else if (nds_enc < 16) {
4577 // implies dst_enc in upper bank with src as scratch
4578 evmovdqul(nds, dst, Assembler::AVX_512bit);
4579 Assembler::vpmullw(nds, nds, src, vector_len);
4580 evmovdqul(dst, nds, Assembler::AVX_512bit);
4581 } else {
4582 // worse case scenario, all regs in upper bank
4583 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4584 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4585 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4586 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4587 }
4588 }
4589
4590 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4591 int dst_enc = dst->encoding();
4592 int nds_enc = nds->encoding();
4593 int src_enc = src->encoding();
4594 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4595 Assembler::vpsubb(dst, nds, src, vector_len);
4596 } else if ((dst_enc < 16) && (src_enc < 16)) {
4597 Assembler::vpsubb(dst, dst, src, vector_len);
4598 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4599 // use nds as scratch for src
4600 evmovdqul(nds, src, Assembler::AVX_512bit);
4601 Assembler::vpsubb(dst, dst, nds, vector_len);
4602 } else if ((src_enc < 16) && (nds_enc < 16)) {
4603 // use nds as scratch for dst
4604 evmovdqul(nds, dst, Assembler::AVX_512bit);
4605 Assembler::vpsubb(nds, nds, src, vector_len);
4606 evmovdqul(dst, nds, Assembler::AVX_512bit);
4607 } else if (dst_enc < 16) {
4608 // use nds as scatch for xmm0 to hold src
4609 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4610 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4611 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4612 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4613 } else {
4614 // worse case scenario, all regs are in the upper bank
4615 subptr(rsp, 64);
4616 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4617 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4618 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4619 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4620 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4621 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4622 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4623 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4624 addptr(rsp, 64);
4625 }
4626 }
4627
4628 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4629 int dst_enc = dst->encoding();
4630 int nds_enc = nds->encoding();
4631 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4632 Assembler::vpsubb(dst, nds, src, vector_len);
4633 } else if (dst_enc < 16) {
4634 Assembler::vpsubb(dst, dst, src, vector_len);
4635 } else if (nds_enc < 16) {
4636 // implies dst_enc in upper bank with src as scratch
4637 evmovdqul(nds, dst, Assembler::AVX_512bit);
4638 Assembler::vpsubb(nds, nds, src, vector_len);
4639 evmovdqul(dst, nds, Assembler::AVX_512bit);
4640 } else {
4641 // worse case scenario, all regs in upper bank
4642 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4643 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4644 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4645 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4646 }
4647 }
4648
4649 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4650 int dst_enc = dst->encoding();
4651 int nds_enc = nds->encoding();
4652 int src_enc = src->encoding();
4653 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4654 Assembler::vpsubw(dst, nds, src, vector_len);
4655 } else if ((dst_enc < 16) && (src_enc < 16)) {
4656 Assembler::vpsubw(dst, dst, src, vector_len);
4657 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4658 // use nds as scratch for src
4659 evmovdqul(nds, src, Assembler::AVX_512bit);
4660 Assembler::vpsubw(dst, dst, nds, vector_len);
4661 } else if ((src_enc < 16) && (nds_enc < 16)) {
4662 // use nds as scratch for dst
4663 evmovdqul(nds, dst, Assembler::AVX_512bit);
4664 Assembler::vpsubw(nds, nds, src, vector_len);
4665 evmovdqul(dst, nds, Assembler::AVX_512bit);
4666 } else if (dst_enc < 16) {
4667 // use nds as scatch for xmm0 to hold src
4668 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4669 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4670 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4671 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4672 } else {
4673 // worse case scenario, all regs are in the upper bank
4674 subptr(rsp, 64);
4675 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4676 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4677 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4678 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4679 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4680 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4681 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4682 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4683 addptr(rsp, 64);
4684 }
4685 }
4686
4687 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4688 int dst_enc = dst->encoding();
4689 int nds_enc = nds->encoding();
4690 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4691 Assembler::vpsubw(dst, nds, src, vector_len);
4692 } else if (dst_enc < 16) {
4693 Assembler::vpsubw(dst, dst, src, vector_len);
4694 } else if (nds_enc < 16) {
4695 // implies dst_enc in upper bank with src as scratch
4696 evmovdqul(nds, dst, Assembler::AVX_512bit);
4697 Assembler::vpsubw(nds, nds, src, vector_len);
4698 evmovdqul(dst, nds, Assembler::AVX_512bit);
4699 } else {
4700 // worse case scenario, all regs in upper bank
4701 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4702 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4703 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4704 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4705 }
4706 }
4707
4708 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4709 int dst_enc = dst->encoding();
4710 int nds_enc = nds->encoding();
4711 int shift_enc = shift->encoding();
4712 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4713 Assembler::vpsraw(dst, nds, shift, vector_len);
4714 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4715 Assembler::vpsraw(dst, dst, shift, vector_len);
4716 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4717 // use nds_enc as scratch with shift
4718 evmovdqul(nds, shift, Assembler::AVX_512bit);
4719 Assembler::vpsraw(dst, dst, nds, vector_len);
4720 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4721 // use nds as scratch with dst
4722 evmovdqul(nds, dst, Assembler::AVX_512bit);
4723 Assembler::vpsraw(nds, nds, shift, vector_len);
4724 evmovdqul(dst, nds, Assembler::AVX_512bit);
4725 } else if (dst_enc < 16) {
4726 // use nds to save a copy of xmm0 and hold shift
4727 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4728 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4729 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4730 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4731 } else if (nds_enc < 16) {
4732 // use nds as dest as temps
4733 evmovdqul(nds, dst, Assembler::AVX_512bit);
4734 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4735 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4736 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4737 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4738 evmovdqul(dst, nds, Assembler::AVX_512bit);
4739 } else {
4740 // worse case scenario, all regs are in the upper bank
4741 subptr(rsp, 64);
4742 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4743 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4744 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4745 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4746 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4747 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4748 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4749 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4750 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4751 addptr(rsp, 64);
4752 }
4753 }
4754
4755 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4756 int dst_enc = dst->encoding();
4757 int nds_enc = nds->encoding();
4758 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4759 Assembler::vpsraw(dst, nds, shift, vector_len);
4760 } else if (dst_enc < 16) {
4761 Assembler::vpsraw(dst, dst, shift, vector_len);
4762 } else if (nds_enc < 16) {
4763 // use nds as scratch
4764 evmovdqul(nds, dst, Assembler::AVX_512bit);
4765 Assembler::vpsraw(nds, nds, shift, vector_len);
4766 evmovdqul(dst, nds, Assembler::AVX_512bit);
4767 } else {
4768 // use nds as scratch for xmm0
4769 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4770 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4771 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4772 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4773 }
4774 }
4775
4776 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4777 int dst_enc = dst->encoding();
4778 int nds_enc = nds->encoding();
4779 int shift_enc = shift->encoding();
4780 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4781 Assembler::vpsrlw(dst, nds, shift, vector_len);
4782 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4783 Assembler::vpsrlw(dst, dst, shift, vector_len);
4784 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4785 // use nds_enc as scratch with shift
4786 evmovdqul(nds, shift, Assembler::AVX_512bit);
4787 Assembler::vpsrlw(dst, dst, nds, vector_len);
4788 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4789 // use nds as scratch with dst
4790 evmovdqul(nds, dst, Assembler::AVX_512bit);
4791 Assembler::vpsrlw(nds, nds, shift, vector_len);
4792 evmovdqul(dst, nds, Assembler::AVX_512bit);
4793 } else if (dst_enc < 16) {
4794 // use nds to save a copy of xmm0 and hold shift
4795 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4796 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4797 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4798 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4799 } else if (nds_enc < 16) {
4800 // use nds as dest as temps
4801 evmovdqul(nds, dst, Assembler::AVX_512bit);
4802 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4803 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4804 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4805 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4806 evmovdqul(dst, nds, Assembler::AVX_512bit);
4807 } else {
4808 // worse case scenario, all regs are in the upper bank
4809 subptr(rsp, 64);
4810 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4811 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4812 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4813 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4814 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4815 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4816 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4817 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4818 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4819 addptr(rsp, 64);
4820 }
4821 }
4822
4823 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4824 int dst_enc = dst->encoding();
4825 int nds_enc = nds->encoding();
4826 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4827 Assembler::vpsrlw(dst, nds, shift, vector_len);
4828 } else if (dst_enc < 16) {
4829 Assembler::vpsrlw(dst, dst, shift, vector_len);
4830 } else if (nds_enc < 16) {
4831 // use nds as scratch
4832 evmovdqul(nds, dst, Assembler::AVX_512bit);
4833 Assembler::vpsrlw(nds, nds, shift, vector_len);
4834 evmovdqul(dst, nds, Assembler::AVX_512bit);
4835 } else {
4836 // use nds as scratch for xmm0
4837 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4838 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4839 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4840 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4841 }
4842 }
4843
4844 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4845 int dst_enc = dst->encoding();
4846 int nds_enc = nds->encoding();
4847 int shift_enc = shift->encoding();
4848 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4849 Assembler::vpsllw(dst, nds, shift, vector_len);
4850 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4851 Assembler::vpsllw(dst, dst, shift, vector_len);
4852 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4853 // use nds_enc as scratch with shift
4854 evmovdqul(nds, shift, Assembler::AVX_512bit);
4855 Assembler::vpsllw(dst, dst, nds, vector_len);
4856 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4857 // use nds as scratch with dst
4858 evmovdqul(nds, dst, Assembler::AVX_512bit);
4859 Assembler::vpsllw(nds, nds, shift, vector_len);
4860 evmovdqul(dst, nds, Assembler::AVX_512bit);
4861 } else if (dst_enc < 16) {
4862 // use nds to save a copy of xmm0 and hold shift
4863 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4864 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4865 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4866 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4867 } else if (nds_enc < 16) {
4868 // use nds as dest as temps
4869 evmovdqul(nds, dst, Assembler::AVX_512bit);
4870 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4871 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4872 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4873 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4874 evmovdqul(dst, nds, Assembler::AVX_512bit);
4875 } else {
4876 // worse case scenario, all regs are in the upper bank
4877 subptr(rsp, 64);
4878 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4879 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4880 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4881 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4882 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4883 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4884 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4885 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4886 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4887 addptr(rsp, 64);
4888 }
4889 }
4890
4891 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4892 int dst_enc = dst->encoding();
4893 int nds_enc = nds->encoding();
4894 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4895 Assembler::vpsllw(dst, nds, shift, vector_len);
4896 } else if (dst_enc < 16) {
4897 Assembler::vpsllw(dst, dst, shift, vector_len);
4898 } else if (nds_enc < 16) {
4899 // use nds as scratch
4900 evmovdqul(nds, dst, Assembler::AVX_512bit);
4901 Assembler::vpsllw(nds, nds, shift, vector_len);
4902 evmovdqul(dst, nds, Assembler::AVX_512bit);
4903 } else {
4904 // use nds as scratch for xmm0
4905 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4906 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4907 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4908 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4909 }
4910 }
4911
4912 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4913 int dst_enc = dst->encoding();
4914 int src_enc = src->encoding();
4915 if ((dst_enc < 16) && (src_enc < 16)) {
4916 Assembler::vptest(dst, src);
4917 } else if (src_enc < 16) {
4918 subptr(rsp, 64);
4919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4920 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4921 Assembler::vptest(xmm0, src);
4922 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4923 addptr(rsp, 64);
4924 } else if (dst_enc < 16) {
4925 subptr(rsp, 64);
4926 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4927 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4928 Assembler::vptest(dst, xmm0);
4929 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4930 addptr(rsp, 64);
4931 } else {
4932 subptr(rsp, 64);
4933 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4934 subptr(rsp, 64);
4935 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4936 movdqu(xmm0, src);
4937 movdqu(xmm1, dst);
4938 Assembler::vptest(xmm1, xmm0);
4939 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4940 addptr(rsp, 64);
4941 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4942 addptr(rsp, 64);
4943 }
4944 }
4945
4946 // This instruction exists within macros, ergo we cannot control its input
4947 // when emitted through those patterns.
4948 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4949 if (VM_Version::supports_avx512nobw()) {
4950 int dst_enc = dst->encoding();
4951 int src_enc = src->encoding();
4952 if (dst_enc == src_enc) {
4953 if (dst_enc < 16) {
4954 Assembler::punpcklbw(dst, src);
4955 } else {
4956 subptr(rsp, 64);
4957 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4958 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4959 Assembler::punpcklbw(xmm0, xmm0);
4960 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4961 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4962 addptr(rsp, 64);
4963 }
4964 } else {
4965 if ((src_enc < 16) && (dst_enc < 16)) {
4966 Assembler::punpcklbw(dst, src);
4967 } else if (src_enc < 16) {
4968 subptr(rsp, 64);
4969 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4970 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4971 Assembler::punpcklbw(xmm0, src);
4972 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4973 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4974 addptr(rsp, 64);
4975 } else if (dst_enc < 16) {
4976 subptr(rsp, 64);
4977 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4978 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4979 Assembler::punpcklbw(dst, xmm0);
4980 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4981 addptr(rsp, 64);
4982 } else {
4983 subptr(rsp, 64);
4984 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4985 subptr(rsp, 64);
4986 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4987 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4988 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4989 Assembler::punpcklbw(xmm0, xmm1);
4990 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4991 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4992 addptr(rsp, 64);
4993 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4994 addptr(rsp, 64);
4995 }
4996 }
4997 } else {
4998 Assembler::punpcklbw(dst, src);
4999 }
5000 }
5001
5002 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
5003 if (VM_Version::supports_avx512vl()) {
5004 Assembler::pshufd(dst, src, mode);
5005 } else {
5006 int dst_enc = dst->encoding();
5007 if (dst_enc < 16) {
5008 Assembler::pshufd(dst, src, mode);
5009 } else {
5010 subptr(rsp, 64);
5011 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5012 Assembler::pshufd(xmm0, src, mode);
5013 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5014 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5015 addptr(rsp, 64);
5016 }
5017 }
5018 }
5019
5020 // This instruction exists within macros, ergo we cannot control its input
5021 // when emitted through those patterns.
5022 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5023 if (VM_Version::supports_avx512nobw()) {
5024 int dst_enc = dst->encoding();
5025 int src_enc = src->encoding();
5026 if (dst_enc == src_enc) {
5027 if (dst_enc < 16) {
5028 Assembler::pshuflw(dst, src, mode);
5029 } else {
5030 subptr(rsp, 64);
5031 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5032 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5033 Assembler::pshuflw(xmm0, xmm0, mode);
5034 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5035 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5036 addptr(rsp, 64);
5037 }
5038 } else {
5039 if ((src_enc < 16) && (dst_enc < 16)) {
5040 Assembler::pshuflw(dst, src, mode);
5041 } else if (src_enc < 16) {
5042 subptr(rsp, 64);
5043 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5044 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5045 Assembler::pshuflw(xmm0, src, mode);
5046 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5047 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5048 addptr(rsp, 64);
5049 } else if (dst_enc < 16) {
5050 subptr(rsp, 64);
5051 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5052 evmovdqul(xmm0, src, Assembler::AVX_512bit);
5053 Assembler::pshuflw(dst, xmm0, mode);
5054 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5055 addptr(rsp, 64);
5056 } else {
5057 subptr(rsp, 64);
5058 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5059 subptr(rsp, 64);
5060 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5061 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5062 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5063 Assembler::pshuflw(xmm0, xmm1, mode);
5064 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5065 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5066 addptr(rsp, 64);
5067 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5068 addptr(rsp, 64);
5069 }
5070 }
5071 } else {
5072 Assembler::pshuflw(dst, src, mode);
5073 }
5074 }
5075
5076 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5077 if (reachable(src)) {
5078 vandpd(dst, nds, as_Address(src), vector_len);
5079 } else {
5080 lea(rscratch1, src);
5081 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5082 }
5083 }
5084
5085 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5086 if (reachable(src)) {
5087 vandps(dst, nds, as_Address(src), vector_len);
5088 } else {
5089 lea(rscratch1, src);
5090 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5091 }
5092 }
5093
5094 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5095 if (reachable(src)) {
5096 vdivsd(dst, nds, as_Address(src));
5097 } else {
5098 lea(rscratch1, src);
5099 vdivsd(dst, nds, Address(rscratch1, 0));
5100 }
5101 }
5102
5103 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5104 if (reachable(src)) {
5105 vdivss(dst, nds, as_Address(src));
5106 } else {
5107 lea(rscratch1, src);
5108 vdivss(dst, nds, Address(rscratch1, 0));
5109 }
5110 }
5111
5112 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5113 if (reachable(src)) {
5114 vmulsd(dst, nds, as_Address(src));
5115 } else {
5116 lea(rscratch1, src);
5117 vmulsd(dst, nds, Address(rscratch1, 0));
5118 }
5119 }
5120
5121 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5122 if (reachable(src)) {
5123 vmulss(dst, nds, as_Address(src));
5124 } else {
5125 lea(rscratch1, src);
5126 vmulss(dst, nds, Address(rscratch1, 0));
5127 }
5128 }
5129
5130 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5131 if (reachable(src)) {
5132 vsubsd(dst, nds, as_Address(src));
5133 } else {
5134 lea(rscratch1, src);
5135 vsubsd(dst, nds, Address(rscratch1, 0));
5136 }
5137 }
5138
5139 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5140 if (reachable(src)) {
5141 vsubss(dst, nds, as_Address(src));
5142 } else {
5143 lea(rscratch1, src);
5144 vsubss(dst, nds, Address(rscratch1, 0));
5145 }
5146 }
5147
5148 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5149 int nds_enc = nds->encoding();
5150 int dst_enc = dst->encoding();
5151 bool dst_upper_bank = (dst_enc > 15);
5152 bool nds_upper_bank = (nds_enc > 15);
5153 if (VM_Version::supports_avx512novl() &&
5154 (nds_upper_bank || dst_upper_bank)) {
5155 if (dst_upper_bank) {
5156 subptr(rsp, 64);
5157 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5158 movflt(xmm0, nds);
5159 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5160 movflt(dst, xmm0);
5161 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5162 addptr(rsp, 64);
5163 } else {
5164 movflt(dst, nds);
5165 vxorps(dst, dst, src, Assembler::AVX_128bit);
5166 }
5167 } else {
5168 vxorps(dst, nds, src, Assembler::AVX_128bit);
5169 }
5170 }
5171
5172 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5173 int nds_enc = nds->encoding();
5174 int dst_enc = dst->encoding();
5175 bool dst_upper_bank = (dst_enc > 15);
5176 bool nds_upper_bank = (nds_enc > 15);
5177 if (VM_Version::supports_avx512novl() &&
5178 (nds_upper_bank || dst_upper_bank)) {
5179 if (dst_upper_bank) {
5180 subptr(rsp, 64);
5181 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5182 movdbl(xmm0, nds);
5183 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5184 movdbl(dst, xmm0);
5185 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5186 addptr(rsp, 64);
5187 } else {
5188 movdbl(dst, nds);
5189 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5190 }
5191 } else {
5192 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5193 }
5194 }
5195
5196 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5197 if (reachable(src)) {
5198 vxorpd(dst, nds, as_Address(src), vector_len);
5199 } else {
5200 lea(rscratch1, src);
5201 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5202 }
5203 }
5204
5205 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5206 if (reachable(src)) {
5207 vxorps(dst, nds, as_Address(src), vector_len);
5208 } else {
5209 lea(rscratch1, src);
5210 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5211 }
5212 }
5213
5214
5215 void MacroAssembler::resolve_jobject(Register value,
5216 Register thread,
5217 Register tmp) {
5218 assert_different_registers(value, thread, tmp);
5219 Label done, not_weak;
5220 testptr(value, value);
5221 jcc(Assembler::zero, done); // Use NULL as-is.
5222 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5223 jcc(Assembler::zero, not_weak);
5224 // Resolve jweak.
5225 movptr(value, Address(value, -JNIHandles::weak_tag_value));
5226 verify_oop(value);
5227 #if INCLUDE_ALL_GCS
5228 if (UseG1GC) {
5229 g1_write_barrier_pre(noreg /* obj */,
5230 value /* pre_val */,
5231 thread /* thread */,
5232 tmp /* tmp */,
5233 true /* tosca_live */,
5234 true /* expand_call */);
5235 }
5236 #endif // INCLUDE_ALL_GCS
5237 jmp(done);
5238 bind(not_weak);
5239 // Resolve (untagged) jobject.
5240 movptr(value, Address(value, 0));
5241 verify_oop(value);
5242 bind(done);
5243 }
5244
5245 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5246 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5247 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5248 // The inverted mask is sign-extended
5249 andptr(possibly_jweak, inverted_jweak_mask);
5250 }
5251
5252 //////////////////////////////////////////////////////////////////////////////////
5253 #if INCLUDE_ALL_GCS
5254
5255 void MacroAssembler::g1_write_barrier_pre(Register obj,
5256 Register pre_val,
5257 Register thread,
5258 Register tmp,
5259 bool tosca_live,
5260 bool expand_call) {
5261
5262 // If expand_call is true then we expand the call_VM_leaf macro
5263 // directly to skip generating the check by
5264 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5265
5266 #ifdef _LP64
5267 assert(thread == r15_thread, "must be");
5268 #endif // _LP64
5269
5270 Label done;
5271 Label runtime;
5272
5273 assert(pre_val != noreg, "check this code");
5274
5275 if (obj != noreg) {
5276 assert_different_registers(obj, pre_val, tmp);
5277 assert(pre_val != rax, "check this code");
5278 }
5279
5280 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5281 SATBMarkQueue::byte_offset_of_active()));
5282 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5283 SATBMarkQueue::byte_offset_of_index()));
5284 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5285 SATBMarkQueue::byte_offset_of_buf()));
5286
5287
5288 // Is marking active?
5289 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5290 cmpl(in_progress, 0);
5291 } else {
5292 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5293 cmpb(in_progress, 0);
5294 }
5295 jcc(Assembler::equal, done);
5296
5297 // Do we need to load the previous value?
5298 if (obj != noreg) {
5299 load_heap_oop(pre_val, Address(obj, 0));
5300 }
5301
5302 // Is the previous value null?
5303 cmpptr(pre_val, (int32_t) NULL_WORD);
5304 jcc(Assembler::equal, done);
5305
5306 // Can we store original value in the thread's buffer?
5307 // Is index == 0?
5308 // (The index field is typed as size_t.)
5309
5310 movptr(tmp, index); // tmp := *index_adr
5311 cmpptr(tmp, 0); // tmp == 0?
5312 jcc(Assembler::equal, runtime); // If yes, goto runtime
5313
5314 subptr(tmp, wordSize); // tmp := tmp - wordSize
5315 movptr(index, tmp); // *index_adr := tmp
5316 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5317
5318 // Record the previous value
5319 movptr(Address(tmp, 0), pre_val);
5320 jmp(done);
5321
5322 bind(runtime);
5323 // save the live input values
5324 if(tosca_live) push(rax);
5325
5326 if (obj != noreg && obj != rax)
5327 push(obj);
5328
5329 if (pre_val != rax)
5330 push(pre_val);
5331
5332 // Calling the runtime using the regular call_VM_leaf mechanism generates
5333 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5334 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5335 //
5336 // If we care generating the pre-barrier without a frame (e.g. in the
5337 // intrinsified Reference.get() routine) then ebp might be pointing to
5338 // the caller frame and so this check will most likely fail at runtime.
5339 //
5340 // Expanding the call directly bypasses the generation of the check.
5341 // So when we do not have have a full interpreter frame on the stack
5342 // expand_call should be passed true.
5343
5344 NOT_LP64( push(thread); )
5345
5346 if (expand_call) {
5347 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5348 pass_arg1(this, thread);
5349 pass_arg0(this, pre_val);
5350 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5351 } else {
5352 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5353 }
5354
5355 NOT_LP64( pop(thread); )
5356
5357 // save the live input values
5358 if (pre_val != rax)
5359 pop(pre_val);
5360
5361 if (obj != noreg && obj != rax)
5362 pop(obj);
5363
5364 if(tosca_live) pop(rax);
5365
5366 bind(done);
5367 }
5368
5369 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5370 Register new_val,
5371 Register thread,
5372 Register tmp,
5373 Register tmp2) {
5374 #ifdef _LP64
5375 assert(thread == r15_thread, "must be");
5376 #endif // _LP64
5377
5378 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5379 DirtyCardQueue::byte_offset_of_index()));
5380 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5381 DirtyCardQueue::byte_offset_of_buf()));
5382
5383 CardTableModRefBS* ct =
5384 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5385 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5386
5387 Label done;
5388 Label runtime;
5389
5390 // Does store cross heap regions?
5391
5392 movptr(tmp, store_addr);
5393 xorptr(tmp, new_val);
5394 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5395 jcc(Assembler::equal, done);
5396
5397 // crosses regions, storing NULL?
5398
5399 cmpptr(new_val, (int32_t) NULL_WORD);
5400 jcc(Assembler::equal, done);
5401
5402 // storing region crossing non-NULL, is card already dirty?
5403
5404 const Register card_addr = tmp;
5405 const Register cardtable = tmp2;
5406
5407 movptr(card_addr, store_addr);
5408 shrptr(card_addr, CardTableModRefBS::card_shift);
5409 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5410 // a valid address and therefore is not properly handled by the relocation code.
5411 movptr(cardtable, (intptr_t)ct->byte_map_base);
5412 addptr(card_addr, cardtable);
5413
5414 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5415 jcc(Assembler::equal, done);
5416
5417 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5418 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5419 jcc(Assembler::equal, done);
5420
5421
5422 // storing a region crossing, non-NULL oop, card is clean.
5423 // dirty card and log.
5424
5425 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5426
5427 cmpl(queue_index, 0);
5428 jcc(Assembler::equal, runtime);
5429 subl(queue_index, wordSize);
5430 movptr(tmp2, buffer);
5431 #ifdef _LP64
5432 movslq(rscratch1, queue_index);
5433 addq(tmp2, rscratch1);
5434 movq(Address(tmp2, 0), card_addr);
5435 #else
5436 addl(tmp2, queue_index);
5437 movl(Address(tmp2, 0), card_addr);
5438 #endif
5439 jmp(done);
5440
5441 bind(runtime);
5442 // save the live input values
5443 push(store_addr);
5444 push(new_val);
5445 #ifdef _LP64
5446 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5447 #else
5448 push(thread);
5449 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5450 pop(thread);
5451 #endif
5452 pop(new_val);
5453 pop(store_addr);
5454
5455 bind(done);
5456 }
5457
5458 #endif // INCLUDE_ALL_GCS
5459 //////////////////////////////////////////////////////////////////////////////////
5460
5461
5462 void MacroAssembler::store_check(Register obj, Address dst) {
5463 store_check(obj);
5464 }
5465
5466 void MacroAssembler::store_check(Register obj) {
5467 // Does a store check for the oop in register obj. The content of
5468 // register obj is destroyed afterwards.
5469 BarrierSet* bs = Universe::heap()->barrier_set();
5470 assert(bs->kind() == BarrierSet::CardTableForRS ||
5471 bs->kind() == BarrierSet::CardTableExtension,
5472 "Wrong barrier set kind");
5473
5474 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5475 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5476
5477 shrptr(obj, CardTableModRefBS::card_shift);
5478
5479 Address card_addr;
5480
5481 // The calculation for byte_map_base is as follows:
5482 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5483 // So this essentially converts an address to a displacement and it will
5484 // never need to be relocated. On 64bit however the value may be too
5485 // large for a 32bit displacement.
5486 intptr_t disp = (intptr_t) ct->byte_map_base;
5487 if (is_simm32(disp)) {
5488 card_addr = Address(noreg, obj, Address::times_1, disp);
5489 } else {
5490 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5491 // displacement and done in a single instruction given favorable mapping and a
5492 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5493 // entry and that entry is not properly handled by the relocation code.
5494 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5495 Address index(noreg, obj, Address::times_1);
5496 card_addr = as_Address(ArrayAddress(cardtable, index));
5497 }
5498
5499 int dirty = CardTableModRefBS::dirty_card_val();
5500 if (UseCondCardMark) {
5501 Label L_already_dirty;
5502 if (UseConcMarkSweepGC) {
5503 membar(Assembler::StoreLoad);
5504 }
5505 cmpb(card_addr, dirty);
5506 jcc(Assembler::equal, L_already_dirty);
5507 movb(card_addr, dirty);
5508 bind(L_already_dirty);
5509 } else {
5510 movb(card_addr, dirty);
5511 }
5512 }
5513
5514 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5515 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5516 }
5517
5518 // Force generation of a 4 byte immediate value even if it fits into 8bit
5519 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5520 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5521 }
5522
5523 void MacroAssembler::subptr(Register dst, Register src) {
5524 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5525 }
5526
5527 // C++ bool manipulation
5528 void MacroAssembler::testbool(Register dst) {
5529 if(sizeof(bool) == 1)
5530 testb(dst, 0xff);
5531 else if(sizeof(bool) == 2) {
5532 // testw implementation needed for two byte bools
5533 ShouldNotReachHere();
5534 } else if(sizeof(bool) == 4)
5535 testl(dst, dst);
5536 else
5537 // unsupported
5538 ShouldNotReachHere();
5539 }
5540
5541 void MacroAssembler::testptr(Register dst, Register src) {
5542 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5543 }
5544
5545 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5546 void MacroAssembler::tlab_allocate(Register obj,
5547 Register var_size_in_bytes,
5548 int con_size_in_bytes,
5549 Register t1,
5550 Register t2,
5551 Label& slow_case) {
5552 assert_different_registers(obj, t1, t2);
5553 assert_different_registers(obj, var_size_in_bytes, t1);
5554 Register end = t2;
5555 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5556
5557 verify_tlab();
5558
5559 NOT_LP64(get_thread(thread));
5560
5561 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5562 if (var_size_in_bytes == noreg) {
5563 lea(end, Address(obj, con_size_in_bytes));
5564 } else {
5565 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5566 }
5567 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5568 jcc(Assembler::above, slow_case);
5569
5570 // update the tlab top pointer
5571 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5572
5573 // recover var_size_in_bytes if necessary
5574 if (var_size_in_bytes == end) {
5575 subptr(var_size_in_bytes, obj);
5576 }
5577 verify_tlab();
5578 }
5579
5580 // Preserves rbx, and rdx.
5581 Register MacroAssembler::tlab_refill(Label& retry,
5582 Label& try_eden,
5583 Label& slow_case) {
5584 Register top = rax;
5585 Register t1 = rcx; // object size
5586 Register t2 = rsi;
5587 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5588 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5589 Label do_refill, discard_tlab;
5590
5591 if (!Universe::heap()->supports_inline_contig_alloc()) {
5592 // No allocation in the shared eden.
5593 jmp(slow_case);
5594 }
5595
5596 NOT_LP64(get_thread(thread_reg));
5597
5598 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5599 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5600
5601 // calculate amount of free space
5602 subptr(t1, top);
5603 shrptr(t1, LogHeapWordSize);
5604
5605 // Retain tlab and allocate object in shared space if
5606 // the amount free in the tlab is too large to discard.
5607 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5608 jcc(Assembler::lessEqual, discard_tlab);
5609
5610 // Retain
5611 // %%% yuck as movptr...
5612 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5613 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5614 if (TLABStats) {
5615 // increment number of slow_allocations
5616 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5617 }
5618 jmp(try_eden);
5619
5620 bind(discard_tlab);
5621 if (TLABStats) {
5622 // increment number of refills
5623 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5624 // accumulate wastage -- t1 is amount free in tlab
5625 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5626 }
5627
5628 // if tlab is currently allocated (top or end != null) then
5629 // fill [top, end + alignment_reserve) with array object
5630 testptr(top, top);
5631 jcc(Assembler::zero, do_refill);
5632
5633 // set up the mark word
5634 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5635 // set the length to the remaining space
5636 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5637 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5638 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5639 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5640 // set klass to intArrayKlass
5641 // dubious reloc why not an oop reloc?
5642 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5643 // store klass last. concurrent gcs assumes klass length is valid if
5644 // klass field is not null.
5645 store_klass(top, t1);
5646
5647 movptr(t1, top);
5648 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5649 incr_allocated_bytes(thread_reg, t1, 0);
5650
5651 // refill the tlab with an eden allocation
5652 bind(do_refill);
5653 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5654 shlptr(t1, LogHeapWordSize);
5655 // allocate new tlab, address returned in top
5656 eden_allocate(top, t1, 0, t2, slow_case);
5657
5658 // Check that t1 was preserved in eden_allocate.
5659 #ifdef ASSERT
5660 if (UseTLAB) {
5661 Label ok;
5662 Register tsize = rsi;
5663 assert_different_registers(tsize, thread_reg, t1);
5664 push(tsize);
5665 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5666 shlptr(tsize, LogHeapWordSize);
5667 cmpptr(t1, tsize);
5668 jcc(Assembler::equal, ok);
5669 STOP("assert(t1 != tlab size)");
5670 should_not_reach_here();
5671
5672 bind(ok);
5673 pop(tsize);
5674 }
5675 #endif
5676 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5677 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5678 addptr(top, t1);
5679 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5680 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5681
5682 if (ZeroTLAB) {
5683 // This is a fast TLAB refill, therefore the GC is not notified of it.
5684 // So compiled code must fill the new TLAB with zeroes.
5685 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5686 zero_memory(top, t1, 0, t2);
5687 }
5688
5689 verify_tlab();
5690 jmp(retry);
5691
5692 return thread_reg; // for use by caller
5693 }
5694
5695 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5696 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5697 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5698 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5699 Label done;
5700
5701 testptr(length_in_bytes, length_in_bytes);
5702 jcc(Assembler::zero, done);
5703
5704 // initialize topmost word, divide index by 2, check if odd and test if zero
5705 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5706 #ifdef ASSERT
5707 {
5708 Label L;
5709 testptr(length_in_bytes, BytesPerWord - 1);
5710 jcc(Assembler::zero, L);
5711 stop("length must be a multiple of BytesPerWord");
5712 bind(L);
5713 }
5714 #endif
5715 Register index = length_in_bytes;
5716 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5717 if (UseIncDec) {
5718 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5719 } else {
5720 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5721 shrptr(index, 1);
5722 }
5723 #ifndef _LP64
5724 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5725 {
5726 Label even;
5727 // note: if index was a multiple of 8, then it cannot
5728 // be 0 now otherwise it must have been 0 before
5729 // => if it is even, we don't need to check for 0 again
5730 jcc(Assembler::carryClear, even);
5731 // clear topmost word (no jump would be needed if conditional assignment worked here)
5732 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5733 // index could be 0 now, must check again
5734 jcc(Assembler::zero, done);
5735 bind(even);
5736 }
5737 #endif // !_LP64
5738 // initialize remaining object fields: index is a multiple of 2 now
5739 {
5740 Label loop;
5741 bind(loop);
5742 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5743 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5744 decrement(index);
5745 jcc(Assembler::notZero, loop);
5746 }
5747
5748 bind(done);
5749 }
5750
5751 void MacroAssembler::incr_allocated_bytes(Register thread,
5752 Register var_size_in_bytes,
5753 int con_size_in_bytes,
5754 Register t1) {
5755 if (!thread->is_valid()) {
5756 #ifdef _LP64
5757 thread = r15_thread;
5758 #else
5759 assert(t1->is_valid(), "need temp reg");
5760 thread = t1;
5761 get_thread(thread);
5762 #endif
5763 }
5764
5765 #ifdef _LP64
5766 if (var_size_in_bytes->is_valid()) {
5767 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5768 } else {
5769 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5770 }
5771 #else
5772 if (var_size_in_bytes->is_valid()) {
5773 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5774 } else {
5775 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5776 }
5777 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5778 #endif
5779 }
5780
5781 // Look up the method for a megamorphic invokeinterface call.
5782 // The target method is determined by <intf_klass, itable_index>.
5783 // The receiver klass is in recv_klass.
5784 // On success, the result will be in method_result, and execution falls through.
5785 // On failure, execution transfers to the given label.
5786 void MacroAssembler::lookup_interface_method(Register recv_klass,
5787 Register intf_klass,
5788 RegisterOrConstant itable_index,
5789 Register method_result,
5790 Register scan_temp,
5791 Label& L_no_such_interface) {
5792 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5793 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5794 "caller must use same register for non-constant itable index as for method");
5795
5796 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5797 int vtable_base = in_bytes(Klass::vtable_start_offset());
5798 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5799 int scan_step = itableOffsetEntry::size() * wordSize;
5800 int vte_size = vtableEntry::size_in_bytes();
5801 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5802 assert(vte_size == wordSize, "else adjust times_vte_scale");
5803
5804 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5805
5806 // %%% Could store the aligned, prescaled offset in the klassoop.
5807 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5808
5809 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5810 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5811 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5812
5813 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5814 // if (scan->interface() == intf) {
5815 // result = (klass + scan->offset() + itable_index);
5816 // }
5817 // }
5818 Label search, found_method;
5819
5820 for (int peel = 1; peel >= 0; peel--) {
5821 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5822 cmpptr(intf_klass, method_result);
5823
5824 if (peel) {
5825 jccb(Assembler::equal, found_method);
5826 } else {
5827 jccb(Assembler::notEqual, search);
5828 // (invert the test to fall through to found_method...)
5829 }
5830
5831 if (!peel) break;
5832
5833 bind(search);
5834
5835 // Check that the previous entry is non-null. A null entry means that
5836 // the receiver class doesn't implement the interface, and wasn't the
5837 // same as when the caller was compiled.
5838 testptr(method_result, method_result);
5839 jcc(Assembler::zero, L_no_such_interface);
5840 addptr(scan_temp, scan_step);
5841 }
5842
5843 bind(found_method);
5844
5845 // Got a hit.
5846 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5847 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5848 }
5849
5850
5851 // virtual method calling
5852 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5853 RegisterOrConstant vtable_index,
5854 Register method_result) {
5855 const int base = in_bytes(Klass::vtable_start_offset());
5856 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5857 Address vtable_entry_addr(recv_klass,
5858 vtable_index, Address::times_ptr,
5859 base + vtableEntry::method_offset_in_bytes());
5860 movptr(method_result, vtable_entry_addr);
5861 }
5862
5863
5864 void MacroAssembler::check_klass_subtype(Register sub_klass,
5865 Register super_klass,
5866 Register temp_reg,
5867 Label& L_success) {
5868 Label L_failure;
5869 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5870 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5871 bind(L_failure);
5872 }
5873
5874
5875 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5876 Register super_klass,
5877 Register temp_reg,
5878 Label* L_success,
5879 Label* L_failure,
5880 Label* L_slow_path,
5881 RegisterOrConstant super_check_offset) {
5882 assert_different_registers(sub_klass, super_klass, temp_reg);
5883 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5884 if (super_check_offset.is_register()) {
5885 assert_different_registers(sub_klass, super_klass,
5886 super_check_offset.as_register());
5887 } else if (must_load_sco) {
5888 assert(temp_reg != noreg, "supply either a temp or a register offset");
5889 }
5890
5891 Label L_fallthrough;
5892 int label_nulls = 0;
5893 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5894 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5895 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5896 assert(label_nulls <= 1, "at most one NULL in the batch");
5897
5898 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5899 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5900 Address super_check_offset_addr(super_klass, sco_offset);
5901
5902 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5903 // range of a jccb. If this routine grows larger, reconsider at
5904 // least some of these.
5905 #define local_jcc(assembler_cond, label) \
5906 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5907 else jcc( assembler_cond, label) /*omit semi*/
5908
5909 // Hacked jmp, which may only be used just before L_fallthrough.
5910 #define final_jmp(label) \
5911 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5912 else jmp(label) /*omit semi*/
5913
5914 // If the pointers are equal, we are done (e.g., String[] elements).
5915 // This self-check enables sharing of secondary supertype arrays among
5916 // non-primary types such as array-of-interface. Otherwise, each such
5917 // type would need its own customized SSA.
5918 // We move this check to the front of the fast path because many
5919 // type checks are in fact trivially successful in this manner,
5920 // so we get a nicely predicted branch right at the start of the check.
5921 cmpptr(sub_klass, super_klass);
5922 local_jcc(Assembler::equal, *L_success);
5923
5924 // Check the supertype display:
5925 if (must_load_sco) {
5926 // Positive movl does right thing on LP64.
5927 movl(temp_reg, super_check_offset_addr);
5928 super_check_offset = RegisterOrConstant(temp_reg);
5929 }
5930 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5931 cmpptr(super_klass, super_check_addr); // load displayed supertype
5932
5933 // This check has worked decisively for primary supers.
5934 // Secondary supers are sought in the super_cache ('super_cache_addr').
5935 // (Secondary supers are interfaces and very deeply nested subtypes.)
5936 // This works in the same check above because of a tricky aliasing
5937 // between the super_cache and the primary super display elements.
5938 // (The 'super_check_addr' can address either, as the case requires.)
5939 // Note that the cache is updated below if it does not help us find
5940 // what we need immediately.
5941 // So if it was a primary super, we can just fail immediately.
5942 // Otherwise, it's the slow path for us (no success at this point).
5943
5944 if (super_check_offset.is_register()) {
5945 local_jcc(Assembler::equal, *L_success);
5946 cmpl(super_check_offset.as_register(), sc_offset);
5947 if (L_failure == &L_fallthrough) {
5948 local_jcc(Assembler::equal, *L_slow_path);
5949 } else {
5950 local_jcc(Assembler::notEqual, *L_failure);
5951 final_jmp(*L_slow_path);
5952 }
5953 } else if (super_check_offset.as_constant() == sc_offset) {
5954 // Need a slow path; fast failure is impossible.
5955 if (L_slow_path == &L_fallthrough) {
5956 local_jcc(Assembler::equal, *L_success);
5957 } else {
5958 local_jcc(Assembler::notEqual, *L_slow_path);
5959 final_jmp(*L_success);
5960 }
5961 } else {
5962 // No slow path; it's a fast decision.
5963 if (L_failure == &L_fallthrough) {
5964 local_jcc(Assembler::equal, *L_success);
5965 } else {
5966 local_jcc(Assembler::notEqual, *L_failure);
5967 final_jmp(*L_success);
5968 }
5969 }
5970
5971 bind(L_fallthrough);
5972
5973 #undef local_jcc
5974 #undef final_jmp
5975 }
5976
5977
5978 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5979 Register super_klass,
5980 Register temp_reg,
5981 Register temp2_reg,
5982 Label* L_success,
5983 Label* L_failure,
5984 bool set_cond_codes) {
5985 assert_different_registers(sub_klass, super_klass, temp_reg);
5986 if (temp2_reg != noreg)
5987 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5988 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5989
5990 Label L_fallthrough;
5991 int label_nulls = 0;
5992 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5993 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5994 assert(label_nulls <= 1, "at most one NULL in the batch");
5995
5996 // a couple of useful fields in sub_klass:
5997 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5998 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5999 Address secondary_supers_addr(sub_klass, ss_offset);
6000 Address super_cache_addr( sub_klass, sc_offset);
6001
6002 // Do a linear scan of the secondary super-klass chain.
6003 // This code is rarely used, so simplicity is a virtue here.
6004 // The repne_scan instruction uses fixed registers, which we must spill.
6005 // Don't worry too much about pre-existing connections with the input regs.
6006
6007 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
6008 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
6009
6010 // Get super_klass value into rax (even if it was in rdi or rcx).
6011 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
6012 if (super_klass != rax || UseCompressedOops) {
6013 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
6014 mov(rax, super_klass);
6015 }
6016 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
6017 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
6018
6019 #ifndef PRODUCT
6020 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
6021 ExternalAddress pst_counter_addr((address) pst_counter);
6022 NOT_LP64( incrementl(pst_counter_addr) );
6023 LP64_ONLY( lea(rcx, pst_counter_addr) );
6024 LP64_ONLY( incrementl(Address(rcx, 0)) );
6025 #endif //PRODUCT
6026
6027 // We will consult the secondary-super array.
6028 movptr(rdi, secondary_supers_addr);
6029 // Load the array length. (Positive movl does right thing on LP64.)
6030 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
6031 // Skip to start of data.
6032 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
6033
6034 // Scan RCX words at [RDI] for an occurrence of RAX.
6035 // Set NZ/Z based on last compare.
6036 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
6037 // not change flags (only scas instruction which is repeated sets flags).
6038 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
6039
6040 testptr(rax,rax); // Set Z = 0
6041 repne_scan();
6042
6043 // Unspill the temp. registers:
6044 if (pushed_rdi) pop(rdi);
6045 if (pushed_rcx) pop(rcx);
6046 if (pushed_rax) pop(rax);
6047
6048 if (set_cond_codes) {
6049 // Special hack for the AD files: rdi is guaranteed non-zero.
6050 assert(!pushed_rdi, "rdi must be left non-NULL");
6051 // Also, the condition codes are properly set Z/NZ on succeed/failure.
6052 }
6053
6054 if (L_failure == &L_fallthrough)
6055 jccb(Assembler::notEqual, *L_failure);
6056 else jcc(Assembler::notEqual, *L_failure);
6057
6058 // Success. Cache the super we found and proceed in triumph.
6059 movptr(super_cache_addr, super_klass);
6060
6061 if (L_success != &L_fallthrough) {
6062 jmp(*L_success);
6063 }
6064
6065 #undef IS_A_TEMP
6066
6067 bind(L_fallthrough);
6068 }
6069
6070
6071 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
6072 if (VM_Version::supports_cmov()) {
6073 cmovl(cc, dst, src);
6074 } else {
6075 Label L;
6076 jccb(negate_condition(cc), L);
6077 movl(dst, src);
6078 bind(L);
6079 }
6080 }
6081
6082 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6083 if (VM_Version::supports_cmov()) {
6084 cmovl(cc, dst, src);
6085 } else {
6086 Label L;
6087 jccb(negate_condition(cc), L);
6088 movl(dst, src);
6089 bind(L);
6090 }
6091 }
6092
6093 void MacroAssembler::verify_oop(Register reg, const char* s) {
6094 if (!VerifyOops) return;
6095
6096 // Pass register number to verify_oop_subroutine
6097 const char* b = NULL;
6098 {
6099 ResourceMark rm;
6100 stringStream ss;
6101 ss.print("verify_oop: %s: %s", reg->name(), s);
6102 b = code_string(ss.as_string());
6103 }
6104 BLOCK_COMMENT("verify_oop {");
6105 #ifdef _LP64
6106 push(rscratch1); // save r10, trashed by movptr()
6107 #endif
6108 push(rax); // save rax,
6109 push(reg); // pass register argument
6110 ExternalAddress buffer((address) b);
6111 // avoid using pushptr, as it modifies scratch registers
6112 // and our contract is not to modify anything
6113 movptr(rax, buffer.addr());
6114 push(rax);
6115 // call indirectly to solve generation ordering problem
6116 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6117 call(rax);
6118 // Caller pops the arguments (oop, message) and restores rax, r10
6119 BLOCK_COMMENT("} verify_oop");
6120 }
6121
6122
6123 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6124 Register tmp,
6125 int offset) {
6126 intptr_t value = *delayed_value_addr;
6127 if (value != 0)
6128 return RegisterOrConstant(value + offset);
6129
6130 // load indirectly to solve generation ordering problem
6131 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6132
6133 #ifdef ASSERT
6134 { Label L;
6135 testptr(tmp, tmp);
6136 if (WizardMode) {
6137 const char* buf = NULL;
6138 {
6139 ResourceMark rm;
6140 stringStream ss;
6141 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6142 buf = code_string(ss.as_string());
6143 }
6144 jcc(Assembler::notZero, L);
6145 STOP(buf);
6146 } else {
6147 jccb(Assembler::notZero, L);
6148 hlt();
6149 }
6150 bind(L);
6151 }
6152 #endif
6153
6154 if (offset != 0)
6155 addptr(tmp, offset);
6156
6157 return RegisterOrConstant(tmp);
6158 }
6159
6160
6161 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6162 int extra_slot_offset) {
6163 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6164 int stackElementSize = Interpreter::stackElementSize;
6165 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6166 #ifdef ASSERT
6167 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6168 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6169 #endif
6170 Register scale_reg = noreg;
6171 Address::ScaleFactor scale_factor = Address::no_scale;
6172 if (arg_slot.is_constant()) {
6173 offset += arg_slot.as_constant() * stackElementSize;
6174 } else {
6175 scale_reg = arg_slot.as_register();
6176 scale_factor = Address::times(stackElementSize);
6177 }
6178 offset += wordSize; // return PC is on stack
6179 return Address(rsp, scale_reg, scale_factor, offset);
6180 }
6181
6182
6183 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6184 if (!VerifyOops) return;
6185
6186 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6187 // Pass register number to verify_oop_subroutine
6188 const char* b = NULL;
6189 {
6190 ResourceMark rm;
6191 stringStream ss;
6192 ss.print("verify_oop_addr: %s", s);
6193 b = code_string(ss.as_string());
6194 }
6195 #ifdef _LP64
6196 push(rscratch1); // save r10, trashed by movptr()
6197 #endif
6198 push(rax); // save rax,
6199 // addr may contain rsp so we will have to adjust it based on the push
6200 // we just did (and on 64 bit we do two pushes)
6201 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6202 // stores rax into addr which is backwards of what was intended.
6203 if (addr.uses(rsp)) {
6204 lea(rax, addr);
6205 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6206 } else {
6207 pushptr(addr);
6208 }
6209
6210 ExternalAddress buffer((address) b);
6211 // pass msg argument
6212 // avoid using pushptr, as it modifies scratch registers
6213 // and our contract is not to modify anything
6214 movptr(rax, buffer.addr());
6215 push(rax);
6216
6217 // call indirectly to solve generation ordering problem
6218 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6219 call(rax);
6220 // Caller pops the arguments (addr, message) and restores rax, r10.
6221 }
6222
6223 void MacroAssembler::verify_tlab() {
6224 #ifdef ASSERT
6225 if (UseTLAB && VerifyOops) {
6226 Label next, ok;
6227 Register t1 = rsi;
6228 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6229
6230 push(t1);
6231 NOT_LP64(push(thread_reg));
6232 NOT_LP64(get_thread(thread_reg));
6233
6234 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6235 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6236 jcc(Assembler::aboveEqual, next);
6237 STOP("assert(top >= start)");
6238 should_not_reach_here();
6239
6240 bind(next);
6241 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6242 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6243 jcc(Assembler::aboveEqual, ok);
6244 STOP("assert(top <= end)");
6245 should_not_reach_here();
6246
6247 bind(ok);
6248 NOT_LP64(pop(thread_reg));
6249 pop(t1);
6250 }
6251 #endif
6252 }
6253
6254 class ControlWord {
6255 public:
6256 int32_t _value;
6257
6258 int rounding_control() const { return (_value >> 10) & 3 ; }
6259 int precision_control() const { return (_value >> 8) & 3 ; }
6260 bool precision() const { return ((_value >> 5) & 1) != 0; }
6261 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6262 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6263 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6264 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6265 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6266
6267 void print() const {
6268 // rounding control
6269 const char* rc;
6270 switch (rounding_control()) {
6271 case 0: rc = "round near"; break;
6272 case 1: rc = "round down"; break;
6273 case 2: rc = "round up "; break;
6274 case 3: rc = "chop "; break;
6275 };
6276 // precision control
6277 const char* pc;
6278 switch (precision_control()) {
6279 case 0: pc = "24 bits "; break;
6280 case 1: pc = "reserved"; break;
6281 case 2: pc = "53 bits "; break;
6282 case 3: pc = "64 bits "; break;
6283 };
6284 // flags
6285 char f[9];
6286 f[0] = ' ';
6287 f[1] = ' ';
6288 f[2] = (precision ()) ? 'P' : 'p';
6289 f[3] = (underflow ()) ? 'U' : 'u';
6290 f[4] = (overflow ()) ? 'O' : 'o';
6291 f[5] = (zero_divide ()) ? 'Z' : 'z';
6292 f[6] = (denormalized()) ? 'D' : 'd';
6293 f[7] = (invalid ()) ? 'I' : 'i';
6294 f[8] = '\x0';
6295 // output
6296 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6297 }
6298
6299 };
6300
6301 class StatusWord {
6302 public:
6303 int32_t _value;
6304
6305 bool busy() const { return ((_value >> 15) & 1) != 0; }
6306 bool C3() const { return ((_value >> 14) & 1) != 0; }
6307 bool C2() const { return ((_value >> 10) & 1) != 0; }
6308 bool C1() const { return ((_value >> 9) & 1) != 0; }
6309 bool C0() const { return ((_value >> 8) & 1) != 0; }
6310 int top() const { return (_value >> 11) & 7 ; }
6311 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6312 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6313 bool precision() const { return ((_value >> 5) & 1) != 0; }
6314 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6315 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6316 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6317 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6318 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6319
6320 void print() const {
6321 // condition codes
6322 char c[5];
6323 c[0] = (C3()) ? '3' : '-';
6324 c[1] = (C2()) ? '2' : '-';
6325 c[2] = (C1()) ? '1' : '-';
6326 c[3] = (C0()) ? '0' : '-';
6327 c[4] = '\x0';
6328 // flags
6329 char f[9];
6330 f[0] = (error_status()) ? 'E' : '-';
6331 f[1] = (stack_fault ()) ? 'S' : '-';
6332 f[2] = (precision ()) ? 'P' : '-';
6333 f[3] = (underflow ()) ? 'U' : '-';
6334 f[4] = (overflow ()) ? 'O' : '-';
6335 f[5] = (zero_divide ()) ? 'Z' : '-';
6336 f[6] = (denormalized()) ? 'D' : '-';
6337 f[7] = (invalid ()) ? 'I' : '-';
6338 f[8] = '\x0';
6339 // output
6340 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6341 }
6342
6343 };
6344
6345 class TagWord {
6346 public:
6347 int32_t _value;
6348
6349 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6350
6351 void print() const {
6352 printf("%04x", _value & 0xFFFF);
6353 }
6354
6355 };
6356
6357 class FPU_Register {
6358 public:
6359 int32_t _m0;
6360 int32_t _m1;
6361 int16_t _ex;
6362
6363 bool is_indefinite() const {
6364 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6365 }
6366
6367 void print() const {
6368 char sign = (_ex < 0) ? '-' : '+';
6369 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6370 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6371 };
6372
6373 };
6374
6375 class FPU_State {
6376 public:
6377 enum {
6378 register_size = 10,
6379 number_of_registers = 8,
6380 register_mask = 7
6381 };
6382
6383 ControlWord _control_word;
6384 StatusWord _status_word;
6385 TagWord _tag_word;
6386 int32_t _error_offset;
6387 int32_t _error_selector;
6388 int32_t _data_offset;
6389 int32_t _data_selector;
6390 int8_t _register[register_size * number_of_registers];
6391
6392 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6393 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6394
6395 const char* tag_as_string(int tag) const {
6396 switch (tag) {
6397 case 0: return "valid";
6398 case 1: return "zero";
6399 case 2: return "special";
6400 case 3: return "empty";
6401 }
6402 ShouldNotReachHere();
6403 return NULL;
6404 }
6405
6406 void print() const {
6407 // print computation registers
6408 { int t = _status_word.top();
6409 for (int i = 0; i < number_of_registers; i++) {
6410 int j = (i - t) & register_mask;
6411 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6412 st(j)->print();
6413 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6414 }
6415 }
6416 printf("\n");
6417 // print control registers
6418 printf("ctrl = "); _control_word.print(); printf("\n");
6419 printf("stat = "); _status_word .print(); printf("\n");
6420 printf("tags = "); _tag_word .print(); printf("\n");
6421 }
6422
6423 };
6424
6425 class Flag_Register {
6426 public:
6427 int32_t _value;
6428
6429 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6430 bool direction() const { return ((_value >> 10) & 1) != 0; }
6431 bool sign() const { return ((_value >> 7) & 1) != 0; }
6432 bool zero() const { return ((_value >> 6) & 1) != 0; }
6433 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6434 bool parity() const { return ((_value >> 2) & 1) != 0; }
6435 bool carry() const { return ((_value >> 0) & 1) != 0; }
6436
6437 void print() const {
6438 // flags
6439 char f[8];
6440 f[0] = (overflow ()) ? 'O' : '-';
6441 f[1] = (direction ()) ? 'D' : '-';
6442 f[2] = (sign ()) ? 'S' : '-';
6443 f[3] = (zero ()) ? 'Z' : '-';
6444 f[4] = (auxiliary_carry()) ? 'A' : '-';
6445 f[5] = (parity ()) ? 'P' : '-';
6446 f[6] = (carry ()) ? 'C' : '-';
6447 f[7] = '\x0';
6448 // output
6449 printf("%08x flags = %s", _value, f);
6450 }
6451
6452 };
6453
6454 class IU_Register {
6455 public:
6456 int32_t _value;
6457
6458 void print() const {
6459 printf("%08x %11d", _value, _value);
6460 }
6461
6462 };
6463
6464 class IU_State {
6465 public:
6466 Flag_Register _eflags;
6467 IU_Register _rdi;
6468 IU_Register _rsi;
6469 IU_Register _rbp;
6470 IU_Register _rsp;
6471 IU_Register _rbx;
6472 IU_Register _rdx;
6473 IU_Register _rcx;
6474 IU_Register _rax;
6475
6476 void print() const {
6477 // computation registers
6478 printf("rax, = "); _rax.print(); printf("\n");
6479 printf("rbx, = "); _rbx.print(); printf("\n");
6480 printf("rcx = "); _rcx.print(); printf("\n");
6481 printf("rdx = "); _rdx.print(); printf("\n");
6482 printf("rdi = "); _rdi.print(); printf("\n");
6483 printf("rsi = "); _rsi.print(); printf("\n");
6484 printf("rbp, = "); _rbp.print(); printf("\n");
6485 printf("rsp = "); _rsp.print(); printf("\n");
6486 printf("\n");
6487 // control registers
6488 printf("flgs = "); _eflags.print(); printf("\n");
6489 }
6490 };
6491
6492
6493 class CPU_State {
6494 public:
6495 FPU_State _fpu_state;
6496 IU_State _iu_state;
6497
6498 void print() const {
6499 printf("--------------------------------------------------\n");
6500 _iu_state .print();
6501 printf("\n");
6502 _fpu_state.print();
6503 printf("--------------------------------------------------\n");
6504 }
6505
6506 };
6507
6508
6509 static void _print_CPU_state(CPU_State* state) {
6510 state->print();
6511 };
6512
6513
6514 void MacroAssembler::print_CPU_state() {
6515 push_CPU_state();
6516 push(rsp); // pass CPU state
6517 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6518 addptr(rsp, wordSize); // discard argument
6519 pop_CPU_state();
6520 }
6521
6522
6523 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6524 static int counter = 0;
6525 FPU_State* fs = &state->_fpu_state;
6526 counter++;
6527 // For leaf calls, only verify that the top few elements remain empty.
6528 // We only need 1 empty at the top for C2 code.
6529 if( stack_depth < 0 ) {
6530 if( fs->tag_for_st(7) != 3 ) {
6531 printf("FPR7 not empty\n");
6532 state->print();
6533 assert(false, "error");
6534 return false;
6535 }
6536 return true; // All other stack states do not matter
6537 }
6538
6539 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6540 "bad FPU control word");
6541
6542 // compute stack depth
6543 int i = 0;
6544 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6545 int d = i;
6546 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6547 // verify findings
6548 if (i != FPU_State::number_of_registers) {
6549 // stack not contiguous
6550 printf("%s: stack not contiguous at ST%d\n", s, i);
6551 state->print();
6552 assert(false, "error");
6553 return false;
6554 }
6555 // check if computed stack depth corresponds to expected stack depth
6556 if (stack_depth < 0) {
6557 // expected stack depth is -stack_depth or less
6558 if (d > -stack_depth) {
6559 // too many elements on the stack
6560 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6561 state->print();
6562 assert(false, "error");
6563 return false;
6564 }
6565 } else {
6566 // expected stack depth is stack_depth
6567 if (d != stack_depth) {
6568 // wrong stack depth
6569 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6570 state->print();
6571 assert(false, "error");
6572 return false;
6573 }
6574 }
6575 // everything is cool
6576 return true;
6577 }
6578
6579
6580 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6581 if (!VerifyFPU) return;
6582 push_CPU_state();
6583 push(rsp); // pass CPU state
6584 ExternalAddress msg((address) s);
6585 // pass message string s
6586 pushptr(msg.addr());
6587 push(stack_depth); // pass stack depth
6588 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6589 addptr(rsp, 3 * wordSize); // discard arguments
6590 // check for error
6591 { Label L;
6592 testl(rax, rax);
6593 jcc(Assembler::notZero, L);
6594 int3(); // break if error condition
6595 bind(L);
6596 }
6597 pop_CPU_state();
6598 }
6599
6600 void MacroAssembler::restore_cpu_control_state_after_jni() {
6601 // Either restore the MXCSR register after returning from the JNI Call
6602 // or verify that it wasn't changed (with -Xcheck:jni flag).
6603 if (VM_Version::supports_sse()) {
6604 if (RestoreMXCSROnJNICalls) {
6605 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6606 } else if (CheckJNICalls) {
6607 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6608 }
6609 }
6610 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6611 vzeroupper();
6612
6613 #ifndef _LP64
6614 // Either restore the x87 floating pointer control word after returning
6615 // from the JNI call or verify that it wasn't changed.
6616 if (CheckJNICalls) {
6617 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6618 }
6619 #endif // _LP64
6620 }
6621
6622 // ((OopHandle)result).resolve();
6623 void MacroAssembler::resolve_oop_handle(Register result) {
6624 // OopHandle::resolve is an indirection.
6625 movptr(result, Address(result, 0));
6626 }
6627
6628 void MacroAssembler::load_mirror(Register mirror, Register method) {
6629 // get mirror
6630 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6631 movptr(mirror, Address(method, Method::const_offset()));
6632 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6633 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6634 movptr(mirror, Address(mirror, mirror_offset));
6635 resolve_oop_handle(mirror);
6636 }
6637
6638 void MacroAssembler::load_klass(Register dst, Register src) {
6639 #ifdef _LP64
6640 if (UseCompressedClassPointers) {
6641 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6642 decode_klass_not_null(dst);
6643 } else
6644 #endif
6645 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6646 }
6647
6648 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6649 load_klass(dst, src);
6650 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6651 }
6652
6653 void MacroAssembler::store_klass(Register dst, Register src) {
6654 #ifdef _LP64
6655 if (UseCompressedClassPointers) {
6656 encode_klass_not_null(src);
6657 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6658 } else
6659 #endif
6660 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6661 }
6662
6663 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6664 #ifdef _LP64
6665 // FIXME: Must change all places where we try to load the klass.
6666 if (UseCompressedOops) {
6667 movl(dst, src);
6668 decode_heap_oop(dst);
6669 } else
6670 #endif
6671 movptr(dst, src);
6672 }
6673
6674 // Doesn't do verfication, generates fixed size code
6675 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6676 #ifdef _LP64
6677 if (UseCompressedOops) {
6678 movl(dst, src);
6679 decode_heap_oop_not_null(dst);
6680 } else
6681 #endif
6682 movptr(dst, src);
6683 }
6684
6685 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6686 #ifdef _LP64
6687 if (UseCompressedOops) {
6688 assert(!dst.uses(src), "not enough registers");
6689 encode_heap_oop(src);
6690 movl(dst, src);
6691 } else
6692 #endif
6693 movptr(dst, src);
6694 }
6695
6696 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6697 assert_different_registers(src1, tmp);
6698 #ifdef _LP64
6699 if (UseCompressedOops) {
6700 bool did_push = false;
6701 if (tmp == noreg) {
6702 tmp = rax;
6703 push(tmp);
6704 did_push = true;
6705 assert(!src2.uses(rsp), "can't push");
6706 }
6707 load_heap_oop(tmp, src2);
6708 cmpptr(src1, tmp);
6709 if (did_push) pop(tmp);
6710 } else
6711 #endif
6712 cmpptr(src1, src2);
6713 }
6714
6715 // Used for storing NULLs.
6716 void MacroAssembler::store_heap_oop_null(Address dst) {
6717 #ifdef _LP64
6718 if (UseCompressedOops) {
6719 movl(dst, (int32_t)NULL_WORD);
6720 } else {
6721 movslq(dst, (int32_t)NULL_WORD);
6722 }
6723 #else
6724 movl(dst, (int32_t)NULL_WORD);
6725 #endif
6726 }
6727
6728 #ifdef _LP64
6729 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6730 if (UseCompressedClassPointers) {
6731 // Store to klass gap in destination
6732 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6733 }
6734 }
6735
6736 #ifdef ASSERT
6737 void MacroAssembler::verify_heapbase(const char* msg) {
6738 assert (UseCompressedOops, "should be compressed");
6739 assert (Universe::heap() != NULL, "java heap should be initialized");
6740 if (CheckCompressedOops) {
6741 Label ok;
6742 push(rscratch1); // cmpptr trashes rscratch1
6743 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6744 jcc(Assembler::equal, ok);
6745 STOP(msg);
6746 bind(ok);
6747 pop(rscratch1);
6748 }
6749 }
6750 #endif
6751
6752 // Algorithm must match oop.inline.hpp encode_heap_oop.
6753 void MacroAssembler::encode_heap_oop(Register r) {
6754 #ifdef ASSERT
6755 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6756 #endif
6757 verify_oop(r, "broken oop in encode_heap_oop");
6758 if (Universe::narrow_oop_base() == NULL) {
6759 if (Universe::narrow_oop_shift() != 0) {
6760 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6761 shrq(r, LogMinObjAlignmentInBytes);
6762 }
6763 return;
6764 }
6765 testq(r, r);
6766 cmovq(Assembler::equal, r, r12_heapbase);
6767 subq(r, r12_heapbase);
6768 shrq(r, LogMinObjAlignmentInBytes);
6769 }
6770
6771 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6772 #ifdef ASSERT
6773 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6774 if (CheckCompressedOops) {
6775 Label ok;
6776 testq(r, r);
6777 jcc(Assembler::notEqual, ok);
6778 STOP("null oop passed to encode_heap_oop_not_null");
6779 bind(ok);
6780 }
6781 #endif
6782 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6783 if (Universe::narrow_oop_base() != NULL) {
6784 subq(r, r12_heapbase);
6785 }
6786 if (Universe::narrow_oop_shift() != 0) {
6787 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6788 shrq(r, LogMinObjAlignmentInBytes);
6789 }
6790 }
6791
6792 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6793 #ifdef ASSERT
6794 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6795 if (CheckCompressedOops) {
6796 Label ok;
6797 testq(src, src);
6798 jcc(Assembler::notEqual, ok);
6799 STOP("null oop passed to encode_heap_oop_not_null2");
6800 bind(ok);
6801 }
6802 #endif
6803 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6804 if (dst != src) {
6805 movq(dst, src);
6806 }
6807 if (Universe::narrow_oop_base() != NULL) {
6808 subq(dst, r12_heapbase);
6809 }
6810 if (Universe::narrow_oop_shift() != 0) {
6811 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6812 shrq(dst, LogMinObjAlignmentInBytes);
6813 }
6814 }
6815
6816 void MacroAssembler::decode_heap_oop(Register r) {
6817 #ifdef ASSERT
6818 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6819 #endif
6820 if (Universe::narrow_oop_base() == NULL) {
6821 if (Universe::narrow_oop_shift() != 0) {
6822 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6823 shlq(r, LogMinObjAlignmentInBytes);
6824 }
6825 } else {
6826 Label done;
6827 shlq(r, LogMinObjAlignmentInBytes);
6828 jccb(Assembler::equal, done);
6829 addq(r, r12_heapbase);
6830 bind(done);
6831 }
6832 verify_oop(r, "broken oop in decode_heap_oop");
6833 }
6834
6835 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6836 // Note: it will change flags
6837 assert (UseCompressedOops, "should only be used for compressed headers");
6838 assert (Universe::heap() != NULL, "java heap should be initialized");
6839 // Cannot assert, unverified entry point counts instructions (see .ad file)
6840 // vtableStubs also counts instructions in pd_code_size_limit.
6841 // Also do not verify_oop as this is called by verify_oop.
6842 if (Universe::narrow_oop_shift() != 0) {
6843 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6844 shlq(r, LogMinObjAlignmentInBytes);
6845 if (Universe::narrow_oop_base() != NULL) {
6846 addq(r, r12_heapbase);
6847 }
6848 } else {
6849 assert (Universe::narrow_oop_base() == NULL, "sanity");
6850 }
6851 }
6852
6853 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6854 // Note: it will change flags
6855 assert (UseCompressedOops, "should only be used for compressed headers");
6856 assert (Universe::heap() != NULL, "java heap should be initialized");
6857 // Cannot assert, unverified entry point counts instructions (see .ad file)
6858 // vtableStubs also counts instructions in pd_code_size_limit.
6859 // Also do not verify_oop as this is called by verify_oop.
6860 if (Universe::narrow_oop_shift() != 0) {
6861 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6862 if (LogMinObjAlignmentInBytes == Address::times_8) {
6863 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6864 } else {
6865 if (dst != src) {
6866 movq(dst, src);
6867 }
6868 shlq(dst, LogMinObjAlignmentInBytes);
6869 if (Universe::narrow_oop_base() != NULL) {
6870 addq(dst, r12_heapbase);
6871 }
6872 }
6873 } else {
6874 assert (Universe::narrow_oop_base() == NULL, "sanity");
6875 if (dst != src) {
6876 movq(dst, src);
6877 }
6878 }
6879 }
6880
6881 void MacroAssembler::encode_klass_not_null(Register r) {
6882 if (Universe::narrow_klass_base() != NULL) {
6883 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6884 assert(r != r12_heapbase, "Encoding a klass in r12");
6885 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6886 subq(r, r12_heapbase);
6887 }
6888 if (Universe::narrow_klass_shift() != 0) {
6889 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6890 shrq(r, LogKlassAlignmentInBytes);
6891 }
6892 if (Universe::narrow_klass_base() != NULL) {
6893 reinit_heapbase();
6894 }
6895 }
6896
6897 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6898 if (dst == src) {
6899 encode_klass_not_null(src);
6900 } else {
6901 if (Universe::narrow_klass_base() != NULL) {
6902 mov64(dst, (int64_t)Universe::narrow_klass_base());
6903 negq(dst);
6904 addq(dst, src);
6905 } else {
6906 movptr(dst, src);
6907 }
6908 if (Universe::narrow_klass_shift() != 0) {
6909 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6910 shrq(dst, LogKlassAlignmentInBytes);
6911 }
6912 }
6913 }
6914
6915 // Function instr_size_for_decode_klass_not_null() counts the instructions
6916 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6917 // when (Universe::heap() != NULL). Hence, if the instructions they
6918 // generate change, then this method needs to be updated.
6919 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6920 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6921 if (Universe::narrow_klass_base() != NULL) {
6922 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6923 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6924 } else {
6925 // longest load decode klass function, mov64, leaq
6926 return 16;
6927 }
6928 }
6929
6930 // !!! If the instructions that get generated here change then function
6931 // instr_size_for_decode_klass_not_null() needs to get updated.
6932 void MacroAssembler::decode_klass_not_null(Register r) {
6933 // Note: it will change flags
6934 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6935 assert(r != r12_heapbase, "Decoding a klass in r12");
6936 // Cannot assert, unverified entry point counts instructions (see .ad file)
6937 // vtableStubs also counts instructions in pd_code_size_limit.
6938 // Also do not verify_oop as this is called by verify_oop.
6939 if (Universe::narrow_klass_shift() != 0) {
6940 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6941 shlq(r, LogKlassAlignmentInBytes);
6942 }
6943 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6944 if (Universe::narrow_klass_base() != NULL) {
6945 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6946 addq(r, r12_heapbase);
6947 reinit_heapbase();
6948 }
6949 }
6950
6951 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6952 // Note: it will change flags
6953 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6954 if (dst == src) {
6955 decode_klass_not_null(dst);
6956 } else {
6957 // Cannot assert, unverified entry point counts instructions (see .ad file)
6958 // vtableStubs also counts instructions in pd_code_size_limit.
6959 // Also do not verify_oop as this is called by verify_oop.
6960 mov64(dst, (int64_t)Universe::narrow_klass_base());
6961 if (Universe::narrow_klass_shift() != 0) {
6962 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6963 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6964 leaq(dst, Address(dst, src, Address::times_8, 0));
6965 } else {
6966 addq(dst, src);
6967 }
6968 }
6969 }
6970
6971 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6972 assert (UseCompressedOops, "should only be used for compressed headers");
6973 assert (Universe::heap() != NULL, "java heap should be initialized");
6974 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6975 int oop_index = oop_recorder()->find_index(obj);
6976 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6977 mov_narrow_oop(dst, oop_index, rspec);
6978 }
6979
6980 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6981 assert (UseCompressedOops, "should only be used for compressed headers");
6982 assert (Universe::heap() != NULL, "java heap should be initialized");
6983 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6984 int oop_index = oop_recorder()->find_index(obj);
6985 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6986 mov_narrow_oop(dst, oop_index, rspec);
6987 }
6988
6989 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6990 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6991 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6992 int klass_index = oop_recorder()->find_index(k);
6993 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6994 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6995 }
6996
6997 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6998 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6999 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7000 int klass_index = oop_recorder()->find_index(k);
7001 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7002 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7003 }
7004
7005 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
7006 assert (UseCompressedOops, "should only be used for compressed headers");
7007 assert (Universe::heap() != NULL, "java heap should be initialized");
7008 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7009 int oop_index = oop_recorder()->find_index(obj);
7010 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7011 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7012 }
7013
7014 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
7015 assert (UseCompressedOops, "should only be used for compressed headers");
7016 assert (Universe::heap() != NULL, "java heap should be initialized");
7017 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7018 int oop_index = oop_recorder()->find_index(obj);
7019 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7020 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7021 }
7022
7023 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
7024 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7025 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7026 int klass_index = oop_recorder()->find_index(k);
7027 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7028 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7029 }
7030
7031 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
7032 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7033 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7034 int klass_index = oop_recorder()->find_index(k);
7035 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7036 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7037 }
7038
7039 void MacroAssembler::reinit_heapbase() {
7040 if (UseCompressedOops || UseCompressedClassPointers) {
7041 if (Universe::heap() != NULL) {
7042 if (Universe::narrow_oop_base() == NULL) {
7043 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
7044 } else {
7045 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
7046 }
7047 } else {
7048 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
7049 }
7050 }
7051 }
7052
7053 #endif // _LP64
7054
7055 // C2 compiled method's prolog code.
7056 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
7057
7058 // WARNING: Initial instruction MUST be 5 bytes or longer so that
7059 // NativeJump::patch_verified_entry will be able to patch out the entry
7060 // code safely. The push to verify stack depth is ok at 5 bytes,
7061 // the frame allocation can be either 3 or 6 bytes. So if we don't do
7062 // stack bang then we must use the 6 byte frame allocation even if
7063 // we have no frame. :-(
7064 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
7065
7066 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7067 // Remove word for return addr
7068 framesize -= wordSize;
7069 stack_bang_size -= wordSize;
7070
7071 // Calls to C2R adapters often do not accept exceptional returns.
7072 // We require that their callers must bang for them. But be careful, because
7073 // some VM calls (such as call site linkage) can use several kilobytes of
7074 // stack. But the stack safety zone should account for that.
7075 // See bugs 4446381, 4468289, 4497237.
7076 if (stack_bang_size > 0) {
7077 generate_stack_overflow_check(stack_bang_size);
7078
7079 // We always push rbp, so that on return to interpreter rbp, will be
7080 // restored correctly and we can correct the stack.
7081 push(rbp);
7082 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7083 if (PreserveFramePointer) {
7084 mov(rbp, rsp);
7085 }
7086 // Remove word for ebp
7087 framesize -= wordSize;
7088
7089 // Create frame
7090 if (framesize) {
7091 subptr(rsp, framesize);
7092 }
7093 } else {
7094 // Create frame (force generation of a 4 byte immediate value)
7095 subptr_imm32(rsp, framesize);
7096
7097 // Save RBP register now.
7098 framesize -= wordSize;
7099 movptr(Address(rsp, framesize), rbp);
7100 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7101 if (PreserveFramePointer) {
7102 movptr(rbp, rsp);
7103 if (framesize > 0) {
7104 addptr(rbp, framesize);
7105 }
7106 }
7107 }
7108
7109 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7110 framesize -= wordSize;
7111 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7112 }
7113
7114 #ifndef _LP64
7115 // If method sets FPU control word do it now
7116 if (fp_mode_24b) {
7117 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7118 }
7119 if (UseSSE >= 2 && VerifyFPU) {
7120 verify_FPU(0, "FPU stack must be clean on entry");
7121 }
7122 #endif
7123
7124 #ifdef ASSERT
7125 if (VerifyStackAtCalls) {
7126 Label L;
7127 push(rax);
7128 mov(rax, rsp);
7129 andptr(rax, StackAlignmentInBytes-1);
7130 cmpptr(rax, StackAlignmentInBytes-wordSize);
7131 pop(rax);
7132 jcc(Assembler::equal, L);
7133 STOP("Stack is not properly aligned!");
7134 bind(L);
7135 }
7136 #endif
7137
7138 }
7139
7140 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7141 // cnt - number of qwords (8-byte words).
7142 // base - start address, qword aligned.
7143 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7144 assert(base==rdi, "base register must be edi for rep stos");
7145 assert(tmp==rax, "tmp register must be eax for rep stos");
7146 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7147 assert(InitArrayShortSize % BytesPerLong == 0,
7148 "InitArrayShortSize should be the multiple of BytesPerLong");
7149
7150 Label DONE;
7151
7152 xorptr(tmp, tmp);
7153
7154 if (!is_large) {
7155 Label LOOP, LONG;
7156 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7157 jccb(Assembler::greater, LONG);
7158
7159 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7160
7161 decrement(cnt);
7162 jccb(Assembler::negative, DONE); // Zero length
7163
7164 // Use individual pointer-sized stores for small counts:
7165 BIND(LOOP);
7166 movptr(Address(base, cnt, Address::times_ptr), tmp);
7167 decrement(cnt);
7168 jccb(Assembler::greaterEqual, LOOP);
7169 jmpb(DONE);
7170
7171 BIND(LONG);
7172 }
7173
7174 // Use longer rep-prefixed ops for non-small counts:
7175 if (UseFastStosb) {
7176 shlptr(cnt, 3); // convert to number of bytes
7177 rep_stosb();
7178 } else {
7179 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7180 rep_stos();
7181 }
7182
7183 BIND(DONE);
7184 }
7185
7186 #ifdef COMPILER2
7187
7188 // IndexOf for constant substrings with size >= 8 chars
7189 // which don't need to be loaded through stack.
7190 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7191 Register cnt1, Register cnt2,
7192 int int_cnt2, Register result,
7193 XMMRegister vec, Register tmp,
7194 int ae) {
7195 ShortBranchVerifier sbv(this);
7196 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7197 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7198
7199 // This method uses the pcmpestri instruction with bound registers
7200 // inputs:
7201 // xmm - substring
7202 // rax - substring length (elements count)
7203 // mem - scanned string
7204 // rdx - string length (elements count)
7205 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7206 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7207 // outputs:
7208 // rcx - matched index in string
7209 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7210 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7211 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7212 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7213 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7214
7215 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7216 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7217 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7218
7219 // Note, inline_string_indexOf() generates checks:
7220 // if (substr.count > string.count) return -1;
7221 // if (substr.count == 0) return 0;
7222 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7223
7224 // Load substring.
7225 if (ae == StrIntrinsicNode::UL) {
7226 pmovzxbw(vec, Address(str2, 0));
7227 } else {
7228 movdqu(vec, Address(str2, 0));
7229 }
7230 movl(cnt2, int_cnt2);
7231 movptr(result, str1); // string addr
7232
7233 if (int_cnt2 > stride) {
7234 jmpb(SCAN_TO_SUBSTR);
7235
7236 // Reload substr for rescan, this code
7237 // is executed only for large substrings (> 8 chars)
7238 bind(RELOAD_SUBSTR);
7239 if (ae == StrIntrinsicNode::UL) {
7240 pmovzxbw(vec, Address(str2, 0));
7241 } else {
7242 movdqu(vec, Address(str2, 0));
7243 }
7244 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7245
7246 bind(RELOAD_STR);
7247 // We came here after the beginning of the substring was
7248 // matched but the rest of it was not so we need to search
7249 // again. Start from the next element after the previous match.
7250
7251 // cnt2 is number of substring reminding elements and
7252 // cnt1 is number of string reminding elements when cmp failed.
7253 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7254 subl(cnt1, cnt2);
7255 addl(cnt1, int_cnt2);
7256 movl(cnt2, int_cnt2); // Now restore cnt2
7257
7258 decrementl(cnt1); // Shift to next element
7259 cmpl(cnt1, cnt2);
7260 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7261
7262 addptr(result, (1<<scale1));
7263
7264 } // (int_cnt2 > 8)
7265
7266 // Scan string for start of substr in 16-byte vectors
7267 bind(SCAN_TO_SUBSTR);
7268 pcmpestri(vec, Address(result, 0), mode);
7269 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7270 subl(cnt1, stride);
7271 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7272 cmpl(cnt1, cnt2);
7273 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7274 addptr(result, 16);
7275 jmpb(SCAN_TO_SUBSTR);
7276
7277 // Found a potential substr
7278 bind(FOUND_CANDIDATE);
7279 // Matched whole vector if first element matched (tmp(rcx) == 0).
7280 if (int_cnt2 == stride) {
7281 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7282 } else { // int_cnt2 > 8
7283 jccb(Assembler::overflow, FOUND_SUBSTR);
7284 }
7285 // After pcmpestri tmp(rcx) contains matched element index
7286 // Compute start addr of substr
7287 lea(result, Address(result, tmp, scale1));
7288
7289 // Make sure string is still long enough
7290 subl(cnt1, tmp);
7291 cmpl(cnt1, cnt2);
7292 if (int_cnt2 == stride) {
7293 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7294 } else { // int_cnt2 > 8
7295 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7296 }
7297 // Left less then substring.
7298
7299 bind(RET_NOT_FOUND);
7300 movl(result, -1);
7301 jmp(EXIT);
7302
7303 if (int_cnt2 > stride) {
7304 // This code is optimized for the case when whole substring
7305 // is matched if its head is matched.
7306 bind(MATCH_SUBSTR_HEAD);
7307 pcmpestri(vec, Address(result, 0), mode);
7308 // Reload only string if does not match
7309 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7310
7311 Label CONT_SCAN_SUBSTR;
7312 // Compare the rest of substring (> 8 chars).
7313 bind(FOUND_SUBSTR);
7314 // First 8 chars are already matched.
7315 negptr(cnt2);
7316 addptr(cnt2, stride);
7317
7318 bind(SCAN_SUBSTR);
7319 subl(cnt1, stride);
7320 cmpl(cnt2, -stride); // Do not read beyond substring
7321 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7322 // Back-up strings to avoid reading beyond substring:
7323 // cnt1 = cnt1 - cnt2 + 8
7324 addl(cnt1, cnt2); // cnt2 is negative
7325 addl(cnt1, stride);
7326 movl(cnt2, stride); negptr(cnt2);
7327 bind(CONT_SCAN_SUBSTR);
7328 if (int_cnt2 < (int)G) {
7329 int tail_off1 = int_cnt2<<scale1;
7330 int tail_off2 = int_cnt2<<scale2;
7331 if (ae == StrIntrinsicNode::UL) {
7332 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7333 } else {
7334 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7335 }
7336 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7337 } else {
7338 // calculate index in register to avoid integer overflow (int_cnt2*2)
7339 movl(tmp, int_cnt2);
7340 addptr(tmp, cnt2);
7341 if (ae == StrIntrinsicNode::UL) {
7342 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7343 } else {
7344 movdqu(vec, Address(str2, tmp, scale2, 0));
7345 }
7346 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7347 }
7348 // Need to reload strings pointers if not matched whole vector
7349 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7350 addptr(cnt2, stride);
7351 jcc(Assembler::negative, SCAN_SUBSTR);
7352 // Fall through if found full substring
7353
7354 } // (int_cnt2 > 8)
7355
7356 bind(RET_FOUND);
7357 // Found result if we matched full small substring.
7358 // Compute substr offset
7359 subptr(result, str1);
7360 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7361 shrl(result, 1); // index
7362 }
7363 bind(EXIT);
7364
7365 } // string_indexofC8
7366
7367 // Small strings are loaded through stack if they cross page boundary.
7368 void MacroAssembler::string_indexof(Register str1, Register str2,
7369 Register cnt1, Register cnt2,
7370 int int_cnt2, Register result,
7371 XMMRegister vec, Register tmp,
7372 int ae) {
7373 ShortBranchVerifier sbv(this);
7374 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7375 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7376
7377 //
7378 // int_cnt2 is length of small (< 8 chars) constant substring
7379 // or (-1) for non constant substring in which case its length
7380 // is in cnt2 register.
7381 //
7382 // Note, inline_string_indexOf() generates checks:
7383 // if (substr.count > string.count) return -1;
7384 // if (substr.count == 0) return 0;
7385 //
7386 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7387 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7388 // This method uses the pcmpestri instruction with bound registers
7389 // inputs:
7390 // xmm - substring
7391 // rax - substring length (elements count)
7392 // mem - scanned string
7393 // rdx - string length (elements count)
7394 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7395 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7396 // outputs:
7397 // rcx - matched index in string
7398 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7399 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7400 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7401 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7402
7403 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7404 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7405 FOUND_CANDIDATE;
7406
7407 { //========================================================
7408 // We don't know where these strings are located
7409 // and we can't read beyond them. Load them through stack.
7410 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7411
7412 movptr(tmp, rsp); // save old SP
7413
7414 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7415 if (int_cnt2 == (1>>scale2)) { // One byte
7416 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7417 load_unsigned_byte(result, Address(str2, 0));
7418 movdl(vec, result); // move 32 bits
7419 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7420 // Not enough header space in 32-bit VM: 12+3 = 15.
7421 movl(result, Address(str2, -1));
7422 shrl(result, 8);
7423 movdl(vec, result); // move 32 bits
7424 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7425 load_unsigned_short(result, Address(str2, 0));
7426 movdl(vec, result); // move 32 bits
7427 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7428 movdl(vec, Address(str2, 0)); // move 32 bits
7429 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7430 movq(vec, Address(str2, 0)); // move 64 bits
7431 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7432 // Array header size is 12 bytes in 32-bit VM
7433 // + 6 bytes for 3 chars == 18 bytes,
7434 // enough space to load vec and shift.
7435 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7436 if (ae == StrIntrinsicNode::UL) {
7437 int tail_off = int_cnt2-8;
7438 pmovzxbw(vec, Address(str2, tail_off));
7439 psrldq(vec, -2*tail_off);
7440 }
7441 else {
7442 int tail_off = int_cnt2*(1<<scale2);
7443 movdqu(vec, Address(str2, tail_off-16));
7444 psrldq(vec, 16-tail_off);
7445 }
7446 }
7447 } else { // not constant substring
7448 cmpl(cnt2, stride);
7449 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7450
7451 // We can read beyond string if srt+16 does not cross page boundary
7452 // since heaps are aligned and mapped by pages.
7453 assert(os::vm_page_size() < (int)G, "default page should be small");
7454 movl(result, str2); // We need only low 32 bits
7455 andl(result, (os::vm_page_size()-1));
7456 cmpl(result, (os::vm_page_size()-16));
7457 jccb(Assembler::belowEqual, CHECK_STR);
7458
7459 // Move small strings to stack to allow load 16 bytes into vec.
7460 subptr(rsp, 16);
7461 int stk_offset = wordSize-(1<<scale2);
7462 push(cnt2);
7463
7464 bind(COPY_SUBSTR);
7465 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7466 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7467 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7468 } else if (ae == StrIntrinsicNode::UU) {
7469 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7470 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7471 }
7472 decrement(cnt2);
7473 jccb(Assembler::notZero, COPY_SUBSTR);
7474
7475 pop(cnt2);
7476 movptr(str2, rsp); // New substring address
7477 } // non constant
7478
7479 bind(CHECK_STR);
7480 cmpl(cnt1, stride);
7481 jccb(Assembler::aboveEqual, BIG_STRINGS);
7482
7483 // Check cross page boundary.
7484 movl(result, str1); // We need only low 32 bits
7485 andl(result, (os::vm_page_size()-1));
7486 cmpl(result, (os::vm_page_size()-16));
7487 jccb(Assembler::belowEqual, BIG_STRINGS);
7488
7489 subptr(rsp, 16);
7490 int stk_offset = -(1<<scale1);
7491 if (int_cnt2 < 0) { // not constant
7492 push(cnt2);
7493 stk_offset += wordSize;
7494 }
7495 movl(cnt2, cnt1);
7496
7497 bind(COPY_STR);
7498 if (ae == StrIntrinsicNode::LL) {
7499 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7500 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7501 } else {
7502 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7503 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7504 }
7505 decrement(cnt2);
7506 jccb(Assembler::notZero, COPY_STR);
7507
7508 if (int_cnt2 < 0) { // not constant
7509 pop(cnt2);
7510 }
7511 movptr(str1, rsp); // New string address
7512
7513 bind(BIG_STRINGS);
7514 // Load substring.
7515 if (int_cnt2 < 0) { // -1
7516 if (ae == StrIntrinsicNode::UL) {
7517 pmovzxbw(vec, Address(str2, 0));
7518 } else {
7519 movdqu(vec, Address(str2, 0));
7520 }
7521 push(cnt2); // substr count
7522 push(str2); // substr addr
7523 push(str1); // string addr
7524 } else {
7525 // Small (< 8 chars) constant substrings are loaded already.
7526 movl(cnt2, int_cnt2);
7527 }
7528 push(tmp); // original SP
7529
7530 } // Finished loading
7531
7532 //========================================================
7533 // Start search
7534 //
7535
7536 movptr(result, str1); // string addr
7537
7538 if (int_cnt2 < 0) { // Only for non constant substring
7539 jmpb(SCAN_TO_SUBSTR);
7540
7541 // SP saved at sp+0
7542 // String saved at sp+1*wordSize
7543 // Substr saved at sp+2*wordSize
7544 // Substr count saved at sp+3*wordSize
7545
7546 // Reload substr for rescan, this code
7547 // is executed only for large substrings (> 8 chars)
7548 bind(RELOAD_SUBSTR);
7549 movptr(str2, Address(rsp, 2*wordSize));
7550 movl(cnt2, Address(rsp, 3*wordSize));
7551 if (ae == StrIntrinsicNode::UL) {
7552 pmovzxbw(vec, Address(str2, 0));
7553 } else {
7554 movdqu(vec, Address(str2, 0));
7555 }
7556 // We came here after the beginning of the substring was
7557 // matched but the rest of it was not so we need to search
7558 // again. Start from the next element after the previous match.
7559 subptr(str1, result); // Restore counter
7560 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7561 shrl(str1, 1);
7562 }
7563 addl(cnt1, str1);
7564 decrementl(cnt1); // Shift to next element
7565 cmpl(cnt1, cnt2);
7566 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7567
7568 addptr(result, (1<<scale1));
7569 } // non constant
7570
7571 // Scan string for start of substr in 16-byte vectors
7572 bind(SCAN_TO_SUBSTR);
7573 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7574 pcmpestri(vec, Address(result, 0), mode);
7575 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7576 subl(cnt1, stride);
7577 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7578 cmpl(cnt1, cnt2);
7579 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7580 addptr(result, 16);
7581
7582 bind(ADJUST_STR);
7583 cmpl(cnt1, stride); // Do not read beyond string
7584 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7585 // Back-up string to avoid reading beyond string.
7586 lea(result, Address(result, cnt1, scale1, -16));
7587 movl(cnt1, stride);
7588 jmpb(SCAN_TO_SUBSTR);
7589
7590 // Found a potential substr
7591 bind(FOUND_CANDIDATE);
7592 // After pcmpestri tmp(rcx) contains matched element index
7593
7594 // Make sure string is still long enough
7595 subl(cnt1, tmp);
7596 cmpl(cnt1, cnt2);
7597 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7598 // Left less then substring.
7599
7600 bind(RET_NOT_FOUND);
7601 movl(result, -1);
7602 jmpb(CLEANUP);
7603
7604 bind(FOUND_SUBSTR);
7605 // Compute start addr of substr
7606 lea(result, Address(result, tmp, scale1));
7607 if (int_cnt2 > 0) { // Constant substring
7608 // Repeat search for small substring (< 8 chars)
7609 // from new point without reloading substring.
7610 // Have to check that we don't read beyond string.
7611 cmpl(tmp, stride-int_cnt2);
7612 jccb(Assembler::greater, ADJUST_STR);
7613 // Fall through if matched whole substring.
7614 } else { // non constant
7615 assert(int_cnt2 == -1, "should be != 0");
7616
7617 addl(tmp, cnt2);
7618 // Found result if we matched whole substring.
7619 cmpl(tmp, stride);
7620 jccb(Assembler::lessEqual, RET_FOUND);
7621
7622 // Repeat search for small substring (<= 8 chars)
7623 // from new point 'str1' without reloading substring.
7624 cmpl(cnt2, stride);
7625 // Have to check that we don't read beyond string.
7626 jccb(Assembler::lessEqual, ADJUST_STR);
7627
7628 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7629 // Compare the rest of substring (> 8 chars).
7630 movptr(str1, result);
7631
7632 cmpl(tmp, cnt2);
7633 // First 8 chars are already matched.
7634 jccb(Assembler::equal, CHECK_NEXT);
7635
7636 bind(SCAN_SUBSTR);
7637 pcmpestri(vec, Address(str1, 0), mode);
7638 // Need to reload strings pointers if not matched whole vector
7639 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7640
7641 bind(CHECK_NEXT);
7642 subl(cnt2, stride);
7643 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7644 addptr(str1, 16);
7645 if (ae == StrIntrinsicNode::UL) {
7646 addptr(str2, 8);
7647 } else {
7648 addptr(str2, 16);
7649 }
7650 subl(cnt1, stride);
7651 cmpl(cnt2, stride); // Do not read beyond substring
7652 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7653 // Back-up strings to avoid reading beyond substring.
7654
7655 if (ae == StrIntrinsicNode::UL) {
7656 lea(str2, Address(str2, cnt2, scale2, -8));
7657 lea(str1, Address(str1, cnt2, scale1, -16));
7658 } else {
7659 lea(str2, Address(str2, cnt2, scale2, -16));
7660 lea(str1, Address(str1, cnt2, scale1, -16));
7661 }
7662 subl(cnt1, cnt2);
7663 movl(cnt2, stride);
7664 addl(cnt1, stride);
7665 bind(CONT_SCAN_SUBSTR);
7666 if (ae == StrIntrinsicNode::UL) {
7667 pmovzxbw(vec, Address(str2, 0));
7668 } else {
7669 movdqu(vec, Address(str2, 0));
7670 }
7671 jmp(SCAN_SUBSTR);
7672
7673 bind(RET_FOUND_LONG);
7674 movptr(str1, Address(rsp, wordSize));
7675 } // non constant
7676
7677 bind(RET_FOUND);
7678 // Compute substr offset
7679 subptr(result, str1);
7680 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7681 shrl(result, 1); // index
7682 }
7683 bind(CLEANUP);
7684 pop(rsp); // restore SP
7685
7686 } // string_indexof
7687
7688 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7689 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7690 ShortBranchVerifier sbv(this);
7691 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7692
7693 int stride = 8;
7694
7695 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7696 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7697 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7698 FOUND_SEQ_CHAR, DONE_LABEL;
7699
7700 movptr(result, str1);
7701 if (UseAVX >= 2) {
7702 cmpl(cnt1, stride);
7703 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7704 cmpl(cnt1, 2*stride);
7705 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7706 movdl(vec1, ch);
7707 vpbroadcastw(vec1, vec1);
7708 vpxor(vec2, vec2);
7709 movl(tmp, cnt1);
7710 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7711 andl(cnt1,0x0000000F); //tail count (in chars)
7712
7713 bind(SCAN_TO_16_CHAR_LOOP);
7714 vmovdqu(vec3, Address(result, 0));
7715 vpcmpeqw(vec3, vec3, vec1, 1);
7716 vptest(vec2, vec3);
7717 jcc(Assembler::carryClear, FOUND_CHAR);
7718 addptr(result, 32);
7719 subl(tmp, 2*stride);
7720 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7721 jmp(SCAN_TO_8_CHAR);
7722 bind(SCAN_TO_8_CHAR_INIT);
7723 movdl(vec1, ch);
7724 pshuflw(vec1, vec1, 0x00);
7725 pshufd(vec1, vec1, 0);
7726 pxor(vec2, vec2);
7727 }
7728 bind(SCAN_TO_8_CHAR);
7729 cmpl(cnt1, stride);
7730 if (UseAVX >= 2) {
7731 jcc(Assembler::less, SCAN_TO_CHAR);
7732 } else {
7733 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7734 movdl(vec1, ch);
7735 pshuflw(vec1, vec1, 0x00);
7736 pshufd(vec1, vec1, 0);
7737 pxor(vec2, vec2);
7738 }
7739 movl(tmp, cnt1);
7740 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7741 andl(cnt1,0x00000007); //tail count (in chars)
7742
7743 bind(SCAN_TO_8_CHAR_LOOP);
7744 movdqu(vec3, Address(result, 0));
7745 pcmpeqw(vec3, vec1);
7746 ptest(vec2, vec3);
7747 jcc(Assembler::carryClear, FOUND_CHAR);
7748 addptr(result, 16);
7749 subl(tmp, stride);
7750 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7751 bind(SCAN_TO_CHAR);
7752 testl(cnt1, cnt1);
7753 jcc(Assembler::zero, RET_NOT_FOUND);
7754 bind(SCAN_TO_CHAR_LOOP);
7755 load_unsigned_short(tmp, Address(result, 0));
7756 cmpl(ch, tmp);
7757 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7758 addptr(result, 2);
7759 subl(cnt1, 1);
7760 jccb(Assembler::zero, RET_NOT_FOUND);
7761 jmp(SCAN_TO_CHAR_LOOP);
7762
7763 bind(RET_NOT_FOUND);
7764 movl(result, -1);
7765 jmpb(DONE_LABEL);
7766
7767 bind(FOUND_CHAR);
7768 if (UseAVX >= 2) {
7769 vpmovmskb(tmp, vec3);
7770 } else {
7771 pmovmskb(tmp, vec3);
7772 }
7773 bsfl(ch, tmp);
7774 addl(result, ch);
7775
7776 bind(FOUND_SEQ_CHAR);
7777 subptr(result, str1);
7778 shrl(result, 1);
7779
7780 bind(DONE_LABEL);
7781 } // string_indexof_char
7782
7783 // helper function for string_compare
7784 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7785 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7786 Address::ScaleFactor scale2, Register index, int ae) {
7787 if (ae == StrIntrinsicNode::LL) {
7788 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7789 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7790 } else if (ae == StrIntrinsicNode::UU) {
7791 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7792 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7793 } else {
7794 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7795 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7796 }
7797 }
7798
7799 // Compare strings, used for char[] and byte[].
7800 void MacroAssembler::string_compare(Register str1, Register str2,
7801 Register cnt1, Register cnt2, Register result,
7802 XMMRegister vec1, int ae) {
7803 ShortBranchVerifier sbv(this);
7804 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7805 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7806 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7807 int stride2x2 = 0x40;
7808 Address::ScaleFactor scale = Address::no_scale;
7809 Address::ScaleFactor scale1 = Address::no_scale;
7810 Address::ScaleFactor scale2 = Address::no_scale;
7811
7812 if (ae != StrIntrinsicNode::LL) {
7813 stride2x2 = 0x20;
7814 }
7815
7816 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7817 shrl(cnt2, 1);
7818 }
7819 // Compute the minimum of the string lengths and the
7820 // difference of the string lengths (stack).
7821 // Do the conditional move stuff
7822 movl(result, cnt1);
7823 subl(cnt1, cnt2);
7824 push(cnt1);
7825 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7826
7827 // Is the minimum length zero?
7828 testl(cnt2, cnt2);
7829 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7830 if (ae == StrIntrinsicNode::LL) {
7831 // Load first bytes
7832 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7833 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7834 } else if (ae == StrIntrinsicNode::UU) {
7835 // Load first characters
7836 load_unsigned_short(result, Address(str1, 0));
7837 load_unsigned_short(cnt1, Address(str2, 0));
7838 } else {
7839 load_unsigned_byte(result, Address(str1, 0));
7840 load_unsigned_short(cnt1, Address(str2, 0));
7841 }
7842 subl(result, cnt1);
7843 jcc(Assembler::notZero, POP_LABEL);
7844
7845 if (ae == StrIntrinsicNode::UU) {
7846 // Divide length by 2 to get number of chars
7847 shrl(cnt2, 1);
7848 }
7849 cmpl(cnt2, 1);
7850 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7851
7852 // Check if the strings start at the same location and setup scale and stride
7853 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7854 cmpptr(str1, str2);
7855 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7856 if (ae == StrIntrinsicNode::LL) {
7857 scale = Address::times_1;
7858 stride = 16;
7859 } else {
7860 scale = Address::times_2;
7861 stride = 8;
7862 }
7863 } else {
7864 scale1 = Address::times_1;
7865 scale2 = Address::times_2;
7866 // scale not used
7867 stride = 8;
7868 }
7869
7870 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7871 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7872 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7873 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7874 Label COMPARE_TAIL_LONG;
7875 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7876
7877 int pcmpmask = 0x19;
7878 if (ae == StrIntrinsicNode::LL) {
7879 pcmpmask &= ~0x01;
7880 }
7881
7882 // Setup to compare 16-chars (32-bytes) vectors,
7883 // start from first character again because it has aligned address.
7884 if (ae == StrIntrinsicNode::LL) {
7885 stride2 = 32;
7886 } else {
7887 stride2 = 16;
7888 }
7889 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7890 adr_stride = stride << scale;
7891 } else {
7892 adr_stride1 = 8; //stride << scale1;
7893 adr_stride2 = 16; //stride << scale2;
7894 }
7895
7896 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7897 // rax and rdx are used by pcmpestri as elements counters
7898 movl(result, cnt2);
7899 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7900 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7901
7902 // fast path : compare first 2 8-char vectors.
7903 bind(COMPARE_16_CHARS);
7904 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7905 movdqu(vec1, Address(str1, 0));
7906 } else {
7907 pmovzxbw(vec1, Address(str1, 0));
7908 }
7909 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7910 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7911
7912 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7913 movdqu(vec1, Address(str1, adr_stride));
7914 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7915 } else {
7916 pmovzxbw(vec1, Address(str1, adr_stride1));
7917 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7918 }
7919 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7920 addl(cnt1, stride);
7921
7922 // Compare the characters at index in cnt1
7923 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7924 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7925 subl(result, cnt2);
7926 jmp(POP_LABEL);
7927
7928 // Setup the registers to start vector comparison loop
7929 bind(COMPARE_WIDE_VECTORS);
7930 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7931 lea(str1, Address(str1, result, scale));
7932 lea(str2, Address(str2, result, scale));
7933 } else {
7934 lea(str1, Address(str1, result, scale1));
7935 lea(str2, Address(str2, result, scale2));
7936 }
7937 subl(result, stride2);
7938 subl(cnt2, stride2);
7939 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7940 negptr(result);
7941
7942 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7943 bind(COMPARE_WIDE_VECTORS_LOOP);
7944
7945 #ifdef _LP64
7946 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7947 cmpl(cnt2, stride2x2);
7948 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7949 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7950 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7951
7952 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7953 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7954 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7955 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7956 } else {
7957 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7958 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7959 }
7960 kortestql(k7, k7);
7961 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7962 addptr(result, stride2x2); // update since we already compared at this addr
7963 subl(cnt2, stride2x2); // and sub the size too
7964 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7965
7966 vpxor(vec1, vec1);
7967 jmpb(COMPARE_WIDE_TAIL);
7968 }//if (VM_Version::supports_avx512vlbw())
7969 #endif // _LP64
7970
7971
7972 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7973 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7974 vmovdqu(vec1, Address(str1, result, scale));
7975 vpxor(vec1, Address(str2, result, scale));
7976 } else {
7977 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7978 vpxor(vec1, Address(str2, result, scale2));
7979 }
7980 vptest(vec1, vec1);
7981 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7982 addptr(result, stride2);
7983 subl(cnt2, stride2);
7984 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7985 // clean upper bits of YMM registers
7986 vpxor(vec1, vec1);
7987
7988 // compare wide vectors tail
7989 bind(COMPARE_WIDE_TAIL);
7990 testptr(result, result);
7991 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7992
7993 movl(result, stride2);
7994 movl(cnt2, result);
7995 negptr(result);
7996 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7997
7998 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7999 bind(VECTOR_NOT_EQUAL);
8000 // clean upper bits of YMM registers
8001 vpxor(vec1, vec1);
8002 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8003 lea(str1, Address(str1, result, scale));
8004 lea(str2, Address(str2, result, scale));
8005 } else {
8006 lea(str1, Address(str1, result, scale1));
8007 lea(str2, Address(str2, result, scale2));
8008 }
8009 jmp(COMPARE_16_CHARS);
8010
8011 // Compare tail chars, length between 1 to 15 chars
8012 bind(COMPARE_TAIL_LONG);
8013 movl(cnt2, result);
8014 cmpl(cnt2, stride);
8015 jcc(Assembler::less, COMPARE_SMALL_STR);
8016
8017 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8018 movdqu(vec1, Address(str1, 0));
8019 } else {
8020 pmovzxbw(vec1, Address(str1, 0));
8021 }
8022 pcmpestri(vec1, Address(str2, 0), pcmpmask);
8023 jcc(Assembler::below, COMPARE_INDEX_CHAR);
8024 subptr(cnt2, stride);
8025 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8026 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8027 lea(str1, Address(str1, result, scale));
8028 lea(str2, Address(str2, result, scale));
8029 } else {
8030 lea(str1, Address(str1, result, scale1));
8031 lea(str2, Address(str2, result, scale2));
8032 }
8033 negptr(cnt2);
8034 jmpb(WHILE_HEAD_LABEL);
8035
8036 bind(COMPARE_SMALL_STR);
8037 } else if (UseSSE42Intrinsics) {
8038 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8039 int pcmpmask = 0x19;
8040 // Setup to compare 8-char (16-byte) vectors,
8041 // start from first character again because it has aligned address.
8042 movl(result, cnt2);
8043 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
8044 if (ae == StrIntrinsicNode::LL) {
8045 pcmpmask &= ~0x01;
8046 }
8047 jcc(Assembler::zero, COMPARE_TAIL);
8048 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8049 lea(str1, Address(str1, result, scale));
8050 lea(str2, Address(str2, result, scale));
8051 } else {
8052 lea(str1, Address(str1, result, scale1));
8053 lea(str2, Address(str2, result, scale2));
8054 }
8055 negptr(result);
8056
8057 // pcmpestri
8058 // inputs:
8059 // vec1- substring
8060 // rax - negative string length (elements count)
8061 // mem - scanned string
8062 // rdx - string length (elements count)
8063 // pcmpmask - cmp mode: 11000 (string compare with negated result)
8064 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
8065 // outputs:
8066 // rcx - first mismatched element index
8067 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
8068
8069 bind(COMPARE_WIDE_VECTORS);
8070 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8071 movdqu(vec1, Address(str1, result, scale));
8072 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8073 } else {
8074 pmovzxbw(vec1, Address(str1, result, scale1));
8075 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8076 }
8077 // After pcmpestri cnt1(rcx) contains mismatched element index
8078
8079 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8080 addptr(result, stride);
8081 subptr(cnt2, stride);
8082 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8083
8084 // compare wide vectors tail
8085 testptr(result, result);
8086 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8087
8088 movl(cnt2, stride);
8089 movl(result, stride);
8090 negptr(result);
8091 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8092 movdqu(vec1, Address(str1, result, scale));
8093 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8094 } else {
8095 pmovzxbw(vec1, Address(str1, result, scale1));
8096 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8097 }
8098 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8099
8100 // Mismatched characters in the vectors
8101 bind(VECTOR_NOT_EQUAL);
8102 addptr(cnt1, result);
8103 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8104 subl(result, cnt2);
8105 jmpb(POP_LABEL);
8106
8107 bind(COMPARE_TAIL); // limit is zero
8108 movl(cnt2, result);
8109 // Fallthru to tail compare
8110 }
8111 // Shift str2 and str1 to the end of the arrays, negate min
8112 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8113 lea(str1, Address(str1, cnt2, scale));
8114 lea(str2, Address(str2, cnt2, scale));
8115 } else {
8116 lea(str1, Address(str1, cnt2, scale1));
8117 lea(str2, Address(str2, cnt2, scale2));
8118 }
8119 decrementl(cnt2); // first character was compared already
8120 negptr(cnt2);
8121
8122 // Compare the rest of the elements
8123 bind(WHILE_HEAD_LABEL);
8124 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8125 subl(result, cnt1);
8126 jccb(Assembler::notZero, POP_LABEL);
8127 increment(cnt2);
8128 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8129
8130 // Strings are equal up to min length. Return the length difference.
8131 bind(LENGTH_DIFF_LABEL);
8132 pop(result);
8133 if (ae == StrIntrinsicNode::UU) {
8134 // Divide diff by 2 to get number of chars
8135 sarl(result, 1);
8136 }
8137 jmpb(DONE_LABEL);
8138
8139 #ifdef _LP64
8140 if (VM_Version::supports_avx512vlbw()) {
8141
8142 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8143
8144 kmovql(cnt1, k7);
8145 notq(cnt1);
8146 bsfq(cnt2, cnt1);
8147 if (ae != StrIntrinsicNode::LL) {
8148 // Divide diff by 2 to get number of chars
8149 sarl(cnt2, 1);
8150 }
8151 addq(result, cnt2);
8152 if (ae == StrIntrinsicNode::LL) {
8153 load_unsigned_byte(cnt1, Address(str2, result));
8154 load_unsigned_byte(result, Address(str1, result));
8155 } else if (ae == StrIntrinsicNode::UU) {
8156 load_unsigned_short(cnt1, Address(str2, result, scale));
8157 load_unsigned_short(result, Address(str1, result, scale));
8158 } else {
8159 load_unsigned_short(cnt1, Address(str2, result, scale2));
8160 load_unsigned_byte(result, Address(str1, result, scale1));
8161 }
8162 subl(result, cnt1);
8163 jmpb(POP_LABEL);
8164 }//if (VM_Version::supports_avx512vlbw())
8165 #endif // _LP64
8166
8167 // Discard the stored length difference
8168 bind(POP_LABEL);
8169 pop(cnt1);
8170
8171 // That's it
8172 bind(DONE_LABEL);
8173 if(ae == StrIntrinsicNode::UL) {
8174 negl(result);
8175 }
8176
8177 }
8178
8179 // Search for Non-ASCII character (Negative byte value) in a byte array,
8180 // return true if it has any and false otherwise.
8181 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8182 // @HotSpotIntrinsicCandidate
8183 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8184 // for (int i = off; i < off + len; i++) {
8185 // if (ba[i] < 0) {
8186 // return true;
8187 // }
8188 // }
8189 // return false;
8190 // }
8191 void MacroAssembler::has_negatives(Register ary1, Register len,
8192 Register result, Register tmp1,
8193 XMMRegister vec1, XMMRegister vec2) {
8194 // rsi: byte array
8195 // rcx: len
8196 // rax: result
8197 ShortBranchVerifier sbv(this);
8198 assert_different_registers(ary1, len, result, tmp1);
8199 assert_different_registers(vec1, vec2);
8200 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8201
8202 // len == 0
8203 testl(len, len);
8204 jcc(Assembler::zero, FALSE_LABEL);
8205
8206 if ((UseAVX > 2) && // AVX512
8207 VM_Version::supports_avx512vlbw() &&
8208 VM_Version::supports_bmi2()) {
8209
8210 set_vector_masking(); // opening of the stub context for programming mask registers
8211
8212 Label test_64_loop, test_tail;
8213 Register tmp3_aliased = len;
8214
8215 movl(tmp1, len);
8216 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8217
8218 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8219 andl(len, ~(64 - 1)); // vector count (in chars)
8220 jccb(Assembler::zero, test_tail);
8221
8222 lea(ary1, Address(ary1, len, Address::times_1));
8223 negptr(len);
8224
8225 bind(test_64_loop);
8226 // Check whether our 64 elements of size byte contain negatives
8227 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8228 kortestql(k2, k2);
8229 jcc(Assembler::notZero, TRUE_LABEL);
8230
8231 addptr(len, 64);
8232 jccb(Assembler::notZero, test_64_loop);
8233
8234
8235 bind(test_tail);
8236 // bail out when there is nothing to be done
8237 testl(tmp1, -1);
8238 jcc(Assembler::zero, FALSE_LABEL);
8239
8240 // Save k1
8241 kmovql(k3, k1);
8242
8243 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8244 #ifdef _LP64
8245 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8246 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8247 notq(tmp3_aliased);
8248 kmovql(k1, tmp3_aliased);
8249 #else
8250 Label k_init;
8251 jmp(k_init);
8252
8253 // We could not read 64-bits from a general purpose register thus we move
8254 // data required to compose 64 1's to the instruction stream
8255 // We emit 64 byte wide series of elements from 0..63 which later on would
8256 // be used as a compare targets with tail count contained in tmp1 register.
8257 // Result would be a k1 register having tmp1 consecutive number or 1
8258 // counting from least significant bit.
8259 address tmp = pc();
8260 emit_int64(0x0706050403020100);
8261 emit_int64(0x0F0E0D0C0B0A0908);
8262 emit_int64(0x1716151413121110);
8263 emit_int64(0x1F1E1D1C1B1A1918);
8264 emit_int64(0x2726252423222120);
8265 emit_int64(0x2F2E2D2C2B2A2928);
8266 emit_int64(0x3736353433323130);
8267 emit_int64(0x3F3E3D3C3B3A3938);
8268
8269 bind(k_init);
8270 lea(len, InternalAddress(tmp));
8271 // create mask to test for negative byte inside a vector
8272 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8273 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8274
8275 #endif
8276 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8277 ktestq(k2, k1);
8278 // Restore k1
8279 kmovql(k1, k3);
8280 jcc(Assembler::notZero, TRUE_LABEL);
8281
8282 jmp(FALSE_LABEL);
8283
8284 clear_vector_masking(); // closing of the stub context for programming mask registers
8285 } else {
8286 movl(result, len); // copy
8287
8288 if (UseAVX == 2 && UseSSE >= 2) {
8289 // With AVX2, use 32-byte vector compare
8290 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8291
8292 // Compare 32-byte vectors
8293 andl(result, 0x0000001f); // tail count (in bytes)
8294 andl(len, 0xffffffe0); // vector count (in bytes)
8295 jccb(Assembler::zero, COMPARE_TAIL);
8296
8297 lea(ary1, Address(ary1, len, Address::times_1));
8298 negptr(len);
8299
8300 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8301 movdl(vec2, tmp1);
8302 vpbroadcastd(vec2, vec2);
8303
8304 bind(COMPARE_WIDE_VECTORS);
8305 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8306 vptest(vec1, vec2);
8307 jccb(Assembler::notZero, TRUE_LABEL);
8308 addptr(len, 32);
8309 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8310
8311 testl(result, result);
8312 jccb(Assembler::zero, FALSE_LABEL);
8313
8314 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8315 vptest(vec1, vec2);
8316 jccb(Assembler::notZero, TRUE_LABEL);
8317 jmpb(FALSE_LABEL);
8318
8319 bind(COMPARE_TAIL); // len is zero
8320 movl(len, result);
8321 // Fallthru to tail compare
8322 } else if (UseSSE42Intrinsics) {
8323 // With SSE4.2, use double quad vector compare
8324 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8325
8326 // Compare 16-byte vectors
8327 andl(result, 0x0000000f); // tail count (in bytes)
8328 andl(len, 0xfffffff0); // vector count (in bytes)
8329 jccb(Assembler::zero, COMPARE_TAIL);
8330
8331 lea(ary1, Address(ary1, len, Address::times_1));
8332 negptr(len);
8333
8334 movl(tmp1, 0x80808080);
8335 movdl(vec2, tmp1);
8336 pshufd(vec2, vec2, 0);
8337
8338 bind(COMPARE_WIDE_VECTORS);
8339 movdqu(vec1, Address(ary1, len, Address::times_1));
8340 ptest(vec1, vec2);
8341 jccb(Assembler::notZero, TRUE_LABEL);
8342 addptr(len, 16);
8343 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8344
8345 testl(result, result);
8346 jccb(Assembler::zero, FALSE_LABEL);
8347
8348 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8349 ptest(vec1, vec2);
8350 jccb(Assembler::notZero, TRUE_LABEL);
8351 jmpb(FALSE_LABEL);
8352
8353 bind(COMPARE_TAIL); // len is zero
8354 movl(len, result);
8355 // Fallthru to tail compare
8356 }
8357 }
8358 // Compare 4-byte vectors
8359 andl(len, 0xfffffffc); // vector count (in bytes)
8360 jccb(Assembler::zero, COMPARE_CHAR);
8361
8362 lea(ary1, Address(ary1, len, Address::times_1));
8363 negptr(len);
8364
8365 bind(COMPARE_VECTORS);
8366 movl(tmp1, Address(ary1, len, Address::times_1));
8367 andl(tmp1, 0x80808080);
8368 jccb(Assembler::notZero, TRUE_LABEL);
8369 addptr(len, 4);
8370 jcc(Assembler::notZero, COMPARE_VECTORS);
8371
8372 // Compare trailing char (final 2 bytes), if any
8373 bind(COMPARE_CHAR);
8374 testl(result, 0x2); // tail char
8375 jccb(Assembler::zero, COMPARE_BYTE);
8376 load_unsigned_short(tmp1, Address(ary1, 0));
8377 andl(tmp1, 0x00008080);
8378 jccb(Assembler::notZero, TRUE_LABEL);
8379 subptr(result, 2);
8380 lea(ary1, Address(ary1, 2));
8381
8382 bind(COMPARE_BYTE);
8383 testl(result, 0x1); // tail byte
8384 jccb(Assembler::zero, FALSE_LABEL);
8385 load_unsigned_byte(tmp1, Address(ary1, 0));
8386 andl(tmp1, 0x00000080);
8387 jccb(Assembler::notEqual, TRUE_LABEL);
8388 jmpb(FALSE_LABEL);
8389
8390 bind(TRUE_LABEL);
8391 movl(result, 1); // return true
8392 jmpb(DONE);
8393
8394 bind(FALSE_LABEL);
8395 xorl(result, result); // return false
8396
8397 // That's it
8398 bind(DONE);
8399 if (UseAVX >= 2 && UseSSE >= 2) {
8400 // clean upper bits of YMM registers
8401 vpxor(vec1, vec1);
8402 vpxor(vec2, vec2);
8403 }
8404 }
8405 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8406 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8407 Register limit, Register result, Register chr,
8408 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8409 ShortBranchVerifier sbv(this);
8410 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8411
8412 int length_offset = arrayOopDesc::length_offset_in_bytes();
8413 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8414
8415 if (is_array_equ) {
8416 // Check the input args
8417 cmpoop(ary1, ary2);
8418 jcc(Assembler::equal, TRUE_LABEL);
8419
8420 // Need additional checks for arrays_equals.
8421 testptr(ary1, ary1);
8422 jcc(Assembler::zero, FALSE_LABEL);
8423 testptr(ary2, ary2);
8424 jcc(Assembler::zero, FALSE_LABEL);
8425
8426 // Check the lengths
8427 movl(limit, Address(ary1, length_offset));
8428 cmpl(limit, Address(ary2, length_offset));
8429 jcc(Assembler::notEqual, FALSE_LABEL);
8430 }
8431
8432 // count == 0
8433 testl(limit, limit);
8434 jcc(Assembler::zero, TRUE_LABEL);
8435
8436 if (is_array_equ) {
8437 // Load array address
8438 lea(ary1, Address(ary1, base_offset));
8439 lea(ary2, Address(ary2, base_offset));
8440 }
8441
8442 if (is_array_equ && is_char) {
8443 // arrays_equals when used for char[].
8444 shll(limit, 1); // byte count != 0
8445 }
8446 movl(result, limit); // copy
8447
8448 if (UseAVX >= 2) {
8449 // With AVX2, use 32-byte vector compare
8450 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8451
8452 // Compare 32-byte vectors
8453 andl(result, 0x0000001f); // tail count (in bytes)
8454 andl(limit, 0xffffffe0); // vector count (in bytes)
8455 jcc(Assembler::zero, COMPARE_TAIL);
8456
8457 lea(ary1, Address(ary1, limit, Address::times_1));
8458 lea(ary2, Address(ary2, limit, Address::times_1));
8459 negptr(limit);
8460
8461 bind(COMPARE_WIDE_VECTORS);
8462
8463 #ifdef _LP64
8464 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8465 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8466
8467 cmpl(limit, -64);
8468 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8469
8470 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8471
8472 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8473 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8474 kortestql(k7, k7);
8475 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8476 addptr(limit, 64); // update since we already compared at this addr
8477 cmpl(limit, -64);
8478 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8479
8480 // At this point we may still need to compare -limit+result bytes.
8481 // We could execute the next two instruction and just continue via non-wide path:
8482 // cmpl(limit, 0);
8483 // jcc(Assembler::equal, COMPARE_TAIL); // true
8484 // But since we stopped at the points ary{1,2}+limit which are
8485 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8486 // (|limit| <= 32 and result < 32),
8487 // we may just compare the last 64 bytes.
8488 //
8489 addptr(result, -64); // it is safe, bc we just came from this area
8490 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8491 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8492 kortestql(k7, k7);
8493 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8494
8495 jmp(TRUE_LABEL);
8496
8497 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8498
8499 }//if (VM_Version::supports_avx512vlbw())
8500 #endif //_LP64
8501
8502 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8503 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8504 vpxor(vec1, vec2);
8505
8506 vptest(vec1, vec1);
8507 jcc(Assembler::notZero, FALSE_LABEL);
8508 addptr(limit, 32);
8509 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8510
8511 testl(result, result);
8512 jcc(Assembler::zero, TRUE_LABEL);
8513
8514 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8515 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8516 vpxor(vec1, vec2);
8517
8518 vptest(vec1, vec1);
8519 jccb(Assembler::notZero, FALSE_LABEL);
8520 jmpb(TRUE_LABEL);
8521
8522 bind(COMPARE_TAIL); // limit is zero
8523 movl(limit, result);
8524 // Fallthru to tail compare
8525 } else if (UseSSE42Intrinsics) {
8526 // With SSE4.2, use double quad vector compare
8527 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8528
8529 // Compare 16-byte vectors
8530 andl(result, 0x0000000f); // tail count (in bytes)
8531 andl(limit, 0xfffffff0); // vector count (in bytes)
8532 jcc(Assembler::zero, COMPARE_TAIL);
8533
8534 lea(ary1, Address(ary1, limit, Address::times_1));
8535 lea(ary2, Address(ary2, limit, Address::times_1));
8536 negptr(limit);
8537
8538 bind(COMPARE_WIDE_VECTORS);
8539 movdqu(vec1, Address(ary1, limit, Address::times_1));
8540 movdqu(vec2, Address(ary2, limit, Address::times_1));
8541 pxor(vec1, vec2);
8542
8543 ptest(vec1, vec1);
8544 jcc(Assembler::notZero, FALSE_LABEL);
8545 addptr(limit, 16);
8546 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8547
8548 testl(result, result);
8549 jcc(Assembler::zero, TRUE_LABEL);
8550
8551 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8552 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8553 pxor(vec1, vec2);
8554
8555 ptest(vec1, vec1);
8556 jccb(Assembler::notZero, FALSE_LABEL);
8557 jmpb(TRUE_LABEL);
8558
8559 bind(COMPARE_TAIL); // limit is zero
8560 movl(limit, result);
8561 // Fallthru to tail compare
8562 }
8563
8564 // Compare 4-byte vectors
8565 andl(limit, 0xfffffffc); // vector count (in bytes)
8566 jccb(Assembler::zero, COMPARE_CHAR);
8567
8568 lea(ary1, Address(ary1, limit, Address::times_1));
8569 lea(ary2, Address(ary2, limit, Address::times_1));
8570 negptr(limit);
8571
8572 bind(COMPARE_VECTORS);
8573 movl(chr, Address(ary1, limit, Address::times_1));
8574 cmpl(chr, Address(ary2, limit, Address::times_1));
8575 jccb(Assembler::notEqual, FALSE_LABEL);
8576 addptr(limit, 4);
8577 jcc(Assembler::notZero, COMPARE_VECTORS);
8578
8579 // Compare trailing char (final 2 bytes), if any
8580 bind(COMPARE_CHAR);
8581 testl(result, 0x2); // tail char
8582 jccb(Assembler::zero, COMPARE_BYTE);
8583 load_unsigned_short(chr, Address(ary1, 0));
8584 load_unsigned_short(limit, Address(ary2, 0));
8585 cmpl(chr, limit);
8586 jccb(Assembler::notEqual, FALSE_LABEL);
8587
8588 if (is_array_equ && is_char) {
8589 bind(COMPARE_BYTE);
8590 } else {
8591 lea(ary1, Address(ary1, 2));
8592 lea(ary2, Address(ary2, 2));
8593
8594 bind(COMPARE_BYTE);
8595 testl(result, 0x1); // tail byte
8596 jccb(Assembler::zero, TRUE_LABEL);
8597 load_unsigned_byte(chr, Address(ary1, 0));
8598 load_unsigned_byte(limit, Address(ary2, 0));
8599 cmpl(chr, limit);
8600 jccb(Assembler::notEqual, FALSE_LABEL);
8601 }
8602 bind(TRUE_LABEL);
8603 movl(result, 1); // return true
8604 jmpb(DONE);
8605
8606 bind(FALSE_LABEL);
8607 xorl(result, result); // return false
8608
8609 // That's it
8610 bind(DONE);
8611 if (UseAVX >= 2) {
8612 // clean upper bits of YMM registers
8613 vpxor(vec1, vec1);
8614 vpxor(vec2, vec2);
8615 }
8616 }
8617
8618 #endif
8619
8620 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8621 Register to, Register value, Register count,
8622 Register rtmp, XMMRegister xtmp) {
8623 ShortBranchVerifier sbv(this);
8624 assert_different_registers(to, value, count, rtmp);
8625 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8626 Label L_fill_2_bytes, L_fill_4_bytes;
8627
8628 int shift = -1;
8629 switch (t) {
8630 case T_BYTE:
8631 shift = 2;
8632 break;
8633 case T_SHORT:
8634 shift = 1;
8635 break;
8636 case T_INT:
8637 shift = 0;
8638 break;
8639 default: ShouldNotReachHere();
8640 }
8641
8642 if (t == T_BYTE) {
8643 andl(value, 0xff);
8644 movl(rtmp, value);
8645 shll(rtmp, 8);
8646 orl(value, rtmp);
8647 }
8648 if (t == T_SHORT) {
8649 andl(value, 0xffff);
8650 }
8651 if (t == T_BYTE || t == T_SHORT) {
8652 movl(rtmp, value);
8653 shll(rtmp, 16);
8654 orl(value, rtmp);
8655 }
8656
8657 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8658 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8659 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8660 // align source address at 4 bytes address boundary
8661 if (t == T_BYTE) {
8662 // One byte misalignment happens only for byte arrays
8663 testptr(to, 1);
8664 jccb(Assembler::zero, L_skip_align1);
8665 movb(Address(to, 0), value);
8666 increment(to);
8667 decrement(count);
8668 BIND(L_skip_align1);
8669 }
8670 // Two bytes misalignment happens only for byte and short (char) arrays
8671 testptr(to, 2);
8672 jccb(Assembler::zero, L_skip_align2);
8673 movw(Address(to, 0), value);
8674 addptr(to, 2);
8675 subl(count, 1<<(shift-1));
8676 BIND(L_skip_align2);
8677 }
8678 if (UseSSE < 2) {
8679 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8680 // Fill 32-byte chunks
8681 subl(count, 8 << shift);
8682 jcc(Assembler::less, L_check_fill_8_bytes);
8683 align(16);
8684
8685 BIND(L_fill_32_bytes_loop);
8686
8687 for (int i = 0; i < 32; i += 4) {
8688 movl(Address(to, i), value);
8689 }
8690
8691 addptr(to, 32);
8692 subl(count, 8 << shift);
8693 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8694 BIND(L_check_fill_8_bytes);
8695 addl(count, 8 << shift);
8696 jccb(Assembler::zero, L_exit);
8697 jmpb(L_fill_8_bytes);
8698
8699 //
8700 // length is too short, just fill qwords
8701 //
8702 BIND(L_fill_8_bytes_loop);
8703 movl(Address(to, 0), value);
8704 movl(Address(to, 4), value);
8705 addptr(to, 8);
8706 BIND(L_fill_8_bytes);
8707 subl(count, 1 << (shift + 1));
8708 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8709 // fall through to fill 4 bytes
8710 } else {
8711 Label L_fill_32_bytes;
8712 if (!UseUnalignedLoadStores) {
8713 // align to 8 bytes, we know we are 4 byte aligned to start
8714 testptr(to, 4);
8715 jccb(Assembler::zero, L_fill_32_bytes);
8716 movl(Address(to, 0), value);
8717 addptr(to, 4);
8718 subl(count, 1<<shift);
8719 }
8720 BIND(L_fill_32_bytes);
8721 {
8722 assert( UseSSE >= 2, "supported cpu only" );
8723 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8724 if (UseAVX > 2) {
8725 movl(rtmp, 0xffff);
8726 kmovwl(k1, rtmp);
8727 }
8728 movdl(xtmp, value);
8729 if (UseAVX > 2 && UseUnalignedLoadStores) {
8730 // Fill 64-byte chunks
8731 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8732 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8733
8734 subl(count, 16 << shift);
8735 jcc(Assembler::less, L_check_fill_32_bytes);
8736 align(16);
8737
8738 BIND(L_fill_64_bytes_loop);
8739 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8740 addptr(to, 64);
8741 subl(count, 16 << shift);
8742 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8743
8744 BIND(L_check_fill_32_bytes);
8745 addl(count, 8 << shift);
8746 jccb(Assembler::less, L_check_fill_8_bytes);
8747 vmovdqu(Address(to, 0), xtmp);
8748 addptr(to, 32);
8749 subl(count, 8 << shift);
8750
8751 BIND(L_check_fill_8_bytes);
8752 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8753 // Fill 64-byte chunks
8754 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8755 vpbroadcastd(xtmp, xtmp);
8756
8757 subl(count, 16 << shift);
8758 jcc(Assembler::less, L_check_fill_32_bytes);
8759 align(16);
8760
8761 BIND(L_fill_64_bytes_loop);
8762 vmovdqu(Address(to, 0), xtmp);
8763 vmovdqu(Address(to, 32), xtmp);
8764 addptr(to, 64);
8765 subl(count, 16 << shift);
8766 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8767
8768 BIND(L_check_fill_32_bytes);
8769 addl(count, 8 << shift);
8770 jccb(Assembler::less, L_check_fill_8_bytes);
8771 vmovdqu(Address(to, 0), xtmp);
8772 addptr(to, 32);
8773 subl(count, 8 << shift);
8774
8775 BIND(L_check_fill_8_bytes);
8776 // clean upper bits of YMM registers
8777 movdl(xtmp, value);
8778 pshufd(xtmp, xtmp, 0);
8779 } else {
8780 // Fill 32-byte chunks
8781 pshufd(xtmp, xtmp, 0);
8782
8783 subl(count, 8 << shift);
8784 jcc(Assembler::less, L_check_fill_8_bytes);
8785 align(16);
8786
8787 BIND(L_fill_32_bytes_loop);
8788
8789 if (UseUnalignedLoadStores) {
8790 movdqu(Address(to, 0), xtmp);
8791 movdqu(Address(to, 16), xtmp);
8792 } else {
8793 movq(Address(to, 0), xtmp);
8794 movq(Address(to, 8), xtmp);
8795 movq(Address(to, 16), xtmp);
8796 movq(Address(to, 24), xtmp);
8797 }
8798
8799 addptr(to, 32);
8800 subl(count, 8 << shift);
8801 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8802
8803 BIND(L_check_fill_8_bytes);
8804 }
8805 addl(count, 8 << shift);
8806 jccb(Assembler::zero, L_exit);
8807 jmpb(L_fill_8_bytes);
8808
8809 //
8810 // length is too short, just fill qwords
8811 //
8812 BIND(L_fill_8_bytes_loop);
8813 movq(Address(to, 0), xtmp);
8814 addptr(to, 8);
8815 BIND(L_fill_8_bytes);
8816 subl(count, 1 << (shift + 1));
8817 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8818 }
8819 }
8820 // fill trailing 4 bytes
8821 BIND(L_fill_4_bytes);
8822 testl(count, 1<<shift);
8823 jccb(Assembler::zero, L_fill_2_bytes);
8824 movl(Address(to, 0), value);
8825 if (t == T_BYTE || t == T_SHORT) {
8826 addptr(to, 4);
8827 BIND(L_fill_2_bytes);
8828 // fill trailing 2 bytes
8829 testl(count, 1<<(shift-1));
8830 jccb(Assembler::zero, L_fill_byte);
8831 movw(Address(to, 0), value);
8832 if (t == T_BYTE) {
8833 addptr(to, 2);
8834 BIND(L_fill_byte);
8835 // fill trailing byte
8836 testl(count, 1);
8837 jccb(Assembler::zero, L_exit);
8838 movb(Address(to, 0), value);
8839 } else {
8840 BIND(L_fill_byte);
8841 }
8842 } else {
8843 BIND(L_fill_2_bytes);
8844 }
8845 BIND(L_exit);
8846 }
8847
8848 // encode char[] to byte[] in ISO_8859_1
8849 //@HotSpotIntrinsicCandidate
8850 //private static int implEncodeISOArray(byte[] sa, int sp,
8851 //byte[] da, int dp, int len) {
8852 // int i = 0;
8853 // for (; i < len; i++) {
8854 // char c = StringUTF16.getChar(sa, sp++);
8855 // if (c > '\u00FF')
8856 // break;
8857 // da[dp++] = (byte)c;
8858 // }
8859 // return i;
8860 //}
8861 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8862 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8863 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8864 Register tmp5, Register result) {
8865
8866 // rsi: src
8867 // rdi: dst
8868 // rdx: len
8869 // rcx: tmp5
8870 // rax: result
8871 ShortBranchVerifier sbv(this);
8872 assert_different_registers(src, dst, len, tmp5, result);
8873 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8874
8875 // set result
8876 xorl(result, result);
8877 // check for zero length
8878 testl(len, len);
8879 jcc(Assembler::zero, L_done);
8880
8881 movl(result, len);
8882
8883 // Setup pointers
8884 lea(src, Address(src, len, Address::times_2)); // char[]
8885 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8886 negptr(len);
8887
8888 if (UseSSE42Intrinsics || UseAVX >= 2) {
8889 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8890 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8891
8892 if (UseAVX >= 2) {
8893 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8894 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8895 movdl(tmp1Reg, tmp5);
8896 vpbroadcastd(tmp1Reg, tmp1Reg);
8897 jmp(L_chars_32_check);
8898
8899 bind(L_copy_32_chars);
8900 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8901 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8902 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8903 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8904 jccb(Assembler::notZero, L_copy_32_chars_exit);
8905 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8906 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8907 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8908
8909 bind(L_chars_32_check);
8910 addptr(len, 32);
8911 jcc(Assembler::lessEqual, L_copy_32_chars);
8912
8913 bind(L_copy_32_chars_exit);
8914 subptr(len, 16);
8915 jccb(Assembler::greater, L_copy_16_chars_exit);
8916
8917 } else if (UseSSE42Intrinsics) {
8918 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8919 movdl(tmp1Reg, tmp5);
8920 pshufd(tmp1Reg, tmp1Reg, 0);
8921 jmpb(L_chars_16_check);
8922 }
8923
8924 bind(L_copy_16_chars);
8925 if (UseAVX >= 2) {
8926 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8927 vptest(tmp2Reg, tmp1Reg);
8928 jcc(Assembler::notZero, L_copy_16_chars_exit);
8929 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8930 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8931 } else {
8932 if (UseAVX > 0) {
8933 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8934 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8935 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8936 } else {
8937 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8938 por(tmp2Reg, tmp3Reg);
8939 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8940 por(tmp2Reg, tmp4Reg);
8941 }
8942 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8943 jccb(Assembler::notZero, L_copy_16_chars_exit);
8944 packuswb(tmp3Reg, tmp4Reg);
8945 }
8946 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8947
8948 bind(L_chars_16_check);
8949 addptr(len, 16);
8950 jcc(Assembler::lessEqual, L_copy_16_chars);
8951
8952 bind(L_copy_16_chars_exit);
8953 if (UseAVX >= 2) {
8954 // clean upper bits of YMM registers
8955 vpxor(tmp2Reg, tmp2Reg);
8956 vpxor(tmp3Reg, tmp3Reg);
8957 vpxor(tmp4Reg, tmp4Reg);
8958 movdl(tmp1Reg, tmp5);
8959 pshufd(tmp1Reg, tmp1Reg, 0);
8960 }
8961 subptr(len, 8);
8962 jccb(Assembler::greater, L_copy_8_chars_exit);
8963
8964 bind(L_copy_8_chars);
8965 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8966 ptest(tmp3Reg, tmp1Reg);
8967 jccb(Assembler::notZero, L_copy_8_chars_exit);
8968 packuswb(tmp3Reg, tmp1Reg);
8969 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8970 addptr(len, 8);
8971 jccb(Assembler::lessEqual, L_copy_8_chars);
8972
8973 bind(L_copy_8_chars_exit);
8974 subptr(len, 8);
8975 jccb(Assembler::zero, L_done);
8976 }
8977
8978 bind(L_copy_1_char);
8979 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8980 testl(tmp5, 0xff00); // check if Unicode char
8981 jccb(Assembler::notZero, L_copy_1_char_exit);
8982 movb(Address(dst, len, Address::times_1, 0), tmp5);
8983 addptr(len, 1);
8984 jccb(Assembler::less, L_copy_1_char);
8985
8986 bind(L_copy_1_char_exit);
8987 addptr(result, len); // len is negative count of not processed elements
8988
8989 bind(L_done);
8990 }
8991
8992 #ifdef _LP64
8993 /**
8994 * Helper for multiply_to_len().
8995 */
8996 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8997 addq(dest_lo, src1);
8998 adcq(dest_hi, 0);
8999 addq(dest_lo, src2);
9000 adcq(dest_hi, 0);
9001 }
9002
9003 /**
9004 * Multiply 64 bit by 64 bit first loop.
9005 */
9006 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
9007 Register y, Register y_idx, Register z,
9008 Register carry, Register product,
9009 Register idx, Register kdx) {
9010 //
9011 // jlong carry, x[], y[], z[];
9012 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9013 // huge_128 product = y[idx] * x[xstart] + carry;
9014 // z[kdx] = (jlong)product;
9015 // carry = (jlong)(product >>> 64);
9016 // }
9017 // z[xstart] = carry;
9018 //
9019
9020 Label L_first_loop, L_first_loop_exit;
9021 Label L_one_x, L_one_y, L_multiply;
9022
9023 decrementl(xstart);
9024 jcc(Assembler::negative, L_one_x);
9025
9026 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9027 rorq(x_xstart, 32); // convert big-endian to little-endian
9028
9029 bind(L_first_loop);
9030 decrementl(idx);
9031 jcc(Assembler::negative, L_first_loop_exit);
9032 decrementl(idx);
9033 jcc(Assembler::negative, L_one_y);
9034 movq(y_idx, Address(y, idx, Address::times_4, 0));
9035 rorq(y_idx, 32); // convert big-endian to little-endian
9036 bind(L_multiply);
9037 movq(product, x_xstart);
9038 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
9039 addq(product, carry);
9040 adcq(rdx, 0);
9041 subl(kdx, 2);
9042 movl(Address(z, kdx, Address::times_4, 4), product);
9043 shrq(product, 32);
9044 movl(Address(z, kdx, Address::times_4, 0), product);
9045 movq(carry, rdx);
9046 jmp(L_first_loop);
9047
9048 bind(L_one_y);
9049 movl(y_idx, Address(y, 0));
9050 jmp(L_multiply);
9051
9052 bind(L_one_x);
9053 movl(x_xstart, Address(x, 0));
9054 jmp(L_first_loop);
9055
9056 bind(L_first_loop_exit);
9057 }
9058
9059 /**
9060 * Multiply 64 bit by 64 bit and add 128 bit.
9061 */
9062 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
9063 Register yz_idx, Register idx,
9064 Register carry, Register product, int offset) {
9065 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
9066 // z[kdx] = (jlong)product;
9067
9068 movq(yz_idx, Address(y, idx, Address::times_4, offset));
9069 rorq(yz_idx, 32); // convert big-endian to little-endian
9070 movq(product, x_xstart);
9071 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9072 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9073 rorq(yz_idx, 32); // convert big-endian to little-endian
9074
9075 add2_with_carry(rdx, product, carry, yz_idx);
9076
9077 movl(Address(z, idx, Address::times_4, offset+4), product);
9078 shrq(product, 32);
9079 movl(Address(z, idx, Address::times_4, offset), product);
9080
9081 }
9082
9083 /**
9084 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9085 */
9086 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9087 Register yz_idx, Register idx, Register jdx,
9088 Register carry, Register product,
9089 Register carry2) {
9090 // jlong carry, x[], y[], z[];
9091 // int kdx = ystart+1;
9092 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9093 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9094 // z[kdx+idx+1] = (jlong)product;
9095 // jlong carry2 = (jlong)(product >>> 64);
9096 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9097 // z[kdx+idx] = (jlong)product;
9098 // carry = (jlong)(product >>> 64);
9099 // }
9100 // idx += 2;
9101 // if (idx > 0) {
9102 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9103 // z[kdx+idx] = (jlong)product;
9104 // carry = (jlong)(product >>> 64);
9105 // }
9106 //
9107
9108 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9109
9110 movl(jdx, idx);
9111 andl(jdx, 0xFFFFFFFC);
9112 shrl(jdx, 2);
9113
9114 bind(L_third_loop);
9115 subl(jdx, 1);
9116 jcc(Assembler::negative, L_third_loop_exit);
9117 subl(idx, 4);
9118
9119 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9120 movq(carry2, rdx);
9121
9122 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9123 movq(carry, rdx);
9124 jmp(L_third_loop);
9125
9126 bind (L_third_loop_exit);
9127
9128 andl (idx, 0x3);
9129 jcc(Assembler::zero, L_post_third_loop_done);
9130
9131 Label L_check_1;
9132 subl(idx, 2);
9133 jcc(Assembler::negative, L_check_1);
9134
9135 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9136 movq(carry, rdx);
9137
9138 bind (L_check_1);
9139 addl (idx, 0x2);
9140 andl (idx, 0x1);
9141 subl(idx, 1);
9142 jcc(Assembler::negative, L_post_third_loop_done);
9143
9144 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9145 movq(product, x_xstart);
9146 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9147 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9148
9149 add2_with_carry(rdx, product, yz_idx, carry);
9150
9151 movl(Address(z, idx, Address::times_4, 0), product);
9152 shrq(product, 32);
9153
9154 shlq(rdx, 32);
9155 orq(product, rdx);
9156 movq(carry, product);
9157
9158 bind(L_post_third_loop_done);
9159 }
9160
9161 /**
9162 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9163 *
9164 */
9165 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9166 Register carry, Register carry2,
9167 Register idx, Register jdx,
9168 Register yz_idx1, Register yz_idx2,
9169 Register tmp, Register tmp3, Register tmp4) {
9170 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9171
9172 // jlong carry, x[], y[], z[];
9173 // int kdx = ystart+1;
9174 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9175 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9176 // jlong carry2 = (jlong)(tmp3 >>> 64);
9177 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9178 // carry = (jlong)(tmp4 >>> 64);
9179 // z[kdx+idx+1] = (jlong)tmp3;
9180 // z[kdx+idx] = (jlong)tmp4;
9181 // }
9182 // idx += 2;
9183 // if (idx > 0) {
9184 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9185 // z[kdx+idx] = (jlong)yz_idx1;
9186 // carry = (jlong)(yz_idx1 >>> 64);
9187 // }
9188 //
9189
9190 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9191
9192 movl(jdx, idx);
9193 andl(jdx, 0xFFFFFFFC);
9194 shrl(jdx, 2);
9195
9196 bind(L_third_loop);
9197 subl(jdx, 1);
9198 jcc(Assembler::negative, L_third_loop_exit);
9199 subl(idx, 4);
9200
9201 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9202 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9203 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9204 rorxq(yz_idx2, yz_idx2, 32);
9205
9206 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9207 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9208
9209 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9210 rorxq(yz_idx1, yz_idx1, 32);
9211 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9212 rorxq(yz_idx2, yz_idx2, 32);
9213
9214 if (VM_Version::supports_adx()) {
9215 adcxq(tmp3, carry);
9216 adoxq(tmp3, yz_idx1);
9217
9218 adcxq(tmp4, tmp);
9219 adoxq(tmp4, yz_idx2);
9220
9221 movl(carry, 0); // does not affect flags
9222 adcxq(carry2, carry);
9223 adoxq(carry2, carry);
9224 } else {
9225 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9226 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9227 }
9228 movq(carry, carry2);
9229
9230 movl(Address(z, idx, Address::times_4, 12), tmp3);
9231 shrq(tmp3, 32);
9232 movl(Address(z, idx, Address::times_4, 8), tmp3);
9233
9234 movl(Address(z, idx, Address::times_4, 4), tmp4);
9235 shrq(tmp4, 32);
9236 movl(Address(z, idx, Address::times_4, 0), tmp4);
9237
9238 jmp(L_third_loop);
9239
9240 bind (L_third_loop_exit);
9241
9242 andl (idx, 0x3);
9243 jcc(Assembler::zero, L_post_third_loop_done);
9244
9245 Label L_check_1;
9246 subl(idx, 2);
9247 jcc(Assembler::negative, L_check_1);
9248
9249 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9250 rorxq(yz_idx1, yz_idx1, 32);
9251 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9252 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9253 rorxq(yz_idx2, yz_idx2, 32);
9254
9255 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9256
9257 movl(Address(z, idx, Address::times_4, 4), tmp3);
9258 shrq(tmp3, 32);
9259 movl(Address(z, idx, Address::times_4, 0), tmp3);
9260 movq(carry, tmp4);
9261
9262 bind (L_check_1);
9263 addl (idx, 0x2);
9264 andl (idx, 0x1);
9265 subl(idx, 1);
9266 jcc(Assembler::negative, L_post_third_loop_done);
9267 movl(tmp4, Address(y, idx, Address::times_4, 0));
9268 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9269 movl(tmp4, Address(z, idx, Address::times_4, 0));
9270
9271 add2_with_carry(carry2, tmp3, tmp4, carry);
9272
9273 movl(Address(z, idx, Address::times_4, 0), tmp3);
9274 shrq(tmp3, 32);
9275
9276 shlq(carry2, 32);
9277 orq(tmp3, carry2);
9278 movq(carry, tmp3);
9279
9280 bind(L_post_third_loop_done);
9281 }
9282
9283 /**
9284 * Code for BigInteger::multiplyToLen() instrinsic.
9285 *
9286 * rdi: x
9287 * rax: xlen
9288 * rsi: y
9289 * rcx: ylen
9290 * r8: z
9291 * r11: zlen
9292 * r12: tmp1
9293 * r13: tmp2
9294 * r14: tmp3
9295 * r15: tmp4
9296 * rbx: tmp5
9297 *
9298 */
9299 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9300 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9301 ShortBranchVerifier sbv(this);
9302 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9303
9304 push(tmp1);
9305 push(tmp2);
9306 push(tmp3);
9307 push(tmp4);
9308 push(tmp5);
9309
9310 push(xlen);
9311 push(zlen);
9312
9313 const Register idx = tmp1;
9314 const Register kdx = tmp2;
9315 const Register xstart = tmp3;
9316
9317 const Register y_idx = tmp4;
9318 const Register carry = tmp5;
9319 const Register product = xlen;
9320 const Register x_xstart = zlen; // reuse register
9321
9322 // First Loop.
9323 //
9324 // final static long LONG_MASK = 0xffffffffL;
9325 // int xstart = xlen - 1;
9326 // int ystart = ylen - 1;
9327 // long carry = 0;
9328 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9329 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9330 // z[kdx] = (int)product;
9331 // carry = product >>> 32;
9332 // }
9333 // z[xstart] = (int)carry;
9334 //
9335
9336 movl(idx, ylen); // idx = ylen;
9337 movl(kdx, zlen); // kdx = xlen+ylen;
9338 xorq(carry, carry); // carry = 0;
9339
9340 Label L_done;
9341
9342 movl(xstart, xlen);
9343 decrementl(xstart);
9344 jcc(Assembler::negative, L_done);
9345
9346 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9347
9348 Label L_second_loop;
9349 testl(kdx, kdx);
9350 jcc(Assembler::zero, L_second_loop);
9351
9352 Label L_carry;
9353 subl(kdx, 1);
9354 jcc(Assembler::zero, L_carry);
9355
9356 movl(Address(z, kdx, Address::times_4, 0), carry);
9357 shrq(carry, 32);
9358 subl(kdx, 1);
9359
9360 bind(L_carry);
9361 movl(Address(z, kdx, Address::times_4, 0), carry);
9362
9363 // Second and third (nested) loops.
9364 //
9365 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9366 // carry = 0;
9367 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9368 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9369 // (z[k] & LONG_MASK) + carry;
9370 // z[k] = (int)product;
9371 // carry = product >>> 32;
9372 // }
9373 // z[i] = (int)carry;
9374 // }
9375 //
9376 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9377
9378 const Register jdx = tmp1;
9379
9380 bind(L_second_loop);
9381 xorl(carry, carry); // carry = 0;
9382 movl(jdx, ylen); // j = ystart+1
9383
9384 subl(xstart, 1); // i = xstart-1;
9385 jcc(Assembler::negative, L_done);
9386
9387 push (z);
9388
9389 Label L_last_x;
9390 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9391 subl(xstart, 1); // i = xstart-1;
9392 jcc(Assembler::negative, L_last_x);
9393
9394 if (UseBMI2Instructions) {
9395 movq(rdx, Address(x, xstart, Address::times_4, 0));
9396 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9397 } else {
9398 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9399 rorq(x_xstart, 32); // convert big-endian to little-endian
9400 }
9401
9402 Label L_third_loop_prologue;
9403 bind(L_third_loop_prologue);
9404
9405 push (x);
9406 push (xstart);
9407 push (ylen);
9408
9409
9410 if (UseBMI2Instructions) {
9411 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9412 } else { // !UseBMI2Instructions
9413 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9414 }
9415
9416 pop(ylen);
9417 pop(xlen);
9418 pop(x);
9419 pop(z);
9420
9421 movl(tmp3, xlen);
9422 addl(tmp3, 1);
9423 movl(Address(z, tmp3, Address::times_4, 0), carry);
9424 subl(tmp3, 1);
9425 jccb(Assembler::negative, L_done);
9426
9427 shrq(carry, 32);
9428 movl(Address(z, tmp3, Address::times_4, 0), carry);
9429 jmp(L_second_loop);
9430
9431 // Next infrequent code is moved outside loops.
9432 bind(L_last_x);
9433 if (UseBMI2Instructions) {
9434 movl(rdx, Address(x, 0));
9435 } else {
9436 movl(x_xstart, Address(x, 0));
9437 }
9438 jmp(L_third_loop_prologue);
9439
9440 bind(L_done);
9441
9442 pop(zlen);
9443 pop(xlen);
9444
9445 pop(tmp5);
9446 pop(tmp4);
9447 pop(tmp3);
9448 pop(tmp2);
9449 pop(tmp1);
9450 }
9451
9452 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9453 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9454 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9455 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9456 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9457 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9458 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9459 Label SAME_TILL_END, DONE;
9460 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9461
9462 //scale is in rcx in both Win64 and Unix
9463 ShortBranchVerifier sbv(this);
9464
9465 shlq(length);
9466 xorq(result, result);
9467
9468 if ((UseAVX > 2) &&
9469 VM_Version::supports_avx512vlbw()) {
9470 set_vector_masking(); // opening of the stub context for programming mask registers
9471 cmpq(length, 64);
9472 jcc(Assembler::less, VECTOR32_TAIL);
9473 movq(tmp1, length);
9474 andq(tmp1, 0x3F); // tail count
9475 andq(length, ~(0x3F)); //vector count
9476
9477 bind(VECTOR64_LOOP);
9478 // AVX512 code to compare 64 byte vectors.
9479 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9480 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9481 kortestql(k7, k7);
9482 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9483 addq(result, 64);
9484 subq(length, 64);
9485 jccb(Assembler::notZero, VECTOR64_LOOP);
9486
9487 //bind(VECTOR64_TAIL);
9488 testq(tmp1, tmp1);
9489 jcc(Assembler::zero, SAME_TILL_END);
9490
9491 bind(VECTOR64_TAIL);
9492 // AVX512 code to compare upto 63 byte vectors.
9493 // Save k1
9494 kmovql(k3, k1);
9495 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9496 shlxq(tmp2, tmp2, tmp1);
9497 notq(tmp2);
9498 kmovql(k1, tmp2);
9499
9500 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9501 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9502
9503 ktestql(k7, k1);
9504 // Restore k1
9505 kmovql(k1, k3);
9506 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9507
9508 bind(VECTOR64_NOT_EQUAL);
9509 kmovql(tmp1, k7);
9510 notq(tmp1);
9511 tzcntq(tmp1, tmp1);
9512 addq(result, tmp1);
9513 shrq(result);
9514 jmp(DONE);
9515 bind(VECTOR32_TAIL);
9516 clear_vector_masking(); // closing of the stub context for programming mask registers
9517 }
9518
9519 cmpq(length, 8);
9520 jcc(Assembler::equal, VECTOR8_LOOP);
9521 jcc(Assembler::less, VECTOR4_TAIL);
9522
9523 if (UseAVX >= 2) {
9524
9525 cmpq(length, 16);
9526 jcc(Assembler::equal, VECTOR16_LOOP);
9527 jcc(Assembler::less, VECTOR8_LOOP);
9528
9529 cmpq(length, 32);
9530 jccb(Assembler::less, VECTOR16_TAIL);
9531
9532 subq(length, 32);
9533 bind(VECTOR32_LOOP);
9534 vmovdqu(rymm0, Address(obja, result));
9535 vmovdqu(rymm1, Address(objb, result));
9536 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9537 vptest(rymm2, rymm2);
9538 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9539 addq(result, 32);
9540 subq(length, 32);
9541 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9542 addq(length, 32);
9543 jcc(Assembler::equal, SAME_TILL_END);
9544 //falling through if less than 32 bytes left //close the branch here.
9545
9546 bind(VECTOR16_TAIL);
9547 cmpq(length, 16);
9548 jccb(Assembler::less, VECTOR8_TAIL);
9549 bind(VECTOR16_LOOP);
9550 movdqu(rymm0, Address(obja, result));
9551 movdqu(rymm1, Address(objb, result));
9552 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9553 ptest(rymm2, rymm2);
9554 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9555 addq(result, 16);
9556 subq(length, 16);
9557 jcc(Assembler::equal, SAME_TILL_END);
9558 //falling through if less than 16 bytes left
9559 } else {//regular intrinsics
9560
9561 cmpq(length, 16);
9562 jccb(Assembler::less, VECTOR8_TAIL);
9563
9564 subq(length, 16);
9565 bind(VECTOR16_LOOP);
9566 movdqu(rymm0, Address(obja, result));
9567 movdqu(rymm1, Address(objb, result));
9568 pxor(rymm0, rymm1);
9569 ptest(rymm0, rymm0);
9570 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9571 addq(result, 16);
9572 subq(length, 16);
9573 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9574 addq(length, 16);
9575 jcc(Assembler::equal, SAME_TILL_END);
9576 //falling through if less than 16 bytes left
9577 }
9578
9579 bind(VECTOR8_TAIL);
9580 cmpq(length, 8);
9581 jccb(Assembler::less, VECTOR4_TAIL);
9582 bind(VECTOR8_LOOP);
9583 movq(tmp1, Address(obja, result));
9584 movq(tmp2, Address(objb, result));
9585 xorq(tmp1, tmp2);
9586 testq(tmp1, tmp1);
9587 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9588 addq(result, 8);
9589 subq(length, 8);
9590 jcc(Assembler::equal, SAME_TILL_END);
9591 //falling through if less than 8 bytes left
9592
9593 bind(VECTOR4_TAIL);
9594 cmpq(length, 4);
9595 jccb(Assembler::less, BYTES_TAIL);
9596 bind(VECTOR4_LOOP);
9597 movl(tmp1, Address(obja, result));
9598 xorl(tmp1, Address(objb, result));
9599 testl(tmp1, tmp1);
9600 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9601 addq(result, 4);
9602 subq(length, 4);
9603 jcc(Assembler::equal, SAME_TILL_END);
9604 //falling through if less than 4 bytes left
9605
9606 bind(BYTES_TAIL);
9607 bind(BYTES_LOOP);
9608 load_unsigned_byte(tmp1, Address(obja, result));
9609 load_unsigned_byte(tmp2, Address(objb, result));
9610 xorl(tmp1, tmp2);
9611 testl(tmp1, tmp1);
9612 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9613 decq(length);
9614 jccb(Assembler::zero, SAME_TILL_END);
9615 incq(result);
9616 load_unsigned_byte(tmp1, Address(obja, result));
9617 load_unsigned_byte(tmp2, Address(objb, result));
9618 xorl(tmp1, tmp2);
9619 testl(tmp1, tmp1);
9620 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9621 decq(length);
9622 jccb(Assembler::zero, SAME_TILL_END);
9623 incq(result);
9624 load_unsigned_byte(tmp1, Address(obja, result));
9625 load_unsigned_byte(tmp2, Address(objb, result));
9626 xorl(tmp1, tmp2);
9627 testl(tmp1, tmp1);
9628 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9629 jmpb(SAME_TILL_END);
9630
9631 if (UseAVX >= 2) {
9632 bind(VECTOR32_NOT_EQUAL);
9633 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9634 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9635 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9636 vpmovmskb(tmp1, rymm0);
9637 bsfq(tmp1, tmp1);
9638 addq(result, tmp1);
9639 shrq(result);
9640 jmpb(DONE);
9641 }
9642
9643 bind(VECTOR16_NOT_EQUAL);
9644 if (UseAVX >= 2) {
9645 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9646 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9647 pxor(rymm0, rymm2);
9648 } else {
9649 pcmpeqb(rymm2, rymm2);
9650 pxor(rymm0, rymm1);
9651 pcmpeqb(rymm0, rymm1);
9652 pxor(rymm0, rymm2);
9653 }
9654 pmovmskb(tmp1, rymm0);
9655 bsfq(tmp1, tmp1);
9656 addq(result, tmp1);
9657 shrq(result);
9658 jmpb(DONE);
9659
9660 bind(VECTOR8_NOT_EQUAL);
9661 bind(VECTOR4_NOT_EQUAL);
9662 bsfq(tmp1, tmp1);
9663 shrq(tmp1, 3);
9664 addq(result, tmp1);
9665 bind(BYTES_NOT_EQUAL);
9666 shrq(result);
9667 jmpb(DONE);
9668
9669 bind(SAME_TILL_END);
9670 mov64(result, -1);
9671
9672 bind(DONE);
9673 }
9674
9675 //Helper functions for square_to_len()
9676
9677 /**
9678 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9679 * Preserves x and z and modifies rest of the registers.
9680 */
9681 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9682 // Perform square and right shift by 1
9683 // Handle odd xlen case first, then for even xlen do the following
9684 // jlong carry = 0;
9685 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9686 // huge_128 product = x[j:j+1] * x[j:j+1];
9687 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9688 // z[i+2:i+3] = (jlong)(product >>> 1);
9689 // carry = (jlong)product;
9690 // }
9691
9692 xorq(tmp5, tmp5); // carry
9693 xorq(rdxReg, rdxReg);
9694 xorl(tmp1, tmp1); // index for x
9695 xorl(tmp4, tmp4); // index for z
9696
9697 Label L_first_loop, L_first_loop_exit;
9698
9699 testl(xlen, 1);
9700 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9701
9702 // Square and right shift by 1 the odd element using 32 bit multiply
9703 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9704 imulq(raxReg, raxReg);
9705 shrq(raxReg, 1);
9706 adcq(tmp5, 0);
9707 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9708 incrementl(tmp1);
9709 addl(tmp4, 2);
9710
9711 // Square and right shift by 1 the rest using 64 bit multiply
9712 bind(L_first_loop);
9713 cmpptr(tmp1, xlen);
9714 jccb(Assembler::equal, L_first_loop_exit);
9715
9716 // Square
9717 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9718 rorq(raxReg, 32); // convert big-endian to little-endian
9719 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9720
9721 // Right shift by 1 and save carry
9722 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9723 rcrq(rdxReg, 1);
9724 rcrq(raxReg, 1);
9725 adcq(tmp5, 0);
9726
9727 // Store result in z
9728 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9729 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9730
9731 // Update indices for x and z
9732 addl(tmp1, 2);
9733 addl(tmp4, 4);
9734 jmp(L_first_loop);
9735
9736 bind(L_first_loop_exit);
9737 }
9738
9739
9740 /**
9741 * Perform the following multiply add operation using BMI2 instructions
9742 * carry:sum = sum + op1*op2 + carry
9743 * op2 should be in rdx
9744 * op2 is preserved, all other registers are modified
9745 */
9746 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9747 // assert op2 is rdx
9748 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9749 addq(sum, carry);
9750 adcq(tmp2, 0);
9751 addq(sum, op1);
9752 adcq(tmp2, 0);
9753 movq(carry, tmp2);
9754 }
9755
9756 /**
9757 * Perform the following multiply add operation:
9758 * carry:sum = sum + op1*op2 + carry
9759 * Preserves op1, op2 and modifies rest of registers
9760 */
9761 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9762 // rdx:rax = op1 * op2
9763 movq(raxReg, op2);
9764 mulq(op1);
9765
9766 // rdx:rax = sum + carry + rdx:rax
9767 addq(sum, carry);
9768 adcq(rdxReg, 0);
9769 addq(sum, raxReg);
9770 adcq(rdxReg, 0);
9771
9772 // carry:sum = rdx:sum
9773 movq(carry, rdxReg);
9774 }
9775
9776 /**
9777 * Add 64 bit long carry into z[] with carry propogation.
9778 * Preserves z and carry register values and modifies rest of registers.
9779 *
9780 */
9781 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9782 Label L_fourth_loop, L_fourth_loop_exit;
9783
9784 movl(tmp1, 1);
9785 subl(zlen, 2);
9786 addq(Address(z, zlen, Address::times_4, 0), carry);
9787
9788 bind(L_fourth_loop);
9789 jccb(Assembler::carryClear, L_fourth_loop_exit);
9790 subl(zlen, 2);
9791 jccb(Assembler::negative, L_fourth_loop_exit);
9792 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9793 jmp(L_fourth_loop);
9794 bind(L_fourth_loop_exit);
9795 }
9796
9797 /**
9798 * Shift z[] left by 1 bit.
9799 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9800 *
9801 */
9802 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9803
9804 Label L_fifth_loop, L_fifth_loop_exit;
9805
9806 // Fifth loop
9807 // Perform primitiveLeftShift(z, zlen, 1)
9808
9809 const Register prev_carry = tmp1;
9810 const Register new_carry = tmp4;
9811 const Register value = tmp2;
9812 const Register zidx = tmp3;
9813
9814 // int zidx, carry;
9815 // long value;
9816 // carry = 0;
9817 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9818 // (carry:value) = (z[i] << 1) | carry ;
9819 // z[i] = value;
9820 // }
9821
9822 movl(zidx, zlen);
9823 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9824
9825 bind(L_fifth_loop);
9826 decl(zidx); // Use decl to preserve carry flag
9827 decl(zidx);
9828 jccb(Assembler::negative, L_fifth_loop_exit);
9829
9830 if (UseBMI2Instructions) {
9831 movq(value, Address(z, zidx, Address::times_4, 0));
9832 rclq(value, 1);
9833 rorxq(value, value, 32);
9834 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9835 }
9836 else {
9837 // clear new_carry
9838 xorl(new_carry, new_carry);
9839
9840 // Shift z[i] by 1, or in previous carry and save new carry
9841 movq(value, Address(z, zidx, Address::times_4, 0));
9842 shlq(value, 1);
9843 adcl(new_carry, 0);
9844
9845 orq(value, prev_carry);
9846 rorq(value, 0x20);
9847 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9848
9849 // Set previous carry = new carry
9850 movl(prev_carry, new_carry);
9851 }
9852 jmp(L_fifth_loop);
9853
9854 bind(L_fifth_loop_exit);
9855 }
9856
9857
9858 /**
9859 * Code for BigInteger::squareToLen() intrinsic
9860 *
9861 * rdi: x
9862 * rsi: len
9863 * r8: z
9864 * rcx: zlen
9865 * r12: tmp1
9866 * r13: tmp2
9867 * r14: tmp3
9868 * r15: tmp4
9869 * rbx: tmp5
9870 *
9871 */
9872 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9873
9874 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9875 push(tmp1);
9876 push(tmp2);
9877 push(tmp3);
9878 push(tmp4);
9879 push(tmp5);
9880
9881 // First loop
9882 // Store the squares, right shifted one bit (i.e., divided by 2).
9883 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9884
9885 // Add in off-diagonal sums.
9886 //
9887 // Second, third (nested) and fourth loops.
9888 // zlen +=2;
9889 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9890 // carry = 0;
9891 // long op2 = x[xidx:xidx+1];
9892 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9893 // k -= 2;
9894 // long op1 = x[j:j+1];
9895 // long sum = z[k:k+1];
9896 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9897 // z[k:k+1] = sum;
9898 // }
9899 // add_one_64(z, k, carry, tmp_regs);
9900 // }
9901
9902 const Register carry = tmp5;
9903 const Register sum = tmp3;
9904 const Register op1 = tmp4;
9905 Register op2 = tmp2;
9906
9907 push(zlen);
9908 push(len);
9909 addl(zlen,2);
9910 bind(L_second_loop);
9911 xorq(carry, carry);
9912 subl(zlen, 4);
9913 subl(len, 2);
9914 push(zlen);
9915 push(len);
9916 cmpl(len, 0);
9917 jccb(Assembler::lessEqual, L_second_loop_exit);
9918
9919 // Multiply an array by one 64 bit long.
9920 if (UseBMI2Instructions) {
9921 op2 = rdxReg;
9922 movq(op2, Address(x, len, Address::times_4, 0));
9923 rorxq(op2, op2, 32);
9924 }
9925 else {
9926 movq(op2, Address(x, len, Address::times_4, 0));
9927 rorq(op2, 32);
9928 }
9929
9930 bind(L_third_loop);
9931 decrementl(len);
9932 jccb(Assembler::negative, L_third_loop_exit);
9933 decrementl(len);
9934 jccb(Assembler::negative, L_last_x);
9935
9936 movq(op1, Address(x, len, Address::times_4, 0));
9937 rorq(op1, 32);
9938
9939 bind(L_multiply);
9940 subl(zlen, 2);
9941 movq(sum, Address(z, zlen, Address::times_4, 0));
9942
9943 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9944 if (UseBMI2Instructions) {
9945 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9946 }
9947 else {
9948 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9949 }
9950
9951 movq(Address(z, zlen, Address::times_4, 0), sum);
9952
9953 jmp(L_third_loop);
9954 bind(L_third_loop_exit);
9955
9956 // Fourth loop
9957 // Add 64 bit long carry into z with carry propogation.
9958 // Uses offsetted zlen.
9959 add_one_64(z, zlen, carry, tmp1);
9960
9961 pop(len);
9962 pop(zlen);
9963 jmp(L_second_loop);
9964
9965 // Next infrequent code is moved outside loops.
9966 bind(L_last_x);
9967 movl(op1, Address(x, 0));
9968 jmp(L_multiply);
9969
9970 bind(L_second_loop_exit);
9971 pop(len);
9972 pop(zlen);
9973 pop(len);
9974 pop(zlen);
9975
9976 // Fifth loop
9977 // Shift z left 1 bit.
9978 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9979
9980 // z[zlen-1] |= x[len-1] & 1;
9981 movl(tmp3, Address(x, len, Address::times_4, -4));
9982 andl(tmp3, 1);
9983 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9984
9985 pop(tmp5);
9986 pop(tmp4);
9987 pop(tmp3);
9988 pop(tmp2);
9989 pop(tmp1);
9990 }
9991
9992 /**
9993 * Helper function for mul_add()
9994 * Multiply the in[] by int k and add to out[] starting at offset offs using
9995 * 128 bit by 32 bit multiply and return the carry in tmp5.
9996 * Only quad int aligned length of in[] is operated on in this function.
9997 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9998 * This function preserves out, in and k registers.
9999 * len and offset point to the appropriate index in "in" & "out" correspondingly
10000 * tmp5 has the carry.
10001 * other registers are temporary and are modified.
10002 *
10003 */
10004 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
10005 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
10006 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10007
10008 Label L_first_loop, L_first_loop_exit;
10009
10010 movl(tmp1, len);
10011 shrl(tmp1, 2);
10012
10013 bind(L_first_loop);
10014 subl(tmp1, 1);
10015 jccb(Assembler::negative, L_first_loop_exit);
10016
10017 subl(len, 4);
10018 subl(offset, 4);
10019
10020 Register op2 = tmp2;
10021 const Register sum = tmp3;
10022 const Register op1 = tmp4;
10023 const Register carry = tmp5;
10024
10025 if (UseBMI2Instructions) {
10026 op2 = rdxReg;
10027 }
10028
10029 movq(op1, Address(in, len, Address::times_4, 8));
10030 rorq(op1, 32);
10031 movq(sum, Address(out, offset, Address::times_4, 8));
10032 rorq(sum, 32);
10033 if (UseBMI2Instructions) {
10034 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10035 }
10036 else {
10037 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10038 }
10039 // Store back in big endian from little endian
10040 rorq(sum, 0x20);
10041 movq(Address(out, offset, Address::times_4, 8), sum);
10042
10043 movq(op1, Address(in, len, Address::times_4, 0));
10044 rorq(op1, 32);
10045 movq(sum, Address(out, offset, Address::times_4, 0));
10046 rorq(sum, 32);
10047 if (UseBMI2Instructions) {
10048 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10049 }
10050 else {
10051 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10052 }
10053 // Store back in big endian from little endian
10054 rorq(sum, 0x20);
10055 movq(Address(out, offset, Address::times_4, 0), sum);
10056
10057 jmp(L_first_loop);
10058 bind(L_first_loop_exit);
10059 }
10060
10061 /**
10062 * Code for BigInteger::mulAdd() intrinsic
10063 *
10064 * rdi: out
10065 * rsi: in
10066 * r11: offs (out.length - offset)
10067 * rcx: len
10068 * r8: k
10069 * r12: tmp1
10070 * r13: tmp2
10071 * r14: tmp3
10072 * r15: tmp4
10073 * rbx: tmp5
10074 * Multiply the in[] by word k and add to out[], return the carry in rax
10075 */
10076 void MacroAssembler::mul_add(Register out, Register in, Register offs,
10077 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
10078 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10079
10080 Label L_carry, L_last_in, L_done;
10081
10082 // carry = 0;
10083 // for (int j=len-1; j >= 0; j--) {
10084 // long product = (in[j] & LONG_MASK) * kLong +
10085 // (out[offs] & LONG_MASK) + carry;
10086 // out[offs--] = (int)product;
10087 // carry = product >>> 32;
10088 // }
10089 //
10090 push(tmp1);
10091 push(tmp2);
10092 push(tmp3);
10093 push(tmp4);
10094 push(tmp5);
10095
10096 Register op2 = tmp2;
10097 const Register sum = tmp3;
10098 const Register op1 = tmp4;
10099 const Register carry = tmp5;
10100
10101 if (UseBMI2Instructions) {
10102 op2 = rdxReg;
10103 movl(op2, k);
10104 }
10105 else {
10106 movl(op2, k);
10107 }
10108
10109 xorq(carry, carry);
10110
10111 //First loop
10112
10113 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10114 //The carry is in tmp5
10115 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10116
10117 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10118 decrementl(len);
10119 jccb(Assembler::negative, L_carry);
10120 decrementl(len);
10121 jccb(Assembler::negative, L_last_in);
10122
10123 movq(op1, Address(in, len, Address::times_4, 0));
10124 rorq(op1, 32);
10125
10126 subl(offs, 2);
10127 movq(sum, Address(out, offs, Address::times_4, 0));
10128 rorq(sum, 32);
10129
10130 if (UseBMI2Instructions) {
10131 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10132 }
10133 else {
10134 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10135 }
10136
10137 // Store back in big endian from little endian
10138 rorq(sum, 0x20);
10139 movq(Address(out, offs, Address::times_4, 0), sum);
10140
10141 testl(len, len);
10142 jccb(Assembler::zero, L_carry);
10143
10144 //Multiply the last in[] entry, if any
10145 bind(L_last_in);
10146 movl(op1, Address(in, 0));
10147 movl(sum, Address(out, offs, Address::times_4, -4));
10148
10149 movl(raxReg, k);
10150 mull(op1); //tmp4 * eax -> edx:eax
10151 addl(sum, carry);
10152 adcl(rdxReg, 0);
10153 addl(sum, raxReg);
10154 adcl(rdxReg, 0);
10155 movl(carry, rdxReg);
10156
10157 movl(Address(out, offs, Address::times_4, -4), sum);
10158
10159 bind(L_carry);
10160 //return tmp5/carry as carry in rax
10161 movl(rax, carry);
10162
10163 bind(L_done);
10164 pop(tmp5);
10165 pop(tmp4);
10166 pop(tmp3);
10167 pop(tmp2);
10168 pop(tmp1);
10169 }
10170 #endif
10171
10172 /**
10173 * Emits code to update CRC-32 with a byte value according to constants in table
10174 *
10175 * @param [in,out]crc Register containing the crc.
10176 * @param [in]val Register containing the byte to fold into the CRC.
10177 * @param [in]table Register containing the table of crc constants.
10178 *
10179 * uint32_t crc;
10180 * val = crc_table[(val ^ crc) & 0xFF];
10181 * crc = val ^ (crc >> 8);
10182 *
10183 */
10184 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10185 xorl(val, crc);
10186 andl(val, 0xFF);
10187 shrl(crc, 8); // unsigned shift
10188 xorl(crc, Address(table, val, Address::times_4, 0));
10189 }
10190
10191 /**
10192 * Fold 128-bit data chunk
10193 */
10194 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10195 if (UseAVX > 0) {
10196 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10197 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10198 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10199 pxor(xcrc, xtmp);
10200 } else {
10201 movdqa(xtmp, xcrc);
10202 pclmulhdq(xtmp, xK); // [123:64]
10203 pclmulldq(xcrc, xK); // [63:0]
10204 pxor(xcrc, xtmp);
10205 movdqu(xtmp, Address(buf, offset));
10206 pxor(xcrc, xtmp);
10207 }
10208 }
10209
10210 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10211 if (UseAVX > 0) {
10212 vpclmulhdq(xtmp, xK, xcrc);
10213 vpclmulldq(xcrc, xK, xcrc);
10214 pxor(xcrc, xbuf);
10215 pxor(xcrc, xtmp);
10216 } else {
10217 movdqa(xtmp, xcrc);
10218 pclmulhdq(xtmp, xK);
10219 pclmulldq(xcrc, xK);
10220 pxor(xcrc, xbuf);
10221 pxor(xcrc, xtmp);
10222 }
10223 }
10224
10225 /**
10226 * 8-bit folds to compute 32-bit CRC
10227 *
10228 * uint64_t xcrc;
10229 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10230 */
10231 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10232 movdl(tmp, xcrc);
10233 andl(tmp, 0xFF);
10234 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10235 psrldq(xcrc, 1); // unsigned shift one byte
10236 pxor(xcrc, xtmp);
10237 }
10238
10239 /**
10240 * uint32_t crc;
10241 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10242 */
10243 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10244 movl(tmp, crc);
10245 andl(tmp, 0xFF);
10246 shrl(crc, 8);
10247 xorl(crc, Address(table, tmp, Address::times_4, 0));
10248 }
10249
10250 /**
10251 * @param crc register containing existing CRC (32-bit)
10252 * @param buf register pointing to input byte buffer (byte*)
10253 * @param len register containing number of bytes
10254 * @param table register that will contain address of CRC table
10255 * @param tmp scratch register
10256 */
10257 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10258 assert_different_registers(crc, buf, len, table, tmp, rax);
10259
10260 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10261 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10262
10263 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10264 // context for the registers used, where all instructions below are using 128-bit mode
10265 // On EVEX without VL and BW, these instructions will all be AVX.
10266 if (VM_Version::supports_avx512vlbw()) {
10267 movl(tmp, 0xffff);
10268 kmovwl(k1, tmp);
10269 }
10270
10271 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10272 notl(crc); // ~crc
10273 cmpl(len, 16);
10274 jcc(Assembler::less, L_tail);
10275
10276 // Align buffer to 16 bytes
10277 movl(tmp, buf);
10278 andl(tmp, 0xF);
10279 jccb(Assembler::zero, L_aligned);
10280 subl(tmp, 16);
10281 addl(len, tmp);
10282
10283 align(4);
10284 BIND(L_align_loop);
10285 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10286 update_byte_crc32(crc, rax, table);
10287 increment(buf);
10288 incrementl(tmp);
10289 jccb(Assembler::less, L_align_loop);
10290
10291 BIND(L_aligned);
10292 movl(tmp, len); // save
10293 shrl(len, 4);
10294 jcc(Assembler::zero, L_tail_restore);
10295
10296 // Fold crc into first bytes of vector
10297 movdqa(xmm1, Address(buf, 0));
10298 movdl(rax, xmm1);
10299 xorl(crc, rax);
10300 if (VM_Version::supports_sse4_1()) {
10301 pinsrd(xmm1, crc, 0);
10302 } else {
10303 pinsrw(xmm1, crc, 0);
10304 shrl(crc, 16);
10305 pinsrw(xmm1, crc, 1);
10306 }
10307 addptr(buf, 16);
10308 subl(len, 4); // len > 0
10309 jcc(Assembler::less, L_fold_tail);
10310
10311 movdqa(xmm2, Address(buf, 0));
10312 movdqa(xmm3, Address(buf, 16));
10313 movdqa(xmm4, Address(buf, 32));
10314 addptr(buf, 48);
10315 subl(len, 3);
10316 jcc(Assembler::lessEqual, L_fold_512b);
10317
10318 // Fold total 512 bits of polynomial on each iteration,
10319 // 128 bits per each of 4 parallel streams.
10320 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10321
10322 align(32);
10323 BIND(L_fold_512b_loop);
10324 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10325 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10326 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10327 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10328 addptr(buf, 64);
10329 subl(len, 4);
10330 jcc(Assembler::greater, L_fold_512b_loop);
10331
10332 // Fold 512 bits to 128 bits.
10333 BIND(L_fold_512b);
10334 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10335 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10336 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10337 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10338
10339 // Fold the rest of 128 bits data chunks
10340 BIND(L_fold_tail);
10341 addl(len, 3);
10342 jccb(Assembler::lessEqual, L_fold_128b);
10343 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10344
10345 BIND(L_fold_tail_loop);
10346 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10347 addptr(buf, 16);
10348 decrementl(len);
10349 jccb(Assembler::greater, L_fold_tail_loop);
10350
10351 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10352 BIND(L_fold_128b);
10353 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10354 if (UseAVX > 0) {
10355 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10356 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10357 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10358 } else {
10359 movdqa(xmm2, xmm0);
10360 pclmulqdq(xmm2, xmm1, 0x1);
10361 movdqa(xmm3, xmm0);
10362 pand(xmm3, xmm2);
10363 pclmulqdq(xmm0, xmm3, 0x1);
10364 }
10365 psrldq(xmm1, 8);
10366 psrldq(xmm2, 4);
10367 pxor(xmm0, xmm1);
10368 pxor(xmm0, xmm2);
10369
10370 // 8 8-bit folds to compute 32-bit CRC.
10371 for (int j = 0; j < 4; j++) {
10372 fold_8bit_crc32(xmm0, table, xmm1, rax);
10373 }
10374 movdl(crc, xmm0); // mov 32 bits to general register
10375 for (int j = 0; j < 4; j++) {
10376 fold_8bit_crc32(crc, table, rax);
10377 }
10378
10379 BIND(L_tail_restore);
10380 movl(len, tmp); // restore
10381 BIND(L_tail);
10382 andl(len, 0xf);
10383 jccb(Assembler::zero, L_exit);
10384
10385 // Fold the rest of bytes
10386 align(4);
10387 BIND(L_tail_loop);
10388 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10389 update_byte_crc32(crc, rax, table);
10390 increment(buf);
10391 decrementl(len);
10392 jccb(Assembler::greater, L_tail_loop);
10393
10394 BIND(L_exit);
10395 notl(crc); // ~c
10396 }
10397
10398 #ifdef _LP64
10399 // S. Gueron / Information Processing Letters 112 (2012) 184
10400 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10401 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10402 // Output: the 64-bit carry-less product of B * CONST
10403 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10404 Register tmp1, Register tmp2, Register tmp3) {
10405 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10406 if (n > 0) {
10407 addq(tmp3, n * 256 * 8);
10408 }
10409 // Q1 = TABLEExt[n][B & 0xFF];
10410 movl(tmp1, in);
10411 andl(tmp1, 0x000000FF);
10412 shll(tmp1, 3);
10413 addq(tmp1, tmp3);
10414 movq(tmp1, Address(tmp1, 0));
10415
10416 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10417 movl(tmp2, in);
10418 shrl(tmp2, 8);
10419 andl(tmp2, 0x000000FF);
10420 shll(tmp2, 3);
10421 addq(tmp2, tmp3);
10422 movq(tmp2, Address(tmp2, 0));
10423
10424 shlq(tmp2, 8);
10425 xorq(tmp1, tmp2);
10426
10427 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10428 movl(tmp2, in);
10429 shrl(tmp2, 16);
10430 andl(tmp2, 0x000000FF);
10431 shll(tmp2, 3);
10432 addq(tmp2, tmp3);
10433 movq(tmp2, Address(tmp2, 0));
10434
10435 shlq(tmp2, 16);
10436 xorq(tmp1, tmp2);
10437
10438 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10439 shrl(in, 24);
10440 andl(in, 0x000000FF);
10441 shll(in, 3);
10442 addq(in, tmp3);
10443 movq(in, Address(in, 0));
10444
10445 shlq(in, 24);
10446 xorq(in, tmp1);
10447 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10448 }
10449
10450 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10451 Register in_out,
10452 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10453 XMMRegister w_xtmp2,
10454 Register tmp1,
10455 Register n_tmp2, Register n_tmp3) {
10456 if (is_pclmulqdq_supported) {
10457 movdl(w_xtmp1, in_out); // modified blindly
10458
10459 movl(tmp1, const_or_pre_comp_const_index);
10460 movdl(w_xtmp2, tmp1);
10461 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10462
10463 movdq(in_out, w_xtmp1);
10464 } else {
10465 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10466 }
10467 }
10468
10469 // Recombination Alternative 2: No bit-reflections
10470 // T1 = (CRC_A * U1) << 1
10471 // T2 = (CRC_B * U2) << 1
10472 // C1 = T1 >> 32
10473 // C2 = T2 >> 32
10474 // T1 = T1 & 0xFFFFFFFF
10475 // T2 = T2 & 0xFFFFFFFF
10476 // T1 = CRC32(0, T1)
10477 // T2 = CRC32(0, T2)
10478 // C1 = C1 ^ T1
10479 // C2 = C2 ^ T2
10480 // CRC = C1 ^ C2 ^ CRC_C
10481 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10482 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10483 Register tmp1, Register tmp2,
10484 Register n_tmp3) {
10485 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10486 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10487 shlq(in_out, 1);
10488 movl(tmp1, in_out);
10489 shrq(in_out, 32);
10490 xorl(tmp2, tmp2);
10491 crc32(tmp2, tmp1, 4);
10492 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10493 shlq(in1, 1);
10494 movl(tmp1, in1);
10495 shrq(in1, 32);
10496 xorl(tmp2, tmp2);
10497 crc32(tmp2, tmp1, 4);
10498 xorl(in1, tmp2);
10499 xorl(in_out, in1);
10500 xorl(in_out, in2);
10501 }
10502
10503 // Set N to predefined value
10504 // Subtract from a lenght of a buffer
10505 // execute in a loop:
10506 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10507 // for i = 1 to N do
10508 // CRC_A = CRC32(CRC_A, A[i])
10509 // CRC_B = CRC32(CRC_B, B[i])
10510 // CRC_C = CRC32(CRC_C, C[i])
10511 // end for
10512 // Recombine
10513 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10514 Register in_out1, Register in_out2, Register in_out3,
10515 Register tmp1, Register tmp2, Register tmp3,
10516 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10517 Register tmp4, Register tmp5,
10518 Register n_tmp6) {
10519 Label L_processPartitions;
10520 Label L_processPartition;
10521 Label L_exit;
10522
10523 bind(L_processPartitions);
10524 cmpl(in_out1, 3 * size);
10525 jcc(Assembler::less, L_exit);
10526 xorl(tmp1, tmp1);
10527 xorl(tmp2, tmp2);
10528 movq(tmp3, in_out2);
10529 addq(tmp3, size);
10530
10531 bind(L_processPartition);
10532 crc32(in_out3, Address(in_out2, 0), 8);
10533 crc32(tmp1, Address(in_out2, size), 8);
10534 crc32(tmp2, Address(in_out2, size * 2), 8);
10535 addq(in_out2, 8);
10536 cmpq(in_out2, tmp3);
10537 jcc(Assembler::less, L_processPartition);
10538 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10539 w_xtmp1, w_xtmp2, w_xtmp3,
10540 tmp4, tmp5,
10541 n_tmp6);
10542 addq(in_out2, 2 * size);
10543 subl(in_out1, 3 * size);
10544 jmp(L_processPartitions);
10545
10546 bind(L_exit);
10547 }
10548 #else
10549 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10550 Register tmp1, Register tmp2, Register tmp3,
10551 XMMRegister xtmp1, XMMRegister xtmp2) {
10552 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10553 if (n > 0) {
10554 addl(tmp3, n * 256 * 8);
10555 }
10556 // Q1 = TABLEExt[n][B & 0xFF];
10557 movl(tmp1, in_out);
10558 andl(tmp1, 0x000000FF);
10559 shll(tmp1, 3);
10560 addl(tmp1, tmp3);
10561 movq(xtmp1, Address(tmp1, 0));
10562
10563 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10564 movl(tmp2, in_out);
10565 shrl(tmp2, 8);
10566 andl(tmp2, 0x000000FF);
10567 shll(tmp2, 3);
10568 addl(tmp2, tmp3);
10569 movq(xtmp2, Address(tmp2, 0));
10570
10571 psllq(xtmp2, 8);
10572 pxor(xtmp1, xtmp2);
10573
10574 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10575 movl(tmp2, in_out);
10576 shrl(tmp2, 16);
10577 andl(tmp2, 0x000000FF);
10578 shll(tmp2, 3);
10579 addl(tmp2, tmp3);
10580 movq(xtmp2, Address(tmp2, 0));
10581
10582 psllq(xtmp2, 16);
10583 pxor(xtmp1, xtmp2);
10584
10585 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10586 shrl(in_out, 24);
10587 andl(in_out, 0x000000FF);
10588 shll(in_out, 3);
10589 addl(in_out, tmp3);
10590 movq(xtmp2, Address(in_out, 0));
10591
10592 psllq(xtmp2, 24);
10593 pxor(xtmp1, xtmp2); // Result in CXMM
10594 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10595 }
10596
10597 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10598 Register in_out,
10599 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10600 XMMRegister w_xtmp2,
10601 Register tmp1,
10602 Register n_tmp2, Register n_tmp3) {
10603 if (is_pclmulqdq_supported) {
10604 movdl(w_xtmp1, in_out);
10605
10606 movl(tmp1, const_or_pre_comp_const_index);
10607 movdl(w_xtmp2, tmp1);
10608 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10609 // Keep result in XMM since GPR is 32 bit in length
10610 } else {
10611 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10612 }
10613 }
10614
10615 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10616 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10617 Register tmp1, Register tmp2,
10618 Register n_tmp3) {
10619 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10620 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10621
10622 psllq(w_xtmp1, 1);
10623 movdl(tmp1, w_xtmp1);
10624 psrlq(w_xtmp1, 32);
10625 movdl(in_out, w_xtmp1);
10626
10627 xorl(tmp2, tmp2);
10628 crc32(tmp2, tmp1, 4);
10629 xorl(in_out, tmp2);
10630
10631 psllq(w_xtmp2, 1);
10632 movdl(tmp1, w_xtmp2);
10633 psrlq(w_xtmp2, 32);
10634 movdl(in1, w_xtmp2);
10635
10636 xorl(tmp2, tmp2);
10637 crc32(tmp2, tmp1, 4);
10638 xorl(in1, tmp2);
10639 xorl(in_out, in1);
10640 xorl(in_out, in2);
10641 }
10642
10643 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10644 Register in_out1, Register in_out2, Register in_out3,
10645 Register tmp1, Register tmp2, Register tmp3,
10646 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10647 Register tmp4, Register tmp5,
10648 Register n_tmp6) {
10649 Label L_processPartitions;
10650 Label L_processPartition;
10651 Label L_exit;
10652
10653 bind(L_processPartitions);
10654 cmpl(in_out1, 3 * size);
10655 jcc(Assembler::less, L_exit);
10656 xorl(tmp1, tmp1);
10657 xorl(tmp2, tmp2);
10658 movl(tmp3, in_out2);
10659 addl(tmp3, size);
10660
10661 bind(L_processPartition);
10662 crc32(in_out3, Address(in_out2, 0), 4);
10663 crc32(tmp1, Address(in_out2, size), 4);
10664 crc32(tmp2, Address(in_out2, size*2), 4);
10665 crc32(in_out3, Address(in_out2, 0+4), 4);
10666 crc32(tmp1, Address(in_out2, size+4), 4);
10667 crc32(tmp2, Address(in_out2, size*2+4), 4);
10668 addl(in_out2, 8);
10669 cmpl(in_out2, tmp3);
10670 jcc(Assembler::less, L_processPartition);
10671
10672 push(tmp3);
10673 push(in_out1);
10674 push(in_out2);
10675 tmp4 = tmp3;
10676 tmp5 = in_out1;
10677 n_tmp6 = in_out2;
10678
10679 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10680 w_xtmp1, w_xtmp2, w_xtmp3,
10681 tmp4, tmp5,
10682 n_tmp6);
10683
10684 pop(in_out2);
10685 pop(in_out1);
10686 pop(tmp3);
10687
10688 addl(in_out2, 2 * size);
10689 subl(in_out1, 3 * size);
10690 jmp(L_processPartitions);
10691
10692 bind(L_exit);
10693 }
10694 #endif //LP64
10695
10696 #ifdef _LP64
10697 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10698 // Input: A buffer I of L bytes.
10699 // Output: the CRC32C value of the buffer.
10700 // Notations:
10701 // Write L = 24N + r, with N = floor (L/24).
10702 // r = L mod 24 (0 <= r < 24).
10703 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10704 // N quadwords, and R consists of r bytes.
10705 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10706 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10707 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10708 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10709 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10710 Register tmp1, Register tmp2, Register tmp3,
10711 Register tmp4, Register tmp5, Register tmp6,
10712 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10713 bool is_pclmulqdq_supported) {
10714 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10715 Label L_wordByWord;
10716 Label L_byteByByteProlog;
10717 Label L_byteByByte;
10718 Label L_exit;
10719
10720 if (is_pclmulqdq_supported ) {
10721 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10722 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10723
10724 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10725 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10726
10727 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10728 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10729 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10730 } else {
10731 const_or_pre_comp_const_index[0] = 1;
10732 const_or_pre_comp_const_index[1] = 0;
10733
10734 const_or_pre_comp_const_index[2] = 3;
10735 const_or_pre_comp_const_index[3] = 2;
10736
10737 const_or_pre_comp_const_index[4] = 5;
10738 const_or_pre_comp_const_index[5] = 4;
10739 }
10740 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10741 in2, in1, in_out,
10742 tmp1, tmp2, tmp3,
10743 w_xtmp1, w_xtmp2, w_xtmp3,
10744 tmp4, tmp5,
10745 tmp6);
10746 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10747 in2, in1, in_out,
10748 tmp1, tmp2, tmp3,
10749 w_xtmp1, w_xtmp2, w_xtmp3,
10750 tmp4, tmp5,
10751 tmp6);
10752 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10753 in2, in1, in_out,
10754 tmp1, tmp2, tmp3,
10755 w_xtmp1, w_xtmp2, w_xtmp3,
10756 tmp4, tmp5,
10757 tmp6);
10758 movl(tmp1, in2);
10759 andl(tmp1, 0x00000007);
10760 negl(tmp1);
10761 addl(tmp1, in2);
10762 addq(tmp1, in1);
10763
10764 BIND(L_wordByWord);
10765 cmpq(in1, tmp1);
10766 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10767 crc32(in_out, Address(in1, 0), 4);
10768 addq(in1, 4);
10769 jmp(L_wordByWord);
10770
10771 BIND(L_byteByByteProlog);
10772 andl(in2, 0x00000007);
10773 movl(tmp2, 1);
10774
10775 BIND(L_byteByByte);
10776 cmpl(tmp2, in2);
10777 jccb(Assembler::greater, L_exit);
10778 crc32(in_out, Address(in1, 0), 1);
10779 incq(in1);
10780 incl(tmp2);
10781 jmp(L_byteByByte);
10782
10783 BIND(L_exit);
10784 }
10785 #else
10786 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10787 Register tmp1, Register tmp2, Register tmp3,
10788 Register tmp4, Register tmp5, Register tmp6,
10789 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10790 bool is_pclmulqdq_supported) {
10791 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10792 Label L_wordByWord;
10793 Label L_byteByByteProlog;
10794 Label L_byteByByte;
10795 Label L_exit;
10796
10797 if (is_pclmulqdq_supported) {
10798 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10799 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10800
10801 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10802 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10803
10804 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10805 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10806 } else {
10807 const_or_pre_comp_const_index[0] = 1;
10808 const_or_pre_comp_const_index[1] = 0;
10809
10810 const_or_pre_comp_const_index[2] = 3;
10811 const_or_pre_comp_const_index[3] = 2;
10812
10813 const_or_pre_comp_const_index[4] = 5;
10814 const_or_pre_comp_const_index[5] = 4;
10815 }
10816 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10817 in2, in1, in_out,
10818 tmp1, tmp2, tmp3,
10819 w_xtmp1, w_xtmp2, w_xtmp3,
10820 tmp4, tmp5,
10821 tmp6);
10822 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10823 in2, in1, in_out,
10824 tmp1, tmp2, tmp3,
10825 w_xtmp1, w_xtmp2, w_xtmp3,
10826 tmp4, tmp5,
10827 tmp6);
10828 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10829 in2, in1, in_out,
10830 tmp1, tmp2, tmp3,
10831 w_xtmp1, w_xtmp2, w_xtmp3,
10832 tmp4, tmp5,
10833 tmp6);
10834 movl(tmp1, in2);
10835 andl(tmp1, 0x00000007);
10836 negl(tmp1);
10837 addl(tmp1, in2);
10838 addl(tmp1, in1);
10839
10840 BIND(L_wordByWord);
10841 cmpl(in1, tmp1);
10842 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10843 crc32(in_out, Address(in1,0), 4);
10844 addl(in1, 4);
10845 jmp(L_wordByWord);
10846
10847 BIND(L_byteByByteProlog);
10848 andl(in2, 0x00000007);
10849 movl(tmp2, 1);
10850
10851 BIND(L_byteByByte);
10852 cmpl(tmp2, in2);
10853 jccb(Assembler::greater, L_exit);
10854 movb(tmp1, Address(in1, 0));
10855 crc32(in_out, tmp1, 1);
10856 incl(in1);
10857 incl(tmp2);
10858 jmp(L_byteByByte);
10859
10860 BIND(L_exit);
10861 }
10862 #endif // LP64
10863 #undef BIND
10864 #undef BLOCK_COMMENT
10865
10866 // Compress char[] array to byte[].
10867 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10868 // @HotSpotIntrinsicCandidate
10869 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10870 // for (int i = 0; i < len; i++) {
10871 // int c = src[srcOff++];
10872 // if (c >>> 8 != 0) {
10873 // return 0;
10874 // }
10875 // dst[dstOff++] = (byte)c;
10876 // }
10877 // return len;
10878 // }
10879 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10880 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10881 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10882 Register tmp5, Register result) {
10883 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10884
10885 // rsi: src
10886 // rdi: dst
10887 // rdx: len
10888 // rcx: tmp5
10889 // rax: result
10890
10891 // rsi holds start addr of source char[] to be compressed
10892 // rdi holds start addr of destination byte[]
10893 // rdx holds length
10894
10895 assert(len != result, "");
10896
10897 // save length for return
10898 push(len);
10899
10900 if ((UseAVX > 2) && // AVX512
10901 VM_Version::supports_avx512vlbw() &&
10902 VM_Version::supports_bmi2()) {
10903
10904 set_vector_masking(); // opening of the stub context for programming mask registers
10905
10906 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10907
10908 // alignement
10909 Label post_alignement;
10910
10911 // if length of the string is less than 16, handle it in an old fashioned
10912 // way
10913 testl(len, -32);
10914 jcc(Assembler::zero, below_threshold);
10915
10916 // First check whether a character is compressable ( <= 0xFF).
10917 // Create mask to test for Unicode chars inside zmm vector
10918 movl(result, 0x00FF);
10919 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10920
10921 // Save k1
10922 kmovql(k3, k1);
10923
10924 testl(len, -64);
10925 jcc(Assembler::zero, post_alignement);
10926
10927 movl(tmp5, dst);
10928 andl(tmp5, (32 - 1));
10929 negl(tmp5);
10930 andl(tmp5, (32 - 1));
10931
10932 // bail out when there is nothing to be done
10933 testl(tmp5, 0xFFFFFFFF);
10934 jcc(Assembler::zero, post_alignement);
10935
10936 // ~(~0 << len), where len is the # of remaining elements to process
10937 movl(result, 0xFFFFFFFF);
10938 shlxl(result, result, tmp5);
10939 notl(result);
10940 kmovdl(k1, result);
10941
10942 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10943 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10944 ktestd(k2, k1);
10945 jcc(Assembler::carryClear, restore_k1_return_zero);
10946
10947 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10948
10949 addptr(src, tmp5);
10950 addptr(src, tmp5);
10951 addptr(dst, tmp5);
10952 subl(len, tmp5);
10953
10954 bind(post_alignement);
10955 // end of alignement
10956
10957 movl(tmp5, len);
10958 andl(tmp5, (32 - 1)); // tail count (in chars)
10959 andl(len, ~(32 - 1)); // vector count (in chars)
10960 jcc(Assembler::zero, copy_loop_tail);
10961
10962 lea(src, Address(src, len, Address::times_2));
10963 lea(dst, Address(dst, len, Address::times_1));
10964 negptr(len);
10965
10966 bind(copy_32_loop);
10967 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10968 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10969 kortestdl(k2, k2);
10970 jcc(Assembler::carryClear, restore_k1_return_zero);
10971
10972 // All elements in current processed chunk are valid candidates for
10973 // compression. Write a truncated byte elements to the memory.
10974 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10975 addptr(len, 32);
10976 jcc(Assembler::notZero, copy_32_loop);
10977
10978 bind(copy_loop_tail);
10979 // bail out when there is nothing to be done
10980 testl(tmp5, 0xFFFFFFFF);
10981 // Restore k1
10982 kmovql(k1, k3);
10983 jcc(Assembler::zero, return_length);
10984
10985 movl(len, tmp5);
10986
10987 // ~(~0 << len), where len is the # of remaining elements to process
10988 movl(result, 0xFFFFFFFF);
10989 shlxl(result, result, len);
10990 notl(result);
10991
10992 kmovdl(k1, result);
10993
10994 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10995 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10996 ktestd(k2, k1);
10997 jcc(Assembler::carryClear, restore_k1_return_zero);
10998
10999 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
11000 // Restore k1
11001 kmovql(k1, k3);
11002 jmp(return_length);
11003
11004 bind(restore_k1_return_zero);
11005 // Restore k1
11006 kmovql(k1, k3);
11007 jmp(return_zero);
11008
11009 clear_vector_masking(); // closing of the stub context for programming mask registers
11010 }
11011 if (UseSSE42Intrinsics) {
11012 Label copy_32_loop, copy_16, copy_tail;
11013
11014 bind(below_threshold);
11015
11016 movl(result, len);
11017
11018 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
11019
11020 // vectored compression
11021 andl(len, 0xfffffff0); // vector count (in chars)
11022 andl(result, 0x0000000f); // tail count (in chars)
11023 testl(len, len);
11024 jccb(Assembler::zero, copy_16);
11025
11026 // compress 16 chars per iter
11027 movdl(tmp1Reg, tmp5);
11028 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
11029 pxor(tmp4Reg, tmp4Reg);
11030
11031 lea(src, Address(src, len, Address::times_2));
11032 lea(dst, Address(dst, len, Address::times_1));
11033 negptr(len);
11034
11035 bind(copy_32_loop);
11036 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
11037 por(tmp4Reg, tmp2Reg);
11038 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
11039 por(tmp4Reg, tmp3Reg);
11040 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
11041 jcc(Assembler::notZero, return_zero);
11042 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
11043 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
11044 addptr(len, 16);
11045 jcc(Assembler::notZero, copy_32_loop);
11046
11047 // compress next vector of 8 chars (if any)
11048 bind(copy_16);
11049 movl(len, result);
11050 andl(len, 0xfffffff8); // vector count (in chars)
11051 andl(result, 0x00000007); // tail count (in chars)
11052 testl(len, len);
11053 jccb(Assembler::zero, copy_tail);
11054
11055 movdl(tmp1Reg, tmp5);
11056 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
11057 pxor(tmp3Reg, tmp3Reg);
11058
11059 movdqu(tmp2Reg, Address(src, 0));
11060 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
11061 jccb(Assembler::notZero, return_zero);
11062 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
11063 movq(Address(dst, 0), tmp2Reg);
11064 addptr(src, 16);
11065 addptr(dst, 8);
11066
11067 bind(copy_tail);
11068 movl(len, result);
11069 }
11070 // compress 1 char per iter
11071 testl(len, len);
11072 jccb(Assembler::zero, return_length);
11073 lea(src, Address(src, len, Address::times_2));
11074 lea(dst, Address(dst, len, Address::times_1));
11075 negptr(len);
11076
11077 bind(copy_chars_loop);
11078 load_unsigned_short(result, Address(src, len, Address::times_2));
11079 testl(result, 0xff00); // check if Unicode char
11080 jccb(Assembler::notZero, return_zero);
11081 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
11082 increment(len);
11083 jcc(Assembler::notZero, copy_chars_loop);
11084
11085 // if compression succeeded, return length
11086 bind(return_length);
11087 pop(result);
11088 jmpb(done);
11089
11090 // if compression failed, return 0
11091 bind(return_zero);
11092 xorl(result, result);
11093 addptr(rsp, wordSize);
11094
11095 bind(done);
11096 }
11097
11098 // Inflate byte[] array to char[].
11099 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11100 // @HotSpotIntrinsicCandidate
11101 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11102 // for (int i = 0; i < len; i++) {
11103 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11104 // }
11105 // }
11106 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11107 XMMRegister tmp1, Register tmp2) {
11108 Label copy_chars_loop, done, below_threshold;
11109 // rsi: src
11110 // rdi: dst
11111 // rdx: len
11112 // rcx: tmp2
11113
11114 // rsi holds start addr of source byte[] to be inflated
11115 // rdi holds start addr of destination char[]
11116 // rdx holds length
11117 assert_different_registers(src, dst, len, tmp2);
11118
11119 if ((UseAVX > 2) && // AVX512
11120 VM_Version::supports_avx512vlbw() &&
11121 VM_Version::supports_bmi2()) {
11122
11123 set_vector_masking(); // opening of the stub context for programming mask registers
11124
11125 Label copy_32_loop, copy_tail;
11126 Register tmp3_aliased = len;
11127
11128 // if length of the string is less than 16, handle it in an old fashioned
11129 // way
11130 testl(len, -16);
11131 jcc(Assembler::zero, below_threshold);
11132
11133 // In order to use only one arithmetic operation for the main loop we use
11134 // this pre-calculation
11135 movl(tmp2, len);
11136 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11137 andl(len, -32); // vector count
11138 jccb(Assembler::zero, copy_tail);
11139
11140 lea(src, Address(src, len, Address::times_1));
11141 lea(dst, Address(dst, len, Address::times_2));
11142 negptr(len);
11143
11144
11145 // inflate 32 chars per iter
11146 bind(copy_32_loop);
11147 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11148 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11149 addptr(len, 32);
11150 jcc(Assembler::notZero, copy_32_loop);
11151
11152 bind(copy_tail);
11153 // bail out when there is nothing to be done
11154 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11155 jcc(Assembler::zero, done);
11156
11157 // Save k1
11158 kmovql(k2, k1);
11159
11160 // ~(~0 << length), where length is the # of remaining elements to process
11161 movl(tmp3_aliased, -1);
11162 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11163 notl(tmp3_aliased);
11164 kmovdl(k1, tmp3_aliased);
11165 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11166 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11167
11168 // Restore k1
11169 kmovql(k1, k2);
11170 jmp(done);
11171
11172 clear_vector_masking(); // closing of the stub context for programming mask registers
11173 }
11174 if (UseSSE42Intrinsics) {
11175 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11176
11177 movl(tmp2, len);
11178
11179 if (UseAVX > 1) {
11180 andl(tmp2, (16 - 1));
11181 andl(len, -16);
11182 jccb(Assembler::zero, copy_new_tail);
11183 } else {
11184 andl(tmp2, 0x00000007); // tail count (in chars)
11185 andl(len, 0xfffffff8); // vector count (in chars)
11186 jccb(Assembler::zero, copy_tail);
11187 }
11188
11189 // vectored inflation
11190 lea(src, Address(src, len, Address::times_1));
11191 lea(dst, Address(dst, len, Address::times_2));
11192 negptr(len);
11193
11194 if (UseAVX > 1) {
11195 bind(copy_16_loop);
11196 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11197 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11198 addptr(len, 16);
11199 jcc(Assembler::notZero, copy_16_loop);
11200
11201 bind(below_threshold);
11202 bind(copy_new_tail);
11203 if ((UseAVX > 2) &&
11204 VM_Version::supports_avx512vlbw() &&
11205 VM_Version::supports_bmi2()) {
11206 movl(tmp2, len);
11207 } else {
11208 movl(len, tmp2);
11209 }
11210 andl(tmp2, 0x00000007);
11211 andl(len, 0xFFFFFFF8);
11212 jccb(Assembler::zero, copy_tail);
11213
11214 pmovzxbw(tmp1, Address(src, 0));
11215 movdqu(Address(dst, 0), tmp1);
11216 addptr(src, 8);
11217 addptr(dst, 2 * 8);
11218
11219 jmp(copy_tail, true);
11220 }
11221
11222 // inflate 8 chars per iter
11223 bind(copy_8_loop);
11224 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11225 movdqu(Address(dst, len, Address::times_2), tmp1);
11226 addptr(len, 8);
11227 jcc(Assembler::notZero, copy_8_loop);
11228
11229 bind(copy_tail);
11230 movl(len, tmp2);
11231
11232 cmpl(len, 4);
11233 jccb(Assembler::less, copy_bytes);
11234
11235 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11236 pmovzxbw(tmp1, tmp1);
11237 movq(Address(dst, 0), tmp1);
11238 subptr(len, 4);
11239 addptr(src, 4);
11240 addptr(dst, 8);
11241
11242 bind(copy_bytes);
11243 }
11244 testl(len, len);
11245 jccb(Assembler::zero, done);
11246 lea(src, Address(src, len, Address::times_1));
11247 lea(dst, Address(dst, len, Address::times_2));
11248 negptr(len);
11249
11250 // inflate 1 char per iter
11251 bind(copy_chars_loop);
11252 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11253 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11254 increment(len);
11255 jcc(Assembler::notZero, copy_chars_loop);
11256
11257 bind(done);
11258 }
11259
11260 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11261 switch (cond) {
11262 // Note some conditions are synonyms for others
11263 case Assembler::zero: return Assembler::notZero;
11264 case Assembler::notZero: return Assembler::zero;
11265 case Assembler::less: return Assembler::greaterEqual;
11266 case Assembler::lessEqual: return Assembler::greater;
11267 case Assembler::greater: return Assembler::lessEqual;
11268 case Assembler::greaterEqual: return Assembler::less;
11269 case Assembler::below: return Assembler::aboveEqual;
11270 case Assembler::belowEqual: return Assembler::above;
11271 case Assembler::above: return Assembler::belowEqual;
11272 case Assembler::aboveEqual: return Assembler::below;
11273 case Assembler::overflow: return Assembler::noOverflow;
11274 case Assembler::noOverflow: return Assembler::overflow;
11275 case Assembler::negative: return Assembler::positive;
11276 case Assembler::positive: return Assembler::negative;
11277 case Assembler::parity: return Assembler::noParity;
11278 case Assembler::noParity: return Assembler::parity;
11279 }
11280 ShouldNotReachHere(); return Assembler::overflow;
11281 }
11282
11283 SkipIfEqual::SkipIfEqual(
11284 MacroAssembler* masm, const bool* flag_addr, bool value) {
11285 _masm = masm;
11286 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11287 _masm->jcc(Assembler::equal, _label);
11288 }
11289
11290 SkipIfEqual::~SkipIfEqual() {
11291 _masm->bind(_label);
11292 }
11293
11294 // 32-bit Windows has its own fast-path implementation
11295 // of get_thread
11296 #if !defined(WIN32) || defined(_LP64)
11297
11298 // This is simply a call to Thread::current()
11299 void MacroAssembler::get_thread(Register thread) {
11300 if (thread != rax) {
11301 push(rax);
11302 }
11303 LP64_ONLY(push(rdi);)
11304 LP64_ONLY(push(rsi);)
11305 push(rdx);
11306 push(rcx);
11307 #ifdef _LP64
11308 push(r8);
11309 push(r9);
11310 push(r10);
11311 push(r11);
11312 #endif
11313
11314 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11315
11316 #ifdef _LP64
11317 pop(r11);
11318 pop(r10);
11319 pop(r9);
11320 pop(r8);
11321 #endif
11322 pop(rcx);
11323 pop(rdx);
11324 LP64_ONLY(pop(rsi);)
11325 LP64_ONLY(pop(rdi);)
11326 if (thread != rax) {
11327 mov(thread, rax);
11328 pop(rax);
11329 }
11330 }
11331
11332 #endif