1 /*
   2  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  */
  24 
  25 #include <stdio.h>
  26 #include <sys/types.h>
  27 
  28 #include "precompiled.hpp"
  29 #include "asm/assembler.hpp"
  30 #include "asm/assembler.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 
  33 #ifndef PRODUCT
  34 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
  35 #endif
  36 
  37 #include "compiler/disassembler.hpp"
  38 #include "memory/resourceArea.hpp"
  39 #include "runtime/interfaceSupport.inline.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 
  42 // for the moment we reuse the logical/floating point immediate encode
  43 // and decode functiosn provided by the simulator. when we move to
  44 // real hardware we will need to pull taht code into here
  45 
  46 #include "immediate_aarch64.hpp"
  47 
  48 extern "C" void entry(CodeBuffer *cb);
  49 
  50 #define __ _masm.
  51 #ifdef PRODUCT
  52 #define BLOCK_COMMENT(str) /* nothing */
  53 #else
  54 #define BLOCK_COMMENT(str) block_comment(str)
  55 #endif
  56 
  57 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
  58 
  59 static float unpack(unsigned value);
  60 
  61 void entry(CodeBuffer *cb) {
  62 
  63   // {
  64   //   for (int i = 0; i < 256; i+=16)
  65   //     {
  66   //    printf("\"%20.20g\", ", unpack(i));
  67   //    printf("\"%20.20g\", ", unpack(i+1));
  68   //     }
  69   //   printf("\n");
  70   // }
  71 
  72   Assembler _masm(cb);
  73   address entry = __ pc();
  74 
  75   // Smoke test for assembler
  76 
  77 #ifdef ASSERT
  78 // BEGIN  Generated code -- do not edit
  79 // Generated by aarch64-asmtest.py
  80     Label back, forth;
  81     __ bind(back);
  82 
  83 // ArithOp
  84     __ add(r19, r22, r7, Assembler::LSL, 28);          //       add     x19, x22, x7, LSL #28
  85     __ sub(r16, r11, r10, Assembler::LSR, 13);         //       sub     x16, x11, x10, LSR #13
  86     __ adds(r27, r13, r28, Assembler::ASR, 2);         //       adds    x27, x13, x28, ASR #2
  87     __ subs(r20, r28, r26, Assembler::ASR, 41);        //       subs    x20, x28, x26, ASR #41
  88     __ addw(r8, r19, r19, Assembler::ASR, 19);         //       add     w8, w19, w19, ASR #19
  89     __ subw(r4, r9, r10, Assembler::LSL, 14);          //       sub     w4, w9, w10, LSL #14
  90     __ addsw(r8, r11, r30, Assembler::LSL, 13);        //       adds    w8, w11, w30, LSL #13
  91     __ subsw(r0, r25, r19, Assembler::LSL, 9);         //       subs    w0, w25, w19, LSL #9
  92     __ andr(r20, r0, r21, Assembler::LSL, 19);         //       and     x20, x0, x21, LSL #19
  93     __ orr(r21, r14, r20, Assembler::LSL, 17);         //       orr     x21, x14, x20, LSL #17
  94     __ eor(r25, r28, r1, Assembler::LSL, 51);          //       eor     x25, x28, x1, LSL #51
  95     __ ands(r10, r27, r11, Assembler::ASR, 15);        //       ands    x10, x27, x11, ASR #15
  96     __ andw(r25, r5, r12, Assembler::ASR, 23);         //       and     w25, w5, w12, ASR #23
  97     __ orrw(r18, r14, r10, Assembler::LSR, 4);         //       orr     w18, w14, w10, LSR #4
  98     __ eorw(r4, r21, r5, Assembler::ASR, 22);          //       eor     w4, w21, w5, ASR #22
  99     __ andsw(r21, r0, r5, Assembler::ASR, 29);         //       ands    w21, w0, w5, ASR #29
 100     __ bic(r26, r30, r6, Assembler::ASR, 37);          //       bic     x26, x30, x6, ASR #37
 101     __ orn(r3, r1, r13, Assembler::LSR, 29);           //       orn     x3, x1, x13, LSR #29
 102     __ eon(r0, r28, r9, Assembler::LSL, 47);           //       eon     x0, x28, x9, LSL #47
 103     __ bics(r29, r5, r28, Assembler::LSL, 46);         //       bics    x29, x5, x28, LSL #46
 104     __ bicw(r9, r18, r7, Assembler::LSR, 20);          //       bic     w9, w18, w7, LSR #20
 105     __ ornw(r26, r13, r25, Assembler::ASR, 24);        //       orn     w26, w13, w25, ASR #24
 106     __ eonw(r25, r4, r19, Assembler::LSL, 6);          //       eon     w25, w4, w19, LSL #6
 107     __ bicsw(r5, r26, r4, Assembler::LSR, 24);         //       bics    w5, w26, w4, LSR #24
 108 
 109 // AddSubImmOp
 110     __ addw(r7, r19, 340u);                            //       add     w7, w19, #340
 111     __ addsw(r8, r0, 401u);                            //       adds    w8, w0, #401
 112     __ subw(r29, r20, 163u);                           //       sub     w29, w20, #163
 113     __ subsw(r8, r23, 759u);                           //       subs    w8, w23, #759
 114     __ add(r1, r12, 523u);                             //       add     x1, x12, #523
 115     __ adds(r2, r11, 426u);                            //       adds    x2, x11, #426
 116     __ sub(r14, r29, 716u);                            //       sub     x14, x29, #716
 117     __ subs(r11, r5, 582u);                            //       subs    x11, x5, #582
 118 
 119 // LogicalImmOp
 120     __ andw(r23, r22, 32768ul);                        //       and     w23, w22, #0x8000
 121     __ orrw(r4, r10, 4042322160ul);                    //       orr     w4, w10, #0xf0f0f0f0
 122     __ eorw(r0, r24, 4042322160ul);                    //       eor     w0, w24, #0xf0f0f0f0
 123     __ andsw(r19, r29, 2139127680ul);                  //       ands    w19, w29, #0x7f807f80
 124     __ andr(r5, r10, 4503599627354112ul);              //       and     x5, x10, #0xfffffffffc000
 125     __ orr(r12, r30, 18445618178097414144ul);          //       orr     x12, x30, #0xfffc0000fffc0000
 126     __ eor(r30, r5, 262128ul);                         //       eor     x30, x5, #0x3fff0
 127     __ ands(r26, r23, 4194300ul);                      //       ands    x26, x23, #0x3ffffc
 128 
 129 // AbsOp
 130     __ b(__ pc());                                     //       b       .
 131     __ b(back);                                        //       b       back
 132     __ b(forth);                                       //       b       forth
 133     __ bl(__ pc());                                    //       bl      .
 134     __ bl(back);                                       //       bl      back
 135     __ bl(forth);                                      //       bl      forth
 136 
 137 // RegAndAbsOp
 138     __ cbzw(r12, __ pc());                             //       cbz     w12, .
 139     __ cbzw(r12, back);                                //       cbz     w12, back
 140     __ cbzw(r12, forth);                               //       cbz     w12, forth
 141     __ cbnzw(r20, __ pc());                            //       cbnz    w20, .
 142     __ cbnzw(r20, back);                               //       cbnz    w20, back
 143     __ cbnzw(r20, forth);                              //       cbnz    w20, forth
 144     __ cbz(r12, __ pc());                              //       cbz     x12, .
 145     __ cbz(r12, back);                                 //       cbz     x12, back
 146     __ cbz(r12, forth);                                //       cbz     x12, forth
 147     __ cbnz(r24, __ pc());                             //       cbnz    x24, .
 148     __ cbnz(r24, back);                                //       cbnz    x24, back
 149     __ cbnz(r24, forth);                               //       cbnz    x24, forth
 150     __ adr(r6, __ pc());                               //       adr     x6, .
 151     __ adr(r6, back);                                  //       adr     x6, back
 152     __ adr(r6, forth);                                 //       adr     x6, forth
 153     __ _adrp(r21, __ pc());                             //      adrp    x21, .
 154 
 155 // RegImmAbsOp
 156     __ tbz(r1, 1, __ pc());                            //       tbz     x1, #1, .
 157     __ tbz(r1, 1, back);                               //       tbz     x1, #1, back
 158     __ tbz(r1, 1, forth);                              //       tbz     x1, #1, forth
 159     __ tbnz(r8, 9, __ pc());                           //       tbnz    x8, #9, .
 160     __ tbnz(r8, 9, back);                              //       tbnz    x8, #9, back
 161     __ tbnz(r8, 9, forth);                             //       tbnz    x8, #9, forth
 162 
 163 // MoveWideImmOp
 164     __ movnw(r12, 23175, 0);                           //       movn    w12, #23175, lsl 0
 165     __ movzw(r11, 20476, 16);                          //       movz    w11, #20476, lsl 16
 166     __ movkw(r21, 3716, 0);                            //       movk    w21, #3716, lsl 0
 167     __ movn(r29, 28661, 48);                           //       movn    x29, #28661, lsl 48
 168     __ movz(r3, 6927, 0);                              //       movz    x3, #6927, lsl 0
 169     __ movk(r22, 9828, 16);                            //       movk    x22, #9828, lsl 16
 170 
 171 // BitfieldOp
 172     __ sbfm(r12, r8, 6, 22);                           //       sbfm    x12, x8, #6, #22
 173     __ bfmw(r19, r25, 25, 19);                         //       bfm     w19, w25, #25, #19
 174     __ ubfmw(r9, r12, 29, 15);                         //       ubfm    w9, w12, #29, #15
 175     __ sbfm(r28, r25, 16, 16);                         //       sbfm    x28, x25, #16, #16
 176     __ bfm(r12, r5, 4, 25);                            //       bfm     x12, x5, #4, #25
 177     __ ubfm(r0, r10, 6, 8);                            //       ubfm    x0, x10, #6, #8
 178 
 179 // ExtractOp
 180     __ extrw(r4, r13, r26, 24);                        //       extr    w4, w13, w26, #24
 181     __ extr(r23, r30, r24, 31);                        //       extr    x23, x30, x24, #31
 182 
 183 // CondBranchOp
 184     __ br(Assembler::EQ, __ pc());                     //       b.EQ    .
 185     __ br(Assembler::EQ, back);                        //       b.EQ    back
 186     __ br(Assembler::EQ, forth);                       //       b.EQ    forth
 187     __ br(Assembler::NE, __ pc());                     //       b.NE    .
 188     __ br(Assembler::NE, back);                        //       b.NE    back
 189     __ br(Assembler::NE, forth);                       //       b.NE    forth
 190     __ br(Assembler::HS, __ pc());                     //       b.HS    .
 191     __ br(Assembler::HS, back);                        //       b.HS    back
 192     __ br(Assembler::HS, forth);                       //       b.HS    forth
 193     __ br(Assembler::CS, __ pc());                     //       b.CS    .
 194     __ br(Assembler::CS, back);                        //       b.CS    back
 195     __ br(Assembler::CS, forth);                       //       b.CS    forth
 196     __ br(Assembler::LO, __ pc());                     //       b.LO    .
 197     __ br(Assembler::LO, back);                        //       b.LO    back
 198     __ br(Assembler::LO, forth);                       //       b.LO    forth
 199     __ br(Assembler::CC, __ pc());                     //       b.CC    .
 200     __ br(Assembler::CC, back);                        //       b.CC    back
 201     __ br(Assembler::CC, forth);                       //       b.CC    forth
 202     __ br(Assembler::MI, __ pc());                     //       b.MI    .
 203     __ br(Assembler::MI, back);                        //       b.MI    back
 204     __ br(Assembler::MI, forth);                       //       b.MI    forth
 205     __ br(Assembler::PL, __ pc());                     //       b.PL    .
 206     __ br(Assembler::PL, back);                        //       b.PL    back
 207     __ br(Assembler::PL, forth);                       //       b.PL    forth
 208     __ br(Assembler::VS, __ pc());                     //       b.VS    .
 209     __ br(Assembler::VS, back);                        //       b.VS    back
 210     __ br(Assembler::VS, forth);                       //       b.VS    forth
 211     __ br(Assembler::VC, __ pc());                     //       b.VC    .
 212     __ br(Assembler::VC, back);                        //       b.VC    back
 213     __ br(Assembler::VC, forth);                       //       b.VC    forth
 214     __ br(Assembler::HI, __ pc());                     //       b.HI    .
 215     __ br(Assembler::HI, back);                        //       b.HI    back
 216     __ br(Assembler::HI, forth);                       //       b.HI    forth
 217     __ br(Assembler::LS, __ pc());                     //       b.LS    .
 218     __ br(Assembler::LS, back);                        //       b.LS    back
 219     __ br(Assembler::LS, forth);                       //       b.LS    forth
 220     __ br(Assembler::GE, __ pc());                     //       b.GE    .
 221     __ br(Assembler::GE, back);                        //       b.GE    back
 222     __ br(Assembler::GE, forth);                       //       b.GE    forth
 223     __ br(Assembler::LT, __ pc());                     //       b.LT    .
 224     __ br(Assembler::LT, back);                        //       b.LT    back
 225     __ br(Assembler::LT, forth);                       //       b.LT    forth
 226     __ br(Assembler::GT, __ pc());                     //       b.GT    .
 227     __ br(Assembler::GT, back);                        //       b.GT    back
 228     __ br(Assembler::GT, forth);                       //       b.GT    forth
 229     __ br(Assembler::LE, __ pc());                     //       b.LE    .
 230     __ br(Assembler::LE, back);                        //       b.LE    back
 231     __ br(Assembler::LE, forth);                       //       b.LE    forth
 232     __ br(Assembler::AL, __ pc());                     //       b.AL    .
 233     __ br(Assembler::AL, back);                        //       b.AL    back
 234     __ br(Assembler::AL, forth);                       //       b.AL    forth
 235     __ br(Assembler::NV, __ pc());                     //       b.NV    .
 236     __ br(Assembler::NV, back);                        //       b.NV    back
 237     __ br(Assembler::NV, forth);                       //       b.NV    forth
 238 
 239 // ImmOp
 240     __ svc(12729);                                     //       svc     #12729
 241     __ hvc(6788);                                      //       hvc     #6788
 242     __ smc(1535);                                      //       smc     #1535
 243     __ brk(16766);                                     //       brk     #16766
 244     __ hlt(9753);                                      //       hlt     #9753
 245 
 246 // Op
 247     __ nop();                                          //       nop
 248     __ eret();                                         //       eret
 249     __ drps();                                         //       drps
 250     __ isb();                                          //       isb
 251 
 252 // SystemOp
 253     __ dsb(Assembler::SY);                             //       dsb     SY
 254     __ dmb(Assembler::ISHST);                          //       dmb     ISHST
 255 
 256 // OneRegOp
 257     __ br(r2);                                         //       br      x2
 258     __ blr(r5);                                        //       blr     x5
 259 
 260 // LoadStoreExclusiveOp
 261     __ stxr(r20, r21, r2);                             //       stxr    w20, x21, [x2]
 262     __ stlxr(r5, r29, r7);                             //       stlxr   w5, x29, [x7]
 263     __ ldxr(r5, r16);                                  //       ldxr    x5, [x16]
 264     __ ldaxr(r27, r29);                                //       ldaxr   x27, [x29]
 265     __ stlr(r0, r29);                                  //       stlr    x0, [x29]
 266     __ ldar(r21, r28);                                 //       ldar    x21, [x28]
 267 
 268 // LoadStoreExclusiveOp
 269     __ stxrw(r21, r24, r7);                            //       stxr    w21, w24, [x7]
 270     __ stlxrw(r21, r26, r28);                          //       stlxr   w21, w26, [x28]
 271     __ ldxrw(r21, r6);                                 //       ldxr    w21, [x6]
 272     __ ldaxrw(r15, r30);                               //       ldaxr   w15, [x30]
 273     __ stlrw(r19, r3);                                 //       stlr    w19, [x3]
 274     __ ldarw(r22, r2);                                 //       ldar    w22, [x2]
 275 
 276 // LoadStoreExclusiveOp
 277     __ stxrh(r18, r15, r0);                            //       stxrh   w18, w15, [x0]
 278     __ stlxrh(r11, r5, r28);                           //       stlxrh  w11, w5, [x28]
 279     __ ldxrh(r29, r6);                                 //       ldxrh   w29, [x6]
 280     __ ldaxrh(r18, r7);                                //       ldaxrh  w18, [x7]
 281     __ stlrh(r25, r28);                                //       stlrh   w25, [x28]
 282     __ ldarh(r2, r19);                                 //       ldarh   w2, [x19]
 283 
 284 // LoadStoreExclusiveOp
 285     __ stxrb(r10, r30, r1);                            //       stxrb   w10, w30, [x1]
 286     __ stlxrb(r20, r21, r22);                          //       stlxrb  w20, w21, [x22]
 287     __ ldxrb(r25, r2);                                 //       ldxrb   w25, [x2]
 288     __ ldaxrb(r24, r5);                                //       ldaxrb  w24, [x5]
 289     __ stlrb(r16, r3);                                 //       stlrb   w16, [x3]
 290     __ ldarb(r22, r29);                                //       ldarb   w22, [x29]
 291 
 292 // LoadStoreExclusiveOp
 293     __ ldxp(r8, r2, r19);                              //       ldxp    x8, x2, [x19]
 294     __ ldaxp(r7, r19, r14);                            //       ldaxp   x7, x19, [x14]
 295     __ stxp(r8, r27, r28, r5);                         //       stxp    w8, x27, x28, [x5]
 296     __ stlxp(r5, r8, r14, r6);                         //       stlxp   w5, x8, x14, [x6]
 297 
 298 // LoadStoreExclusiveOp
 299     __ ldxpw(r25, r4, r22);                            //       ldxp    w25, w4, [x22]
 300     __ ldaxpw(r13, r14, r15);                          //       ldaxp   w13, w14, [x15]
 301     __ stxpw(r20, r26, r8, r10);                       //       stxp    w20, w26, w8, [x10]
 302     __ stlxpw(r23, r18, r18, r18);                     //       stlxp   w23, w18, w18, [x18]
 303 
 304 // base_plus_unscaled_offset
 305 // LoadStoreOp
 306     __ str(r30, Address(r11, 99));                     //       str     x30, [x11, 99]
 307     __ strw(r23, Address(r25, -77));                   //       str     w23, [x25, -77]
 308     __ strb(r2, Address(r14, 3));                      //       strb    w2, [x14, 3]
 309     __ strh(r9, Address(r10, 5));                      //       strh    w9, [x10, 5]
 310     __ ldr(r20, Address(r15, 57));                     //       ldr     x20, [x15, 57]
 311     __ ldrw(r12, Address(r16, -78));                   //       ldr     w12, [x16, -78]
 312     __ ldrb(r22, Address(r26, -3));                    //       ldrb    w22, [x26, -3]
 313     __ ldrh(r30, Address(r19, -47));                   //       ldrh    w30, [x19, -47]
 314     __ ldrsb(r9, Address(r10, -12));                   //       ldrsb   x9, [x10, -12]
 315     __ ldrsh(r28, Address(r17, 14));                   //       ldrsh   x28, [x17, 14]
 316     __ ldrshw(r3, Address(r5, 10));                    //       ldrsh   w3, [x5, 10]
 317     __ ldrsw(r17, Address(r17, -91));                  //       ldrsw   x17, [x17, -91]
 318     __ ldrd(v2, Address(r20, -17));                    //       ldr     d2, [x20, -17]
 319     __ ldrs(v22, Address(r7, -10));                    //       ldr     s22, [x7, -10]
 320     __ strd(v30, Address(r18, -223));                  //       str     d30, [x18, -223]
 321     __ strs(v13, Address(r22, 21));                    //       str     s13, [x22, 21]
 322 
 323 // pre
 324 // LoadStoreOp
 325     __ str(r9, Address(__ pre(r18, -112)));            //       str     x9, [x18, -112]!
 326     __ strw(r29, Address(__ pre(r23, 11)));            //       str     w29, [x23, 11]!
 327     __ strb(r18, Address(__ pre(r12, -1)));            //       strb    w18, [x12, -1]!
 328     __ strh(r16, Address(__ pre(r20, -23)));           //       strh    w16, [x20, -23]!
 329     __ ldr(r3, Address(__ pre(r29, 9)));               //       ldr     x3, [x29, 9]!
 330     __ ldrw(r25, Address(__ pre(r3, 19)));             //       ldr     w25, [x3, 19]!
 331     __ ldrb(r1, Address(__ pre(r29, -1)));             //       ldrb    w1, [x29, -1]!
 332     __ ldrh(r8, Address(__ pre(r29, -57)));            //       ldrh    w8, [x29, -57]!
 333     __ ldrsb(r5, Address(__ pre(r14, -13)));           //       ldrsb   x5, [x14, -13]!
 334     __ ldrsh(r10, Address(__ pre(r27, 1)));            //       ldrsh   x10, [x27, 1]!
 335     __ ldrshw(r11, Address(__ pre(r10, 25)));          //       ldrsh   w11, [x10, 25]!
 336     __ ldrsw(r4, Address(__ pre(r22, -92)));           //       ldrsw   x4, [x22, -92]!
 337     __ ldrd(v11, Address(__ pre(r23, 8)));             //       ldr     d11, [x23, 8]!
 338     __ ldrs(v25, Address(__ pre(r19, 54)));            //       ldr     s25, [x19, 54]!
 339     __ strd(v1, Address(__ pre(r7, -174)));            //       str     d1, [x7, -174]!
 340     __ strs(v8, Address(__ pre(r25, 54)));             //       str     s8, [x25, 54]!
 341 
 342 // post
 343 // LoadStoreOp
 344     __ str(r5, Address(__ post(r11, 37)));             //       str     x5, [x11], 37
 345     __ strw(r24, Address(__ post(r15, 19)));           //       str     w24, [x15], 19
 346     __ strb(r15, Address(__ post(r26, -1)));           //       strb    w15, [x26], -1
 347     __ strh(r18, Address(__ post(r18, -6)));           //       strh    w18, [x18], -6
 348     __ ldr(r7, Address(__ post(r2, -230)));            //       ldr     x7, [x2], -230
 349     __ ldrw(r27, Address(__ post(r11, -27)));          //       ldr     w27, [x11], -27
 350     __ ldrb(r18, Address(__ post(r3, -25)));           //       ldrb    w18, [x3], -25
 351     __ ldrh(r10, Address(__ post(r24, -32)));          //       ldrh    w10, [x24], -32
 352     __ ldrsb(r22, Address(__ post(r10, 4)));           //       ldrsb   x22, [x10], 4
 353     __ ldrsh(r17, Address(__ post(r12, 25)));          //       ldrsh   x17, [x12], 25
 354     __ ldrshw(r8, Address(__ post(r7, -62)));          //       ldrsh   w8, [x7], -62
 355     __ ldrsw(r23, Address(__ post(r22, -51)));         //       ldrsw   x23, [x22], -51
 356     __ ldrd(v24, Address(__ post(r25, 48)));           //       ldr     d24, [x25], 48
 357     __ ldrs(v21, Address(__ post(r12, -10)));          //       ldr     s21, [x12], -10
 358     __ strd(v18, Address(__ post(r13, -222)));         //       str     d18, [x13], -222
 359     __ strs(v16, Address(__ post(r1, -41)));           //       str     s16, [x1], -41
 360 
 361 // base_plus_reg
 362 // LoadStoreOp
 363     __ str(r2, Address(r22, r15, Address::sxtw(0)));   //       str     x2, [x22, w15, sxtw #0]
 364     __ strw(r2, Address(r16, r29, Address::lsl(0)));   //       str     w2, [x16, x29, lsl #0]
 365     __ strb(r20, Address(r18, r14, Address::uxtw(0))); //       strb    w20, [x18, w14, uxtw #0]
 366     __ strh(r6, Address(r19, r20, Address::sxtx(1)));  //       strh    w6, [x19, x20, sxtx #1]
 367     __ ldr(r14, Address(r29, r14, Address::sxtw(0)));  //       ldr     x14, [x29, w14, sxtw #0]
 368     __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); //       ldr     w16, [x20, w12, sxtw #2]
 369     __ ldrb(r9, Address(r12, r0, Address::sxtw(0)));   //       ldrb    w9, [x12, w0, sxtw #0]
 370     __ ldrh(r12, Address(r17, r3, Address::lsl(1)));   //       ldrh    w12, [x17, x3, lsl #1]
 371     __ ldrsb(r2, Address(r17, r3, Address::sxtx(0)));  //       ldrsb   x2, [x17, x3, sxtx #0]
 372     __ ldrsh(r7, Address(r1, r17, Address::uxtw(1)));  //       ldrsh   x7, [x1, w17, uxtw #1]
 373     __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); //     ldrsh   w25, [x15, w18, sxtw #1]
 374     __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); //       ldrsw   x23, [x21, x12, lsl #0]
 375     __ ldrd(v5, Address(r13, r8, Address::lsl(3)));    //       ldr     d5, [x13, x8, lsl #3]
 376     __ ldrs(v3, Address(r10, r22, Address::lsl(2)));   //       ldr     s3, [x10, x22, lsl #2]
 377     __ strd(v14, Address(r2, r27, Address::sxtw(0)));  //       str     d14, [x2, w27, sxtw #0]
 378     __ strs(v20, Address(r6, r25, Address::lsl(0)));   //       str     s20, [x6, x25, lsl #0]
 379 
 380 // base_plus_scaled_offset
 381 // LoadStoreOp
 382     __ str(r30, Address(r7, 16256));                   //       str     x30, [x7, 16256]
 383     __ strw(r15, Address(r8, 7588));                   //       str     w15, [x8, 7588]
 384     __ strb(r11, Address(r0, 1866));                   //       strb    w11, [x0, 1866]
 385     __ strh(r3, Address(r17, 3734));                   //       strh    w3, [x17, 3734]
 386     __ ldr(r2, Address(r7, 14224));                    //       ldr     x2, [x7, 14224]
 387     __ ldrw(r5, Address(r9, 7396));                    //       ldr     w5, [x9, 7396]
 388     __ ldrb(r28, Address(r9, 1721));                   //       ldrb    w28, [x9, 1721]
 389     __ ldrh(r2, Address(r20, 3656));                   //       ldrh    w2, [x20, 3656]
 390     __ ldrsb(r22, Address(r14, 1887));                 //       ldrsb   x22, [x14, 1887]
 391     __ ldrsh(r8, Address(r0, 4080));                   //       ldrsh   x8, [x0, 4080]
 392     __ ldrshw(r0, Address(r30, 3916));                 //       ldrsh   w0, [x30, 3916]
 393     __ ldrsw(r24, Address(r19, 6828));                 //       ldrsw   x24, [x19, 6828]
 394     __ ldrd(v24, Address(r12, 13032));                 //       ldr     d24, [x12, 13032]
 395     __ ldrs(v8, Address(r8, 7452));                    //       ldr     s8, [x8, 7452]
 396     __ strd(v10, Address(r15, 15992));                 //       str     d10, [x15, 15992]
 397     __ strs(v26, Address(r19, 6688));                  //       str     s26, [x19, 6688]
 398 
 399 // pcrel
 400 // LoadStoreOp
 401     __ ldr(r10, forth);                                //       ldr     x10, forth
 402     __ ldrw(r3, __ pc());                              //       ldr     w3, .
 403 
 404 // LoadStoreOp
 405     __ prfm(Address(r23, 9));                          //       prfm    PLDL1KEEP, [x23, 9]
 406 
 407 // LoadStoreOp
 408     __ prfm(back);                                     //       prfm    PLDL1KEEP, back
 409 
 410 // LoadStoreOp
 411     __ prfm(Address(r3, r8, Address::uxtw(0)));        //       prfm    PLDL1KEEP, [x3, w8, uxtw #0]
 412 
 413 // LoadStoreOp
 414     __ prfm(Address(r11, 15080));                      //       prfm    PLDL1KEEP, [x11, 15080]
 415 
 416 // AddSubCarryOp
 417     __ adcw(r13, r9, r28);                             //       adc     w13, w9, w28
 418     __ adcsw(r27, r19, r28);                           //       adcs    w27, w19, w28
 419     __ sbcw(r19, r18, r6);                             //       sbc     w19, w18, w6
 420     __ sbcsw(r14, r20, r3);                            //       sbcs    w14, w20, w3
 421     __ adc(r16, r14, r8);                              //       adc     x16, x14, x8
 422     __ adcs(r0, r29, r8);                              //       adcs    x0, x29, x8
 423     __ sbc(r8, r24, r20);                              //       sbc     x8, x24, x20
 424     __ sbcs(r12, r28, r0);                             //       sbcs    x12, x28, x0
 425 
 426 // AddSubExtendedOp
 427     __ addw(r23, r6, r16, ext::uxtb, 4);               //       add     w23, w6, w16, uxtb #4
 428     __ addsw(r25, r25, r23, ext::sxth, 2);             //       adds    w25, w25, w23, sxth #2
 429     __ sub(r26, r22, r4, ext::uxtx, 1);                //       sub     x26, x22, x4, uxtx #1
 430     __ subsw(r17, r29, r19, ext::sxtx, 3);             //       subs    w17, w29, w19, sxtx #3
 431     __ add(r11, r30, r21, ext::uxtb, 3);               //       add     x11, x30, x21, uxtb #3
 432     __ adds(r16, r19, r0, ext::sxtb, 2);               //       adds    x16, x19, x0, sxtb #2
 433     __ sub(r11, r9, r25, ext::sxtx, 1);                //       sub     x11, x9, x25, sxtx #1
 434     __ subs(r17, r20, r12, ext::sxtb, 4);              //       subs    x17, x20, x12, sxtb #4
 435 
 436 // ConditionalCompareOp
 437     __ ccmnw(r13, r11, 3u, Assembler::LE);             //       ccmn    w13, w11, #3, LE
 438     __ ccmpw(r13, r12, 2u, Assembler::HI);             //       ccmp    w13, w12, #2, HI
 439     __ ccmn(r3, r2, 12u, Assembler::NE);               //       ccmn    x3, x2, #12, NE
 440     __ ccmp(r7, r21, 3u, Assembler::VS);               //       ccmp    x7, x21, #3, VS
 441 
 442 // ConditionalCompareImmedOp
 443     __ ccmnw(r2, 14, 4, Assembler::CC);                //       ccmn    w2, #14, #4, CC
 444     __ ccmpw(r17, 17, 6, Assembler::PL);               //       ccmp    w17, #17, #6, PL
 445     __ ccmn(r10, 12, 0, Assembler::CS);                //       ccmn    x10, #12, #0, CS
 446     __ ccmp(r21, 18, 14, Assembler::GE);               //       ccmp    x21, #18, #14, GE
 447 
 448 // ConditionalSelectOp
 449     __ cselw(r21, r13, r12, Assembler::GT);            //       csel    w21, w13, w12, GT
 450     __ csincw(r10, r27, r15, Assembler::LS);           //       csinc   w10, w27, w15, LS
 451     __ csinvw(r0, r13, r9, Assembler::HI);             //       csinv   w0, w13, w9, HI
 452     __ csnegw(r18, r4, r26, Assembler::VS);            //       csneg   w18, w4, w26, VS
 453     __ csel(r12, r29, r7, Assembler::LS);              //       csel    x12, x29, x7, LS
 454     __ csinc(r6, r7, r20, Assembler::VC);              //       csinc   x6, x7, x20, VC
 455     __ csinv(r22, r21, r3, Assembler::LE);             //       csinv   x22, x21, x3, LE
 456     __ csneg(r19, r12, r27, Assembler::LS);            //       csneg   x19, x12, x27, LS
 457 
 458 // TwoRegOp
 459     __ rbitw(r0, r16);                                 //       rbit    w0, w16
 460     __ rev16w(r17, r23);                               //       rev16   w17, w23
 461     __ revw(r17, r14);                                 //       rev     w17, w14
 462     __ clzw(r24, r30);                                 //       clz     w24, w30
 463     __ clsw(r24, r22);                                 //       cls     w24, w22
 464     __ rbit(r3, r17);                                  //       rbit    x3, x17
 465     __ rev16(r12, r13);                                //       rev16   x12, x13
 466     __ rev32(r9, r22);                                 //       rev32   x9, x22
 467     __ rev(r0, r0);                                    //       rev     x0, x0
 468     __ clz(r5, r16);                                   //       clz     x5, x16
 469     __ cls(r25, r22);                                  //       cls     x25, x22
 470 
 471 // ThreeRegOp
 472     __ udivw(r29, r4, r0);                             //       udiv    w29, w4, w0
 473     __ sdivw(r0, r29, r29);                            //       sdiv    w0, w29, w29
 474     __ lslvw(r5, r17, r21);                            //       lslv    w5, w17, w21
 475     __ lsrvw(r9, r9, r18);                             //       lsrv    w9, w9, w18
 476     __ asrvw(r1, r27, r8);                             //       asrv    w1, w27, w8
 477     __ rorvw(r18, r20, r13);                           //       rorv    w18, w20, w13
 478     __ udiv(r8, r25, r12);                             //       udiv    x8, x25, x12
 479     __ sdiv(r7, r5, r28);                              //       sdiv    x7, x5, x28
 480     __ lslv(r5, r17, r27);                             //       lslv    x5, x17, x27
 481     __ lsrv(r23, r26, r20);                            //       lsrv    x23, x26, x20
 482     __ asrv(r28, r8, r28);                             //       asrv    x28, x8, x28
 483     __ rorv(r3, r29, r4);                              //       rorv    x3, x29, x4
 484 
 485 // FourRegMulOp
 486     __ maddw(r17, r14, r26, r21);                      //       madd    w17, w14, w26, w21
 487     __ msubw(r1, r30, r11, r11);                       //       msub    w1, w30, w11, w11
 488     __ madd(r1, r17, r6, r28);                         //       madd    x1, x17, x6, x28
 489     __ msub(r30, r6, r30, r8);                         //       msub    x30, x6, x30, x8
 490     __ smaddl(r21, r6, r14, r8);                       //       smaddl  x21, w6, w14, x8
 491     __ smsubl(r10, r10, r24, r19);                     //       smsubl  x10, w10, w24, x19
 492     __ umaddl(r20, r18, r14, r24);                     //       umaddl  x20, w18, w14, x24
 493     __ umsubl(r18, r2, r5, r5);                        //       umsubl  x18, w2, w5, x5
 494 
 495 // ThreeRegFloatOp
 496     __ fmuls(v8, v18, v13);                            //       fmul    s8, s18, s13
 497     __ fdivs(v2, v14, v28);                            //       fdiv    s2, s14, s28
 498     __ fadds(v15, v12, v28);                           //       fadd    s15, s12, s28
 499     __ fsubs(v0, v12, v1);                             //       fsub    s0, s12, s1
 500     __ fmuls(v15, v29, v4);                            //       fmul    s15, s29, s4
 501     __ fmuld(v12, v1, v23);                            //       fmul    d12, d1, d23
 502     __ fdivd(v27, v8, v18);                            //       fdiv    d27, d8, d18
 503     __ faddd(v23, v20, v11);                           //       fadd    d23, d20, d11
 504     __ fsubd(v8, v12, v18);                            //       fsub    d8, d12, d18
 505     __ fmuld(v26, v24, v23);                           //       fmul    d26, d24, d23
 506 
 507 // FourRegFloatOp
 508     __ fmadds(v21, v23, v13, v25);                     //       fmadd   s21, s23, s13, s25
 509     __ fmsubs(v22, v10, v1, v14);                      //       fmsub   s22, s10, s1, s14
 510     __ fnmadds(v14, v20, v2, v30);                     //       fnmadd  s14, s20, s2, s30
 511     __ fnmadds(v7, v29, v22, v22);                     //       fnmadd  s7, s29, s22, s22
 512     __ fmaddd(v13, v5, v15, v5);                       //       fmadd   d13, d5, d15, d5
 513     __ fmsubd(v14, v12, v5, v10);                      //       fmsub   d14, d12, d5, d10
 514     __ fnmaddd(v10, v19, v0, v1);                      //       fnmadd  d10, d19, d0, d1
 515     __ fnmaddd(v20, v2, v2, v0);                       //       fnmadd  d20, d2, d2, d0
 516 
 517 // TwoRegFloatOp
 518     __ fmovs(v25, v9);                                 //       fmov    s25, s9
 519     __ fabss(v20, v4);                                 //       fabs    s20, s4
 520     __ fnegs(v3, v27);                                 //       fneg    s3, s27
 521     __ fsqrts(v1, v2);                                 //       fsqrt   s1, s2
 522     __ fcvts(v30, v0);                                 //       fcvt    d30, s0
 523     __ fmovd(v12, v4);                                 //       fmov    d12, d4
 524     __ fabsd(v1, v27);                                 //       fabs    d1, d27
 525     __ fnegd(v8, v22);                                 //       fneg    d8, d22
 526     __ fsqrtd(v11, v11);                               //       fsqrt   d11, d11
 527     __ fcvtd(v22, v28);                                //       fcvt    s22, d28
 528 
 529 // FloatConvertOp
 530     __ fcvtzsw(r28, v22);                              //       fcvtzs  w28, s22
 531     __ fcvtzs(r20, v27);                               //       fcvtzs  x20, s27
 532     __ fcvtzdw(r14, v0);                               //       fcvtzs  w14, d0
 533     __ fcvtzd(r26, v11);                               //       fcvtzs  x26, d11
 534     __ scvtfws(v28, r22);                              //       scvtf   s28, w22
 535     __ scvtfs(v16, r10);                               //       scvtf   s16, x10
 536     __ scvtfwd(v8, r21);                               //       scvtf   d8, w21
 537     __ scvtfd(v21, r28);                               //       scvtf   d21, x28
 538     __ fmovs(r24, v24);                                //       fmov    w24, s24
 539     __ fmovd(r8, v19);                                 //       fmov    x8, d19
 540     __ fmovs(v8, r12);                                 //       fmov    s8, w12
 541     __ fmovd(v6, r7);                                  //       fmov    d6, x7
 542 
 543 // TwoRegFloatOp
 544     __ fcmps(v30, v16);                                //       fcmp    s30, s16
 545     __ fcmpd(v25, v11);                                //       fcmp    d25, d11
 546     __ fcmps(v11, 0.0);                                //       fcmp    s11, #0.0
 547     __ fcmpd(v11, 0.0);                                //       fcmp    d11, #0.0
 548 
 549 // LoadStorePairOp
 550     __ stpw(r29, r12, Address(r17, 128));              //       stp     w29, w12, [x17, #128]
 551     __ ldpw(r22, r18, Address(r14, -96));              //       ldp     w22, w18, [x14, #-96]
 552     __ ldpsw(r11, r16, Address(r1, 64));               //       ldpsw   x11, x16, [x1, #64]
 553     __ stp(r0, r11, Address(r26, 112));                //       stp     x0, x11, [x26, #112]
 554     __ ldp(r7, r1, Address(r26, 16));                  //       ldp     x7, x1, [x26, #16]
 555 
 556 // LoadStorePairOp
 557     __ stpw(r10, r7, Address(__ pre(r24, 0)));         //       stp     w10, w7, [x24, #0]!
 558     __ ldpw(r7, r28, Address(__ pre(r24, -256)));      //       ldp     w7, w28, [x24, #-256]!
 559     __ ldpsw(r25, r28, Address(__ pre(r21, -240)));    //       ldpsw   x25, x28, [x21, #-240]!
 560     __ stp(r20, r18, Address(__ pre(r14, -16)));       //       stp     x20, x18, [x14, #-16]!
 561     __ ldp(r8, r10, Address(__ pre(r13, 80)));         //       ldp     x8, x10, [x13, #80]!
 562 
 563 // LoadStorePairOp
 564     __ stpw(r26, r24, Address(__ post(r2, -128)));     //       stp     w26, w24, [x2], #-128
 565     __ ldpw(r2, r25, Address(__ post(r21, -192)));     //       ldp     w2, w25, [x21], #-192
 566     __ ldpsw(r17, r2, Address(__ post(r21, -144)));    //       ldpsw   x17, x2, [x21], #-144
 567     __ stp(r12, r10, Address(__ post(r11, 96)));       //       stp     x12, x10, [x11], #96
 568     __ ldp(r24, r6, Address(__ post(r17, -32)));       //       ldp     x24, x6, [x17], #-32
 569 
 570 // LoadStorePairOp
 571     __ stnpw(r3, r30, Address(r14, -224));             //       stnp    w3, w30, [x14, #-224]
 572     __ ldnpw(r15, r20, Address(r26, -144));            //       ldnp    w15, w20, [x26, #-144]
 573     __ stnp(r22, r25, Address(r12, -128));             //       stnp    x22, x25, [x12, #-128]
 574     __ ldnp(r27, r22, Address(r17, -176));             //       ldnp    x27, x22, [x17, #-176]
 575 
 576 // FloatImmediateOp
 577     __ fmovd(v0, 2.0);                                 //       fmov d0, #2.0
 578     __ fmovd(v0, 2.125);                               //       fmov d0, #2.125
 579     __ fmovd(v0, 4.0);                                 //       fmov d0, #4.0
 580     __ fmovd(v0, 4.25);                                //       fmov d0, #4.25
 581     __ fmovd(v0, 8.0);                                 //       fmov d0, #8.0
 582     __ fmovd(v0, 8.5);                                 //       fmov d0, #8.5
 583     __ fmovd(v0, 16.0);                                //       fmov d0, #16.0
 584     __ fmovd(v0, 17.0);                                //       fmov d0, #17.0
 585     __ fmovd(v0, 0.125);                               //       fmov d0, #0.125
 586     __ fmovd(v0, 0.1328125);                           //       fmov d0, #0.1328125
 587     __ fmovd(v0, 0.25);                                //       fmov d0, #0.25
 588     __ fmovd(v0, 0.265625);                            //       fmov d0, #0.265625
 589     __ fmovd(v0, 0.5);                                 //       fmov d0, #0.5
 590     __ fmovd(v0, 0.53125);                             //       fmov d0, #0.53125
 591     __ fmovd(v0, 1.0);                                 //       fmov d0, #1.0
 592     __ fmovd(v0, 1.0625);                              //       fmov d0, #1.0625
 593     __ fmovd(v0, -2.0);                                //       fmov d0, #-2.0
 594     __ fmovd(v0, -2.125);                              //       fmov d0, #-2.125
 595     __ fmovd(v0, -4.0);                                //       fmov d0, #-4.0
 596     __ fmovd(v0, -4.25);                               //       fmov d0, #-4.25
 597     __ fmovd(v0, -8.0);                                //       fmov d0, #-8.0
 598     __ fmovd(v0, -8.5);                                //       fmov d0, #-8.5
 599     __ fmovd(v0, -16.0);                               //       fmov d0, #-16.0
 600     __ fmovd(v0, -17.0);                               //       fmov d0, #-17.0
 601     __ fmovd(v0, -0.125);                              //       fmov d0, #-0.125
 602     __ fmovd(v0, -0.1328125);                          //       fmov d0, #-0.1328125
 603     __ fmovd(v0, -0.25);                               //       fmov d0, #-0.25
 604     __ fmovd(v0, -0.265625);                           //       fmov d0, #-0.265625
 605     __ fmovd(v0, -0.5);                                //       fmov d0, #-0.5
 606     __ fmovd(v0, -0.53125);                            //       fmov d0, #-0.53125
 607     __ fmovd(v0, -1.0);                                //       fmov d0, #-1.0
 608     __ fmovd(v0, -1.0625);                             //       fmov d0, #-1.0625
 609 
 610     __ bind(forth);
 611 
 612 /*
 613 aarch64ops.o:     file format elf64-littleaarch64
 614 
 615 
 616 Disassembly of section .text:
 617 
 618 0000000000000000 <back>:
 619    0:   8b0772d3        add     x19, x22, x7, lsl #28
 620    4:   cb4a3570        sub     x16, x11, x10, lsr #13
 621    8:   ab9c09bb        adds    x27, x13, x28, asr #2
 622    c:   eb9aa794        subs    x20, x28, x26, asr #41
 623   10:   0b934e68        add     w8, w19, w19, asr #19
 624   14:   4b0a3924        sub     w4, w9, w10, lsl #14
 625   18:   2b1e3568        adds    w8, w11, w30, lsl #13
 626   1c:   6b132720        subs    w0, w25, w19, lsl #9
 627   20:   8a154c14        and     x20, x0, x21, lsl #19
 628   24:   aa1445d5        orr     x21, x14, x20, lsl #17
 629   28:   ca01cf99        eor     x25, x28, x1, lsl #51
 630   2c:   ea8b3f6a        ands    x10, x27, x11, asr #15
 631   30:   0a8c5cb9        and     w25, w5, w12, asr #23
 632   34:   2a4a11d2        orr     w18, w14, w10, lsr #4
 633   38:   4a855aa4        eor     w4, w21, w5, asr #22
 634   3c:   6a857415        ands    w21, w0, w5, asr #29
 635   40:   8aa697da        bic     x26, x30, x6, asr #37
 636   44:   aa6d7423        orn     x3, x1, x13, lsr #29
 637   48:   ca29bf80        eon     x0, x28, x9, lsl #47
 638   4c:   ea3cb8bd        bics    x29, x5, x28, lsl #46
 639   50:   0a675249        bic     w9, w18, w7, lsr #20
 640   54:   2ab961ba        orn     w26, w13, w25, asr #24
 641   58:   4a331899        eon     w25, w4, w19, lsl #6
 642   5c:   6a646345        bics    w5, w26, w4, lsr #24
 643   60:   11055267        add     w7, w19, #0x154
 644   64:   31064408        adds    w8, w0, #0x191
 645   68:   51028e9d        sub     w29, w20, #0xa3
 646   6c:   710bdee8        subs    w8, w23, #0x2f7
 647   70:   91082d81        add     x1, x12, #0x20b
 648   74:   b106a962        adds    x2, x11, #0x1aa
 649   78:   d10b33ae        sub     x14, x29, #0x2cc
 650   7c:   f10918ab        subs    x11, x5, #0x246
 651   80:   121102d7        and     w23, w22, #0x8000
 652   84:   3204cd44        orr     w4, w10, #0xf0f0f0f0
 653   88:   5204cf00        eor     w0, w24, #0xf0f0f0f0
 654   8c:   72099fb3        ands    w19, w29, #0x7f807f80
 655   90:   92729545        and     x5, x10, #0xfffffffffc000
 656   94:   b20e37cc        orr     x12, x30, #0xfffc0000fffc0000
 657   98:   d27c34be        eor     x30, x5, #0x3fff0
 658   9c:   f27e4efa        ands    x26, x23, #0x3ffffc
 659   a0:   14000000        b       a0 <back+0xa0>
 660   a4:   17ffffd7        b       0 <back>
 661   a8:   1400017f        b       6a4 <forth>
 662   ac:   94000000        bl      ac <back+0xac>
 663   b0:   97ffffd4        bl      0 <back>
 664   b4:   9400017c        bl      6a4 <forth>
 665   b8:   3400000c        cbz     w12, b8 <back+0xb8>
 666   bc:   34fffa2c        cbz     w12, 0 <back>
 667   c0:   34002f2c        cbz     w12, 6a4 <forth>
 668   c4:   35000014        cbnz    w20, c4 <back+0xc4>
 669   c8:   35fff9d4        cbnz    w20, 0 <back>
 670   cc:   35002ed4        cbnz    w20, 6a4 <forth>
 671   d0:   b400000c        cbz     x12, d0 <back+0xd0>
 672   d4:   b4fff96c        cbz     x12, 0 <back>
 673   d8:   b4002e6c        cbz     x12, 6a4 <forth>
 674   dc:   b5000018        cbnz    x24, dc <back+0xdc>
 675   e0:   b5fff918        cbnz    x24, 0 <back>
 676   e4:   b5002e18        cbnz    x24, 6a4 <forth>
 677   e8:   10000006        adr     x6, e8 <back+0xe8>
 678   ec:   10fff8a6        adr     x6, 0 <back>
 679   f0:   10002da6        adr     x6, 6a4 <forth>
 680   f4:   90000015        adrp    x21, 0 <back>
 681   f8:   36080001        tbz     w1, #1, f8 <back+0xf8>
 682   fc:   360ff821        tbz     w1, #1, 0 <back>
 683  100:   36082d21        tbz     w1, #1, 6a4 <forth>
 684  104:   37480008        tbnz    w8, #9, 104 <back+0x104>
 685  108:   374ff7c8        tbnz    w8, #9, 0 <back>
 686  10c:   37482cc8        tbnz    w8, #9, 6a4 <forth>
 687  110:   128b50ec        movn    w12, #0x5a87
 688  114:   52a9ff8b        movz    w11, #0x4ffc, lsl #16
 689  118:   7281d095        movk    w21, #0xe84
 690  11c:   92edfebd        movn    x29, #0x6ff5, lsl #48
 691  120:   d28361e3        movz    x3, #0x1b0f
 692  124:   f2a4cc96        movk    x22, #0x2664, lsl #16
 693  128:   9346590c        sbfx    x12, x8, #6, #17
 694  12c:   33194f33        bfi     w19, w25, #7, #20
 695  130:   531d3d89        ubfiz   w9, w12, #3, #16
 696  134:   9350433c        sbfx    x28, x25, #16, #1
 697  138:   b34464ac        bfxil   x12, x5, #4, #22
 698  13c:   d3462140        ubfx    x0, x10, #6, #3
 699  140:   139a61a4        extr    w4, w13, w26, #24
 700  144:   93d87fd7        extr    x23, x30, x24, #31
 701  148:   54000000        b.eq    148 <back+0x148>
 702  14c:   54fff5a0        b.eq    0 <back>
 703  150:   54002aa0        b.eq    6a4 <forth>
 704  154:   54000001        b.ne    154 <back+0x154>
 705  158:   54fff541        b.ne    0 <back>
 706  15c:   54002a41        b.ne    6a4 <forth>
 707  160:   54000002        b.cs    160 <back+0x160>
 708  164:   54fff4e2        b.cs    0 <back>
 709  168:   540029e2        b.cs    6a4 <forth>
 710  16c:   54000002        b.cs    16c <back+0x16c>
 711  170:   54fff482        b.cs    0 <back>
 712  174:   54002982        b.cs    6a4 <forth>
 713  178:   54000003        b.cc    178 <back+0x178>
 714  17c:   54fff423        b.cc    0 <back>
 715  180:   54002923        b.cc    6a4 <forth>
 716  184:   54000003        b.cc    184 <back+0x184>
 717  188:   54fff3c3        b.cc    0 <back>
 718  18c:   540028c3        b.cc    6a4 <forth>
 719  190:   54000004        b.mi    190 <back+0x190>
 720  194:   54fff364        b.mi    0 <back>
 721  198:   54002864        b.mi    6a4 <forth>
 722  19c:   54000005        b.pl    19c <back+0x19c>
 723  1a0:   54fff305        b.pl    0 <back>
 724  1a4:   54002805        b.pl    6a4 <forth>
 725  1a8:   54000006        b.vs    1a8 <back+0x1a8>
 726  1ac:   54fff2a6        b.vs    0 <back>
 727  1b0:   540027a6        b.vs    6a4 <forth>
 728  1b4:   54000007        b.vc    1b4 <back+0x1b4>
 729  1b8:   54fff247        b.vc    0 <back>
 730  1bc:   54002747        b.vc    6a4 <forth>
 731  1c0:   54000008        b.hi    1c0 <back+0x1c0>
 732  1c4:   54fff1e8        b.hi    0 <back>
 733  1c8:   540026e8        b.hi    6a4 <forth>
 734  1cc:   54000009        b.ls    1cc <back+0x1cc>
 735  1d0:   54fff189        b.ls    0 <back>
 736  1d4:   54002689        b.ls    6a4 <forth>
 737  1d8:   5400000a        b.ge    1d8 <back+0x1d8>
 738  1dc:   54fff12a        b.ge    0 <back>
 739  1e0:   5400262a        b.ge    6a4 <forth>
 740  1e4:   5400000b        b.lt    1e4 <back+0x1e4>
 741  1e8:   54fff0cb        b.lt    0 <back>
 742  1ec:   540025cb        b.lt    6a4 <forth>
 743  1f0:   5400000c        b.gt    1f0 <back+0x1f0>
 744  1f4:   54fff06c        b.gt    0 <back>
 745  1f8:   5400256c        b.gt    6a4 <forth>
 746  1fc:   5400000d        b.le    1fc <back+0x1fc>
 747  200:   54fff00d        b.le    0 <back>
 748  204:   5400250d        b.le    6a4 <forth>
 749  208:   5400000e        b.al    208 <back+0x208>
 750  20c:   54ffefae        b.al    0 <back>
 751  210:   540024ae        b.al    6a4 <forth>
 752  214:   5400000f        b.nv    214 <back+0x214>
 753  218:   54ffef4f        b.nv    0 <back>
 754  21c:   5400244f        b.nv    6a4 <forth>
 755  220:   d4063721        svc     #0x31b9
 756  224:   d4035082        hvc     #0x1a84
 757  228:   d400bfe3        smc     #0x5ff
 758  22c:   d4282fc0        brk     #0x417e
 759  230:   d444c320        hlt     #0x2619
 760  234:   d503201f        nop
 761  238:   d69f03e0        eret
 762  23c:   d6bf03e0        drps
 763  240:   d5033fdf        isb
 764  244:   d5033f9f        dsb     sy
 765  248:   d5033abf        dmb     ishst
 766  24c:   d61f0040        br      x2
 767  250:   d63f00a0        blr     x5
 768  254:   c8147c55        stxr    w20, x21, [x2]
 769  258:   c805fcfd        stlxr   w5, x29, [x7]
 770  25c:   c85f7e05        ldxr    x5, [x16]
 771  260:   c85fffbb        ldaxr   x27, [x29]
 772  264:   c89fffa0        stlr    x0, [x29]
 773  268:   c8dfff95        ldar    x21, [x28]
 774  26c:   88157cf8        stxr    w21, w24, [x7]
 775  270:   8815ff9a        stlxr   w21, w26, [x28]
 776  274:   885f7cd5        ldxr    w21, [x6]
 777  278:   885fffcf        ldaxr   w15, [x30]
 778  27c:   889ffc73        stlr    w19, [x3]
 779  280:   88dffc56        ldar    w22, [x2]
 780  284:   48127c0f        stxrh   w18, w15, [x0]
 781  288:   480bff85        stlxrh  w11, w5, [x28]
 782  28c:   485f7cdd        ldxrh   w29, [x6]
 783  290:   485ffcf2        ldaxrh  w18, [x7]
 784  294:   489fff99        stlrh   w25, [x28]
 785  298:   48dffe62        ldarh   w2, [x19]
 786  29c:   080a7c3e        stxrb   w10, w30, [x1]
 787  2a0:   0814fed5        stlxrb  w20, w21, [x22]
 788  2a4:   085f7c59        ldxrb   w25, [x2]
 789  2a8:   085ffcb8        ldaxrb  w24, [x5]
 790  2ac:   089ffc70        stlrb   w16, [x3]
 791  2b0:   08dfffb6        ldarb   w22, [x29]
 792  2b4:   c87f0a68        ldxp    x8, x2, [x19]
 793  2b8:   c87fcdc7        ldaxp   x7, x19, [x14]
 794  2bc:   c82870bb        stxp    w8, x27, x28, [x5]
 795  2c0:   c825b8c8        stlxp   w5, x8, x14, [x6]
 796  2c4:   887f12d9        ldxp    w25, w4, [x22]
 797  2c8:   887fb9ed        ldaxp   w13, w14, [x15]
 798  2cc:   8834215a        stxp    w20, w26, w8, [x10]
 799  2d0:   8837ca52        stlxp   w23, w18, w18, [x18]
 800  2d4:   f806317e        str     x30, [x11,#99]
 801  2d8:   b81b3337        str     w23, [x25,#-77]
 802  2dc:   39000dc2        strb    w2, [x14,#3]
 803  2e0:   78005149        strh    w9, [x10,#5]
 804  2e4:   f84391f4        ldr     x20, [x15,#57]
 805  2e8:   b85b220c        ldr     w12, [x16,#-78]
 806  2ec:   385fd356        ldrb    w22, [x26,#-3]
 807  2f0:   785d127e        ldrh    w30, [x19,#-47]
 808  2f4:   389f4149        ldrsb   x9, [x10,#-12]
 809  2f8:   79801e3c        ldrsh   x28, [x17,#14]
 810  2fc:   79c014a3        ldrsh   w3, [x5,#10]
 811  300:   b89a5231        ldrsw   x17, [x17,#-91]
 812  304:   fc5ef282        ldr     d2, [x20,#-17]
 813  308:   bc5f60f6        ldr     s22, [x7,#-10]
 814  30c:   fc12125e        str     d30, [x18,#-223]
 815  310:   bc0152cd        str     s13, [x22,#21]
 816  314:   f8190e49        str     x9, [x18,#-112]!
 817  318:   b800befd        str     w29, [x23,#11]!
 818  31c:   381ffd92        strb    w18, [x12,#-1]!
 819  320:   781e9e90        strh    w16, [x20,#-23]!
 820  324:   f8409fa3        ldr     x3, [x29,#9]!
 821  328:   b8413c79        ldr     w25, [x3,#19]!
 822  32c:   385fffa1        ldrb    w1, [x29,#-1]!
 823  330:   785c7fa8        ldrh    w8, [x29,#-57]!
 824  334:   389f3dc5        ldrsb   x5, [x14,#-13]!
 825  338:   78801f6a        ldrsh   x10, [x27,#1]!
 826  33c:   78c19d4b        ldrsh   w11, [x10,#25]!
 827  340:   b89a4ec4        ldrsw   x4, [x22,#-92]!
 828  344:   fc408eeb        ldr     d11, [x23,#8]!
 829  348:   bc436e79        ldr     s25, [x19,#54]!
 830  34c:   fc152ce1        str     d1, [x7,#-174]!
 831  350:   bc036f28        str     s8, [x25,#54]!
 832  354:   f8025565        str     x5, [x11],#37
 833  358:   b80135f8        str     w24, [x15],#19
 834  35c:   381ff74f        strb    w15, [x26],#-1
 835  360:   781fa652        strh    w18, [x18],#-6
 836  364:   f851a447        ldr     x7, [x2],#-230
 837  368:   b85e557b        ldr     w27, [x11],#-27
 838  36c:   385e7472        ldrb    w18, [x3],#-25
 839  370:   785e070a        ldrh    w10, [x24],#-32
 840  374:   38804556        ldrsb   x22, [x10],#4
 841  378:   78819591        ldrsh   x17, [x12],#25
 842  37c:   78dc24e8        ldrsh   w8, [x7],#-62
 843  380:   b89cd6d7        ldrsw   x23, [x22],#-51
 844  384:   fc430738        ldr     d24, [x25],#48
 845  388:   bc5f6595        ldr     s21, [x12],#-10
 846  38c:   fc1225b2        str     d18, [x13],#-222
 847  390:   bc1d7430        str     s16, [x1],#-41
 848  394:   f82fcac2        str     x2, [x22,w15,sxtw]
 849  398:   b83d6a02        str     w2, [x16,x29]
 850  39c:   382e5a54        strb    w20, [x18,w14,uxtw #0]
 851  3a0:   7834fa66        strh    w6, [x19,x20,sxtx #1]
 852  3a4:   f86ecbae        ldr     x14, [x29,w14,sxtw]
 853  3a8:   b86cda90        ldr     w16, [x20,w12,sxtw #2]
 854  3ac:   3860d989        ldrb    w9, [x12,w0,sxtw #0]
 855  3b0:   78637a2c        ldrh    w12, [x17,x3,lsl #1]
 856  3b4:   38a3fa22        ldrsb   x2, [x17,x3,sxtx #0]
 857  3b8:   78b15827        ldrsh   x7, [x1,w17,uxtw #1]
 858  3bc:   78f2d9f9        ldrsh   w25, [x15,w18,sxtw #1]
 859  3c0:   b8ac6ab7        ldrsw   x23, [x21,x12]
 860  3c4:   fc6879a5        ldr     d5, [x13,x8,lsl #3]
 861  3c8:   bc767943        ldr     s3, [x10,x22,lsl #2]
 862  3cc:   fc3bc84e        str     d14, [x2,w27,sxtw]
 863  3d0:   bc3968d4        str     s20, [x6,x25]
 864  3d4:   f91fc0fe        str     x30, [x7,#16256]
 865  3d8:   b91da50f        str     w15, [x8,#7588]
 866  3dc:   391d280b        strb    w11, [x0,#1866]
 867  3e0:   791d2e23        strh    w3, [x17,#3734]
 868  3e4:   f95bc8e2        ldr     x2, [x7,#14224]
 869  3e8:   b95ce525        ldr     w5, [x9,#7396]
 870  3ec:   395ae53c        ldrb    w28, [x9,#1721]
 871  3f0:   795c9282        ldrh    w2, [x20,#3656]
 872  3f4:   399d7dd6        ldrsb   x22, [x14,#1887]
 873  3f8:   799fe008        ldrsh   x8, [x0,#4080]
 874  3fc:   79de9bc0        ldrsh   w0, [x30,#3916]
 875  400:   b99aae78        ldrsw   x24, [x19,#6828]
 876  404:   fd597598        ldr     d24, [x12,#13032]
 877  408:   bd5d1d08        ldr     s8, [x8,#7452]
 878  40c:   fd1f3dea        str     d10, [x15,#15992]
 879  410:   bd1a227a        str     s26, [x19,#6688]
 880  414:   5800148a        ldr     x10, 6a4 <forth>
 881  418:   18000003        ldr     w3, 418 <back+0x418>
 882  41c:   f88092e0        prfm    pldl1keep, [x23,#9]
 883  420:   d8ffdf00        prfm    pldl1keep, 0 <back>
 884  424:   f8a84860        prfm    pldl1keep, [x3,w8,uxtw]
 885  428:   f99d7560        prfm    pldl1keep, [x11,#15080]
 886  42c:   1a1c012d        adc     w13, w9, w28
 887  430:   3a1c027b        adcs    w27, w19, w28
 888  434:   5a060253        sbc     w19, w18, w6
 889  438:   7a03028e        sbcs    w14, w20, w3
 890  43c:   9a0801d0        adc     x16, x14, x8
 891  440:   ba0803a0        adcs    x0, x29, x8
 892  444:   da140308        sbc     x8, x24, x20
 893  448:   fa00038c        sbcs    x12, x28, x0
 894  44c:   0b3010d7        add     w23, w6, w16, uxtb #4
 895  450:   2b37ab39        adds    w25, w25, w23, sxth #2
 896  454:   cb2466da        sub     x26, x22, x4, uxtx #1
 897  458:   6b33efb1        subs    w17, w29, w19, sxtx #3
 898  45c:   8b350fcb        add     x11, x30, w21, uxtb #3
 899  460:   ab208a70        adds    x16, x19, w0, sxtb #2
 900  464:   cb39e52b        sub     x11, x9, x25, sxtx #1
 901  468:   eb2c9291        subs    x17, x20, w12, sxtb #4
 902  46c:   3a4bd1a3        ccmn    w13, w11, #0x3, le
 903  470:   7a4c81a2        ccmp    w13, w12, #0x2, hi
 904  474:   ba42106c        ccmn    x3, x2, #0xc, ne
 905  478:   fa5560e3        ccmp    x7, x21, #0x3, vs
 906  47c:   3a4e3844        ccmn    w2, #0xe, #0x4, cc
 907  480:   7a515a26        ccmp    w17, #0x11, #0x6, pl
 908  484:   ba4c2940        ccmn    x10, #0xc, #0x0, cs
 909  488:   fa52aaae        ccmp    x21, #0x12, #0xe, ge
 910  48c:   1a8cc1b5        csel    w21, w13, w12, gt
 911  490:   1a8f976a        csinc   w10, w27, w15, ls
 912  494:   5a8981a0        csinv   w0, w13, w9, hi
 913  498:   5a9a6492        csneg   w18, w4, w26, vs
 914  49c:   9a8793ac        csel    x12, x29, x7, ls
 915  4a0:   9a9474e6        csinc   x6, x7, x20, vc
 916  4a4:   da83d2b6        csinv   x22, x21, x3, le
 917  4a8:   da9b9593        csneg   x19, x12, x27, ls
 918  4ac:   5ac00200        rbit    w0, w16
 919  4b0:   5ac006f1        rev16   w17, w23
 920  4b4:   5ac009d1        rev     w17, w14
 921  4b8:   5ac013d8        clz     w24, w30
 922  4bc:   5ac016d8        cls     w24, w22
 923  4c0:   dac00223        rbit    x3, x17
 924  4c4:   dac005ac        rev16   x12, x13
 925  4c8:   dac00ac9        rev32   x9, x22
 926  4cc:   dac00c00        rev     x0, x0
 927  4d0:   dac01205        clz     x5, x16
 928  4d4:   dac016d9        cls     x25, x22
 929  4d8:   1ac0089d        udiv    w29, w4, w0
 930  4dc:   1add0fa0        sdiv    w0, w29, w29
 931  4e0:   1ad52225        lsl     w5, w17, w21
 932  4e4:   1ad22529        lsr     w9, w9, w18
 933  4e8:   1ac82b61        asr     w1, w27, w8
 934  4ec:   1acd2e92        ror     w18, w20, w13
 935  4f0:   9acc0b28        udiv    x8, x25, x12
 936  4f4:   9adc0ca7        sdiv    x7, x5, x28
 937  4f8:   9adb2225        lsl     x5, x17, x27
 938  4fc:   9ad42757        lsr     x23, x26, x20
 939  500:   9adc291c        asr     x28, x8, x28
 940  504:   9ac42fa3        ror     x3, x29, x4
 941  508:   1b1a55d1        madd    w17, w14, w26, w21
 942  50c:   1b0bafc1        msub    w1, w30, w11, w11
 943  510:   9b067221        madd    x1, x17, x6, x28
 944  514:   9b1ea0de        msub    x30, x6, x30, x8
 945  518:   9b2e20d5        smaddl  x21, w6, w14, x8
 946  51c:   9b38cd4a        smsubl  x10, w10, w24, x19
 947  520:   9bae6254        umaddl  x20, w18, w14, x24
 948  524:   9ba59452        umsubl  x18, w2, w5, x5
 949  528:   1e2d0a48        fmul    s8, s18, s13
 950  52c:   1e3c19c2        fdiv    s2, s14, s28
 951  530:   1e3c298f        fadd    s15, s12, s28
 952  534:   1e213980        fsub    s0, s12, s1
 953  538:   1e240baf        fmul    s15, s29, s4
 954  53c:   1e77082c        fmul    d12, d1, d23
 955  540:   1e72191b        fdiv    d27, d8, d18
 956  544:   1e6b2a97        fadd    d23, d20, d11
 957  548:   1e723988        fsub    d8, d12, d18
 958  54c:   1e770b1a        fmul    d26, d24, d23
 959  550:   1f0d66f5        fmadd   s21, s23, s13, s25
 960  554:   1f01b956        fmsub   s22, s10, s1, s14
 961  558:   1f227a8e        fnmadd  s14, s20, s2, s30
 962  55c:   1f365ba7        fnmadd  s7, s29, s22, s22
 963  560:   1f4f14ad        fmadd   d13, d5, d15, d5
 964  564:   1f45a98e        fmsub   d14, d12, d5, d10
 965  568:   1f60066a        fnmadd  d10, d19, d0, d1
 966  56c:   1f620054        fnmadd  d20, d2, d2, d0
 967  570:   1e204139        fmov    s25, s9
 968  574:   1e20c094        fabs    s20, s4
 969  578:   1e214363        fneg    s3, s27
 970  57c:   1e21c041        fsqrt   s1, s2
 971  580:   1e22c01e        fcvt    d30, s0
 972  584:   1e60408c        fmov    d12, d4
 973  588:   1e60c361        fabs    d1, d27
 974  58c:   1e6142c8        fneg    d8, d22
 975  590:   1e61c16b        fsqrt   d11, d11
 976  594:   1e624396        fcvt    s22, d28
 977  598:   1e3802dc        fcvtzs  w28, s22
 978  59c:   9e380374        fcvtzs  x20, s27
 979  5a0:   1e78000e        fcvtzs  w14, d0
 980  5a4:   9e78017a        fcvtzs  x26, d11
 981  5a8:   1e2202dc        scvtf   s28, w22
 982  5ac:   9e220150        scvtf   s16, x10
 983  5b0:   1e6202a8        scvtf   d8, w21
 984  5b4:   9e620395        scvtf   d21, x28
 985  5b8:   1e260318        fmov    w24, s24
 986  5bc:   9e660268        fmov    x8, d19
 987  5c0:   1e270188        fmov    s8, w12
 988  5c4:   9e6700e6        fmov    d6, x7
 989  5c8:   1e3023c0        fcmp    s30, s16
 990  5cc:   1e6b2320        fcmp    d25, d11
 991  5d0:   1e202168        fcmp    s11, #0.0
 992  5d4:   1e602168        fcmp    d11, #0.0
 993  5d8:   2910323d        stp     w29, w12, [x17,#128]
 994  5dc:   297449d6        ldp     w22, w18, [x14,#-96]
 995  5e0:   6948402b        ldpsw   x11, x16, [x1,#64]
 996  5e4:   a9072f40        stp     x0, x11, [x26,#112]
 997  5e8:   a9410747        ldp     x7, x1, [x26,#16]
 998  5ec:   29801f0a        stp     w10, w7, [x24,#0]!
 999  5f0:   29e07307        ldp     w7, w28, [x24,#-256]!
1000  5f4:   69e272b9        ldpsw   x25, x28, [x21,#-240]!
1001  5f8:   a9bf49d4        stp     x20, x18, [x14,#-16]!
1002  5fc:   a9c529a8        ldp     x8, x10, [x13,#80]!
1003  600:   28b0605a        stp     w26, w24, [x2],#-128
1004  604:   28e866a2        ldp     w2, w25, [x21],#-192
1005  608:   68ee0ab1        ldpsw   x17, x2, [x21],#-144
1006  60c:   a886296c        stp     x12, x10, [x11],#96
1007  610:   a8fe1a38        ldp     x24, x6, [x17],#-32
1008  614:   282479c3        stnp    w3, w30, [x14,#-224]
1009  618:   286e534f        ldnp    w15, w20, [x26,#-144]
1010  61c:   a8386596        stnp    x22, x25, [x12,#-128]
1011  620:   a8755a3b        ldnp    x27, x22, [x17,#-176]
1012  624:   1e601000        fmov    d0, #2.000000000000000000e+00
1013  628:   1e603000        fmov    d0, #2.125000000000000000e+00
1014  62c:   1e621000        fmov    d0, #4.000000000000000000e+00
1015  630:   1e623000        fmov    d0, #4.250000000000000000e+00
1016  634:   1e641000        fmov    d0, #8.000000000000000000e+00
1017  638:   1e643000        fmov    d0, #8.500000000000000000e+00
1018  63c:   1e661000        fmov    d0, #1.600000000000000000e+01
1019  640:   1e663000        fmov    d0, #1.700000000000000000e+01
1020  644:   1e681000        fmov    d0, #1.250000000000000000e-01
1021  648:   1e683000        fmov    d0, #1.328125000000000000e-01
1022  64c:   1e6a1000        fmov    d0, #2.500000000000000000e-01
1023  650:   1e6a3000        fmov    d0, #2.656250000000000000e-01
1024  654:   1e6c1000        fmov    d0, #5.000000000000000000e-01
1025  658:   1e6c3000        fmov    d0, #5.312500000000000000e-01
1026  65c:   1e6e1000        fmov    d0, #1.000000000000000000e+00
1027  660:   1e6e3000        fmov    d0, #1.062500000000000000e+00
1028  664:   1e701000        fmov    d0, #-2.000000000000000000e+00
1029  668:   1e703000        fmov    d0, #-2.125000000000000000e+00
1030  66c:   1e721000        fmov    d0, #-4.000000000000000000e+00
1031  670:   1e723000        fmov    d0, #-4.250000000000000000e+00
1032  674:   1e741000        fmov    d0, #-8.000000000000000000e+00
1033  678:   1e743000        fmov    d0, #-8.500000000000000000e+00
1034  67c:   1e761000        fmov    d0, #-1.600000000000000000e+01
1035  680:   1e763000        fmov    d0, #-1.700000000000000000e+01
1036  684:   1e781000        fmov    d0, #-1.250000000000000000e-01
1037  688:   1e783000        fmov    d0, #-1.328125000000000000e-01
1038  68c:   1e7a1000        fmov    d0, #-2.500000000000000000e-01
1039  690:   1e7a3000        fmov    d0, #-2.656250000000000000e-01
1040  694:   1e7c1000        fmov    d0, #-5.000000000000000000e-01
1041  698:   1e7c3000        fmov    d0, #-5.312500000000000000e-01
1042  69c:   1e7e1000        fmov    d0, #-1.000000000000000000e+00
1043  6a0:   1e7e3000        fmov    d0, #-1.062500000000000000e+00
1044  */
1045 
1046   static const unsigned int insns[] =
1047   {
1048     0x8b0772d3,     0xcb4a3570,     0xab9c09bb,     0xeb9aa794,
1049     0x0b934e68,     0x4b0a3924,     0x2b1e3568,     0x6b132720,
1050     0x8a154c14,     0xaa1445d5,     0xca01cf99,     0xea8b3f6a,
1051     0x0a8c5cb9,     0x2a4a11d2,     0x4a855aa4,     0x6a857415,
1052     0x8aa697da,     0xaa6d7423,     0xca29bf80,     0xea3cb8bd,
1053     0x0a675249,     0x2ab961ba,     0x4a331899,     0x6a646345,
1054     0x11055267,     0x31064408,     0x51028e9d,     0x710bdee8,
1055     0x91082d81,     0xb106a962,     0xd10b33ae,     0xf10918ab,
1056     0x121102d7,     0x3204cd44,     0x5204cf00,     0x72099fb3,
1057     0x92729545,     0xb20e37cc,     0xd27c34be,     0xf27e4efa,
1058     0x14000000,     0x17ffffd7,     0x1400017f,     0x94000000,
1059     0x97ffffd4,     0x9400017c,     0x3400000c,     0x34fffa2c,
1060     0x34002f2c,     0x35000014,     0x35fff9d4,     0x35002ed4,
1061     0xb400000c,     0xb4fff96c,     0xb4002e6c,     0xb5000018,
1062     0xb5fff918,     0xb5002e18,     0x10000006,     0x10fff8a6,
1063     0x10002da6,     0x90000015,     0x36080001,     0x360ff821,
1064     0x36082d21,     0x37480008,     0x374ff7c8,     0x37482cc8,
1065     0x128b50ec,     0x52a9ff8b,     0x7281d095,     0x92edfebd,
1066     0xd28361e3,     0xf2a4cc96,     0x9346590c,     0x33194f33,
1067     0x531d3d89,     0x9350433c,     0xb34464ac,     0xd3462140,
1068     0x139a61a4,     0x93d87fd7,     0x54000000,     0x54fff5a0,
1069     0x54002aa0,     0x54000001,     0x54fff541,     0x54002a41,
1070     0x54000002,     0x54fff4e2,     0x540029e2,     0x54000002,
1071     0x54fff482,     0x54002982,     0x54000003,     0x54fff423,
1072     0x54002923,     0x54000003,     0x54fff3c3,     0x540028c3,
1073     0x54000004,     0x54fff364,     0x54002864,     0x54000005,
1074     0x54fff305,     0x54002805,     0x54000006,     0x54fff2a6,
1075     0x540027a6,     0x54000007,     0x54fff247,     0x54002747,
1076     0x54000008,     0x54fff1e8,     0x540026e8,     0x54000009,
1077     0x54fff189,     0x54002689,     0x5400000a,     0x54fff12a,
1078     0x5400262a,     0x5400000b,     0x54fff0cb,     0x540025cb,
1079     0x5400000c,     0x54fff06c,     0x5400256c,     0x5400000d,
1080     0x54fff00d,     0x5400250d,     0x5400000e,     0x54ffefae,
1081     0x540024ae,     0x5400000f,     0x54ffef4f,     0x5400244f,
1082     0xd4063721,     0xd4035082,     0xd400bfe3,     0xd4282fc0,
1083     0xd444c320,     0xd503201f,     0xd69f03e0,     0xd6bf03e0,
1084     0xd5033fdf,     0xd5033f9f,     0xd5033abf,     0xd61f0040,
1085     0xd63f00a0,     0xc8147c55,     0xc805fcfd,     0xc85f7e05,
1086     0xc85fffbb,     0xc89fffa0,     0xc8dfff95,     0x88157cf8,
1087     0x8815ff9a,     0x885f7cd5,     0x885fffcf,     0x889ffc73,
1088     0x88dffc56,     0x48127c0f,     0x480bff85,     0x485f7cdd,
1089     0x485ffcf2,     0x489fff99,     0x48dffe62,     0x080a7c3e,
1090     0x0814fed5,     0x085f7c59,     0x085ffcb8,     0x089ffc70,
1091     0x08dfffb6,     0xc87f0a68,     0xc87fcdc7,     0xc82870bb,
1092     0xc825b8c8,     0x887f12d9,     0x887fb9ed,     0x8834215a,
1093     0x8837ca52,     0xf806317e,     0xb81b3337,     0x39000dc2,
1094     0x78005149,     0xf84391f4,     0xb85b220c,     0x385fd356,
1095     0x785d127e,     0x389f4149,     0x79801e3c,     0x79c014a3,
1096     0xb89a5231,     0xfc5ef282,     0xbc5f60f6,     0xfc12125e,
1097     0xbc0152cd,     0xf8190e49,     0xb800befd,     0x381ffd92,
1098     0x781e9e90,     0xf8409fa3,     0xb8413c79,     0x385fffa1,
1099     0x785c7fa8,     0x389f3dc5,     0x78801f6a,     0x78c19d4b,
1100     0xb89a4ec4,     0xfc408eeb,     0xbc436e79,     0xfc152ce1,
1101     0xbc036f28,     0xf8025565,     0xb80135f8,     0x381ff74f,
1102     0x781fa652,     0xf851a447,     0xb85e557b,     0x385e7472,
1103     0x785e070a,     0x38804556,     0x78819591,     0x78dc24e8,
1104     0xb89cd6d7,     0xfc430738,     0xbc5f6595,     0xfc1225b2,
1105     0xbc1d7430,     0xf82fcac2,     0xb83d6a02,     0x382e5a54,
1106     0x7834fa66,     0xf86ecbae,     0xb86cda90,     0x3860d989,
1107     0x78637a2c,     0x38a3fa22,     0x78b15827,     0x78f2d9f9,
1108     0xb8ac6ab7,     0xfc6879a5,     0xbc767943,     0xfc3bc84e,
1109     0xbc3968d4,     0xf91fc0fe,     0xb91da50f,     0x391d280b,
1110     0x791d2e23,     0xf95bc8e2,     0xb95ce525,     0x395ae53c,
1111     0x795c9282,     0x399d7dd6,     0x799fe008,     0x79de9bc0,
1112     0xb99aae78,     0xfd597598,     0xbd5d1d08,     0xfd1f3dea,
1113     0xbd1a227a,     0x5800148a,     0x18000003,     0xf88092e0,
1114     0xd8ffdf00,     0xf8a84860,     0xf99d7560,     0x1a1c012d,
1115     0x3a1c027b,     0x5a060253,     0x7a03028e,     0x9a0801d0,
1116     0xba0803a0,     0xda140308,     0xfa00038c,     0x0b3010d7,
1117     0x2b37ab39,     0xcb2466da,     0x6b33efb1,     0x8b350fcb,
1118     0xab208a70,     0xcb39e52b,     0xeb2c9291,     0x3a4bd1a3,
1119     0x7a4c81a2,     0xba42106c,     0xfa5560e3,     0x3a4e3844,
1120     0x7a515a26,     0xba4c2940,     0xfa52aaae,     0x1a8cc1b5,
1121     0x1a8f976a,     0x5a8981a0,     0x5a9a6492,     0x9a8793ac,
1122     0x9a9474e6,     0xda83d2b6,     0xda9b9593,     0x5ac00200,
1123     0x5ac006f1,     0x5ac009d1,     0x5ac013d8,     0x5ac016d8,
1124     0xdac00223,     0xdac005ac,     0xdac00ac9,     0xdac00c00,
1125     0xdac01205,     0xdac016d9,     0x1ac0089d,     0x1add0fa0,
1126     0x1ad52225,     0x1ad22529,     0x1ac82b61,     0x1acd2e92,
1127     0x9acc0b28,     0x9adc0ca7,     0x9adb2225,     0x9ad42757,
1128     0x9adc291c,     0x9ac42fa3,     0x1b1a55d1,     0x1b0bafc1,
1129     0x9b067221,     0x9b1ea0de,     0x9b2e20d5,     0x9b38cd4a,
1130     0x9bae6254,     0x9ba59452,     0x1e2d0a48,     0x1e3c19c2,
1131     0x1e3c298f,     0x1e213980,     0x1e240baf,     0x1e77082c,
1132     0x1e72191b,     0x1e6b2a97,     0x1e723988,     0x1e770b1a,
1133     0x1f0d66f5,     0x1f01b956,     0x1f227a8e,     0x1f365ba7,
1134     0x1f4f14ad,     0x1f45a98e,     0x1f60066a,     0x1f620054,
1135     0x1e204139,     0x1e20c094,     0x1e214363,     0x1e21c041,
1136     0x1e22c01e,     0x1e60408c,     0x1e60c361,     0x1e6142c8,
1137     0x1e61c16b,     0x1e624396,     0x1e3802dc,     0x9e380374,
1138     0x1e78000e,     0x9e78017a,     0x1e2202dc,     0x9e220150,
1139     0x1e6202a8,     0x9e620395,     0x1e260318,     0x9e660268,
1140     0x1e270188,     0x9e6700e6,     0x1e3023c0,     0x1e6b2320,
1141     0x1e202168,     0x1e602168,     0x2910323d,     0x297449d6,
1142     0x6948402b,     0xa9072f40,     0xa9410747,     0x29801f0a,
1143     0x29e07307,     0x69e272b9,     0xa9bf49d4,     0xa9c529a8,
1144     0x28b0605a,     0x28e866a2,     0x68ee0ab1,     0xa886296c,
1145     0xa8fe1a38,     0x282479c3,     0x286e534f,     0xa8386596,
1146     0xa8755a3b,     0x1e601000,     0x1e603000,     0x1e621000,
1147     0x1e623000,     0x1e641000,     0x1e643000,     0x1e661000,
1148     0x1e663000,     0x1e681000,     0x1e683000,     0x1e6a1000,
1149     0x1e6a3000,     0x1e6c1000,     0x1e6c3000,     0x1e6e1000,
1150     0x1e6e3000,     0x1e701000,     0x1e703000,     0x1e721000,
1151     0x1e723000,     0x1e741000,     0x1e743000,     0x1e761000,
1152     0x1e763000,     0x1e781000,     0x1e783000,     0x1e7a1000,
1153     0x1e7a3000,     0x1e7c1000,     0x1e7c3000,     0x1e7e1000,
1154     0x1e7e3000,
1155   };
1156 // END  Generated code -- do not edit
1157 
1158   {
1159     bool ok = true;
1160     unsigned int *insns1 = (unsigned int *)entry;
1161     for (unsigned int i = 0; i < sizeof insns / sizeof insns[0]; i++) {
1162       if (insns[i] != insns1[i]) {
1163         ok = false;
1164         printf("Ours:\n");
1165         Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
1166         printf("Theirs:\n");
1167         Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
1168         printf("\n");
1169       }
1170     }
1171     assert(ok, "Assembler smoke test failed");
1172   }
1173 
1174 #ifndef PRODUCT
1175 
1176   address PC = __ pc();
1177   __ ld1(v0, __ T16B, Address(r16)); // No offset
1178   __ ld1(v0, __ T16B, __ post(r16, 0)); // Post-index
1179   __ ld1(v0, __ T16B, Address(r16, r17)); //
1180 
1181 
1182 #endif // PRODUCT
1183 #endif // ASSERT
1184 }
1185 
1186 #undef __
1187 
1188 void Assembler::emit_data64(jlong data,
1189                             relocInfo::relocType rtype,
1190                             int format) {
1191   if (rtype == relocInfo::none) {
1192     emit_int64(data);
1193   } else {
1194     emit_data64(data, Relocation::spec_simple(rtype), format);
1195   }
1196 }
1197 
1198 void Assembler::emit_data64(jlong data,
1199                             RelocationHolder const& rspec,
1200                             int format) {
1201 
1202   assert(inst_mark() != NULL, "must be inside InstructionMark");
1203   // Do not use AbstractAssembler::relocate, which is not intended for
1204   // embedded words.  Instead, relocate to the enclosing instruction.
1205   code_section()->relocate(inst_mark(), rspec, format);
1206   emit_int64(data);
1207 }
1208 
1209 extern "C" {
1210   void das(uint64_t start, int len) {
1211     ResourceMark rm;
1212     len <<= 2;
1213     if (len < 0)
1214       Disassembler::decode((address)start + len, (address)start);
1215     else
1216       Disassembler::decode((address)start, (address)start + len);
1217   }
1218 
1219   JNIEXPORT void das1(unsigned long insn) {
1220     das(insn, 1);
1221   }
1222 }
1223 
1224 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1225 
1226 #define __ as->
1227 
1228 void Address::lea(MacroAssembler *as, Register r) const {
1229   Relocation* reloc = _rspec.reloc();
1230   relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1231 
1232   switch(_mode) {
1233   case base_plus_offset: {
1234     if (_offset == 0 && _base == r) // it's a nop
1235       break;
1236     if (_offset > 0)
1237       __ add(r, _base, _offset);
1238     else
1239       __ sub(r, _base, -_offset);
1240       break;
1241   }
1242   case base_plus_offset_reg: {
1243     __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1244     break;
1245   }
1246   case literal: {
1247     if (rtype == relocInfo::none)
1248       __ mov(r, target());
1249     else
1250       __ movptr(r, (uint64_t)target());
1251     break;
1252   }
1253   default:
1254     ShouldNotReachHere();
1255   }
1256 }
1257 
1258 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1259   ShouldNotReachHere();
1260 }
1261 
1262 #undef __
1263 
1264 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1265 
1266   void Assembler::adr(Register Rd, address adr) {
1267     long offset = adr - pc();
1268     int offset_lo = offset & 3;
1269     offset >>= 2;
1270     starti;
1271     f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1272     rf(Rd, 0);
1273   }
1274 
1275   void Assembler::_adrp(Register Rd, address adr) {
1276     uint64_t pc_page = (uint64_t)pc() >> 12;
1277     uint64_t adr_page = (uint64_t)adr >> 12;
1278     long offset = adr_page - pc_page;
1279     int offset_lo = offset & 3;
1280     offset >>= 2;
1281     starti;
1282     f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1283     rf(Rd, 0);
1284   }
1285 
1286 #undef starti
1287 
1288 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1289   _is_lval = false;
1290   _target = target;
1291   switch (rtype) {
1292   case relocInfo::oop_type:
1293   case relocInfo::metadata_type:
1294     // Oops are a special case. Normally they would be their own section
1295     // but in cases like icBuffer they are literals in the code stream that
1296     // we don't have a section for. We use none so that we get a literal address
1297     // which is always patchable.
1298     break;
1299   case relocInfo::external_word_type:
1300     _rspec = external_word_Relocation::spec(target);
1301     break;
1302   case relocInfo::internal_word_type:
1303     _rspec = internal_word_Relocation::spec(target);
1304     break;
1305   case relocInfo::opt_virtual_call_type:
1306     _rspec = opt_virtual_call_Relocation::spec();
1307     break;
1308   case relocInfo::static_call_type:
1309     _rspec = static_call_Relocation::spec();
1310     break;
1311   case relocInfo::runtime_call_type:
1312     _rspec = runtime_call_Relocation::spec();
1313     break;
1314   case relocInfo::poll_type:
1315   case relocInfo::poll_return_type:
1316     _rspec = Relocation::spec_simple(rtype);
1317     break;
1318   case relocInfo::none:
1319     _rspec = RelocationHolder::none;
1320     break;
1321   default:
1322     ShouldNotReachHere();
1323     break;
1324   }
1325 }
1326 
1327 void Assembler::b(const Address &dest) {
1328   code_section()->relocate(pc(), dest.rspec());
1329   b(dest.target());
1330 }
1331 
1332 void Assembler::bl(const Address &dest) {
1333   code_section()->relocate(pc(), dest.rspec());
1334   bl(dest.target());
1335 }
1336 
1337 void Assembler::adr(Register r, const Address &dest) {
1338   code_section()->relocate(pc(), dest.rspec());
1339   adr(r, dest.target());
1340 }
1341 
1342 void Assembler::br(Condition cc, Label &L) {
1343   if (L.is_bound()) {
1344     br(cc, target(L));
1345   } else {
1346     L.add_patch_at(code(), locator());
1347     br(cc, pc());
1348   }
1349 }
1350 
1351 void Assembler::wrap_label(Label &L,
1352                                  Assembler::uncond_branch_insn insn) {
1353   if (L.is_bound()) {
1354     (this->*insn)(target(L));
1355   } else {
1356     L.add_patch_at(code(), locator());
1357     (this->*insn)(pc());
1358   }
1359 }
1360 
1361 void Assembler::wrap_label(Register r, Label &L,
1362                                  compare_and_branch_insn insn) {
1363   if (L.is_bound()) {
1364     (this->*insn)(r, target(L));
1365   } else {
1366     L.add_patch_at(code(), locator());
1367     (this->*insn)(r, pc());
1368   }
1369 }
1370 
1371 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1372                                  test_and_branch_insn insn) {
1373   if (L.is_bound()) {
1374     (this->*insn)(r, bitpos, target(L));
1375   } else {
1376     L.add_patch_at(code(), locator());
1377     (this->*insn)(r, bitpos, pc());
1378   }
1379 }
1380 
1381 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1382   if (L.is_bound()) {
1383     (this->*insn)(target(L), op);
1384   } else {
1385     L.add_patch_at(code(), locator());
1386     (this->*insn)(pc(), op);
1387   }
1388 }
1389 
1390 // An "all-purpose" add/subtract immediate, per ARM documentation:
1391 // A "programmer-friendly" assembler may accept a negative immediate
1392 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1393 // requested ADD operation to a SUB, or vice versa, and then encode
1394 // the absolute value of the immediate as for uimm24.
1395 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1396                                   int negated_op) {
1397   bool sets_flags = op & 1;   // this op sets flags
1398   union {
1399     unsigned u;
1400     int imm;
1401   };
1402   u = uimm;
1403   bool shift = false;
1404   bool neg = imm < 0;
1405   if (neg) {
1406     imm = -imm;
1407     op = negated_op;
1408   }
1409   assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1410   if (imm >= (1 << 11)
1411       && ((imm >> 12) << 12 == imm)) {
1412     imm >>= 12;
1413     shift = true;
1414   }
1415   f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1416 
1417   // add/subtract immediate ops with the S bit set treat r31 as zr;
1418   // with S unset they use sp.
1419   if (sets_flags)
1420     zrf(Rd, 0);
1421   else
1422     srf(Rd, 0);
1423 
1424   srf(Rn, 5);
1425 }
1426 
1427 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1428   bool shift = false;
1429   unsigned long uimm = uabs(imm);
1430   if (uimm < (1 << 12))
1431     return true;
1432   if (uimm < (1 << 24)
1433       && ((uimm >> 12) << 12 == uimm)) {
1434     return true;
1435   }
1436   return false;
1437 }
1438 
1439 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1440   return encode_logical_immediate(is32, imm) != 0xffffffff;
1441 }
1442 
1443 static uint64_t doubleTo64Bits(jdouble d) {
1444   union {
1445     jdouble double_value;
1446     uint64_t double_bits;
1447   };
1448 
1449   double_value = d;
1450   return double_bits;
1451 }
1452 
1453 bool Assembler::operand_valid_for_float_immediate(double imm) {
1454   // If imm is all zero bits we can use ZR as the source of a
1455   // floating-point value.
1456   if (doubleTo64Bits(imm) == 0)
1457     return true;
1458 
1459   // Otherwise try to encode imm then convert the encoded value back
1460   // and make sure it's the exact same bit pattern.
1461   unsigned result = encoding_for_fp_immediate(imm);
1462   return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1463 }
1464 
1465 int AbstractAssembler::code_fill_byte() {
1466   return 0;
1467 }
1468 
1469 // n.b. this is implemented in subclass MacroAssembler
1470 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1471 
1472 
1473 // these are the functions provided by the simulator which are used to
1474 // encode and decode logical immediates and floating point immediates
1475 //
1476 //   u_int64_t logical_immediate_for_encoding(u_int32_t encoding);
1477 //
1478 //   u_int32_t encoding_for_logical_immediate(u_int64_t immediate);
1479 //
1480 //   u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp);
1481 //
1482 //   u_int32_t encoding_for_fp_immediate(float immediate);
1483 //
1484 // we currently import these from the simulator librray but the
1485 // definitions will need to be moved to here when we switch to real
1486 // hardware.
1487 
1488 // and now the routines called by the assembler which encapsulate the
1489 // above encode and decode functions
1490 
1491 uint32_t
1492 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1493 {
1494   if (is32) {
1495     /* Allow all zeros or all ones in top 32-bits, so that
1496        constant expressions like ~1 are permitted. */
1497     if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1498       return 0xffffffff;
1499     /* Replicate the 32 lower bits to the 32 upper bits.  */
1500     imm &= 0xffffffff;
1501     imm |= imm << 32;
1502   }
1503 
1504   return encoding_for_logical_immediate(imm);
1505 }
1506 
1507 unsigned Assembler::pack(double value) {
1508   float val = (float)value;
1509   unsigned result = encoding_for_fp_immediate(val);
1510   guarantee(unpack(result) == value,
1511             "Invalid floating-point immediate operand");
1512   return result;
1513 }
1514 
1515 // Packed operands for  Floating-point Move (immediate)
1516 
1517 static float unpack(unsigned value) {
1518   union {
1519     unsigned ival;
1520     float val;
1521   };
1522   ival = fp_immediate_for_encoding(value, 0);
1523   return val;
1524 }
--- EOF ---