1 /* 2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "ci/ciEnv.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "interpreter/interpreterRuntime.hpp" 33 #include "interpreter/templateInterpreterGenerator.hpp" 34 #include "memory/resourceArea.hpp" 35 #include "prims/jvm_misc.hpp" 36 #include "prims/methodHandles.hpp" 37 #include "runtime/biasedLocking.hpp" 38 #include "runtime/interfaceSupport.inline.hpp" 39 #include "runtime/objectMonitor.hpp" 40 #include "runtime/os.hpp" 41 #include "runtime/sharedRuntime.hpp" 42 #include "runtime/stubRoutines.hpp" 43 #include "utilities/hashtable.hpp" 44 #include "utilities/macros.hpp" 45 #if INCLUDE_ALL_GCS 46 #include "gc/g1/g1BarrierSet.hpp" 47 #include "gc/g1/g1CollectedHeap.inline.hpp" 48 #include "gc/g1/heapRegion.hpp" 49 #endif // INCLUDE_ALL_GCS 50 51 // Returns whether given imm has equal bit fields <0:size-1> and <size:2*size-1>. 52 inline bool Assembler::LogicalImmediate::has_equal_subpatterns(uintx imm, int size) { 53 uintx mask = right_n_bits(size); 54 uintx subpattern1 = mask_bits(imm, mask); 55 uintx subpattern2 = mask_bits(imm >> size, mask); 56 return subpattern1 == subpattern2; 57 } 58 59 // Returns least size that is a power of two from 2 to 64 with the proviso that given 60 // imm is composed of repeating patterns of this size. 61 inline int Assembler::LogicalImmediate::least_pattern_size(uintx imm) { 62 int size = BitsPerWord; 63 while (size > 2 && has_equal_subpatterns(imm, size >> 1)) { 64 size >>= 1; 65 } 66 return size; 67 } 68 69 // Returns count of set bits in given imm. Based on variable-precision SWAR algorithm. 70 inline int Assembler::LogicalImmediate::population_count(uintx x) { 71 x -= ((x >> 1) & 0x5555555555555555L); 72 x = (((x >> 2) & 0x3333333333333333L) + (x & 0x3333333333333333L)); 73 x = (((x >> 4) + x) & 0x0f0f0f0f0f0f0f0fL); 74 x += (x >> 8); 75 x += (x >> 16); 76 x += (x >> 32); 77 return(x & 0x7f); 78 } 79 80 // Let given x be <A:B> where B = 0 and least bit of A = 1. Returns <A:C>, where C is B-size set bits. 81 inline uintx Assembler::LogicalImmediate::set_least_zeroes(uintx x) { 82 return x | (x - 1); 83 } 84 85 86 #ifdef ASSERT 87 88 // Restores immediate by encoded bit masks. 89 uintx Assembler::LogicalImmediate::decode() { 90 assert (_encoded, "should be"); 91 92 int len_code = (_immN << 6) | ((~_imms) & 0x3f); 93 assert (len_code != 0, "should be"); 94 95 int len = 6; 96 while (!is_set_nth_bit(len_code, len)) len--; 97 int esize = 1 << len; 98 assert (len > 0, "should be"); 99 assert ((_is32bit ? 32 : 64) >= esize, "should be"); 100 101 int levels = right_n_bits(len); 102 int S = _imms & levels; 103 int R = _immr & levels; 104 105 assert (S != levels, "should be"); 106 107 uintx welem = right_n_bits(S + 1); 108 uintx wmask = (R == 0) ? welem : ((welem >> R) | (welem << (esize - R))); 109 110 for (int size = esize; size < 64; size <<= 1) { 111 wmask |= (wmask << size); 112 } 113 114 return wmask; 115 } 116 117 #endif 118 119 120 // Constructs LogicalImmediate by given imm. Figures out if given imm can be used in AArch64 logical 121 // instructions (AND, ANDS, EOR, ORR) and saves its encoding. 122 void Assembler::LogicalImmediate::construct(uintx imm, bool is32) { 123 _is32bit = is32; 124 125 if (is32) { 126 assert(((imm >> 32) == 0) || (((intx)imm >> 31) == -1), "32-bit immediate is out of range"); 127 128 // Replicate low 32 bits. 129 imm &= 0xffffffff; 130 imm |= imm << 32; 131 } 132 133 // All-zeroes and all-ones can not be encoded. 134 if (imm != 0 && (~imm != 0)) { 135 136 // Let LPS (least pattern size) be the least size (power of two from 2 to 64) of repeating 137 // patterns in the immediate. If immediate value can be encoded, it is encoded by pattern 138 // of exactly LPS size (due to structure of valid patterns). In order to verify 139 // that immediate value can be encoded, LPS is calculated and <LPS-1:0> bits of immediate 140 // are verified to be valid pattern. 141 int lps = least_pattern_size(imm); 142 uintx lps_mask = right_n_bits(lps); 143 144 // A valid pattern has one of the following forms: 145 // | 0 x A | 1 x B | 0 x C |, where B > 0 and C > 0, or 146 // | 1 x A | 0 x B | 1 x C |, where B > 0 and C > 0. 147 // For simplicity, the second form of the pattern is inverted into the first form. 148 bool inverted = imm & 0x1; 149 uintx pattern = (inverted ? ~imm : imm) & lps_mask; 150 151 // | 0 x A | 1 x (B + C) | 152 uintx without_least_zeroes = set_least_zeroes(pattern); 153 154 // Pattern is valid iff without least zeroes it is a power of two - 1. 155 if ((without_least_zeroes & (without_least_zeroes + 1)) == 0) { 156 157 // Count B as population count of pattern. 158 int bits_count = population_count(pattern); 159 160 // Count B+C as population count of pattern without least zeroes 161 int left_range = population_count(without_least_zeroes); 162 163 // S-prefix is a part of imms field which encodes LPS. 164 // LPS | S prefix 165 // 64 | not defined 166 // 32 | 0b0 167 // 16 | 0b10 168 // 8 | 0b110 169 // 4 | 0b1110 170 // 2 | 0b11110 171 int s_prefix = (lps == 64) ? 0 : ~set_least_zeroes(lps) & 0x3f; 172 173 // immN bit is set iff LPS == 64. 174 _immN = (lps == 64) ? 1 : 0; 175 assert (!is32 || (_immN == 0), "32-bit immediate should be encoded with zero N-bit"); 176 177 // immr is the rotation size. 178 _immr = lps + (inverted ? 0 : bits_count) - left_range; 179 180 // imms is the field that encodes bits count and S-prefix. 181 _imms = ((inverted ? (lps - bits_count) : bits_count) - 1) | s_prefix; 182 183 _encoded = true; 184 assert (decode() == imm, "illegal encoding"); 185 186 return; 187 } 188 } 189 190 _encoded = false; 191 }