1 /* 2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_Compilation.hpp" 27 #include "c1/c1_LIRAssembler.hpp" 28 #include "c1/c1_MacroAssembler.hpp" 29 #include "c1/c1_Runtime1.hpp" 30 #include "c1/c1_ValueStack.hpp" 31 #include "ci/ciArrayKlass.hpp" 32 #include "ci/ciInstance.hpp" 33 #include "gc/shared/barrierSet.hpp" 34 #include "gc/shared/cardTableModRefBS.hpp" 35 #include "gc/shared/collectedHeap.hpp" 36 #include "nativeInst_sparc.hpp" 37 #include "oops/objArrayKlass.hpp" 38 #include "runtime/jniHandles.inline.hpp" 39 #include "runtime/safepointMechanism.inline.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 42 #define __ _masm-> 43 44 45 //------------------------------------------------------------ 46 47 48 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 49 if (opr->is_constant()) { 50 LIR_Const* constant = opr->as_constant_ptr(); 51 switch (constant->type()) { 52 case T_INT: { 53 jint value = constant->as_jint(); 54 return Assembler::is_simm13(value); 55 } 56 57 default: 58 return false; 59 } 60 } 61 return false; 62 } 63 64 65 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { 66 switch (op->code()) { 67 case lir_null_check: 68 return true; 69 70 71 case lir_add: 72 case lir_ushr: 73 case lir_shr: 74 case lir_shl: 75 // integer shifts and adds are always one instruction 76 return op->result_opr()->is_single_cpu(); 77 78 79 case lir_move: { 80 LIR_Op1* op1 = op->as_Op1(); 81 LIR_Opr src = op1->in_opr(); 82 LIR_Opr dst = op1->result_opr(); 83 84 if (src == dst) { 85 NEEDS_CLEANUP; 86 // this works around a problem where moves with the same src and dst 87 // end up in the delay slot and then the assembler swallows the mov 88 // since it has no effect and then it complains because the delay slot 89 // is empty. returning false stops the optimizer from putting this in 90 // the delay slot 91 return false; 92 } 93 94 // don't put moves involving oops into the delay slot since the VerifyOops code 95 // will make it much larger than a single instruction. 96 if (VerifyOops) { 97 return false; 98 } 99 100 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || 101 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { 102 return false; 103 } 104 105 if (UseCompressedOops) { 106 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false; 107 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false; 108 } 109 110 if (UseCompressedClassPointers) { 111 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS && 112 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false; 113 } 114 115 if (dst->is_register()) { 116 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { 117 return !PatchALot; 118 } else if (src->is_single_stack()) { 119 return true; 120 } 121 } 122 123 if (src->is_register()) { 124 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { 125 return !PatchALot; 126 } else if (dst->is_single_stack()) { 127 return true; 128 } 129 } 130 131 if (dst->is_register() && 132 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || 133 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { 134 return true; 135 } 136 137 return false; 138 } 139 140 default: 141 return false; 142 } 143 ShouldNotReachHere(); 144 } 145 146 147 LIR_Opr LIR_Assembler::receiverOpr() { 148 return FrameMap::O0_oop_opr; 149 } 150 151 152 LIR_Opr LIR_Assembler::osrBufferPointer() { 153 return FrameMap::I0_opr; 154 } 155 156 157 int LIR_Assembler::initial_frame_size_in_bytes() const { 158 return in_bytes(frame_map()->framesize_in_bytes()); 159 } 160 161 162 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); 163 // we fetch the class of the receiver (O0) and compare it with the cached class. 164 // If they do not match we jump to slow case. 165 int LIR_Assembler::check_icache() { 166 int offset = __ offset(); 167 __ inline_cache_check(O0, G5_inline_cache_reg); 168 return offset; 169 } 170 171 172 void LIR_Assembler::osr_entry() { 173 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): 174 // 175 // 1. Create a new compiled activation. 176 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 177 // at the osr_bci; it is not initialized. 178 // 3. Jump to the continuation address in compiled code to resume execution. 179 180 // OSR entry point 181 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 182 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 183 ValueStack* entry_state = osr_entry->end()->state(); 184 int number_of_locks = entry_state->locks_size(); 185 186 // Create a frame for the compiled activation. 187 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 188 189 // OSR buffer is 190 // 191 // locals[nlocals-1..0] 192 // monitors[number_of_locks-1..0] 193 // 194 // locals is a direct copy of the interpreter frame so in the osr buffer 195 // so first slot in the local array is the last local from the interpreter 196 // and last slot is local[0] (receiver) from the interpreter 197 // 198 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 199 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 200 // in the interpreter frame (the method lock if a sync method) 201 202 // Initialize monitors in the compiled activation. 203 // I0: pointer to osr buffer 204 // 205 // All other registers are dead at this point and the locals will be 206 // copied into place by code emitted in the IR. 207 208 Register OSR_buf = osrBufferPointer()->as_register(); 209 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 210 int monitor_offset = BytesPerWord * method()->max_locals() + 211 (2 * BytesPerWord) * (number_of_locks - 1); 212 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 213 // the OSR buffer using 2 word entries: first the lock and then 214 // the oop. 215 for (int i = 0; i < number_of_locks; i++) { 216 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 217 #ifdef ASSERT 218 // verify the interpreter's monitor has a non-null object 219 { 220 Label L; 221 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 222 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L); 223 __ stop("locked object is NULL"); 224 __ bind(L); 225 } 226 #endif // ASSERT 227 // Copy the lock field into the compiled activation. 228 __ ld_ptr(OSR_buf, slot_offset + 0, O7); 229 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); 230 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 231 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); 232 } 233 } 234 } 235 236 237 // -------------------------------------------------------------------------------------------- 238 239 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { 240 if (!GenerateSynchronizationCode) return; 241 242 Register obj_reg = obj_opr->as_register(); 243 Register lock_reg = lock_opr->as_register(); 244 245 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 246 Register reg = mon_addr.base(); 247 int offset = mon_addr.disp(); 248 // compute pointer to BasicLock 249 if (mon_addr.is_simm13()) { 250 __ add(reg, offset, lock_reg); 251 } 252 else { 253 __ set(offset, lock_reg); 254 __ add(reg, lock_reg, lock_reg); 255 } 256 // unlock object 257 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); 258 // _slow_case_stubs->append(slow_case); 259 // temporary fix: must be created after exceptionhandler, therefore as call stub 260 _slow_case_stubs->append(slow_case); 261 if (UseFastLocking) { 262 // try inlined fast unlocking first, revert to slow locking if it fails 263 // note: lock_reg points to the displaced header since the displaced header offset is 0! 264 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 265 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 266 } else { 267 // always do slow unlocking 268 // note: the slow unlocking code could be inlined here, however if we use 269 // slow unlocking, speed doesn't matter anyway and this solution is 270 // simpler and requires less duplicated code - additionally, the 271 // slow unlocking code is the same in either case which simplifies 272 // debugging 273 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); 274 __ delayed()->nop(); 275 } 276 // done 277 __ bind(*slow_case->continuation()); 278 } 279 280 281 int LIR_Assembler::emit_exception_handler() { 282 // if the last instruction is a call (typically to do a throw which 283 // is coming at the end after block reordering) the return address 284 // must still point into the code area in order to avoid assertion 285 // failures when searching for the corresponding bci => add a nop 286 // (was bug 5/14/1999 - gri) 287 __ nop(); 288 289 // generate code for exception handler 290 ciMethod* method = compilation()->method(); 291 292 address handler_base = __ start_a_stub(exception_handler_size()); 293 294 if (handler_base == NULL) { 295 // not enough space left for the handler 296 bailout("exception handler overflow"); 297 return -1; 298 } 299 300 int offset = code_offset(); 301 302 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type); 303 __ delayed()->nop(); 304 __ should_not_reach_here(); 305 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 306 __ end_a_stub(); 307 308 return offset; 309 } 310 311 312 // Emit the code to remove the frame from the stack in the exception 313 // unwind path. 314 int LIR_Assembler::emit_unwind_handler() { 315 #ifndef PRODUCT 316 if (CommentedAssembly) { 317 _masm->block_comment("Unwind handler"); 318 } 319 #endif 320 321 int offset = code_offset(); 322 323 // Fetch the exception from TLS and clear out exception related thread state 324 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); 325 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); 326 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); 327 328 __ bind(_unwind_handler_entry); 329 __ verify_not_null_oop(O0); 330 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 331 __ mov(O0, I0); // Preserve the exception 332 } 333 334 // Preform needed unlocking 335 MonitorExitStub* stub = NULL; 336 if (method()->is_synchronized()) { 337 monitor_address(0, FrameMap::I1_opr); 338 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); 339 __ unlock_object(I3, I2, I1, *stub->entry()); 340 __ bind(*stub->continuation()); 341 } 342 343 if (compilation()->env()->dtrace_method_probes()) { 344 __ mov(G2_thread, O0); 345 __ save_thread(I1); // need to preserve thread in G2 across 346 // runtime call 347 metadata2reg(method()->constant_encoding(), O1); 348 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); 349 __ delayed()->nop(); 350 __ restore_thread(I1); 351 } 352 353 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 354 __ mov(I0, O0); // Restore the exception 355 } 356 357 // dispatch to the unwind logic 358 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); 359 __ delayed()->nop(); 360 361 // Emit the slow path assembly 362 if (stub != NULL) { 363 stub->emit_code(this); 364 } 365 366 return offset; 367 } 368 369 370 int LIR_Assembler::emit_deopt_handler() { 371 // if the last instruction is a call (typically to do a throw which 372 // is coming at the end after block reordering) the return address 373 // must still point into the code area in order to avoid assertion 374 // failures when searching for the corresponding bci => add a nop 375 // (was bug 5/14/1999 - gri) 376 __ nop(); 377 378 // generate code for deopt handler 379 ciMethod* method = compilation()->method(); 380 address handler_base = __ start_a_stub(deopt_handler_size()); 381 if (handler_base == NULL) { 382 // not enough space left for the handler 383 bailout("deopt handler overflow"); 384 return -1; 385 } 386 387 int offset = code_offset(); 388 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 389 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp 390 __ delayed()->nop(); 391 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 392 __ end_a_stub(); 393 394 return offset; 395 } 396 397 398 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 399 if (o == NULL) { 400 __ set(NULL_WORD, reg); 401 } else { 402 #ifdef ASSERT 403 { 404 ThreadInVMfromNative tiv(JavaThread::current()); 405 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop"); 406 } 407 #endif 408 int oop_index = __ oop_recorder()->find_index(o); 409 RelocationHolder rspec = oop_Relocation::spec(oop_index); 410 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created 411 } 412 } 413 414 415 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 416 // Allocate a new index in table to hold the object once it's been patched 417 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 418 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 419 420 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); 421 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 422 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 423 // NULL will be dynamically patched later and the patched value may be large. We must 424 // therefore generate the sethi/add as a placeholders 425 __ patchable_set(addrlit, reg); 426 427 patching_epilog(patch, lir_patch_normal, reg, info); 428 } 429 430 431 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { 432 __ set_metadata_constant(o, reg); 433 } 434 435 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 436 // Allocate a new index in table to hold the klass once it's been patched 437 int index = __ oop_recorder()->allocate_metadata_index(NULL); 438 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 439 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index)); 440 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 441 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 442 // NULL will be dynamically patched later and the patched value may be large. We must 443 // therefore generate the sethi/add as a placeholders 444 __ patchable_set(addrlit, reg); 445 446 patching_epilog(patch, lir_patch_normal, reg, info); 447 } 448 449 void LIR_Assembler::emit_op3(LIR_Op3* op) { 450 switch (op->code()) { 451 case lir_idiv: 452 case lir_irem: // Both idiv & irem are handled after the switch (below). 453 break; 454 case lir_fmaf: 455 __ fmadd(FloatRegisterImpl::S, 456 op->in_opr1()->as_float_reg(), 457 op->in_opr2()->as_float_reg(), 458 op->in_opr3()->as_float_reg(), 459 op->result_opr()->as_float_reg()); 460 return; 461 case lir_fmad: 462 __ fmadd(FloatRegisterImpl::D, 463 op->in_opr1()->as_double_reg(), 464 op->in_opr2()->as_double_reg(), 465 op->in_opr3()->as_double_reg(), 466 op->result_opr()->as_double_reg()); 467 return; 468 default: 469 ShouldNotReachHere(); 470 break; 471 } 472 473 // Handle idiv & irem: 474 475 Register Rdividend = op->in_opr1()->as_register(); 476 Register Rdivisor = noreg; 477 Register Rscratch = op->in_opr3()->as_register(); 478 Register Rresult = op->result_opr()->as_register(); 479 int divisor = -1; 480 481 if (op->in_opr2()->is_register()) { 482 Rdivisor = op->in_opr2()->as_register(); 483 } else { 484 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); 485 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 486 } 487 488 assert(Rdividend != Rscratch, ""); 489 assert(Rdivisor != Rscratch, ""); 490 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); 491 492 if (Rdivisor == noreg && is_power_of_2(divisor)) { 493 // convert division by a power of two into some shifts and logical operations 494 if (op->code() == lir_idiv) { 495 if (divisor == 2) { 496 __ srl(Rdividend, 31, Rscratch); 497 } else { 498 __ sra(Rdividend, 31, Rscratch); 499 __ and3(Rscratch, divisor - 1, Rscratch); 500 } 501 __ add(Rdividend, Rscratch, Rscratch); 502 __ sra(Rscratch, log2_intptr(divisor), Rresult); 503 return; 504 } else { 505 if (divisor == 2) { 506 __ srl(Rdividend, 31, Rscratch); 507 } else { 508 __ sra(Rdividend, 31, Rscratch); 509 __ and3(Rscratch, divisor - 1,Rscratch); 510 } 511 __ add(Rdividend, Rscratch, Rscratch); 512 __ andn(Rscratch, divisor - 1,Rscratch); 513 __ sub(Rdividend, Rscratch, Rresult); 514 return; 515 } 516 } 517 518 __ sra(Rdividend, 31, Rscratch); 519 __ wry(Rscratch); 520 521 add_debug_info_for_div0_here(op->info()); 522 523 if (Rdivisor != noreg) { 524 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 525 } else { 526 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 527 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 528 } 529 530 Label skip; 531 __ br(Assembler::overflowSet, true, Assembler::pn, skip); 532 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); 533 __ bind(skip); 534 535 if (op->code() == lir_irem) { 536 if (Rdivisor != noreg) { 537 __ smul(Rscratch, Rdivisor, Rscratch); 538 } else { 539 __ smul(Rscratch, divisor, Rscratch); 540 } 541 __ sub(Rdividend, Rscratch, Rresult); 542 } 543 } 544 545 546 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 547 #ifdef ASSERT 548 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 549 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 550 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 551 #endif 552 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 553 554 if (op->cond() == lir_cond_always) { 555 __ br(Assembler::always, false, Assembler::pt, *(op->label())); 556 } else if (op->code() == lir_cond_float_branch) { 557 assert(op->ublock() != NULL, "must have unordered successor"); 558 bool is_unordered = (op->ublock() == op->block()); 559 Assembler::Condition acond; 560 switch (op->cond()) { 561 case lir_cond_equal: acond = Assembler::f_equal; break; 562 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; 563 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; 564 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; 565 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; 566 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; 567 default : ShouldNotReachHere(); 568 } 569 __ fb( acond, false, Assembler::pn, *(op->label())); 570 } else { 571 assert (op->code() == lir_branch, "just checking"); 572 573 Assembler::Condition acond; 574 switch (op->cond()) { 575 case lir_cond_equal: acond = Assembler::equal; break; 576 case lir_cond_notEqual: acond = Assembler::notEqual; break; 577 case lir_cond_less: acond = Assembler::less; break; 578 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 579 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 580 case lir_cond_greater: acond = Assembler::greater; break; 581 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 582 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 583 default: ShouldNotReachHere(); 584 }; 585 586 // sparc has different condition codes for testing 32-bit 587 // vs. 64-bit values. We could always test xcc is we could 588 // guarantee that 32-bit loads always sign extended but that isn't 589 // true and since sign extension isn't free, it would impose a 590 // slight cost. 591 if (op->type() == T_INT) { 592 __ br(acond, false, Assembler::pn, *(op->label())); 593 } else 594 __ brx(acond, false, Assembler::pn, *(op->label())); 595 } 596 // The peephole pass fills the delay slot 597 } 598 599 600 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 601 Bytecodes::Code code = op->bytecode(); 602 LIR_Opr dst = op->result_opr(); 603 604 switch(code) { 605 case Bytecodes::_i2l: { 606 Register rlo = dst->as_register_lo(); 607 Register rhi = dst->as_register_hi(); 608 Register rval = op->in_opr()->as_register(); 609 __ sra(rval, 0, rlo); 610 break; 611 } 612 case Bytecodes::_i2d: 613 case Bytecodes::_i2f: { 614 bool is_double = (code == Bytecodes::_i2d); 615 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 616 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 617 FloatRegister rsrc = op->in_opr()->as_float_reg(); 618 if (rsrc != rdst) { 619 __ fmov(FloatRegisterImpl::S, rsrc, rdst); 620 } 621 __ fitof(w, rdst, rdst); 622 break; 623 } 624 case Bytecodes::_f2i:{ 625 FloatRegister rsrc = op->in_opr()->as_float_reg(); 626 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); 627 Label L; 628 // result must be 0 if value is NaN; test by comparing value to itself 629 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); 630 __ fb(Assembler::f_unordered, true, Assembler::pn, L); 631 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN 632 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); 633 // move integer result from float register to int register 634 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); 635 __ bind (L); 636 break; 637 } 638 case Bytecodes::_l2i: { 639 Register rlo = op->in_opr()->as_register_lo(); 640 Register rhi = op->in_opr()->as_register_hi(); 641 Register rdst = dst->as_register(); 642 __ sra(rlo, 0, rdst); 643 break; 644 } 645 case Bytecodes::_d2f: 646 case Bytecodes::_f2d: { 647 bool is_double = (code == Bytecodes::_f2d); 648 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); 649 LIR_Opr val = op->in_opr(); 650 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); 651 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 652 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; 653 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 654 __ ftof(vw, dw, rval, rdst); 655 break; 656 } 657 case Bytecodes::_i2s: 658 case Bytecodes::_i2b: { 659 Register rval = op->in_opr()->as_register(); 660 Register rdst = dst->as_register(); 661 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); 662 __ sll (rval, shift, rdst); 663 __ sra (rdst, shift, rdst); 664 break; 665 } 666 case Bytecodes::_i2c: { 667 Register rval = op->in_opr()->as_register(); 668 Register rdst = dst->as_register(); 669 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; 670 __ sll (rval, shift, rdst); 671 __ srl (rdst, shift, rdst); 672 break; 673 } 674 675 default: ShouldNotReachHere(); 676 } 677 } 678 679 680 void LIR_Assembler::align_call(LIR_Code) { 681 // do nothing since all instructions are word aligned on sparc 682 } 683 684 685 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 686 __ call(op->addr(), rtype); 687 // The peephole pass fills the delay slot, add_call_info is done in 688 // LIR_Assembler::emit_delay. 689 } 690 691 692 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 693 __ ic_call(op->addr(), false); 694 // The peephole pass fills the delay slot, add_call_info is done in 695 // LIR_Assembler::emit_delay. 696 } 697 698 699 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 700 add_debug_info_for_null_check_here(op->info()); 701 __ load_klass(O0, G3_scratch); 702 if (Assembler::is_simm13(op->vtable_offset())) { 703 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); 704 } else { 705 // This will generate 2 instructions 706 __ set(op->vtable_offset(), G5_method); 707 // ld_ptr, set_hi, set 708 __ ld_ptr(G3_scratch, G5_method, G5_method); 709 } 710 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch); 711 __ callr(G3_scratch, G0); 712 // the peephole pass fills the delay slot 713 } 714 715 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { 716 int store_offset; 717 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 718 assert(base != O7, "destroying register"); 719 assert(!unaligned, "can't handle this"); 720 // for offsets larger than a simm13 we setup the offset in O7 721 __ set(offset, O7); 722 store_offset = store(from_reg, base, O7, type, wide); 723 } else { 724 if (type == T_ARRAY || type == T_OBJECT) { 725 __ verify_oop(from_reg->as_register()); 726 } 727 store_offset = code_offset(); 728 switch (type) { 729 case T_BOOLEAN: // fall through 730 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; 731 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; 732 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; 733 case T_INT : __ stw(from_reg->as_register(), base, offset); break; 734 case T_LONG : 735 if (unaligned || PatchALot) { 736 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem) 737 assert(G3_scratch != base, "can't handle this"); 738 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this"); 739 __ srax(from_reg->as_register_lo(), 32, G3_scratch); 740 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 741 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes); 742 } else { 743 __ stx(from_reg->as_register_lo(), base, offset); 744 } 745 break; 746 case T_ADDRESS: 747 case T_METADATA: 748 __ st_ptr(from_reg->as_register(), base, offset); 749 break; 750 case T_ARRAY : // fall through 751 case T_OBJECT: 752 { 753 if (UseCompressedOops && !wide) { 754 __ encode_heap_oop(from_reg->as_register(), G3_scratch); 755 store_offset = code_offset(); 756 __ stw(G3_scratch, base, offset); 757 } else { 758 __ st_ptr(from_reg->as_register(), base, offset); 759 } 760 break; 761 } 762 763 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; 764 case T_DOUBLE: 765 { 766 FloatRegister reg = from_reg->as_double_reg(); 767 // split unaligned stores 768 if (unaligned || PatchALot) { 769 assert(Assembler::is_simm13(offset + 4), "must be"); 770 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); 771 __ stf(FloatRegisterImpl::S, reg, base, offset); 772 } else { 773 __ stf(FloatRegisterImpl::D, reg, base, offset); 774 } 775 break; 776 } 777 default : ShouldNotReachHere(); 778 } 779 } 780 return store_offset; 781 } 782 783 784 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { 785 if (type == T_ARRAY || type == T_OBJECT) { 786 __ verify_oop(from_reg->as_register()); 787 } 788 int store_offset = code_offset(); 789 switch (type) { 790 case T_BOOLEAN: // fall through 791 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; 792 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; 793 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; 794 case T_INT : __ stw(from_reg->as_register(), base, disp); break; 795 case T_LONG : 796 __ stx(from_reg->as_register_lo(), base, disp); 797 break; 798 case T_ADDRESS: 799 __ st_ptr(from_reg->as_register(), base, disp); 800 break; 801 case T_ARRAY : // fall through 802 case T_OBJECT: 803 { 804 if (UseCompressedOops && !wide) { 805 __ encode_heap_oop(from_reg->as_register(), G3_scratch); 806 store_offset = code_offset(); 807 __ stw(G3_scratch, base, disp); 808 } else { 809 __ st_ptr(from_reg->as_register(), base, disp); 810 } 811 break; 812 } 813 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; 814 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; 815 default : ShouldNotReachHere(); 816 } 817 return store_offset; 818 } 819 820 821 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { 822 int load_offset; 823 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 824 assert(base != O7, "destroying register"); 825 assert(!unaligned, "can't handle this"); 826 // for offsets larger than a simm13 we setup the offset in O7 827 __ set(offset, O7); 828 load_offset = load(base, O7, to_reg, type, wide); 829 } else { 830 load_offset = code_offset(); 831 switch(type) { 832 case T_BOOLEAN: // fall through 833 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; 834 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; 835 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; 836 case T_INT : __ ld(base, offset, to_reg->as_register()); break; 837 case T_LONG : 838 if (!unaligned && !PatchALot) { 839 __ ldx(base, offset, to_reg->as_register_lo()); 840 } else { 841 assert(base != to_reg->as_register_lo(), "can't handle this"); 842 assert(O7 != to_reg->as_register_lo(), "can't handle this"); 843 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); 844 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last 845 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); 846 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); 847 } 848 break; 849 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break; 850 case T_ADDRESS: 851 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) { 852 __ lduw(base, offset, to_reg->as_register()); 853 __ decode_klass_not_null(to_reg->as_register()); 854 } else 855 { 856 __ ld_ptr(base, offset, to_reg->as_register()); 857 } 858 break; 859 case T_ARRAY : // fall through 860 case T_OBJECT: 861 { 862 if (UseCompressedOops && !wide) { 863 __ lduw(base, offset, to_reg->as_register()); 864 __ decode_heap_oop(to_reg->as_register()); 865 } else { 866 __ ld_ptr(base, offset, to_reg->as_register()); 867 } 868 break; 869 } 870 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; 871 case T_DOUBLE: 872 { 873 FloatRegister reg = to_reg->as_double_reg(); 874 // split unaligned loads 875 if (unaligned || PatchALot) { 876 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); 877 __ ldf(FloatRegisterImpl::S, base, offset, reg); 878 } else { 879 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); 880 } 881 break; 882 } 883 default : ShouldNotReachHere(); 884 } 885 if (type == T_ARRAY || type == T_OBJECT) { 886 __ verify_oop(to_reg->as_register()); 887 } 888 } 889 return load_offset; 890 } 891 892 893 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { 894 int load_offset = code_offset(); 895 switch(type) { 896 case T_BOOLEAN: // fall through 897 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; 898 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; 899 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; 900 case T_INT : __ ld(base, disp, to_reg->as_register()); break; 901 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break; 902 case T_ARRAY : // fall through 903 case T_OBJECT: 904 { 905 if (UseCompressedOops && !wide) { 906 __ lduw(base, disp, to_reg->as_register()); 907 __ decode_heap_oop(to_reg->as_register()); 908 } else { 909 __ ld_ptr(base, disp, to_reg->as_register()); 910 } 911 break; 912 } 913 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; 914 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; 915 case T_LONG : 916 __ ldx(base, disp, to_reg->as_register_lo()); 917 break; 918 default : ShouldNotReachHere(); 919 } 920 if (type == T_ARRAY || type == T_OBJECT) { 921 __ verify_oop(to_reg->as_register()); 922 } 923 return load_offset; 924 } 925 926 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 927 LIR_Const* c = src->as_constant_ptr(); 928 switch (c->type()) { 929 case T_INT: 930 case T_FLOAT: { 931 Register src_reg = O7; 932 int value = c->as_jint_bits(); 933 if (value == 0) { 934 src_reg = G0; 935 } else { 936 __ set(value, O7); 937 } 938 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 939 __ stw(src_reg, addr.base(), addr.disp()); 940 break; 941 } 942 case T_ADDRESS: { 943 Register src_reg = O7; 944 int value = c->as_jint_bits(); 945 if (value == 0) { 946 src_reg = G0; 947 } else { 948 __ set(value, O7); 949 } 950 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 951 __ st_ptr(src_reg, addr.base(), addr.disp()); 952 break; 953 } 954 case T_OBJECT: { 955 Register src_reg = O7; 956 jobject2reg(c->as_jobject(), src_reg); 957 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 958 __ st_ptr(src_reg, addr.base(), addr.disp()); 959 break; 960 } 961 case T_LONG: 962 case T_DOUBLE: { 963 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 964 965 Register tmp = O7; 966 int value_lo = c->as_jint_lo_bits(); 967 if (value_lo == 0) { 968 tmp = G0; 969 } else { 970 __ set(value_lo, O7); 971 } 972 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); 973 int value_hi = c->as_jint_hi_bits(); 974 if (value_hi == 0) { 975 tmp = G0; 976 } else { 977 __ set(value_hi, O7); 978 } 979 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); 980 break; 981 } 982 default: 983 Unimplemented(); 984 } 985 } 986 987 988 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 989 LIR_Const* c = src->as_constant_ptr(); 990 LIR_Address* addr = dest->as_address_ptr(); 991 Register base = addr->base()->as_pointer_register(); 992 int offset = -1; 993 994 switch (c->type()) { 995 case T_FLOAT: type = T_INT; // Float constants are stored by int store instructions. 996 case T_INT: 997 case T_ADDRESS: { 998 LIR_Opr tmp = FrameMap::O7_opr; 999 int value = c->as_jint_bits(); 1000 if (value == 0) { 1001 tmp = FrameMap::G0_opr; 1002 } else if (Assembler::is_simm13(value)) { 1003 __ set(value, O7); 1004 } 1005 if (addr->index()->is_valid()) { 1006 assert(addr->disp() == 0, "must be zero"); 1007 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 1008 } else { 1009 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1010 offset = store(tmp, base, addr->disp(), type, wide, false); 1011 } 1012 break; 1013 } 1014 case T_LONG: 1015 case T_DOUBLE: { 1016 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); 1017 assert(Assembler::is_simm13(addr->disp()) && 1018 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); 1019 1020 LIR_Opr tmp = FrameMap::O7_opr; 1021 int value_lo = c->as_jint_lo_bits(); 1022 if (value_lo == 0) { 1023 tmp = FrameMap::G0_opr; 1024 } else { 1025 __ set(value_lo, O7); 1026 } 1027 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false); 1028 int value_hi = c->as_jint_hi_bits(); 1029 if (value_hi == 0) { 1030 tmp = FrameMap::G0_opr; 1031 } else { 1032 __ set(value_hi, O7); 1033 } 1034 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false); 1035 break; 1036 } 1037 case T_OBJECT: { 1038 jobject obj = c->as_jobject(); 1039 LIR_Opr tmp; 1040 if (obj == NULL) { 1041 tmp = FrameMap::G0_opr; 1042 } else { 1043 tmp = FrameMap::O7_opr; 1044 jobject2reg(c->as_jobject(), O7); 1045 } 1046 // handle either reg+reg or reg+disp address 1047 if (addr->index()->is_valid()) { 1048 assert(addr->disp() == 0, "must be zero"); 1049 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 1050 } else { 1051 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1052 offset = store(tmp, base, addr->disp(), type, wide, false); 1053 } 1054 1055 break; 1056 } 1057 default: 1058 Unimplemented(); 1059 } 1060 if (info != NULL) { 1061 assert(offset != -1, "offset should've been set"); 1062 add_debug_info_for_null_check(offset, info); 1063 } 1064 } 1065 1066 1067 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 1068 LIR_Const* c = src->as_constant_ptr(); 1069 LIR_Opr to_reg = dest; 1070 1071 switch (c->type()) { 1072 case T_INT: 1073 case T_ADDRESS: 1074 { 1075 jint con = c->as_jint(); 1076 if (to_reg->is_single_cpu()) { 1077 assert(patch_code == lir_patch_none, "no patching handled here"); 1078 __ set(con, to_reg->as_register()); 1079 } else { 1080 ShouldNotReachHere(); 1081 assert(to_reg->is_single_fpu(), "wrong register kind"); 1082 1083 __ set(con, O7); 1084 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); 1085 __ st(O7, temp_slot); 1086 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); 1087 } 1088 } 1089 break; 1090 1091 case T_LONG: 1092 { 1093 jlong con = c->as_jlong(); 1094 1095 if (to_reg->is_double_cpu()) { 1096 __ set(con, to_reg->as_register_lo()); 1097 } else if (to_reg->is_single_cpu()) { 1098 __ set(con, to_reg->as_register()); 1099 } else { 1100 ShouldNotReachHere(); 1101 assert(to_reg->is_double_fpu(), "wrong register kind"); 1102 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); 1103 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); 1104 __ set(low(con), O7); 1105 __ st(O7, temp_slot_lo); 1106 __ set(high(con), O7); 1107 __ st(O7, temp_slot_hi); 1108 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); 1109 } 1110 } 1111 break; 1112 1113 case T_OBJECT: 1114 { 1115 if (patch_code == lir_patch_none) { 1116 jobject2reg(c->as_jobject(), to_reg->as_register()); 1117 } else { 1118 jobject2reg_with_patching(to_reg->as_register(), info); 1119 } 1120 } 1121 break; 1122 1123 case T_METADATA: 1124 { 1125 if (patch_code == lir_patch_none) { 1126 metadata2reg(c->as_metadata(), to_reg->as_register()); 1127 } else { 1128 klass2reg_with_patching(to_reg->as_register(), info); 1129 } 1130 } 1131 break; 1132 1133 case T_FLOAT: 1134 { 1135 address const_addr = __ float_constant(c->as_jfloat()); 1136 if (const_addr == NULL) { 1137 bailout("const section overflow"); 1138 break; 1139 } 1140 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1141 AddressLiteral const_addrlit(const_addr, rspec); 1142 if (to_reg->is_single_fpu()) { 1143 __ patchable_sethi(const_addrlit, O7); 1144 __ relocate(rspec); 1145 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); 1146 1147 } else { 1148 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1149 1150 __ set(const_addrlit, O7); 1151 __ ld(O7, 0, to_reg->as_register()); 1152 } 1153 } 1154 break; 1155 1156 case T_DOUBLE: 1157 { 1158 address const_addr = __ double_constant(c->as_jdouble()); 1159 if (const_addr == NULL) { 1160 bailout("const section overflow"); 1161 break; 1162 } 1163 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1164 1165 if (to_reg->is_double_fpu()) { 1166 AddressLiteral const_addrlit(const_addr, rspec); 1167 __ patchable_sethi(const_addrlit, O7); 1168 __ relocate(rspec); 1169 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); 1170 } else { 1171 assert(to_reg->is_double_cpu(), "Must be a long register."); 1172 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); 1173 } 1174 1175 } 1176 break; 1177 1178 default: 1179 ShouldNotReachHere(); 1180 } 1181 } 1182 1183 Address LIR_Assembler::as_Address(LIR_Address* addr) { 1184 Register reg = addr->base()->as_pointer_register(); 1185 LIR_Opr index = addr->index(); 1186 if (index->is_illegal()) { 1187 return Address(reg, addr->disp()); 1188 } else { 1189 assert (addr->disp() == 0, "unsupported address mode"); 1190 return Address(reg, index->as_pointer_register()); 1191 } 1192 } 1193 1194 1195 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1196 switch (type) { 1197 case T_INT: 1198 case T_FLOAT: { 1199 Register tmp = O7; 1200 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1201 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1202 __ lduw(from.base(), from.disp(), tmp); 1203 __ stw(tmp, to.base(), to.disp()); 1204 break; 1205 } 1206 case T_ADDRESS: 1207 case T_OBJECT: { 1208 Register tmp = O7; 1209 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1210 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1211 __ ld_ptr(from.base(), from.disp(), tmp); 1212 __ st_ptr(tmp, to.base(), to.disp()); 1213 break; 1214 } 1215 case T_LONG: 1216 case T_DOUBLE: { 1217 Register tmp = O7; 1218 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1219 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1220 __ lduw(from.base(), from.disp(), tmp); 1221 __ stw(tmp, to.base(), to.disp()); 1222 __ lduw(from.base(), from.disp() + 4, tmp); 1223 __ stw(tmp, to.base(), to.disp() + 4); 1224 break; 1225 } 1226 1227 default: 1228 ShouldNotReachHere(); 1229 } 1230 } 1231 1232 1233 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1234 Address base = as_Address(addr); 1235 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); 1236 } 1237 1238 1239 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1240 Address base = as_Address(addr); 1241 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); 1242 } 1243 1244 1245 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1246 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { 1247 1248 assert(type != T_METADATA, "load of metadata ptr not supported"); 1249 LIR_Address* addr = src_opr->as_address_ptr(); 1250 LIR_Opr to_reg = dest; 1251 1252 Register src = addr->base()->as_pointer_register(); 1253 Register disp_reg = noreg; 1254 int disp_value = addr->disp(); 1255 bool needs_patching = (patch_code != lir_patch_none); 1256 1257 if (addr->base()->type() == T_OBJECT) { 1258 __ verify_oop(src); 1259 } 1260 1261 PatchingStub* patch = NULL; 1262 if (needs_patching) { 1263 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1264 assert(!to_reg->is_double_cpu() || 1265 patch_code == lir_patch_none || 1266 patch_code == lir_patch_normal, "patching doesn't match register"); 1267 } 1268 1269 if (addr->index()->is_illegal()) { 1270 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1271 if (needs_patching) { 1272 __ patchable_set(0, O7); 1273 } else { 1274 __ set(disp_value, O7); 1275 } 1276 disp_reg = O7; 1277 } 1278 } else if (unaligned || PatchALot) { 1279 __ add(src, addr->index()->as_pointer_register(), O7); 1280 src = O7; 1281 } else { 1282 disp_reg = addr->index()->as_pointer_register(); 1283 assert(disp_value == 0, "can't handle 3 operand addresses"); 1284 } 1285 1286 // remember the offset of the load. The patching_epilog must be done 1287 // before the call to add_debug_info, otherwise the PcDescs don't get 1288 // entered in increasing order. 1289 int offset = code_offset(); 1290 1291 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1292 if (disp_reg == noreg) { 1293 offset = load(src, disp_value, to_reg, type, wide, unaligned); 1294 } else { 1295 assert(!unaligned, "can't handle this"); 1296 offset = load(src, disp_reg, to_reg, type, wide); 1297 } 1298 1299 if (patch != NULL) { 1300 patching_epilog(patch, patch_code, src, info); 1301 } 1302 if (info != NULL) add_debug_info_for_null_check(offset, info); 1303 } 1304 1305 1306 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1307 Address addr; 1308 if (src->is_single_word()) { 1309 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1310 } else if (src->is_double_word()) { 1311 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1312 } 1313 1314 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1315 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); 1316 } 1317 1318 1319 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1320 Address addr; 1321 if (dest->is_single_word()) { 1322 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1323 } else if (dest->is_double_word()) { 1324 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1325 } 1326 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1327 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); 1328 } 1329 1330 1331 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1332 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1333 if (from_reg->is_double_fpu()) { 1334 // double to double moves 1335 assert(to_reg->is_double_fpu(), "should match"); 1336 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); 1337 } else { 1338 // float to float moves 1339 assert(to_reg->is_single_fpu(), "should match"); 1340 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); 1341 } 1342 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1343 if (from_reg->is_double_cpu()) { 1344 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); 1345 } else if (to_reg->is_double_cpu()) { 1346 // int to int moves 1347 __ mov(from_reg->as_register(), to_reg->as_register_lo()); 1348 } else { 1349 // int to int moves 1350 __ mov(from_reg->as_register(), to_reg->as_register()); 1351 } 1352 } else { 1353 ShouldNotReachHere(); 1354 } 1355 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1356 __ verify_oop(to_reg->as_register()); 1357 } 1358 } 1359 1360 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1361 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1362 bool wide, bool unaligned) { 1363 assert(type != T_METADATA, "store of metadata ptr not supported"); 1364 LIR_Address* addr = dest->as_address_ptr(); 1365 1366 Register src = addr->base()->as_pointer_register(); 1367 Register disp_reg = noreg; 1368 int disp_value = addr->disp(); 1369 bool needs_patching = (patch_code != lir_patch_none); 1370 1371 if (addr->base()->is_oop_register()) { 1372 __ verify_oop(src); 1373 } 1374 1375 PatchingStub* patch = NULL; 1376 if (needs_patching) { 1377 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1378 assert(!from_reg->is_double_cpu() || 1379 patch_code == lir_patch_none || 1380 patch_code == lir_patch_normal, "patching doesn't match register"); 1381 } 1382 1383 if (addr->index()->is_illegal()) { 1384 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1385 if (needs_patching) { 1386 __ patchable_set(0, O7); 1387 } else { 1388 __ set(disp_value, O7); 1389 } 1390 disp_reg = O7; 1391 } 1392 } else if (unaligned || PatchALot) { 1393 __ add(src, addr->index()->as_pointer_register(), O7); 1394 src = O7; 1395 } else { 1396 disp_reg = addr->index()->as_pointer_register(); 1397 assert(disp_value == 0, "can't handle 3 operand addresses"); 1398 } 1399 1400 // remember the offset of the store. The patching_epilog must be done 1401 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1402 // entered in increasing order. 1403 int offset; 1404 1405 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1406 if (disp_reg == noreg) { 1407 offset = store(from_reg, src, disp_value, type, wide, unaligned); 1408 } else { 1409 assert(!unaligned, "can't handle this"); 1410 offset = store(from_reg, src, disp_reg, type, wide); 1411 } 1412 1413 if (patch != NULL) { 1414 patching_epilog(patch, patch_code, src, info); 1415 } 1416 1417 if (info != NULL) add_debug_info_for_null_check(offset, info); 1418 } 1419 1420 1421 void LIR_Assembler::return_op(LIR_Opr result) { 1422 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1423 __ reserved_stack_check(); 1424 } 1425 if (SafepointMechanism::uses_thread_local_poll()) { 1426 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0); 1427 } else { 1428 __ set((intptr_t)os::get_polling_page(), L0); 1429 } 1430 __ relocate(relocInfo::poll_return_type); 1431 __ ld_ptr(L0, 0, G0); 1432 __ ret(); 1433 __ delayed()->restore(); 1434 } 1435 1436 1437 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1438 if (SafepointMechanism::uses_thread_local_poll()) { 1439 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), tmp->as_register()); 1440 } else { 1441 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); 1442 } 1443 if (info != NULL) { 1444 add_debug_info_for_branch(info); 1445 } 1446 int offset = __ offset(); 1447 1448 __ relocate(relocInfo::poll_type); 1449 __ ld_ptr(tmp->as_register(), 0, G0); 1450 return offset; 1451 } 1452 1453 1454 void LIR_Assembler::emit_static_call_stub() { 1455 address call_pc = __ pc(); 1456 address stub = __ start_a_stub(call_stub_size()); 1457 if (stub == NULL) { 1458 bailout("static call stub overflow"); 1459 return; 1460 } 1461 1462 int start = __ offset(); 1463 __ relocate(static_stub_Relocation::spec(call_pc)); 1464 1465 __ set_metadata(NULL, G5); 1466 // must be set to -1 at code generation time 1467 AddressLiteral addrlit(-1); 1468 __ jump_to(addrlit, G3); 1469 __ delayed()->nop(); 1470 1471 assert(__ offset() - start <= call_stub_size(), "stub too big"); 1472 __ end_a_stub(); 1473 } 1474 1475 1476 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1477 if (opr1->is_single_fpu()) { 1478 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); 1479 } else if (opr1->is_double_fpu()) { 1480 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); 1481 } else if (opr1->is_single_cpu()) { 1482 if (opr2->is_constant()) { 1483 switch (opr2->as_constant_ptr()->type()) { 1484 case T_INT: 1485 { jint con = opr2->as_constant_ptr()->as_jint(); 1486 if (Assembler::is_simm13(con)) { 1487 __ cmp(opr1->as_register(), con); 1488 } else { 1489 __ set(con, O7); 1490 __ cmp(opr1->as_register(), O7); 1491 } 1492 } 1493 break; 1494 1495 case T_OBJECT: 1496 // there are only equal/notequal comparisions on objects 1497 { jobject con = opr2->as_constant_ptr()->as_jobject(); 1498 if (con == NULL) { 1499 __ cmp(opr1->as_register(), 0); 1500 } else { 1501 jobject2reg(con, O7); 1502 __ cmp(opr1->as_register(), O7); 1503 } 1504 } 1505 break; 1506 1507 default: 1508 ShouldNotReachHere(); 1509 break; 1510 } 1511 } else { 1512 if (opr2->is_address()) { 1513 LIR_Address * addr = opr2->as_address_ptr(); 1514 BasicType type = addr->type(); 1515 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1516 else __ ld(as_Address(addr), O7); 1517 __ cmp(opr1->as_register(), O7); 1518 } else { 1519 __ cmp(opr1->as_register(), opr2->as_register()); 1520 } 1521 } 1522 } else if (opr1->is_double_cpu()) { 1523 Register xlo = opr1->as_register_lo(); 1524 Register xhi = opr1->as_register_hi(); 1525 if (opr2->is_constant() && opr2->as_jlong() == 0) { 1526 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); 1527 __ orcc(xhi, G0, G0); 1528 } else if (opr2->is_register()) { 1529 Register ylo = opr2->as_register_lo(); 1530 Register yhi = opr2->as_register_hi(); 1531 __ cmp(xlo, ylo); 1532 } else { 1533 ShouldNotReachHere(); 1534 } 1535 } else if (opr1->is_address()) { 1536 LIR_Address * addr = opr1->as_address_ptr(); 1537 BasicType type = addr->type(); 1538 assert (opr2->is_constant(), "Checking"); 1539 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1540 else __ ld(as_Address(addr), O7); 1541 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); 1542 } else { 1543 ShouldNotReachHere(); 1544 } 1545 } 1546 1547 1548 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1549 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1550 bool is_unordered_less = (code == lir_ucmp_fd2i); 1551 if (left->is_single_fpu()) { 1552 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 1553 } else if (left->is_double_fpu()) { 1554 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 1555 } else { 1556 ShouldNotReachHere(); 1557 } 1558 } else if (code == lir_cmp_l2i) { 1559 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); 1560 } else { 1561 ShouldNotReachHere(); 1562 } 1563 } 1564 1565 1566 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1567 Assembler::Condition acond; 1568 switch (condition) { 1569 case lir_cond_equal: acond = Assembler::equal; break; 1570 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1571 case lir_cond_less: acond = Assembler::less; break; 1572 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1573 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 1574 case lir_cond_greater: acond = Assembler::greater; break; 1575 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 1576 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 1577 default: ShouldNotReachHere(); 1578 }; 1579 1580 if (opr1->is_constant() && opr1->type() == T_INT) { 1581 Register dest = result->as_register(); 1582 // load up first part of constant before branch 1583 // and do the rest in the delay slot. 1584 if (!Assembler::is_simm13(opr1->as_jint())) { 1585 __ sethi(opr1->as_jint(), dest); 1586 } 1587 } else if (opr1->is_constant()) { 1588 const2reg(opr1, result, lir_patch_none, NULL); 1589 } else if (opr1->is_register()) { 1590 reg2reg(opr1, result); 1591 } else if (opr1->is_stack()) { 1592 stack2reg(opr1, result, result->type()); 1593 } else { 1594 ShouldNotReachHere(); 1595 } 1596 Label skip; 1597 if (type == T_INT) { 1598 __ br(acond, false, Assembler::pt, skip); 1599 } else { 1600 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit 1601 } 1602 if (opr1->is_constant() && opr1->type() == T_INT) { 1603 Register dest = result->as_register(); 1604 if (Assembler::is_simm13(opr1->as_jint())) { 1605 __ delayed()->or3(G0, opr1->as_jint(), dest); 1606 } else { 1607 // the sethi has been done above, so just put in the low 10 bits 1608 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); 1609 } 1610 } else { 1611 // can't do anything useful in the delay slot 1612 __ delayed()->nop(); 1613 } 1614 if (opr2->is_constant()) { 1615 const2reg(opr2, result, lir_patch_none, NULL); 1616 } else if (opr2->is_register()) { 1617 reg2reg(opr2, result); 1618 } else if (opr2->is_stack()) { 1619 stack2reg(opr2, result, result->type()); 1620 } else { 1621 ShouldNotReachHere(); 1622 } 1623 __ bind(skip); 1624 } 1625 1626 1627 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1628 assert(info == NULL, "unused on this code path"); 1629 assert(left->is_register(), "wrong items state"); 1630 assert(dest->is_register(), "wrong items state"); 1631 1632 if (right->is_register()) { 1633 if (dest->is_float_kind()) { 1634 1635 FloatRegister lreg, rreg, res; 1636 FloatRegisterImpl::Width w; 1637 if (right->is_single_fpu()) { 1638 w = FloatRegisterImpl::S; 1639 lreg = left->as_float_reg(); 1640 rreg = right->as_float_reg(); 1641 res = dest->as_float_reg(); 1642 } else { 1643 w = FloatRegisterImpl::D; 1644 lreg = left->as_double_reg(); 1645 rreg = right->as_double_reg(); 1646 res = dest->as_double_reg(); 1647 } 1648 1649 switch (code) { 1650 case lir_add: __ fadd(w, lreg, rreg, res); break; 1651 case lir_sub: __ fsub(w, lreg, rreg, res); break; 1652 case lir_mul: // fall through 1653 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; 1654 case lir_div: // fall through 1655 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; 1656 default: ShouldNotReachHere(); 1657 } 1658 1659 } else if (dest->is_double_cpu()) { 1660 Register dst_lo = dest->as_register_lo(); 1661 Register op1_lo = left->as_pointer_register(); 1662 Register op2_lo = right->as_pointer_register(); 1663 1664 switch (code) { 1665 case lir_add: 1666 __ add(op1_lo, op2_lo, dst_lo); 1667 break; 1668 1669 case lir_sub: 1670 __ sub(op1_lo, op2_lo, dst_lo); 1671 break; 1672 1673 default: ShouldNotReachHere(); 1674 } 1675 } else { 1676 assert (right->is_single_cpu(), "Just Checking"); 1677 1678 Register lreg = left->as_register(); 1679 Register res = dest->as_register(); 1680 Register rreg = right->as_register(); 1681 switch (code) { 1682 case lir_add: __ add (lreg, rreg, res); break; 1683 case lir_sub: __ sub (lreg, rreg, res); break; 1684 case lir_mul: __ mulx (lreg, rreg, res); break; 1685 default: ShouldNotReachHere(); 1686 } 1687 } 1688 } else { 1689 assert (right->is_constant(), "must be constant"); 1690 1691 if (dest->is_single_cpu()) { 1692 Register lreg = left->as_register(); 1693 Register res = dest->as_register(); 1694 int simm13 = right->as_constant_ptr()->as_jint(); 1695 1696 switch (code) { 1697 case lir_add: __ add (lreg, simm13, res); break; 1698 case lir_sub: __ sub (lreg, simm13, res); break; 1699 case lir_mul: __ mulx (lreg, simm13, res); break; 1700 default: ShouldNotReachHere(); 1701 } 1702 } else { 1703 Register lreg = left->as_pointer_register(); 1704 Register res = dest->as_register_lo(); 1705 long con = right->as_constant_ptr()->as_jlong(); 1706 assert(Assembler::is_simm13(con), "must be simm13"); 1707 1708 switch (code) { 1709 case lir_add: __ add (lreg, (int)con, res); break; 1710 case lir_sub: __ sub (lreg, (int)con, res); break; 1711 case lir_mul: __ mulx (lreg, (int)con, res); break; 1712 default: ShouldNotReachHere(); 1713 } 1714 } 1715 } 1716 } 1717 1718 1719 void LIR_Assembler::fpop() { 1720 // do nothing 1721 } 1722 1723 1724 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1725 switch (code) { 1726 case lir_tan: { 1727 assert(thread->is_valid(), "preserve the thread object for performance reasons"); 1728 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); 1729 break; 1730 } 1731 case lir_sqrt: { 1732 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1733 FloatRegister src_reg = value->as_double_reg(); 1734 FloatRegister dst_reg = dest->as_double_reg(); 1735 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); 1736 break; 1737 } 1738 case lir_abs: { 1739 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 1740 FloatRegister src_reg = value->as_double_reg(); 1741 FloatRegister dst_reg = dest->as_double_reg(); 1742 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); 1743 break; 1744 } 1745 default: { 1746 ShouldNotReachHere(); 1747 break; 1748 } 1749 } 1750 } 1751 1752 1753 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1754 if (right->is_constant()) { 1755 if (dest->is_single_cpu()) { 1756 int simm13 = right->as_constant_ptr()->as_jint(); 1757 switch (code) { 1758 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; 1759 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; 1760 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; 1761 default: ShouldNotReachHere(); 1762 } 1763 } else { 1764 long c = right->as_constant_ptr()->as_jlong(); 1765 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); 1766 int simm13 = (int)c; 1767 switch (code) { 1768 case lir_logic_and: 1769 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1770 break; 1771 1772 case lir_logic_or: 1773 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1774 break; 1775 1776 case lir_logic_xor: 1777 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1778 break; 1779 1780 default: ShouldNotReachHere(); 1781 } 1782 } 1783 } else { 1784 assert(right->is_register(), "right should be in register"); 1785 1786 if (dest->is_single_cpu()) { 1787 switch (code) { 1788 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; 1789 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; 1790 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; 1791 default: ShouldNotReachHere(); 1792 } 1793 } else { 1794 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 1795 left->as_register_lo(); 1796 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 1797 right->as_register_lo(); 1798 1799 switch (code) { 1800 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; 1801 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; 1802 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; 1803 default: ShouldNotReachHere(); 1804 } 1805 } 1806 } 1807 } 1808 1809 1810 int LIR_Assembler::shift_amount(BasicType t) { 1811 int elem_size = type2aelembytes(t); 1812 switch (elem_size) { 1813 case 1 : return 0; 1814 case 2 : return 1; 1815 case 4 : return 2; 1816 case 8 : return 3; 1817 } 1818 ShouldNotReachHere(); 1819 return -1; 1820 } 1821 1822 1823 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1824 assert(exceptionOop->as_register() == Oexception, "should match"); 1825 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); 1826 1827 info->add_register_oop(exceptionOop); 1828 1829 // reuse the debug info from the safepoint poll for the throw op itself 1830 address pc_for_athrow = __ pc(); 1831 int pc_for_athrow_offset = __ offset(); 1832 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 1833 __ set(pc_for_athrow, Oissuing_pc, rspec); 1834 add_call_info(pc_for_athrow_offset, info); // for exception handler 1835 1836 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 1837 __ delayed()->nop(); 1838 } 1839 1840 1841 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1842 assert(exceptionOop->as_register() == Oexception, "should match"); 1843 1844 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); 1845 __ delayed()->nop(); 1846 } 1847 1848 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1849 Register src = op->src()->as_register(); 1850 Register dst = op->dst()->as_register(); 1851 Register src_pos = op->src_pos()->as_register(); 1852 Register dst_pos = op->dst_pos()->as_register(); 1853 Register length = op->length()->as_register(); 1854 Register tmp = op->tmp()->as_register(); 1855 Register tmp2 = O7; 1856 1857 int flags = op->flags(); 1858 ciArrayKlass* default_type = op->expected_type(); 1859 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1860 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1861 1862 // higher 32bits must be null 1863 __ sra(dst_pos, 0, dst_pos); 1864 __ sra(src_pos, 0, src_pos); 1865 __ sra(length, 0, length); 1866 1867 // set up the arraycopy stub information 1868 ArrayCopyStub* stub = op->stub(); 1869 1870 // always do stub if no type information is available. it's ok if 1871 // the known type isn't loaded since the code sanity checks 1872 // in debug mode and the type isn't required when we know the exact type 1873 // also check that the type is an array type. 1874 if (op->expected_type() == NULL) { 1875 __ mov(src, O0); 1876 __ mov(src_pos, O1); 1877 __ mov(dst, O2); 1878 __ mov(dst_pos, O3); 1879 __ mov(length, O4); 1880 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1881 1882 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 1883 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); 1884 } else { 1885 #ifndef PRODUCT 1886 if (PrintC1Statistics) { 1887 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; 1888 __ inc_counter(counter, G1, G3); 1889 } 1890 #endif 1891 __ call_VM_leaf(tmp, copyfunc_addr); 1892 } 1893 1894 if (copyfunc_addr != NULL) { 1895 __ xor3(O0, -1, tmp); 1896 __ sub(length, tmp, length); 1897 __ add(src_pos, tmp, src_pos); 1898 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); 1899 __ delayed()->add(dst_pos, tmp, dst_pos); 1900 } else { 1901 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); 1902 __ delayed()->nop(); 1903 } 1904 __ bind(*stub->continuation()); 1905 return; 1906 } 1907 1908 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 1909 1910 // make sure src and dst are non-null and load array length 1911 if (flags & LIR_OpArrayCopy::src_null_check) { 1912 __ tst(src); 1913 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); 1914 __ delayed()->nop(); 1915 } 1916 1917 if (flags & LIR_OpArrayCopy::dst_null_check) { 1918 __ tst(dst); 1919 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); 1920 __ delayed()->nop(); 1921 } 1922 1923 // If the compiler was not able to prove that exact type of the source or the destination 1924 // of the arraycopy is an array type, check at runtime if the source or the destination is 1925 // an instance type. 1926 if (flags & LIR_OpArrayCopy::type_check) { 1927 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { 1928 __ load_klass(dst, tmp); 1929 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2); 1930 __ cmp(tmp2, Klass::_lh_neutral_value); 1931 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry()); 1932 __ delayed()->nop(); 1933 } 1934 1935 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { 1936 __ load_klass(src, tmp); 1937 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2); 1938 __ cmp(tmp2, Klass::_lh_neutral_value); 1939 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry()); 1940 __ delayed()->nop(); 1941 } 1942 } 1943 1944 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 1945 // test src_pos register 1946 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry()); 1947 __ delayed()->nop(); 1948 } 1949 1950 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 1951 // test dst_pos register 1952 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry()); 1953 __ delayed()->nop(); 1954 } 1955 1956 if (flags & LIR_OpArrayCopy::length_positive_check) { 1957 // make sure length isn't negative 1958 __ cmp_zero_and_br(Assembler::less, length, *stub->entry()); 1959 __ delayed()->nop(); 1960 } 1961 1962 if (flags & LIR_OpArrayCopy::src_range_check) { 1963 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); 1964 __ add(length, src_pos, tmp); 1965 __ cmp(tmp2, tmp); 1966 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 1967 __ delayed()->nop(); 1968 } 1969 1970 if (flags & LIR_OpArrayCopy::dst_range_check) { 1971 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); 1972 __ add(length, dst_pos, tmp); 1973 __ cmp(tmp2, tmp); 1974 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 1975 __ delayed()->nop(); 1976 } 1977 1978 int shift = shift_amount(basic_type); 1979 1980 if (flags & LIR_OpArrayCopy::type_check) { 1981 // We don't know the array types are compatible 1982 if (basic_type != T_OBJECT) { 1983 // Simple test for basic type arrays 1984 if (UseCompressedClassPointers) { 1985 // We don't need decode because we just need to compare 1986 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp); 1987 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); 1988 __ cmp(tmp, tmp2); 1989 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 1990 } else { 1991 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); 1992 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 1993 __ cmp(tmp, tmp2); 1994 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 1995 } 1996 __ delayed()->nop(); 1997 } else { 1998 // For object arrays, if src is a sub class of dst then we can 1999 // safely do the copy. 2000 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2001 2002 Label cont, slow; 2003 assert_different_registers(tmp, tmp2, G3, G1); 2004 2005 __ load_klass(src, G3); 2006 __ load_klass(dst, G1); 2007 2008 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL); 2009 2010 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2011 __ delayed()->nop(); 2012 2013 __ cmp(G3, 0); 2014 if (copyfunc_addr != NULL) { // use stub if available 2015 // src is not a sub class of dst so we have to do a 2016 // per-element check. 2017 __ br(Assembler::notEqual, false, Assembler::pt, cont); 2018 __ delayed()->nop(); 2019 2020 __ bind(slow); 2021 2022 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2023 if ((flags & mask) != mask) { 2024 // Check that at least both of them object arrays. 2025 assert(flags & mask, "one of the two should be known to be an object array"); 2026 2027 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2028 __ load_klass(src, tmp); 2029 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2030 __ load_klass(dst, tmp); 2031 } 2032 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2033 2034 __ lduw(tmp, lh_offset, tmp2); 2035 2036 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2037 __ set(objArray_lh, tmp); 2038 __ cmp(tmp, tmp2); 2039 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2040 __ delayed()->nop(); 2041 } 2042 2043 Register src_ptr = O0; 2044 Register dst_ptr = O1; 2045 Register len = O2; 2046 Register chk_off = O3; 2047 Register super_k = O4; 2048 2049 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2050 if (shift == 0) { 2051 __ add(src_ptr, src_pos, src_ptr); 2052 } else { 2053 __ sll(src_pos, shift, tmp); 2054 __ add(src_ptr, tmp, src_ptr); 2055 } 2056 2057 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2058 if (shift == 0) { 2059 __ add(dst_ptr, dst_pos, dst_ptr); 2060 } else { 2061 __ sll(dst_pos, shift, tmp); 2062 __ add(dst_ptr, tmp, dst_ptr); 2063 } 2064 __ mov(length, len); 2065 __ load_klass(dst, tmp); 2066 2067 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); 2068 __ ld_ptr(tmp, ek_offset, super_k); 2069 2070 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2071 __ lduw(super_k, sco_offset, chk_off); 2072 2073 __ call_VM_leaf(tmp, copyfunc_addr); 2074 2075 #ifndef PRODUCT 2076 if (PrintC1Statistics) { 2077 Label failed; 2078 __ br_notnull_short(O0, Assembler::pn, failed); 2079 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3); 2080 __ bind(failed); 2081 } 2082 #endif 2083 2084 __ br_null(O0, false, Assembler::pt, *stub->continuation()); 2085 __ delayed()->xor3(O0, -1, tmp); 2086 2087 #ifndef PRODUCT 2088 if (PrintC1Statistics) { 2089 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3); 2090 } 2091 #endif 2092 2093 __ sub(length, tmp, length); 2094 __ add(src_pos, tmp, src_pos); 2095 __ br(Assembler::always, false, Assembler::pt, *stub->entry()); 2096 __ delayed()->add(dst_pos, tmp, dst_pos); 2097 2098 __ bind(cont); 2099 } else { 2100 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2101 __ delayed()->nop(); 2102 __ bind(cont); 2103 } 2104 } 2105 } 2106 2107 #ifdef ASSERT 2108 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2109 // Sanity check the known type with the incoming class. For the 2110 // primitive case the types must match exactly with src.klass and 2111 // dst.klass each exactly matching the default type. For the 2112 // object array case, if no type check is needed then either the 2113 // dst type is exactly the expected type and the src type is a 2114 // subtype which we can't check or src is the same array as dst 2115 // but not necessarily exactly of type default_type. 2116 Label known_ok, halt; 2117 metadata2reg(op->expected_type()->constant_encoding(), tmp); 2118 if (UseCompressedClassPointers) { 2119 // tmp holds the default type. It currently comes uncompressed after the 2120 // load of a constant, so encode it. 2121 __ encode_klass_not_null(tmp); 2122 // load the raw value of the dst klass, since we will be comparing 2123 // uncompressed values directly. 2124 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2125 if (basic_type != T_OBJECT) { 2126 __ cmp(tmp, tmp2); 2127 __ br(Assembler::notEqual, false, Assembler::pn, halt); 2128 // load the raw value of the src klass. 2129 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2); 2130 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); 2131 } else { 2132 __ cmp(tmp, tmp2); 2133 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2134 __ delayed()->cmp(src, dst); 2135 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2136 __ delayed()->nop(); 2137 } 2138 } else { 2139 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2140 if (basic_type != T_OBJECT) { 2141 __ cmp(tmp, tmp2); 2142 __ brx(Assembler::notEqual, false, Assembler::pn, halt); 2143 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); 2144 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); 2145 } else { 2146 __ cmp(tmp, tmp2); 2147 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2148 __ delayed()->cmp(src, dst); 2149 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2150 __ delayed()->nop(); 2151 } 2152 } 2153 __ bind(halt); 2154 __ stop("incorrect type information in arraycopy"); 2155 __ bind(known_ok); 2156 } 2157 #endif 2158 2159 #ifndef PRODUCT 2160 if (PrintC1Statistics) { 2161 address counter = Runtime1::arraycopy_count_address(basic_type); 2162 __ inc_counter(counter, G1, G3); 2163 } 2164 #endif 2165 2166 Register src_ptr = O0; 2167 Register dst_ptr = O1; 2168 Register len = O2; 2169 2170 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2171 if (shift == 0) { 2172 __ add(src_ptr, src_pos, src_ptr); 2173 } else { 2174 __ sll(src_pos, shift, tmp); 2175 __ add(src_ptr, tmp, src_ptr); 2176 } 2177 2178 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2179 if (shift == 0) { 2180 __ add(dst_ptr, dst_pos, dst_ptr); 2181 } else { 2182 __ sll(dst_pos, shift, tmp); 2183 __ add(dst_ptr, tmp, dst_ptr); 2184 } 2185 2186 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2187 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2188 const char *name; 2189 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2190 2191 // arraycopy stubs takes a length in number of elements, so don't scale it. 2192 __ mov(length, len); 2193 __ call_VM_leaf(tmp, entry); 2194 2195 __ bind(*stub->continuation()); 2196 } 2197 2198 2199 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2200 if (dest->is_single_cpu()) { 2201 if (left->type() == T_OBJECT) { 2202 switch (code) { 2203 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; 2204 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; 2205 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2206 default: ShouldNotReachHere(); 2207 } 2208 } else 2209 switch (code) { 2210 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; 2211 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; 2212 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2213 default: ShouldNotReachHere(); 2214 } 2215 } else { 2216 switch (code) { 2217 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2218 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2219 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2220 default: ShouldNotReachHere(); 2221 } 2222 } 2223 } 2224 2225 2226 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2227 if (left->type() == T_OBJECT) { 2228 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) 2229 Register l = left->as_register(); 2230 Register d = dest->as_register_lo(); 2231 switch (code) { 2232 case lir_shl: __ sllx (l, count, d); break; 2233 case lir_shr: __ srax (l, count, d); break; 2234 case lir_ushr: __ srlx (l, count, d); break; 2235 default: ShouldNotReachHere(); 2236 } 2237 return; 2238 } 2239 2240 if (dest->is_single_cpu()) { 2241 count = count & 0x1F; // Java spec 2242 switch (code) { 2243 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; 2244 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; 2245 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; 2246 default: ShouldNotReachHere(); 2247 } 2248 } else if (dest->is_double_cpu()) { 2249 count = count & 63; // Java spec 2250 switch (code) { 2251 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2252 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2253 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2254 default: ShouldNotReachHere(); 2255 } 2256 } else { 2257 ShouldNotReachHere(); 2258 } 2259 } 2260 2261 2262 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2263 assert(op->tmp1()->as_register() == G1 && 2264 op->tmp2()->as_register() == G3 && 2265 op->tmp3()->as_register() == G4 && 2266 op->obj()->as_register() == O0 && 2267 op->klass()->as_register() == G5, "must be"); 2268 if (op->init_check()) { 2269 add_debug_info_for_null_check_here(op->stub()->info()); 2270 __ ldub(op->klass()->as_register(), 2271 in_bytes(InstanceKlass::init_state_offset()), 2272 op->tmp1()->as_register()); 2273 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized); 2274 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); 2275 __ delayed()->nop(); 2276 } 2277 __ allocate_object(op->obj()->as_register(), 2278 op->tmp1()->as_register(), 2279 op->tmp2()->as_register(), 2280 op->tmp3()->as_register(), 2281 op->header_size(), 2282 op->object_size(), 2283 op->klass()->as_register(), 2284 *op->stub()->entry()); 2285 __ bind(*op->stub()->continuation()); 2286 __ verify_oop(op->obj()->as_register()); 2287 } 2288 2289 2290 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2291 assert(op->tmp1()->as_register() == G1 && 2292 op->tmp2()->as_register() == G3 && 2293 op->tmp3()->as_register() == G4 && 2294 op->tmp4()->as_register() == O1 && 2295 op->klass()->as_register() == G5, "must be"); 2296 2297 __ signx(op->len()->as_register()); 2298 if (UseSlowPath || 2299 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2300 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2301 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2302 __ delayed()->nop(); 2303 } else { 2304 __ allocate_array(op->obj()->as_register(), 2305 op->len()->as_register(), 2306 op->tmp1()->as_register(), 2307 op->tmp2()->as_register(), 2308 op->tmp3()->as_register(), 2309 arrayOopDesc::header_size(op->type()), 2310 type2aelembytes(op->type()), 2311 op->klass()->as_register(), 2312 *op->stub()->entry()); 2313 } 2314 __ bind(*op->stub()->continuation()); 2315 } 2316 2317 2318 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2319 ciMethodData *md, ciProfileData *data, 2320 Register recv, Register tmp1, Label* update_done) { 2321 uint i; 2322 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2323 Label next_test; 2324 // See if the receiver is receiver[n]. 2325 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2326 mdo_offset_bias); 2327 __ ld_ptr(receiver_addr, tmp1); 2328 __ verify_klass_ptr(tmp1); 2329 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test); 2330 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2331 mdo_offset_bias); 2332 __ ld_ptr(data_addr, tmp1); 2333 __ add(tmp1, DataLayout::counter_increment, tmp1); 2334 __ st_ptr(tmp1, data_addr); 2335 __ ba(*update_done); 2336 __ delayed()->nop(); 2337 __ bind(next_test); 2338 } 2339 2340 // Didn't find receiver; find next empty slot and fill it in 2341 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2342 Label next_test; 2343 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2344 mdo_offset_bias); 2345 __ ld_ptr(recv_addr, tmp1); 2346 __ br_notnull_short(tmp1, Assembler::pt, next_test); 2347 __ st_ptr(recv, recv_addr); 2348 __ set(DataLayout::counter_increment, tmp1); 2349 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2350 mdo_offset_bias); 2351 __ ba(*update_done); 2352 __ delayed()->nop(); 2353 __ bind(next_test); 2354 } 2355 } 2356 2357 2358 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2359 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2360 md = method->method_data_or_null(); 2361 assert(md != NULL, "Sanity"); 2362 data = md->bci_to_data(bci); 2363 assert(data != NULL, "need data for checkcast"); 2364 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2365 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2366 // The offset is large so bias the mdo by the base of the slot so 2367 // that the ld can use simm13s to reference the slots of the data 2368 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2369 } 2370 } 2371 2372 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2373 // we always need a stub for the failure case. 2374 CodeStub* stub = op->stub(); 2375 Register obj = op->object()->as_register(); 2376 Register k_RInfo = op->tmp1()->as_register(); 2377 Register klass_RInfo = op->tmp2()->as_register(); 2378 Register dst = op->result_opr()->as_register(); 2379 Register Rtmp1 = op->tmp3()->as_register(); 2380 ciKlass* k = op->klass(); 2381 2382 2383 if (obj == k_RInfo) { 2384 k_RInfo = klass_RInfo; 2385 klass_RInfo = obj; 2386 } 2387 2388 ciMethodData* md; 2389 ciProfileData* data; 2390 int mdo_offset_bias = 0; 2391 if (op->should_profile()) { 2392 ciMethod* method = op->profiled_method(); 2393 assert(method != NULL, "Should have method"); 2394 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2395 2396 Label not_null; 2397 __ br_notnull_short(obj, Assembler::pn, not_null); 2398 Register mdo = k_RInfo; 2399 Register data_val = Rtmp1; 2400 metadata2reg(md->constant_encoding(), mdo); 2401 if (mdo_offset_bias > 0) { 2402 __ set(mdo_offset_bias, data_val); 2403 __ add(mdo, data_val, mdo); 2404 } 2405 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2406 __ ldub(flags_addr, data_val); 2407 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2408 __ stb(data_val, flags_addr); 2409 __ ba(*obj_is_null); 2410 __ delayed()->nop(); 2411 __ bind(not_null); 2412 } else { 2413 __ br_null(obj, false, Assembler::pn, *obj_is_null); 2414 __ delayed()->nop(); 2415 } 2416 2417 Label profile_cast_failure, profile_cast_success; 2418 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 2419 Label *success_target = op->should_profile() ? &profile_cast_success : success; 2420 2421 // patching may screw with our temporaries on sparc, 2422 // so let's do it before loading the class 2423 if (k->is_loaded()) { 2424 metadata2reg(k->constant_encoding(), k_RInfo); 2425 } else { 2426 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2427 } 2428 assert(obj != k_RInfo, "must be different"); 2429 2430 // get object class 2431 // not a safepoint as obj null check happens earlier 2432 __ load_klass(obj, klass_RInfo); 2433 if (op->fast_check()) { 2434 assert_different_registers(klass_RInfo, k_RInfo); 2435 __ cmp(k_RInfo, klass_RInfo); 2436 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); 2437 __ delayed()->nop(); 2438 } else { 2439 bool need_slow_path = true; 2440 if (k->is_loaded()) { 2441 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) 2442 need_slow_path = false; 2443 // perform the fast part of the checking logic 2444 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, 2445 (need_slow_path ? success_target : NULL), 2446 failure_target, NULL, 2447 RegisterOrConstant(k->super_check_offset())); 2448 } else { 2449 // perform the fast part of the checking logic 2450 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, 2451 failure_target, NULL); 2452 } 2453 if (need_slow_path) { 2454 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2455 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2456 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2457 __ delayed()->nop(); 2458 __ cmp(G3, 0); 2459 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2460 __ delayed()->nop(); 2461 // Fall through to success case 2462 } 2463 } 2464 2465 if (op->should_profile()) { 2466 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2467 assert_different_registers(obj, mdo, recv, tmp1); 2468 __ bind(profile_cast_success); 2469 metadata2reg(md->constant_encoding(), mdo); 2470 if (mdo_offset_bias > 0) { 2471 __ set(mdo_offset_bias, tmp1); 2472 __ add(mdo, tmp1, mdo); 2473 } 2474 __ load_klass(obj, recv); 2475 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); 2476 // Jump over the failure case 2477 __ ba(*success); 2478 __ delayed()->nop(); 2479 // Cast failure case 2480 __ bind(profile_cast_failure); 2481 metadata2reg(md->constant_encoding(), mdo); 2482 if (mdo_offset_bias > 0) { 2483 __ set(mdo_offset_bias, tmp1); 2484 __ add(mdo, tmp1, mdo); 2485 } 2486 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2487 __ ld_ptr(data_addr, tmp1); 2488 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2489 __ st_ptr(tmp1, data_addr); 2490 __ ba(*failure); 2491 __ delayed()->nop(); 2492 } 2493 __ ba(*success); 2494 __ delayed()->nop(); 2495 } 2496 2497 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2498 LIR_Code code = op->code(); 2499 if (code == lir_store_check) { 2500 Register value = op->object()->as_register(); 2501 Register array = op->array()->as_register(); 2502 Register k_RInfo = op->tmp1()->as_register(); 2503 Register klass_RInfo = op->tmp2()->as_register(); 2504 Register Rtmp1 = op->tmp3()->as_register(); 2505 2506 __ verify_oop(value); 2507 CodeStub* stub = op->stub(); 2508 // check if it needs to be profiled 2509 ciMethodData* md; 2510 ciProfileData* data; 2511 int mdo_offset_bias = 0; 2512 if (op->should_profile()) { 2513 ciMethod* method = op->profiled_method(); 2514 assert(method != NULL, "Should have method"); 2515 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2516 } 2517 Label profile_cast_success, profile_cast_failure, done; 2518 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 2519 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 2520 2521 if (op->should_profile()) { 2522 Label not_null; 2523 __ br_notnull_short(value, Assembler::pn, not_null); 2524 Register mdo = k_RInfo; 2525 Register data_val = Rtmp1; 2526 metadata2reg(md->constant_encoding(), mdo); 2527 if (mdo_offset_bias > 0) { 2528 __ set(mdo_offset_bias, data_val); 2529 __ add(mdo, data_val, mdo); 2530 } 2531 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2532 __ ldub(flags_addr, data_val); 2533 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2534 __ stb(data_val, flags_addr); 2535 __ ba_short(done); 2536 __ bind(not_null); 2537 } else { 2538 __ br_null_short(value, Assembler::pn, done); 2539 } 2540 add_debug_info_for_null_check_here(op->info_for_exception()); 2541 __ load_klass(array, k_RInfo); 2542 __ load_klass(value, klass_RInfo); 2543 2544 // get instance klass 2545 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo); 2546 // perform the fast part of the checking logic 2547 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); 2548 2549 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2550 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2551 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2552 __ delayed()->nop(); 2553 __ cmp(G3, 0); 2554 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2555 __ delayed()->nop(); 2556 // fall through to the success case 2557 2558 if (op->should_profile()) { 2559 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2560 assert_different_registers(value, mdo, recv, tmp1); 2561 __ bind(profile_cast_success); 2562 metadata2reg(md->constant_encoding(), mdo); 2563 if (mdo_offset_bias > 0) { 2564 __ set(mdo_offset_bias, tmp1); 2565 __ add(mdo, tmp1, mdo); 2566 } 2567 __ load_klass(value, recv); 2568 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2569 __ ba_short(done); 2570 // Cast failure case 2571 __ bind(profile_cast_failure); 2572 metadata2reg(md->constant_encoding(), mdo); 2573 if (mdo_offset_bias > 0) { 2574 __ set(mdo_offset_bias, tmp1); 2575 __ add(mdo, tmp1, mdo); 2576 } 2577 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2578 __ ld_ptr(data_addr, tmp1); 2579 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2580 __ st_ptr(tmp1, data_addr); 2581 __ ba(*stub->entry()); 2582 __ delayed()->nop(); 2583 } 2584 __ bind(done); 2585 } else if (code == lir_checkcast) { 2586 Register obj = op->object()->as_register(); 2587 Register dst = op->result_opr()->as_register(); 2588 Label success; 2589 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 2590 __ bind(success); 2591 __ mov(obj, dst); 2592 } else if (code == lir_instanceof) { 2593 Register obj = op->object()->as_register(); 2594 Register dst = op->result_opr()->as_register(); 2595 Label success, failure, done; 2596 emit_typecheck_helper(op, &success, &failure, &failure); 2597 __ bind(failure); 2598 __ set(0, dst); 2599 __ ba_short(done); 2600 __ bind(success); 2601 __ set(1, dst); 2602 __ bind(done); 2603 } else { 2604 ShouldNotReachHere(); 2605 } 2606 2607 } 2608 2609 2610 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2611 if (op->code() == lir_cas_long) { 2612 assert(VM_Version::supports_cx8(), "wrong machine"); 2613 Register addr = op->addr()->as_pointer_register(); 2614 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2615 Register cmp_value_hi = op->cmp_value()->as_register_hi(); 2616 Register new_value_lo = op->new_value()->as_register_lo(); 2617 Register new_value_hi = op->new_value()->as_register_hi(); 2618 Register t1 = op->tmp1()->as_register(); 2619 Register t2 = op->tmp2()->as_register(); 2620 __ mov(cmp_value_lo, t1); 2621 __ mov(new_value_lo, t2); 2622 // perform the compare and swap operation 2623 __ casx(addr, t1, t2); 2624 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2625 // overwritten with the original value in "addr" and will be equal to t1. 2626 __ cmp(t1, t2); 2627 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2628 Register addr = op->addr()->as_pointer_register(); 2629 Register cmp_value = op->cmp_value()->as_register(); 2630 Register new_value = op->new_value()->as_register(); 2631 Register t1 = op->tmp1()->as_register(); 2632 Register t2 = op->tmp2()->as_register(); 2633 __ mov(cmp_value, t1); 2634 __ mov(new_value, t2); 2635 if (op->code() == lir_cas_obj) { 2636 if (UseCompressedOops) { 2637 __ encode_heap_oop(t1); 2638 __ encode_heap_oop(t2); 2639 __ cas(addr, t1, t2); 2640 } else { 2641 __ cas_ptr(addr, t1, t2); 2642 } 2643 } else { 2644 __ cas(addr, t1, t2); 2645 } 2646 __ cmp(t1, t2); 2647 } else { 2648 Unimplemented(); 2649 } 2650 } 2651 2652 void LIR_Assembler::set_24bit_FPU() { 2653 Unimplemented(); 2654 } 2655 2656 2657 void LIR_Assembler::reset_FPU() { 2658 Unimplemented(); 2659 } 2660 2661 2662 void LIR_Assembler::breakpoint() { 2663 __ breakpoint_trap(); 2664 } 2665 2666 2667 void LIR_Assembler::push(LIR_Opr opr) { 2668 Unimplemented(); 2669 } 2670 2671 2672 void LIR_Assembler::pop(LIR_Opr opr) { 2673 Unimplemented(); 2674 } 2675 2676 2677 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2678 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2679 Register dst = dst_opr->as_register(); 2680 Register reg = mon_addr.base(); 2681 int offset = mon_addr.disp(); 2682 // compute pointer to BasicLock 2683 if (mon_addr.is_simm13()) { 2684 __ add(reg, offset, dst); 2685 } else { 2686 __ set(offset, dst); 2687 __ add(dst, reg, dst); 2688 } 2689 } 2690 2691 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 2692 assert(op->crc()->is_single_cpu(), "crc must be register"); 2693 assert(op->val()->is_single_cpu(), "byte value must be register"); 2694 assert(op->result_opr()->is_single_cpu(), "result must be register"); 2695 Register crc = op->crc()->as_register(); 2696 Register val = op->val()->as_register(); 2697 Register table = op->result_opr()->as_register(); 2698 Register res = op->result_opr()->as_register(); 2699 2700 assert_different_registers(val, crc, table); 2701 2702 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table); 2703 __ not1(crc); 2704 __ clruwu(crc); 2705 __ update_byte_crc32(crc, val, table); 2706 __ not1(crc); 2707 2708 __ mov(crc, res); 2709 } 2710 2711 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2712 Register obj = op->obj_opr()->as_register(); 2713 Register hdr = op->hdr_opr()->as_register(); 2714 Register lock = op->lock_opr()->as_register(); 2715 2716 // obj may not be an oop 2717 if (op->code() == lir_lock) { 2718 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2719 if (UseFastLocking) { 2720 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2721 // add debug info for NullPointerException only if one is possible 2722 if (op->info() != NULL) { 2723 add_debug_info_for_null_check_here(op->info()); 2724 } 2725 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2726 } else { 2727 // always do slow locking 2728 // note: the slow locking code could be inlined here, however if we use 2729 // slow locking, speed doesn't matter anyway and this solution is 2730 // simpler and requires less duplicated code - additionally, the 2731 // slow locking code is the same in either case which simplifies 2732 // debugging 2733 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2734 __ delayed()->nop(); 2735 } 2736 } else { 2737 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2738 if (UseFastLocking) { 2739 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2740 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2741 } else { 2742 // always do slow unlocking 2743 // note: the slow unlocking code could be inlined here, however if we use 2744 // slow unlocking, speed doesn't matter anyway and this solution is 2745 // simpler and requires less duplicated code - additionally, the 2746 // slow unlocking code is the same in either case which simplifies 2747 // debugging 2748 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2749 __ delayed()->nop(); 2750 } 2751 } 2752 __ bind(*op->stub()->continuation()); 2753 } 2754 2755 2756 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2757 ciMethod* method = op->profiled_method(); 2758 int bci = op->profiled_bci(); 2759 ciMethod* callee = op->profiled_callee(); 2760 2761 // Update counter for all call types 2762 ciMethodData* md = method->method_data_or_null(); 2763 assert(md != NULL, "Sanity"); 2764 ciProfileData* data = md->bci_to_data(bci); 2765 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2766 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2767 Register mdo = op->mdo()->as_register(); 2768 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2769 Register tmp1 = op->tmp1()->as_register_lo(); 2770 metadata2reg(md->constant_encoding(), mdo); 2771 int mdo_offset_bias = 0; 2772 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2773 data->size_in_bytes())) { 2774 // The offset is large so bias the mdo by the base of the slot so 2775 // that the ld can use simm13s to reference the slots of the data 2776 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2777 __ set(mdo_offset_bias, O7); 2778 __ add(mdo, O7, mdo); 2779 } 2780 2781 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2782 // Perform additional virtual call profiling for invokevirtual and 2783 // invokeinterface bytecodes 2784 if (op->should_profile_receiver_type()) { 2785 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2786 Register recv = op->recv()->as_register(); 2787 assert_different_registers(mdo, tmp1, recv); 2788 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2789 ciKlass* known_klass = op->known_holder(); 2790 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2791 // We know the type that will be seen at this call site; we can 2792 // statically update the MethodData* rather than needing to do 2793 // dynamic tests on the receiver type 2794 2795 // NOTE: we should probably put a lock around this search to 2796 // avoid collisions by concurrent compilations 2797 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2798 uint i; 2799 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2800 ciKlass* receiver = vc_data->receiver(i); 2801 if (known_klass->equals(receiver)) { 2802 Address data_addr(mdo, md->byte_offset_of_slot(data, 2803 VirtualCallData::receiver_count_offset(i)) - 2804 mdo_offset_bias); 2805 __ ld_ptr(data_addr, tmp1); 2806 __ add(tmp1, DataLayout::counter_increment, tmp1); 2807 __ st_ptr(tmp1, data_addr); 2808 return; 2809 } 2810 } 2811 2812 // Receiver type not found in profile data; select an empty slot 2813 2814 // Note that this is less efficient than it should be because it 2815 // always does a write to the receiver part of the 2816 // VirtualCallData rather than just the first time 2817 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2818 ciKlass* receiver = vc_data->receiver(i); 2819 if (receiver == NULL) { 2820 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 2821 mdo_offset_bias); 2822 metadata2reg(known_klass->constant_encoding(), tmp1); 2823 __ st_ptr(tmp1, recv_addr); 2824 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 2825 mdo_offset_bias); 2826 __ ld_ptr(data_addr, tmp1); 2827 __ add(tmp1, DataLayout::counter_increment, tmp1); 2828 __ st_ptr(tmp1, data_addr); 2829 return; 2830 } 2831 } 2832 } else { 2833 __ load_klass(recv, recv); 2834 Label update_done; 2835 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 2836 // Receiver did not match any saved receiver and there is no empty row for it. 2837 // Increment total counter to indicate polymorphic case. 2838 __ ld_ptr(counter_addr, tmp1); 2839 __ add(tmp1, DataLayout::counter_increment, tmp1); 2840 __ st_ptr(tmp1, counter_addr); 2841 2842 __ bind(update_done); 2843 } 2844 } else { 2845 // Static call 2846 __ ld_ptr(counter_addr, tmp1); 2847 __ add(tmp1, DataLayout::counter_increment, tmp1); 2848 __ st_ptr(tmp1, counter_addr); 2849 } 2850 } 2851 2852 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2853 Register obj = op->obj()->as_register(); 2854 Register tmp1 = op->tmp()->as_pointer_register(); 2855 Register tmp2 = G1; 2856 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2857 ciKlass* exact_klass = op->exact_klass(); 2858 intptr_t current_klass = op->current_klass(); 2859 bool not_null = op->not_null(); 2860 bool no_conflict = op->no_conflict(); 2861 2862 Label update, next, none; 2863 2864 bool do_null = !not_null; 2865 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2866 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2867 2868 assert(do_null || do_update, "why are we here?"); 2869 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2870 2871 __ verify_oop(obj); 2872 2873 if (tmp1 != obj) { 2874 __ mov(obj, tmp1); 2875 } 2876 if (do_null) { 2877 __ br_notnull_short(tmp1, Assembler::pt, update); 2878 if (!TypeEntries::was_null_seen(current_klass)) { 2879 __ ld_ptr(mdo_addr, tmp1); 2880 __ or3(tmp1, TypeEntries::null_seen, tmp1); 2881 __ st_ptr(tmp1, mdo_addr); 2882 } 2883 if (do_update) { 2884 __ ba(next); 2885 __ delayed()->nop(); 2886 } 2887 #ifdef ASSERT 2888 } else { 2889 __ br_notnull_short(tmp1, Assembler::pt, update); 2890 __ stop("unexpect null obj"); 2891 #endif 2892 } 2893 2894 __ bind(update); 2895 2896 if (do_update) { 2897 #ifdef ASSERT 2898 if (exact_klass != NULL) { 2899 Label ok; 2900 __ load_klass(tmp1, tmp1); 2901 metadata2reg(exact_klass->constant_encoding(), tmp2); 2902 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok); 2903 __ stop("exact klass and actual klass differ"); 2904 __ bind(ok); 2905 } 2906 #endif 2907 2908 Label do_update; 2909 __ ld_ptr(mdo_addr, tmp2); 2910 2911 if (!no_conflict) { 2912 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 2913 if (exact_klass != NULL) { 2914 metadata2reg(exact_klass->constant_encoding(), tmp1); 2915 } else { 2916 __ load_klass(tmp1, tmp1); 2917 } 2918 2919 __ xor3(tmp1, tmp2, tmp1); 2920 __ btst(TypeEntries::type_klass_mask, tmp1); 2921 // klass seen before, nothing to do. The unknown bit may have been 2922 // set already but no need to check. 2923 __ brx(Assembler::zero, false, Assembler::pt, next); 2924 __ delayed()-> 2925 2926 btst(TypeEntries::type_unknown, tmp1); 2927 // already unknown. Nothing to do anymore. 2928 __ brx(Assembler::notZero, false, Assembler::pt, next); 2929 2930 if (TypeEntries::is_type_none(current_klass)) { 2931 __ delayed()->btst(TypeEntries::type_mask, tmp2); 2932 __ brx(Assembler::zero, true, Assembler::pt, do_update); 2933 // first time here. Set profile type. 2934 __ delayed()->or3(tmp2, tmp1, tmp2); 2935 } else { 2936 __ delayed()->nop(); 2937 } 2938 } else { 2939 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2940 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2941 2942 __ btst(TypeEntries::type_unknown, tmp2); 2943 // already unknown. Nothing to do anymore. 2944 __ brx(Assembler::notZero, false, Assembler::pt, next); 2945 __ delayed()->nop(); 2946 } 2947 2948 // different than before. Cannot keep accurate profile. 2949 __ or3(tmp2, TypeEntries::type_unknown, tmp2); 2950 } else { 2951 // There's a single possible klass at this profile point 2952 assert(exact_klass != NULL, "should be"); 2953 if (TypeEntries::is_type_none(current_klass)) { 2954 metadata2reg(exact_klass->constant_encoding(), tmp1); 2955 __ xor3(tmp1, tmp2, tmp1); 2956 __ btst(TypeEntries::type_klass_mask, tmp1); 2957 __ brx(Assembler::zero, false, Assembler::pt, next); 2958 #ifdef ASSERT 2959 2960 { 2961 Label ok; 2962 __ delayed()->btst(TypeEntries::type_mask, tmp2); 2963 __ brx(Assembler::zero, true, Assembler::pt, ok); 2964 __ delayed()->nop(); 2965 2966 __ stop("unexpected profiling mismatch"); 2967 __ bind(ok); 2968 } 2969 // first time here. Set profile type. 2970 __ or3(tmp2, tmp1, tmp2); 2971 #else 2972 // first time here. Set profile type. 2973 __ delayed()->or3(tmp2, tmp1, tmp2); 2974 #endif 2975 2976 } else { 2977 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2978 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 2979 2980 // already unknown. Nothing to do anymore. 2981 __ btst(TypeEntries::type_unknown, tmp2); 2982 __ brx(Assembler::notZero, false, Assembler::pt, next); 2983 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2); 2984 } 2985 } 2986 2987 __ bind(do_update); 2988 __ st_ptr(tmp2, mdo_addr); 2989 2990 __ bind(next); 2991 } 2992 } 2993 2994 void LIR_Assembler::align_backward_branch_target() { 2995 __ align(OptoLoopAlignment); 2996 } 2997 2998 2999 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 3000 // make sure we are expecting a delay 3001 // this has the side effect of clearing the delay state 3002 // so we can use _masm instead of _masm->delayed() to do the 3003 // code generation. 3004 __ delayed(); 3005 3006 // make sure we only emit one instruction 3007 int offset = code_offset(); 3008 op->delay_op()->emit_code(this); 3009 #ifdef ASSERT 3010 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { 3011 op->delay_op()->print(); 3012 } 3013 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, 3014 "only one instruction can go in a delay slot"); 3015 #endif 3016 3017 // we may also be emitting the call info for the instruction 3018 // which we are the delay slot of. 3019 CodeEmitInfo* call_info = op->call_info(); 3020 if (call_info) { 3021 add_call_info(code_offset(), call_info); 3022 } 3023 3024 if (VerifyStackAtCalls) { 3025 _masm->sub(FP, SP, O7); 3026 _masm->cmp(O7, initial_frame_size_in_bytes()); 3027 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); 3028 } 3029 } 3030 3031 3032 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3033 assert(left->is_register(), "can only handle registers"); 3034 3035 if (left->is_single_cpu()) { 3036 __ neg(left->as_register(), dest->as_register()); 3037 } else if (left->is_single_fpu()) { 3038 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); 3039 } else if (left->is_double_fpu()) { 3040 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); 3041 } else { 3042 assert (left->is_double_cpu(), "Must be a long"); 3043 Register Rlow = left->as_register_lo(); 3044 Register Rhi = left->as_register_hi(); 3045 __ sub(G0, Rlow, dest->as_register_lo()); 3046 } 3047 } 3048 3049 3050 void LIR_Assembler::fxch(int i) { 3051 Unimplemented(); 3052 } 3053 3054 void LIR_Assembler::fld(int i) { 3055 Unimplemented(); 3056 } 3057 3058 void LIR_Assembler::ffree(int i) { 3059 Unimplemented(); 3060 } 3061 3062 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 3063 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3064 3065 // if tmp is invalid, then the function being called doesn't destroy the thread 3066 if (tmp->is_valid()) { 3067 __ save_thread(tmp->as_pointer_register()); 3068 } 3069 __ call(dest, relocInfo::runtime_call_type); 3070 __ delayed()->nop(); 3071 if (info != NULL) { 3072 add_call_info_here(info); 3073 } 3074 if (tmp->is_valid()) { 3075 __ restore_thread(tmp->as_pointer_register()); 3076 } 3077 3078 #ifdef ASSERT 3079 __ verify_thread(); 3080 #endif // ASSERT 3081 } 3082 3083 3084 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3085 ShouldNotReachHere(); 3086 3087 NEEDS_CLEANUP; 3088 if (type == T_LONG) { 3089 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); 3090 3091 // (extended to allow indexed as well as constant displaced for JSR-166) 3092 Register idx = noreg; // contains either constant offset or index 3093 3094 int disp = mem_addr->disp(); 3095 if (mem_addr->index() == LIR_OprFact::illegalOpr) { 3096 if (!Assembler::is_simm13(disp)) { 3097 idx = O7; 3098 __ set(disp, idx); 3099 } 3100 } else { 3101 assert(disp == 0, "not both indexed and disp"); 3102 idx = mem_addr->index()->as_register(); 3103 } 3104 3105 int null_check_offset = -1; 3106 3107 Register base = mem_addr->base()->as_register(); 3108 if (src->is_register() && dest->is_address()) { 3109 // G4 is high half, G5 is low half 3110 // clear the top bits of G5, and scale up G4 3111 __ srl (src->as_register_lo(), 0, G5); 3112 __ sllx(src->as_register_hi(), 32, G4); 3113 // combine the two halves into the 64 bits of G4 3114 __ or3(G4, G5, G4); 3115 null_check_offset = __ offset(); 3116 if (idx == noreg) { 3117 __ stx(G4, base, disp); 3118 } else { 3119 __ stx(G4, base, idx); 3120 } 3121 } else if (src->is_address() && dest->is_register()) { 3122 null_check_offset = __ offset(); 3123 if (idx == noreg) { 3124 __ ldx(base, disp, G5); 3125 } else { 3126 __ ldx(base, idx, G5); 3127 } 3128 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi 3129 __ mov (G5, dest->as_register_lo()); // copy low half into lo 3130 } else { 3131 Unimplemented(); 3132 } 3133 if (info != NULL) { 3134 add_debug_info_for_null_check(null_check_offset, info); 3135 } 3136 3137 } else { 3138 // use normal move for all other volatiles since they don't need 3139 // special handling to remain atomic. 3140 move_op(src, dest, type, lir_patch_none, info, false, false, false); 3141 } 3142 } 3143 3144 void LIR_Assembler::membar() { 3145 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode 3146 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3147 } 3148 3149 void LIR_Assembler::membar_acquire() { 3150 // no-op on TSO 3151 } 3152 3153 void LIR_Assembler::membar_release() { 3154 // no-op on TSO 3155 } 3156 3157 void LIR_Assembler::membar_loadload() { 3158 // no-op 3159 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3160 } 3161 3162 void LIR_Assembler::membar_storestore() { 3163 // no-op 3164 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3165 } 3166 3167 void LIR_Assembler::membar_loadstore() { 3168 // no-op 3169 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3170 } 3171 3172 void LIR_Assembler::membar_storeload() { 3173 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3174 } 3175 3176 void LIR_Assembler::on_spin_wait() { 3177 Unimplemented(); 3178 } 3179 3180 // Pack two sequential registers containing 32 bit values 3181 // into a single 64 bit register. 3182 // src and src->successor() are packed into dst 3183 // src and dst may be the same register. 3184 // Note: src is destroyed 3185 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { 3186 Register rs = src->as_register(); 3187 Register rd = dst->as_register_lo(); 3188 __ sllx(rs, 32, rs); 3189 __ srl(rs->successor(), 0, rs->successor()); 3190 __ or3(rs, rs->successor(), rd); 3191 } 3192 3193 // Unpack a 64 bit value in a register into 3194 // two sequential registers. 3195 // src is unpacked into dst and dst->successor() 3196 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { 3197 Register rs = src->as_register_lo(); 3198 Register rd = dst->as_register_hi(); 3199 assert_different_registers(rs, rd, rd->successor()); 3200 __ srlx(rs, 32, rd); 3201 __ srl (rs, 0, rd->successor()); 3202 } 3203 3204 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 3205 const LIR_Address* addr = addr_opr->as_address_ptr(); 3206 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet"); 3207 const Register dest_reg = dest->as_pointer_register(); 3208 const Register base_reg = addr->base()->as_pointer_register(); 3209 3210 if (Assembler::is_simm13(addr->disp())) { 3211 if (addr->index()->is_valid()) { 3212 const Register index_reg = addr->index()->as_pointer_register(); 3213 assert(index_reg != G3_scratch, "invariant"); 3214 __ add(base_reg, addr->disp(), G3_scratch); 3215 __ add(index_reg, G3_scratch, dest_reg); 3216 } else { 3217 __ add(base_reg, addr->disp(), dest_reg); 3218 } 3219 } else { 3220 __ set(addr->disp(), G3_scratch); 3221 if (addr->index()->is_valid()) { 3222 const Register index_reg = addr->index()->as_pointer_register(); 3223 assert(index_reg != G3_scratch, "invariant"); 3224 __ add(index_reg, G3_scratch, G3_scratch); 3225 } 3226 __ add(base_reg, G3_scratch, dest_reg); 3227 } 3228 } 3229 3230 3231 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3232 assert(result_reg->is_register(), "check"); 3233 __ mov(G2_thread, result_reg->as_register()); 3234 } 3235 3236 #ifdef ASSERT 3237 // emit run-time assertion 3238 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3239 assert(op->code() == lir_assert, "must be"); 3240 3241 if (op->in_opr1()->is_valid()) { 3242 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3243 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3244 } else { 3245 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3246 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3247 } 3248 3249 Label ok; 3250 if (op->condition() != lir_cond_always) { 3251 Assembler::Condition acond; 3252 switch (op->condition()) { 3253 case lir_cond_equal: acond = Assembler::equal; break; 3254 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3255 case lir_cond_less: acond = Assembler::less; break; 3256 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3257 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 3258 case lir_cond_greater: acond = Assembler::greater; break; 3259 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 3260 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 3261 default: ShouldNotReachHere(); 3262 }; 3263 __ br(acond, false, Assembler::pt, ok); 3264 __ delayed()->nop(); 3265 } 3266 if (op->halt()) { 3267 const char* str = __ code_string(op->msg()); 3268 __ stop(str); 3269 } else { 3270 breakpoint(); 3271 } 3272 __ bind(ok); 3273 } 3274 #endif 3275 3276 void LIR_Assembler::peephole(LIR_List* lir) { 3277 LIR_OpList* inst = lir->instructions_list(); 3278 for (int i = 0; i < inst->length(); i++) { 3279 LIR_Op* op = inst->at(i); 3280 switch (op->code()) { 3281 case lir_cond_float_branch: 3282 case lir_branch: { 3283 LIR_OpBranch* branch = op->as_OpBranch(); 3284 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); 3285 LIR_Op* delay_op = NULL; 3286 // we'd like to be able to pull following instructions into 3287 // this slot but we don't know enough to do it safely yet so 3288 // only optimize block to block control flow. 3289 if (LIRFillDelaySlots && branch->block()) { 3290 LIR_Op* prev = inst->at(i - 1); 3291 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { 3292 // swap previous instruction into delay slot 3293 inst->at_put(i - 1, op); 3294 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3295 #ifndef PRODUCT 3296 if (LIRTracePeephole) { 3297 tty->print_cr("delayed"); 3298 inst->at(i - 1)->print(); 3299 inst->at(i)->print(); 3300 tty->cr(); 3301 } 3302 #endif 3303 continue; 3304 } 3305 } 3306 3307 if (!delay_op) { 3308 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); 3309 } 3310 inst->insert_before(i + 1, delay_op); 3311 break; 3312 } 3313 case lir_static_call: 3314 case lir_virtual_call: 3315 case lir_icvirtual_call: 3316 case lir_optvirtual_call: 3317 case lir_dynamic_call: { 3318 LIR_Op* prev = inst->at(i - 1); 3319 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && 3320 (op->code() != lir_virtual_call || 3321 !prev->result_opr()->is_single_cpu() || 3322 prev->result_opr()->as_register() != O0) && 3323 LIR_Assembler::is_single_instruction(prev)) { 3324 // Only moves without info can be put into the delay slot. 3325 // Also don't allow the setup of the receiver in the delay 3326 // slot for vtable calls. 3327 inst->at_put(i - 1, op); 3328 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3329 #ifndef PRODUCT 3330 if (LIRTracePeephole) { 3331 tty->print_cr("delayed"); 3332 inst->at(i - 1)->print(); 3333 inst->at(i)->print(); 3334 tty->cr(); 3335 } 3336 #endif 3337 } else { 3338 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); 3339 inst->insert_before(i + 1, delay_op); 3340 i++; 3341 } 3342 break; 3343 } 3344 } 3345 } 3346 } 3347 3348 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3349 LIR_Address* addr = src->as_address_ptr(); 3350 3351 assert(data == dest, "swap uses only 2 operands"); 3352 assert (code == lir_xchg, "no xadd on sparc"); 3353 3354 if (data->type() == T_INT) { 3355 __ swap(as_Address(addr), data->as_register()); 3356 } else if (data->is_oop()) { 3357 Register obj = data->as_register(); 3358 Register narrow = tmp->as_register(); 3359 assert(UseCompressedOops, "swap is 32bit only"); 3360 __ encode_heap_oop(obj, narrow); 3361 __ swap(as_Address(addr), narrow); 3362 __ decode_heap_oop(narrow, obj); 3363 } else { 3364 ShouldNotReachHere(); 3365 } 3366 } 3367 3368 #undef __