1 /* 2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableModRefBS.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/safepointMechanism.hpp" 41 #include "runtime/sharedRuntime.hpp" 42 #include "vmreg_x86.inline.hpp" 43 44 45 // These masks are used to provide 128-bit aligned bitmasks to the XMM 46 // instructions, to allow sign-masking or sign-bit flipping. They allow 47 // fast versions of NegF/NegD and AbsF/AbsD. 48 49 // Note: 'double' and 'long long' have 32-bits alignment on x86. 50 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 51 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 52 // of 128-bits operands for SSE instructions. 53 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 54 // Store the value to a 128-bits operand. 55 operand[0] = lo; 56 operand[1] = hi; 57 return operand; 58 } 59 60 // Buffer for 128-bits masks used by SSE instructions. 61 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 62 63 // Static initialization during VM startup. 64 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 65 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 66 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 67 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 68 69 70 71 NEEDS_CLEANUP // remove this definitions ? 72 const Register IC_Klass = rax; // where the IC klass is cached 73 const Register SYNC_header = rax; // synchronization header 74 const Register SHIFT_count = rcx; // where count for shift operations must be 75 76 #define __ _masm-> 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2) { 83 if (tmp1 == preserve) { 84 assert_different_registers(tmp1, tmp2, extra); 85 tmp1 = extra; 86 } else if (tmp2 == preserve) { 87 assert_different_registers(tmp1, tmp2, extra); 88 tmp2 = extra; 89 } 90 assert_different_registers(preserve, tmp1, tmp2); 91 } 92 93 94 95 static void select_different_registers(Register preserve, 96 Register extra, 97 Register &tmp1, 98 Register &tmp2, 99 Register &tmp3) { 100 if (tmp1 == preserve) { 101 assert_different_registers(tmp1, tmp2, tmp3, extra); 102 tmp1 = extra; 103 } else if (tmp2 == preserve) { 104 assert_different_registers(tmp1, tmp2, tmp3, extra); 105 tmp2 = extra; 106 } else if (tmp3 == preserve) { 107 assert_different_registers(tmp1, tmp2, tmp3, extra); 108 tmp3 = extra; 109 } 110 assert_different_registers(preserve, tmp1, tmp2, tmp3); 111 } 112 113 114 115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 116 if (opr->is_constant()) { 117 LIR_Const* constant = opr->as_constant_ptr(); 118 switch (constant->type()) { 119 case T_INT: { 120 return true; 121 } 122 123 default: 124 return false; 125 } 126 } 127 return false; 128 } 129 130 131 LIR_Opr LIR_Assembler::receiverOpr() { 132 return FrameMap::receiver_opr; 133 } 134 135 LIR_Opr LIR_Assembler::osrBufferPointer() { 136 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 137 } 138 139 //--------------fpu register translations----------------------- 140 141 142 address LIR_Assembler::float_constant(float f) { 143 address const_addr = __ float_constant(f); 144 if (const_addr == NULL) { 145 bailout("const section overflow"); 146 return __ code()->consts()->start(); 147 } else { 148 return const_addr; 149 } 150 } 151 152 153 address LIR_Assembler::double_constant(double d) { 154 address const_addr = __ double_constant(d); 155 if (const_addr == NULL) { 156 bailout("const section overflow"); 157 return __ code()->consts()->start(); 158 } else { 159 return const_addr; 160 } 161 } 162 163 164 void LIR_Assembler::set_24bit_FPU() { 165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 166 } 167 168 void LIR_Assembler::reset_FPU() { 169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 170 } 171 172 void LIR_Assembler::fpop() { 173 __ fpop(); 174 } 175 176 void LIR_Assembler::fxch(int i) { 177 __ fxch(i); 178 } 179 180 void LIR_Assembler::fld(int i) { 181 __ fld_s(i); 182 } 183 184 void LIR_Assembler::ffree(int i) { 185 __ ffree(i); 186 } 187 188 void LIR_Assembler::breakpoint() { 189 __ int3(); 190 } 191 192 void LIR_Assembler::push(LIR_Opr opr) { 193 if (opr->is_single_cpu()) { 194 __ push_reg(opr->as_register()); 195 } else if (opr->is_double_cpu()) { 196 NOT_LP64(__ push_reg(opr->as_register_hi())); 197 __ push_reg(opr->as_register_lo()); 198 } else if (opr->is_stack()) { 199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 200 } else if (opr->is_constant()) { 201 LIR_Const* const_opr = opr->as_constant_ptr(); 202 if (const_opr->type() == T_OBJECT) { 203 __ push_oop(const_opr->as_jobject()); 204 } else if (const_opr->type() == T_INT) { 205 __ push_jint(const_opr->as_jint()); 206 } else { 207 ShouldNotReachHere(); 208 } 209 210 } else { 211 ShouldNotReachHere(); 212 } 213 } 214 215 void LIR_Assembler::pop(LIR_Opr opr) { 216 if (opr->is_single_cpu()) { 217 __ pop_reg(opr->as_register()); 218 } else { 219 ShouldNotReachHere(); 220 } 221 } 222 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 224 return addr->base()->is_illegal() && addr->index()->is_illegal(); 225 } 226 227 //------------------------------------------- 228 229 Address LIR_Assembler::as_Address(LIR_Address* addr) { 230 return as_Address(addr, rscratch1); 231 } 232 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 234 if (addr->base()->is_illegal()) { 235 assert(addr->index()->is_illegal(), "must be illegal too"); 236 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 237 if (! __ reachable(laddr)) { 238 __ movptr(tmp, laddr.addr()); 239 Address res(tmp, 0); 240 return res; 241 } else { 242 return __ as_Address(laddr); 243 } 244 } 245 246 Register base = addr->base()->as_pointer_register(); 247 248 if (addr->index()->is_illegal()) { 249 return Address( base, addr->disp()); 250 } else if (addr->index()->is_cpu_register()) { 251 Register index = addr->index()->as_pointer_register(); 252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 253 } else if (addr->index()->is_constant()) { 254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 255 assert(Assembler::is_simm32(addr_offset), "must be"); 256 257 return Address(base, addr_offset); 258 } else { 259 Unimplemented(); 260 return Address(); 261 } 262 } 263 264 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 266 Address base = as_Address(addr); 267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 268 } 269 270 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 272 return as_Address(addr); 273 } 274 275 276 void LIR_Assembler::osr_entry() { 277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 278 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 279 ValueStack* entry_state = osr_entry->state(); 280 int number_of_locks = entry_state->locks_size(); 281 282 // we jump here if osr happens with the interpreter 283 // state set up to continue at the beginning of the 284 // loop that triggered osr - in particular, we have 285 // the following registers setup: 286 // 287 // rcx: osr buffer 288 // 289 290 // build frame 291 ciMethod* m = compilation()->method(); 292 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 293 294 // OSR buffer is 295 // 296 // locals[nlocals-1..0] 297 // monitors[0..number_of_locks] 298 // 299 // locals is a direct copy of the interpreter frame so in the osr buffer 300 // so first slot in the local array is the last local from the interpreter 301 // and last slot is local[0] (receiver) from the interpreter 302 // 303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 305 // in the interpreter frame (the method lock if a sync method) 306 307 // Initialize monitors in the compiled activation. 308 // rcx: pointer to osr buffer 309 // 310 // All other registers are dead at this point and the locals will be 311 // copied into place by code emitted in the IR. 312 313 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 315 int monitor_offset = BytesPerWord * method()->max_locals() + 316 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 318 // the OSR buffer using 2 word entries: first the lock and then 319 // the oop. 320 for (int i = 0; i < number_of_locks; i++) { 321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 322 #ifdef ASSERT 323 // verify the interpreter's monitor has a non-null object 324 { 325 Label L; 326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 327 __ jcc(Assembler::notZero, L); 328 __ stop("locked object is NULL"); 329 __ bind(L); 330 } 331 #endif 332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 335 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 336 } 337 } 338 } 339 340 341 // inline cache check; done before the frame is built. 342 int LIR_Assembler::check_icache() { 343 Register receiver = FrameMap::receiver_opr->as_register(); 344 Register ic_klass = IC_Klass; 345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 346 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 347 if (!do_post_padding) { 348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 349 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 350 } 351 int offset = __ offset(); 352 __ inline_cache_check(receiver, IC_Klass); 353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 354 if (do_post_padding) { 355 // force alignment after the cache check. 356 // It's been verified to be aligned if !VerifyOops 357 __ align(CodeEntryAlignment); 358 } 359 return offset; 360 } 361 362 363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 364 jobject o = NULL; 365 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 366 __ movoop(reg, o); 367 patching_epilog(patch, lir_patch_normal, reg, info); 368 } 369 370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 371 Metadata* o = NULL; 372 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 373 __ mov_metadata(reg, o); 374 patching_epilog(patch, lir_patch_normal, reg, info); 375 } 376 377 // This specifies the rsp decrement needed to build the frame 378 int LIR_Assembler::initial_frame_size_in_bytes() const { 379 // if rounding, must let FrameMap know! 380 381 // The frame_map records size in slots (32bit word) 382 383 // subtract two words to account for return address and link 384 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 385 } 386 387 388 int LIR_Assembler::emit_exception_handler() { 389 // if the last instruction is a call (typically to do a throw which 390 // is coming at the end after block reordering) the return address 391 // must still point into the code area in order to avoid assertion 392 // failures when searching for the corresponding bci => add a nop 393 // (was bug 5/14/1999 - gri) 394 __ nop(); 395 396 // generate code for exception handler 397 address handler_base = __ start_a_stub(exception_handler_size()); 398 if (handler_base == NULL) { 399 // not enough space left for the handler 400 bailout("exception handler overflow"); 401 return -1; 402 } 403 404 int offset = code_offset(); 405 406 // the exception oop and pc are in rax, and rdx 407 // no other registers need to be preserved, so invalidate them 408 __ invalidate_registers(false, true, true, false, true, true); 409 410 // check that there is really an exception 411 __ verify_not_null_oop(rax); 412 413 // search an exception handler (rax: exception oop, rdx: throwing pc) 414 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 415 __ should_not_reach_here(); 416 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 417 __ end_a_stub(); 418 419 return offset; 420 } 421 422 423 // Emit the code to remove the frame from the stack in the exception 424 // unwind path. 425 int LIR_Assembler::emit_unwind_handler() { 426 #ifndef PRODUCT 427 if (CommentedAssembly) { 428 _masm->block_comment("Unwind handler"); 429 } 430 #endif 431 432 int offset = code_offset(); 433 434 // Fetch the exception from TLS and clear out exception related thread state 435 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 436 NOT_LP64(__ get_thread(rsi)); 437 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 438 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 439 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 440 441 __ bind(_unwind_handler_entry); 442 __ verify_not_null_oop(rax); 443 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 444 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 445 } 446 447 // Preform needed unlocking 448 MonitorExitStub* stub = NULL; 449 if (method()->is_synchronized()) { 450 monitor_address(0, FrameMap::rax_opr); 451 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 452 __ unlock_object(rdi, rsi, rax, *stub->entry()); 453 __ bind(*stub->continuation()); 454 } 455 456 if (compilation()->env()->dtrace_method_probes()) { 457 #ifdef _LP64 458 __ mov(rdi, r15_thread); 459 __ mov_metadata(rsi, method()->constant_encoding()); 460 #else 461 __ get_thread(rax); 462 __ movptr(Address(rsp, 0), rax); 463 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 464 #endif 465 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 466 } 467 468 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 469 __ mov(rax, rbx); // Restore the exception 470 } 471 472 // remove the activation and dispatch to the unwind handler 473 __ remove_frame(initial_frame_size_in_bytes()); 474 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 475 476 // Emit the slow path assembly 477 if (stub != NULL) { 478 stub->emit_code(this); 479 } 480 481 return offset; 482 } 483 484 485 int LIR_Assembler::emit_deopt_handler() { 486 // if the last instruction is a call (typically to do a throw which 487 // is coming at the end after block reordering) the return address 488 // must still point into the code area in order to avoid assertion 489 // failures when searching for the corresponding bci => add a nop 490 // (was bug 5/14/1999 - gri) 491 __ nop(); 492 493 // generate code for exception handler 494 address handler_base = __ start_a_stub(deopt_handler_size()); 495 if (handler_base == NULL) { 496 // not enough space left for the handler 497 bailout("deopt handler overflow"); 498 return -1; 499 } 500 501 int offset = code_offset(); 502 InternalAddress here(__ pc()); 503 504 __ pushptr(here.addr()); 505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 506 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 507 __ end_a_stub(); 508 509 return offset; 510 } 511 512 513 void LIR_Assembler::return_op(LIR_Opr result) { 514 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 515 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 516 assert(result->fpu() == 0, "result must already be on TOS"); 517 } 518 519 // Pop the stack before the safepoint code 520 __ remove_frame(initial_frame_size_in_bytes()); 521 522 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 523 __ reserved_stack_check(); 524 } 525 526 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 527 528 // Note: we do not need to round double result; float result has the right precision 529 // the poll sets the condition code, but no data registers 530 531 if (SafepointMechanism::uses_thread_local_poll()) { 532 #ifdef _LP64 533 const Register poll_addr = rscratch1; 534 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 535 #else 536 const Register poll_addr = rbx; 537 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite"); 538 __ get_thread(poll_addr); 539 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset())); 540 #endif 541 __ relocate(relocInfo::poll_return_type); 542 __ testl(rax, Address(poll_addr, 0)); 543 } else { 544 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 545 546 if (Assembler::is_polling_page_far()) { 547 __ lea(rscratch1, polling_page); 548 __ relocate(relocInfo::poll_return_type); 549 __ testl(rax, Address(rscratch1, 0)); 550 } else { 551 __ testl(rax, polling_page); 552 } 553 } 554 __ ret(0); 555 } 556 557 558 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 559 guarantee(info != NULL, "Shouldn't be NULL"); 560 int offset = __ offset(); 561 if (SafepointMechanism::uses_thread_local_poll()) { 562 #ifdef _LP64 563 const Register poll_addr = rscratch1; 564 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 565 #else 566 assert(tmp->is_cpu_register(), "needed"); 567 const Register poll_addr = tmp->as_register(); 568 __ get_thread(poll_addr); 569 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset()))); 570 #endif 571 add_debug_info_for_branch(info); 572 __ relocate(relocInfo::poll_type); 573 address pre_pc = __ pc(); 574 __ testl(rax, Address(poll_addr, 0)); 575 address post_pc = __ pc(); 576 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 577 } else { 578 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 579 if (Assembler::is_polling_page_far()) { 580 __ lea(rscratch1, polling_page); 581 offset = __ offset(); 582 add_debug_info_for_branch(info); 583 __ relocate(relocInfo::poll_type); 584 __ testl(rax, Address(rscratch1, 0)); 585 } else { 586 add_debug_info_for_branch(info); 587 __ testl(rax, polling_page); 588 } 589 } 590 return offset; 591 } 592 593 594 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 595 if (from_reg != to_reg) __ mov(to_reg, from_reg); 596 } 597 598 void LIR_Assembler::swap_reg(Register a, Register b) { 599 __ xchgptr(a, b); 600 } 601 602 603 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 604 assert(src->is_constant(), "should not call otherwise"); 605 assert(dest->is_register(), "should not call otherwise"); 606 LIR_Const* c = src->as_constant_ptr(); 607 608 switch (c->type()) { 609 case T_INT: { 610 assert(patch_code == lir_patch_none, "no patching handled here"); 611 __ movl(dest->as_register(), c->as_jint()); 612 break; 613 } 614 615 case T_ADDRESS: { 616 assert(patch_code == lir_patch_none, "no patching handled here"); 617 __ movptr(dest->as_register(), c->as_jint()); 618 break; 619 } 620 621 case T_LONG: { 622 assert(patch_code == lir_patch_none, "no patching handled here"); 623 #ifdef _LP64 624 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 625 #else 626 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 627 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 628 #endif // _LP64 629 break; 630 } 631 632 case T_OBJECT: { 633 if (patch_code != lir_patch_none) { 634 jobject2reg_with_patching(dest->as_register(), info); 635 } else { 636 __ movoop(dest->as_register(), c->as_jobject()); 637 } 638 break; 639 } 640 641 case T_METADATA: { 642 if (patch_code != lir_patch_none) { 643 klass2reg_with_patching(dest->as_register(), info); 644 } else { 645 __ mov_metadata(dest->as_register(), c->as_metadata()); 646 } 647 break; 648 } 649 650 case T_FLOAT: { 651 if (dest->is_single_xmm()) { 652 if (c->is_zero_float()) { 653 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 654 } else { 655 __ movflt(dest->as_xmm_float_reg(), 656 InternalAddress(float_constant(c->as_jfloat()))); 657 } 658 } else { 659 assert(dest->is_single_fpu(), "must be"); 660 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 661 if (c->is_zero_float()) { 662 __ fldz(); 663 } else if (c->is_one_float()) { 664 __ fld1(); 665 } else { 666 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 667 } 668 } 669 break; 670 } 671 672 case T_DOUBLE: { 673 if (dest->is_double_xmm()) { 674 if (c->is_zero_double()) { 675 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 676 } else { 677 __ movdbl(dest->as_xmm_double_reg(), 678 InternalAddress(double_constant(c->as_jdouble()))); 679 } 680 } else { 681 assert(dest->is_double_fpu(), "must be"); 682 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 683 if (c->is_zero_double()) { 684 __ fldz(); 685 } else if (c->is_one_double()) { 686 __ fld1(); 687 } else { 688 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 689 } 690 } 691 break; 692 } 693 694 default: 695 ShouldNotReachHere(); 696 } 697 } 698 699 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 700 assert(src->is_constant(), "should not call otherwise"); 701 assert(dest->is_stack(), "should not call otherwise"); 702 LIR_Const* c = src->as_constant_ptr(); 703 704 switch (c->type()) { 705 case T_INT: // fall through 706 case T_FLOAT: 707 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 708 break; 709 710 case T_ADDRESS: 711 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 712 break; 713 714 case T_OBJECT: 715 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 716 break; 717 718 case T_LONG: // fall through 719 case T_DOUBLE: 720 #ifdef _LP64 721 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 722 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 723 #else 724 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 725 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 726 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 727 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 728 #endif // _LP64 729 break; 730 731 default: 732 ShouldNotReachHere(); 733 } 734 } 735 736 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 737 assert(src->is_constant(), "should not call otherwise"); 738 assert(dest->is_address(), "should not call otherwise"); 739 LIR_Const* c = src->as_constant_ptr(); 740 LIR_Address* addr = dest->as_address_ptr(); 741 742 int null_check_here = code_offset(); 743 switch (type) { 744 case T_INT: // fall through 745 case T_FLOAT: 746 __ movl(as_Address(addr), c->as_jint_bits()); 747 break; 748 749 case T_ADDRESS: 750 __ movptr(as_Address(addr), c->as_jint_bits()); 751 break; 752 753 case T_OBJECT: // fall through 754 case T_ARRAY: 755 if (c->as_jobject() == NULL) { 756 if (UseCompressedOops && !wide) { 757 __ movl(as_Address(addr), (int32_t)NULL_WORD); 758 } else { 759 #ifdef _LP64 760 __ xorptr(rscratch1, rscratch1); 761 null_check_here = code_offset(); 762 __ movptr(as_Address(addr), rscratch1); 763 #else 764 __ movptr(as_Address(addr), NULL_WORD); 765 #endif 766 } 767 } else { 768 if (is_literal_address(addr)) { 769 ShouldNotReachHere(); 770 __ movoop(as_Address(addr, noreg), c->as_jobject()); 771 } else { 772 #ifdef _LP64 773 __ movoop(rscratch1, c->as_jobject()); 774 if (UseCompressedOops && !wide) { 775 __ encode_heap_oop(rscratch1); 776 null_check_here = code_offset(); 777 __ movl(as_Address_lo(addr), rscratch1); 778 } else { 779 null_check_here = code_offset(); 780 __ movptr(as_Address_lo(addr), rscratch1); 781 } 782 #else 783 __ movoop(as_Address(addr), c->as_jobject()); 784 #endif 785 } 786 } 787 break; 788 789 case T_LONG: // fall through 790 case T_DOUBLE: 791 #ifdef _LP64 792 if (is_literal_address(addr)) { 793 ShouldNotReachHere(); 794 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 795 } else { 796 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 797 null_check_here = code_offset(); 798 __ movptr(as_Address_lo(addr), r10); 799 } 800 #else 801 // Always reachable in 32bit so this doesn't produce useless move literal 802 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 803 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 804 #endif // _LP64 805 break; 806 807 case T_BOOLEAN: // fall through 808 case T_BYTE: 809 __ movb(as_Address(addr), c->as_jint() & 0xFF); 810 break; 811 812 case T_CHAR: // fall through 813 case T_SHORT: 814 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 815 break; 816 817 default: 818 ShouldNotReachHere(); 819 }; 820 821 if (info != NULL) { 822 add_debug_info_for_null_check(null_check_here, info); 823 } 824 } 825 826 827 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 828 assert(src->is_register(), "should not call otherwise"); 829 assert(dest->is_register(), "should not call otherwise"); 830 831 // move between cpu-registers 832 if (dest->is_single_cpu()) { 833 #ifdef _LP64 834 if (src->type() == T_LONG) { 835 // Can do LONG -> OBJECT 836 move_regs(src->as_register_lo(), dest->as_register()); 837 return; 838 } 839 #endif 840 assert(src->is_single_cpu(), "must match"); 841 if (src->type() == T_OBJECT) { 842 __ verify_oop(src->as_register()); 843 } 844 move_regs(src->as_register(), dest->as_register()); 845 846 } else if (dest->is_double_cpu()) { 847 #ifdef _LP64 848 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 849 // Surprising to me but we can see move of a long to t_object 850 __ verify_oop(src->as_register()); 851 move_regs(src->as_register(), dest->as_register_lo()); 852 return; 853 } 854 #endif 855 assert(src->is_double_cpu(), "must match"); 856 Register f_lo = src->as_register_lo(); 857 Register f_hi = src->as_register_hi(); 858 Register t_lo = dest->as_register_lo(); 859 Register t_hi = dest->as_register_hi(); 860 #ifdef _LP64 861 assert(f_hi == f_lo, "must be same"); 862 assert(t_hi == t_lo, "must be same"); 863 move_regs(f_lo, t_lo); 864 #else 865 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 866 867 868 if (f_lo == t_hi && f_hi == t_lo) { 869 swap_reg(f_lo, f_hi); 870 } else if (f_hi == t_lo) { 871 assert(f_lo != t_hi, "overwriting register"); 872 move_regs(f_hi, t_hi); 873 move_regs(f_lo, t_lo); 874 } else { 875 assert(f_hi != t_lo, "overwriting register"); 876 move_regs(f_lo, t_lo); 877 move_regs(f_hi, t_hi); 878 } 879 #endif // LP64 880 881 // special moves from fpu-register to xmm-register 882 // necessary for method results 883 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 884 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 885 __ fld_s(Address(rsp, 0)); 886 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 887 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 888 __ fld_d(Address(rsp, 0)); 889 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 890 __ fstp_s(Address(rsp, 0)); 891 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 892 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 893 __ fstp_d(Address(rsp, 0)); 894 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 895 896 // move between xmm-registers 897 } else if (dest->is_single_xmm()) { 898 assert(src->is_single_xmm(), "must match"); 899 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 900 } else if (dest->is_double_xmm()) { 901 assert(src->is_double_xmm(), "must match"); 902 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 903 904 // move between fpu-registers (no instruction necessary because of fpu-stack) 905 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 906 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 907 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 908 } else { 909 ShouldNotReachHere(); 910 } 911 } 912 913 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 914 assert(src->is_register(), "should not call otherwise"); 915 assert(dest->is_stack(), "should not call otherwise"); 916 917 if (src->is_single_cpu()) { 918 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 919 if (type == T_OBJECT || type == T_ARRAY) { 920 __ verify_oop(src->as_register()); 921 __ movptr (dst, src->as_register()); 922 } else if (type == T_METADATA) { 923 __ movptr (dst, src->as_register()); 924 } else { 925 __ movl (dst, src->as_register()); 926 } 927 928 } else if (src->is_double_cpu()) { 929 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 930 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 931 __ movptr (dstLO, src->as_register_lo()); 932 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 933 934 } else if (src->is_single_xmm()) { 935 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 936 __ movflt(dst_addr, src->as_xmm_float_reg()); 937 938 } else if (src->is_double_xmm()) { 939 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 940 __ movdbl(dst_addr, src->as_xmm_double_reg()); 941 942 } else if (src->is_single_fpu()) { 943 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 944 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 945 if (pop_fpu_stack) __ fstp_s (dst_addr); 946 else __ fst_s (dst_addr); 947 948 } else if (src->is_double_fpu()) { 949 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 950 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 951 if (pop_fpu_stack) __ fstp_d (dst_addr); 952 else __ fst_d (dst_addr); 953 954 } else { 955 ShouldNotReachHere(); 956 } 957 } 958 959 960 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 961 LIR_Address* to_addr = dest->as_address_ptr(); 962 PatchingStub* patch = NULL; 963 Register compressed_src = rscratch1; 964 965 if (type == T_ARRAY || type == T_OBJECT) { 966 __ verify_oop(src->as_register()); 967 #ifdef _LP64 968 if (UseCompressedOops && !wide) { 969 __ movptr(compressed_src, src->as_register()); 970 __ encode_heap_oop(compressed_src); 971 if (patch_code != lir_patch_none) { 972 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 973 } 974 } 975 #endif 976 } 977 978 if (patch_code != lir_patch_none) { 979 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 980 Address toa = as_Address(to_addr); 981 assert(toa.disp() != 0, "must have"); 982 } 983 984 int null_check_here = code_offset(); 985 switch (type) { 986 case T_FLOAT: { 987 if (src->is_single_xmm()) { 988 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 989 } else { 990 assert(src->is_single_fpu(), "must be"); 991 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 992 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 993 else __ fst_s (as_Address(to_addr)); 994 } 995 break; 996 } 997 998 case T_DOUBLE: { 999 if (src->is_double_xmm()) { 1000 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1001 } else { 1002 assert(src->is_double_fpu(), "must be"); 1003 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1004 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1005 else __ fst_d (as_Address(to_addr)); 1006 } 1007 break; 1008 } 1009 1010 case T_ARRAY: // fall through 1011 case T_OBJECT: // fall through 1012 if (UseCompressedOops && !wide) { 1013 __ movl(as_Address(to_addr), compressed_src); 1014 } else { 1015 __ movptr(as_Address(to_addr), src->as_register()); 1016 } 1017 break; 1018 case T_METADATA: 1019 // We get here to store a method pointer to the stack to pass to 1020 // a dtrace runtime call. This can't work on 64 bit with 1021 // compressed klass ptrs: T_METADATA can be a compressed klass 1022 // ptr or a 64 bit method pointer. 1023 LP64_ONLY(ShouldNotReachHere()); 1024 __ movptr(as_Address(to_addr), src->as_register()); 1025 break; 1026 case T_ADDRESS: 1027 __ movptr(as_Address(to_addr), src->as_register()); 1028 break; 1029 case T_INT: 1030 __ movl(as_Address(to_addr), src->as_register()); 1031 break; 1032 1033 case T_LONG: { 1034 Register from_lo = src->as_register_lo(); 1035 Register from_hi = src->as_register_hi(); 1036 #ifdef _LP64 1037 __ movptr(as_Address_lo(to_addr), from_lo); 1038 #else 1039 Register base = to_addr->base()->as_register(); 1040 Register index = noreg; 1041 if (to_addr->index()->is_register()) { 1042 index = to_addr->index()->as_register(); 1043 } 1044 if (base == from_lo || index == from_lo) { 1045 assert(base != from_hi, "can't be"); 1046 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1047 __ movl(as_Address_hi(to_addr), from_hi); 1048 if (patch != NULL) { 1049 patching_epilog(patch, lir_patch_high, base, info); 1050 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1051 patch_code = lir_patch_low; 1052 } 1053 __ movl(as_Address_lo(to_addr), from_lo); 1054 } else { 1055 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1056 __ movl(as_Address_lo(to_addr), from_lo); 1057 if (patch != NULL) { 1058 patching_epilog(patch, lir_patch_low, base, info); 1059 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1060 patch_code = lir_patch_high; 1061 } 1062 __ movl(as_Address_hi(to_addr), from_hi); 1063 } 1064 #endif // _LP64 1065 break; 1066 } 1067 1068 case T_BYTE: // fall through 1069 case T_BOOLEAN: { 1070 Register src_reg = src->as_register(); 1071 Address dst_addr = as_Address(to_addr); 1072 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1073 __ movb(dst_addr, src_reg); 1074 break; 1075 } 1076 1077 case T_CHAR: // fall through 1078 case T_SHORT: 1079 __ movw(as_Address(to_addr), src->as_register()); 1080 break; 1081 1082 default: 1083 ShouldNotReachHere(); 1084 } 1085 if (info != NULL) { 1086 add_debug_info_for_null_check(null_check_here, info); 1087 } 1088 1089 if (patch_code != lir_patch_none) { 1090 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1091 } 1092 } 1093 1094 1095 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1096 assert(src->is_stack(), "should not call otherwise"); 1097 assert(dest->is_register(), "should not call otherwise"); 1098 1099 if (dest->is_single_cpu()) { 1100 if (type == T_ARRAY || type == T_OBJECT) { 1101 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1102 __ verify_oop(dest->as_register()); 1103 } else if (type == T_METADATA) { 1104 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1105 } else { 1106 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1107 } 1108 1109 } else if (dest->is_double_cpu()) { 1110 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1111 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1112 __ movptr(dest->as_register_lo(), src_addr_LO); 1113 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1114 1115 } else if (dest->is_single_xmm()) { 1116 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1117 __ movflt(dest->as_xmm_float_reg(), src_addr); 1118 1119 } else if (dest->is_double_xmm()) { 1120 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1121 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1122 1123 } else if (dest->is_single_fpu()) { 1124 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1125 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1126 __ fld_s(src_addr); 1127 1128 } else if (dest->is_double_fpu()) { 1129 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1130 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1131 __ fld_d(src_addr); 1132 1133 } else { 1134 ShouldNotReachHere(); 1135 } 1136 } 1137 1138 1139 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1140 if (src->is_single_stack()) { 1141 if (type == T_OBJECT || type == T_ARRAY) { 1142 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1143 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1144 } else { 1145 #ifndef _LP64 1146 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1147 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1148 #else 1149 //no pushl on 64bits 1150 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1151 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1152 #endif 1153 } 1154 1155 } else if (src->is_double_stack()) { 1156 #ifdef _LP64 1157 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1158 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1159 #else 1160 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1161 // push and pop the part at src + wordSize, adding wordSize for the previous push 1162 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1163 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1165 #endif // _LP64 1166 1167 } else { 1168 ShouldNotReachHere(); 1169 } 1170 } 1171 1172 1173 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1174 assert(src->is_address(), "should not call otherwise"); 1175 assert(dest->is_register(), "should not call otherwise"); 1176 1177 LIR_Address* addr = src->as_address_ptr(); 1178 Address from_addr = as_Address(addr); 1179 1180 if (addr->base()->type() == T_OBJECT) { 1181 __ verify_oop(addr->base()->as_pointer_register()); 1182 } 1183 1184 switch (type) { 1185 case T_BOOLEAN: // fall through 1186 case T_BYTE: // fall through 1187 case T_CHAR: // fall through 1188 case T_SHORT: 1189 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1190 // on pre P6 processors we may get partial register stalls 1191 // so blow away the value of to_rinfo before loading a 1192 // partial word into it. Do it here so that it precedes 1193 // the potential patch point below. 1194 __ xorptr(dest->as_register(), dest->as_register()); 1195 } 1196 break; 1197 default: 1198 break; 1199 } 1200 1201 PatchingStub* patch = NULL; 1202 if (patch_code != lir_patch_none) { 1203 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1204 assert(from_addr.disp() != 0, "must have"); 1205 } 1206 if (info != NULL) { 1207 add_debug_info_for_null_check_here(info); 1208 } 1209 1210 switch (type) { 1211 case T_FLOAT: { 1212 if (dest->is_single_xmm()) { 1213 __ movflt(dest->as_xmm_float_reg(), from_addr); 1214 } else { 1215 assert(dest->is_single_fpu(), "must be"); 1216 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1217 __ fld_s(from_addr); 1218 } 1219 break; 1220 } 1221 1222 case T_DOUBLE: { 1223 if (dest->is_double_xmm()) { 1224 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1225 } else { 1226 assert(dest->is_double_fpu(), "must be"); 1227 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1228 __ fld_d(from_addr); 1229 } 1230 break; 1231 } 1232 1233 case T_OBJECT: // fall through 1234 case T_ARRAY: // fall through 1235 if (UseCompressedOops && !wide) { 1236 __ movl(dest->as_register(), from_addr); 1237 } else { 1238 __ movptr(dest->as_register(), from_addr); 1239 } 1240 break; 1241 1242 case T_ADDRESS: 1243 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1244 __ movl(dest->as_register(), from_addr); 1245 } else { 1246 __ movptr(dest->as_register(), from_addr); 1247 } 1248 break; 1249 case T_INT: 1250 __ movl(dest->as_register(), from_addr); 1251 break; 1252 1253 case T_LONG: { 1254 Register to_lo = dest->as_register_lo(); 1255 Register to_hi = dest->as_register_hi(); 1256 #ifdef _LP64 1257 __ movptr(to_lo, as_Address_lo(addr)); 1258 #else 1259 Register base = addr->base()->as_register(); 1260 Register index = noreg; 1261 if (addr->index()->is_register()) { 1262 index = addr->index()->as_register(); 1263 } 1264 if ((base == to_lo && index == to_hi) || 1265 (base == to_hi && index == to_lo)) { 1266 // addresses with 2 registers are only formed as a result of 1267 // array access so this code will never have to deal with 1268 // patches or null checks. 1269 assert(info == NULL && patch == NULL, "must be"); 1270 __ lea(to_hi, as_Address(addr)); 1271 __ movl(to_lo, Address(to_hi, 0)); 1272 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1273 } else if (base == to_lo || index == to_lo) { 1274 assert(base != to_hi, "can't be"); 1275 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1276 __ movl(to_hi, as_Address_hi(addr)); 1277 if (patch != NULL) { 1278 patching_epilog(patch, lir_patch_high, base, info); 1279 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1280 patch_code = lir_patch_low; 1281 } 1282 __ movl(to_lo, as_Address_lo(addr)); 1283 } else { 1284 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1285 __ movl(to_lo, as_Address_lo(addr)); 1286 if (patch != NULL) { 1287 patching_epilog(patch, lir_patch_low, base, info); 1288 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1289 patch_code = lir_patch_high; 1290 } 1291 __ movl(to_hi, as_Address_hi(addr)); 1292 } 1293 #endif // _LP64 1294 break; 1295 } 1296 1297 case T_BOOLEAN: // fall through 1298 case T_BYTE: { 1299 Register dest_reg = dest->as_register(); 1300 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1301 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1302 __ movsbl(dest_reg, from_addr); 1303 } else { 1304 __ movb(dest_reg, from_addr); 1305 __ shll(dest_reg, 24); 1306 __ sarl(dest_reg, 24); 1307 } 1308 break; 1309 } 1310 1311 case T_CHAR: { 1312 Register dest_reg = dest->as_register(); 1313 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1314 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1315 __ movzwl(dest_reg, from_addr); 1316 } else { 1317 __ movw(dest_reg, from_addr); 1318 } 1319 break; 1320 } 1321 1322 case T_SHORT: { 1323 Register dest_reg = dest->as_register(); 1324 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1325 __ movswl(dest_reg, from_addr); 1326 } else { 1327 __ movw(dest_reg, from_addr); 1328 __ shll(dest_reg, 16); 1329 __ sarl(dest_reg, 16); 1330 } 1331 break; 1332 } 1333 1334 default: 1335 ShouldNotReachHere(); 1336 } 1337 1338 if (patch != NULL) { 1339 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1340 } 1341 1342 if (type == T_ARRAY || type == T_OBJECT) { 1343 #ifdef _LP64 1344 if (UseCompressedOops && !wide) { 1345 __ decode_heap_oop(dest->as_register()); 1346 } 1347 #endif 1348 __ verify_oop(dest->as_register()); 1349 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1350 #ifdef _LP64 1351 if (UseCompressedClassPointers) { 1352 __ decode_klass_not_null(dest->as_register()); 1353 } 1354 #endif 1355 } 1356 } 1357 1358 1359 NEEDS_CLEANUP; // This could be static? 1360 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1361 int elem_size = type2aelembytes(type); 1362 switch (elem_size) { 1363 case 1: return Address::times_1; 1364 case 2: return Address::times_2; 1365 case 4: return Address::times_4; 1366 case 8: return Address::times_8; 1367 } 1368 ShouldNotReachHere(); 1369 return Address::no_scale; 1370 } 1371 1372 1373 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1374 switch (op->code()) { 1375 case lir_idiv: 1376 case lir_irem: 1377 arithmetic_idiv(op->code(), 1378 op->in_opr1(), 1379 op->in_opr2(), 1380 op->in_opr3(), 1381 op->result_opr(), 1382 op->info()); 1383 break; 1384 case lir_fmad: 1385 __ fmad(op->result_opr()->as_xmm_double_reg(), 1386 op->in_opr1()->as_xmm_double_reg(), 1387 op->in_opr2()->as_xmm_double_reg(), 1388 op->in_opr3()->as_xmm_double_reg()); 1389 break; 1390 case lir_fmaf: 1391 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1392 op->in_opr1()->as_xmm_float_reg(), 1393 op->in_opr2()->as_xmm_float_reg(), 1394 op->in_opr3()->as_xmm_float_reg()); 1395 break; 1396 default: ShouldNotReachHere(); break; 1397 } 1398 } 1399 1400 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1401 #ifdef ASSERT 1402 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1403 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1404 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1405 #endif 1406 1407 if (op->cond() == lir_cond_always) { 1408 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1409 __ jmp (*(op->label())); 1410 } else { 1411 Assembler::Condition acond = Assembler::zero; 1412 if (op->code() == lir_cond_float_branch) { 1413 assert(op->ublock() != NULL, "must have unordered successor"); 1414 __ jcc(Assembler::parity, *(op->ublock()->label())); 1415 switch(op->cond()) { 1416 case lir_cond_equal: acond = Assembler::equal; break; 1417 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1418 case lir_cond_less: acond = Assembler::below; break; 1419 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1420 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1421 case lir_cond_greater: acond = Assembler::above; break; 1422 default: ShouldNotReachHere(); 1423 } 1424 } else { 1425 switch (op->cond()) { 1426 case lir_cond_equal: acond = Assembler::equal; break; 1427 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1428 case lir_cond_less: acond = Assembler::less; break; 1429 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1430 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1431 case lir_cond_greater: acond = Assembler::greater; break; 1432 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1433 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1434 default: ShouldNotReachHere(); 1435 } 1436 } 1437 __ jcc(acond,*(op->label())); 1438 } 1439 } 1440 1441 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1442 LIR_Opr src = op->in_opr(); 1443 LIR_Opr dest = op->result_opr(); 1444 1445 switch (op->bytecode()) { 1446 case Bytecodes::_i2l: 1447 #ifdef _LP64 1448 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1449 #else 1450 move_regs(src->as_register(), dest->as_register_lo()); 1451 move_regs(src->as_register(), dest->as_register_hi()); 1452 __ sarl(dest->as_register_hi(), 31); 1453 #endif // LP64 1454 break; 1455 1456 case Bytecodes::_l2i: 1457 #ifdef _LP64 1458 __ movl(dest->as_register(), src->as_register_lo()); 1459 #else 1460 move_regs(src->as_register_lo(), dest->as_register()); 1461 #endif 1462 break; 1463 1464 case Bytecodes::_i2b: 1465 move_regs(src->as_register(), dest->as_register()); 1466 __ sign_extend_byte(dest->as_register()); 1467 break; 1468 1469 case Bytecodes::_i2c: 1470 move_regs(src->as_register(), dest->as_register()); 1471 __ andl(dest->as_register(), 0xFFFF); 1472 break; 1473 1474 case Bytecodes::_i2s: 1475 move_regs(src->as_register(), dest->as_register()); 1476 __ sign_extend_short(dest->as_register()); 1477 break; 1478 1479 1480 case Bytecodes::_f2d: 1481 case Bytecodes::_d2f: 1482 if (dest->is_single_xmm()) { 1483 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1484 } else if (dest->is_double_xmm()) { 1485 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1486 } else { 1487 assert(src->fpu() == dest->fpu(), "register must be equal"); 1488 // do nothing (float result is rounded later through spilling) 1489 } 1490 break; 1491 1492 case Bytecodes::_i2f: 1493 case Bytecodes::_i2d: 1494 if (dest->is_single_xmm()) { 1495 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1496 } else if (dest->is_double_xmm()) { 1497 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1498 } else { 1499 assert(dest->fpu() == 0, "result must be on TOS"); 1500 __ movl(Address(rsp, 0), src->as_register()); 1501 __ fild_s(Address(rsp, 0)); 1502 } 1503 break; 1504 1505 case Bytecodes::_f2i: 1506 case Bytecodes::_d2i: 1507 if (src->is_single_xmm()) { 1508 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1509 } else if (src->is_double_xmm()) { 1510 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1511 } else { 1512 assert(src->fpu() == 0, "input must be on TOS"); 1513 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1514 __ fist_s(Address(rsp, 0)); 1515 __ movl(dest->as_register(), Address(rsp, 0)); 1516 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1517 } 1518 1519 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1520 assert(op->stub() != NULL, "stub required"); 1521 __ cmpl(dest->as_register(), 0x80000000); 1522 __ jcc(Assembler::equal, *op->stub()->entry()); 1523 __ bind(*op->stub()->continuation()); 1524 break; 1525 1526 case Bytecodes::_l2f: 1527 case Bytecodes::_l2d: 1528 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1529 assert(dest->fpu() == 0, "result must be on TOS"); 1530 1531 __ movptr(Address(rsp, 0), src->as_register_lo()); 1532 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1533 __ fild_d(Address(rsp, 0)); 1534 // float result is rounded later through spilling 1535 break; 1536 1537 case Bytecodes::_f2l: 1538 case Bytecodes::_d2l: 1539 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1540 assert(src->fpu() == 0, "input must be on TOS"); 1541 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1542 1543 // instruction sequence too long to inline it here 1544 { 1545 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1546 } 1547 break; 1548 1549 default: ShouldNotReachHere(); 1550 } 1551 } 1552 1553 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1554 if (op->init_check()) { 1555 add_debug_info_for_null_check_here(op->stub()->info()); 1556 __ cmpb(Address(op->klass()->as_register(), 1557 InstanceKlass::init_state_offset()), 1558 InstanceKlass::fully_initialized); 1559 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1560 } 1561 __ allocate_object(op->obj()->as_register(), 1562 op->tmp1()->as_register(), 1563 op->tmp2()->as_register(), 1564 op->header_size(), 1565 op->object_size(), 1566 op->klass()->as_register(), 1567 *op->stub()->entry()); 1568 __ bind(*op->stub()->continuation()); 1569 } 1570 1571 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1572 Register len = op->len()->as_register(); 1573 LP64_ONLY( __ movslq(len, len); ) 1574 1575 if (UseSlowPath || 1576 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1577 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1578 __ jmp(*op->stub()->entry()); 1579 } else { 1580 Register tmp1 = op->tmp1()->as_register(); 1581 Register tmp2 = op->tmp2()->as_register(); 1582 Register tmp3 = op->tmp3()->as_register(); 1583 if (len == tmp1) { 1584 tmp1 = tmp3; 1585 } else if (len == tmp2) { 1586 tmp2 = tmp3; 1587 } else if (len == tmp3) { 1588 // everything is ok 1589 } else { 1590 __ mov(tmp3, len); 1591 } 1592 __ allocate_array(op->obj()->as_register(), 1593 len, 1594 tmp1, 1595 tmp2, 1596 arrayOopDesc::header_size(op->type()), 1597 array_element_size(op->type()), 1598 op->klass()->as_register(), 1599 *op->stub()->entry()); 1600 } 1601 __ bind(*op->stub()->continuation()); 1602 } 1603 1604 void LIR_Assembler::type_profile_helper(Register mdo, 1605 ciMethodData *md, ciProfileData *data, 1606 Register recv, Label* update_done) { 1607 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1608 Label next_test; 1609 // See if the receiver is receiver[n]. 1610 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1611 __ jccb(Assembler::notEqual, next_test); 1612 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1613 __ addptr(data_addr, DataLayout::counter_increment); 1614 __ jmp(*update_done); 1615 __ bind(next_test); 1616 } 1617 1618 // Didn't find receiver; find next empty slot and fill it in 1619 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1620 Label next_test; 1621 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1622 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1623 __ jccb(Assembler::notEqual, next_test); 1624 __ movptr(recv_addr, recv); 1625 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1626 __ jmp(*update_done); 1627 __ bind(next_test); 1628 } 1629 } 1630 1631 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1632 // we always need a stub for the failure case. 1633 CodeStub* stub = op->stub(); 1634 Register obj = op->object()->as_register(); 1635 Register k_RInfo = op->tmp1()->as_register(); 1636 Register klass_RInfo = op->tmp2()->as_register(); 1637 Register dst = op->result_opr()->as_register(); 1638 ciKlass* k = op->klass(); 1639 Register Rtmp1 = noreg; 1640 1641 // check if it needs to be profiled 1642 ciMethodData* md = NULL; 1643 ciProfileData* data = NULL; 1644 1645 if (op->should_profile()) { 1646 ciMethod* method = op->profiled_method(); 1647 assert(method != NULL, "Should have method"); 1648 int bci = op->profiled_bci(); 1649 md = method->method_data_or_null(); 1650 assert(md != NULL, "Sanity"); 1651 data = md->bci_to_data(bci); 1652 assert(data != NULL, "need data for type check"); 1653 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1654 } 1655 Label profile_cast_success, profile_cast_failure; 1656 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1657 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1658 1659 if (obj == k_RInfo) { 1660 k_RInfo = dst; 1661 } else if (obj == klass_RInfo) { 1662 klass_RInfo = dst; 1663 } 1664 if (k->is_loaded() && !UseCompressedClassPointers) { 1665 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1666 } else { 1667 Rtmp1 = op->tmp3()->as_register(); 1668 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1669 } 1670 1671 assert_different_registers(obj, k_RInfo, klass_RInfo); 1672 1673 __ cmpptr(obj, (int32_t)NULL_WORD); 1674 if (op->should_profile()) { 1675 Label not_null; 1676 __ jccb(Assembler::notEqual, not_null); 1677 // Object is null; update MDO and exit 1678 Register mdo = klass_RInfo; 1679 __ mov_metadata(mdo, md->constant_encoding()); 1680 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1681 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1682 __ orl(data_addr, header_bits); 1683 __ jmp(*obj_is_null); 1684 __ bind(not_null); 1685 } else { 1686 __ jcc(Assembler::equal, *obj_is_null); 1687 } 1688 1689 if (!k->is_loaded()) { 1690 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1691 } else { 1692 #ifdef _LP64 1693 __ mov_metadata(k_RInfo, k->constant_encoding()); 1694 #endif // _LP64 1695 } 1696 __ verify_oop(obj); 1697 1698 if (op->fast_check()) { 1699 // get object class 1700 // not a safepoint as obj null check happens earlier 1701 #ifdef _LP64 1702 if (UseCompressedClassPointers) { 1703 __ load_klass(Rtmp1, obj); 1704 __ cmpptr(k_RInfo, Rtmp1); 1705 } else { 1706 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1707 } 1708 #else 1709 if (k->is_loaded()) { 1710 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1711 } else { 1712 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1713 } 1714 #endif 1715 __ jcc(Assembler::notEqual, *failure_target); 1716 // successful cast, fall through to profile or jump 1717 } else { 1718 // get object class 1719 // not a safepoint as obj null check happens earlier 1720 __ load_klass(klass_RInfo, obj); 1721 if (k->is_loaded()) { 1722 // See if we get an immediate positive hit 1723 #ifdef _LP64 1724 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1725 #else 1726 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1727 #endif // _LP64 1728 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1729 __ jcc(Assembler::notEqual, *failure_target); 1730 // successful cast, fall through to profile or jump 1731 } else { 1732 // See if we get an immediate positive hit 1733 __ jcc(Assembler::equal, *success_target); 1734 // check for self 1735 #ifdef _LP64 1736 __ cmpptr(klass_RInfo, k_RInfo); 1737 #else 1738 __ cmpklass(klass_RInfo, k->constant_encoding()); 1739 #endif // _LP64 1740 __ jcc(Assembler::equal, *success_target); 1741 1742 __ push(klass_RInfo); 1743 #ifdef _LP64 1744 __ push(k_RInfo); 1745 #else 1746 __ pushklass(k->constant_encoding()); 1747 #endif // _LP64 1748 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1749 __ pop(klass_RInfo); 1750 __ pop(klass_RInfo); 1751 // result is a boolean 1752 __ cmpl(klass_RInfo, 0); 1753 __ jcc(Assembler::equal, *failure_target); 1754 // successful cast, fall through to profile or jump 1755 } 1756 } else { 1757 // perform the fast part of the checking logic 1758 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1759 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1760 __ push(klass_RInfo); 1761 __ push(k_RInfo); 1762 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1763 __ pop(klass_RInfo); 1764 __ pop(k_RInfo); 1765 // result is a boolean 1766 __ cmpl(k_RInfo, 0); 1767 __ jcc(Assembler::equal, *failure_target); 1768 // successful cast, fall through to profile or jump 1769 } 1770 } 1771 if (op->should_profile()) { 1772 Register mdo = klass_RInfo, recv = k_RInfo; 1773 __ bind(profile_cast_success); 1774 __ mov_metadata(mdo, md->constant_encoding()); 1775 __ load_klass(recv, obj); 1776 Label update_done; 1777 type_profile_helper(mdo, md, data, recv, success); 1778 __ jmp(*success); 1779 1780 __ bind(profile_cast_failure); 1781 __ mov_metadata(mdo, md->constant_encoding()); 1782 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1783 __ subptr(counter_addr, DataLayout::counter_increment); 1784 __ jmp(*failure); 1785 } 1786 __ jmp(*success); 1787 } 1788 1789 1790 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1791 LIR_Code code = op->code(); 1792 if (code == lir_store_check) { 1793 Register value = op->object()->as_register(); 1794 Register array = op->array()->as_register(); 1795 Register k_RInfo = op->tmp1()->as_register(); 1796 Register klass_RInfo = op->tmp2()->as_register(); 1797 Register Rtmp1 = op->tmp3()->as_register(); 1798 1799 CodeStub* stub = op->stub(); 1800 1801 // check if it needs to be profiled 1802 ciMethodData* md = NULL; 1803 ciProfileData* data = NULL; 1804 1805 if (op->should_profile()) { 1806 ciMethod* method = op->profiled_method(); 1807 assert(method != NULL, "Should have method"); 1808 int bci = op->profiled_bci(); 1809 md = method->method_data_or_null(); 1810 assert(md != NULL, "Sanity"); 1811 data = md->bci_to_data(bci); 1812 assert(data != NULL, "need data for type check"); 1813 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1814 } 1815 Label profile_cast_success, profile_cast_failure, done; 1816 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1817 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1818 1819 __ cmpptr(value, (int32_t)NULL_WORD); 1820 if (op->should_profile()) { 1821 Label not_null; 1822 __ jccb(Assembler::notEqual, not_null); 1823 // Object is null; update MDO and exit 1824 Register mdo = klass_RInfo; 1825 __ mov_metadata(mdo, md->constant_encoding()); 1826 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1827 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1828 __ orl(data_addr, header_bits); 1829 __ jmp(done); 1830 __ bind(not_null); 1831 } else { 1832 __ jcc(Assembler::equal, done); 1833 } 1834 1835 add_debug_info_for_null_check_here(op->info_for_exception()); 1836 __ load_klass(k_RInfo, array); 1837 __ load_klass(klass_RInfo, value); 1838 1839 // get instance klass (it's already uncompressed) 1840 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1841 // perform the fast part of the checking logic 1842 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1843 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1844 __ push(klass_RInfo); 1845 __ push(k_RInfo); 1846 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1847 __ pop(klass_RInfo); 1848 __ pop(k_RInfo); 1849 // result is a boolean 1850 __ cmpl(k_RInfo, 0); 1851 __ jcc(Assembler::equal, *failure_target); 1852 // fall through to the success case 1853 1854 if (op->should_profile()) { 1855 Register mdo = klass_RInfo, recv = k_RInfo; 1856 __ bind(profile_cast_success); 1857 __ mov_metadata(mdo, md->constant_encoding()); 1858 __ load_klass(recv, value); 1859 Label update_done; 1860 type_profile_helper(mdo, md, data, recv, &done); 1861 __ jmpb(done); 1862 1863 __ bind(profile_cast_failure); 1864 __ mov_metadata(mdo, md->constant_encoding()); 1865 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1866 __ subptr(counter_addr, DataLayout::counter_increment); 1867 __ jmp(*stub->entry()); 1868 } 1869 1870 __ bind(done); 1871 } else 1872 if (code == lir_checkcast) { 1873 Register obj = op->object()->as_register(); 1874 Register dst = op->result_opr()->as_register(); 1875 Label success; 1876 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1877 __ bind(success); 1878 if (dst != obj) { 1879 __ mov(dst, obj); 1880 } 1881 } else 1882 if (code == lir_instanceof) { 1883 Register obj = op->object()->as_register(); 1884 Register dst = op->result_opr()->as_register(); 1885 Label success, failure, done; 1886 emit_typecheck_helper(op, &success, &failure, &failure); 1887 __ bind(failure); 1888 __ xorptr(dst, dst); 1889 __ jmpb(done); 1890 __ bind(success); 1891 __ movptr(dst, 1); 1892 __ bind(done); 1893 } else { 1894 ShouldNotReachHere(); 1895 } 1896 1897 } 1898 1899 1900 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1901 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1902 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1903 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1904 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1905 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1906 Register addr = op->addr()->as_register(); 1907 if (os::is_MP()) { 1908 __ lock(); 1909 } 1910 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1911 1912 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1913 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1914 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1915 Register newval = op->new_value()->as_register(); 1916 Register cmpval = op->cmp_value()->as_register(); 1917 assert(cmpval == rax, "wrong register"); 1918 assert(newval != NULL, "new val must be register"); 1919 assert(cmpval != newval, "cmp and new values must be in different registers"); 1920 assert(cmpval != addr, "cmp and addr must be in different registers"); 1921 assert(newval != addr, "new value and addr must be in different registers"); 1922 1923 if ( op->code() == lir_cas_obj) { 1924 #ifdef _LP64 1925 if (UseCompressedOops) { 1926 __ encode_heap_oop(cmpval); 1927 __ mov(rscratch1, newval); 1928 __ encode_heap_oop(rscratch1); 1929 if (os::is_MP()) { 1930 __ lock(); 1931 } 1932 // cmpval (rax) is implicitly used by this instruction 1933 __ cmpxchgl(rscratch1, Address(addr, 0)); 1934 } else 1935 #endif 1936 { 1937 if (os::is_MP()) { 1938 __ lock(); 1939 } 1940 __ cmpxchgptr(newval, Address(addr, 0)); 1941 } 1942 } else { 1943 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1944 if (os::is_MP()) { 1945 __ lock(); 1946 } 1947 __ cmpxchgl(newval, Address(addr, 0)); 1948 } 1949 #ifdef _LP64 1950 } else if (op->code() == lir_cas_long) { 1951 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1952 Register newval = op->new_value()->as_register_lo(); 1953 Register cmpval = op->cmp_value()->as_register_lo(); 1954 assert(cmpval == rax, "wrong register"); 1955 assert(newval != NULL, "new val must be register"); 1956 assert(cmpval != newval, "cmp and new values must be in different registers"); 1957 assert(cmpval != addr, "cmp and addr must be in different registers"); 1958 assert(newval != addr, "new value and addr must be in different registers"); 1959 if (os::is_MP()) { 1960 __ lock(); 1961 } 1962 __ cmpxchgq(newval, Address(addr, 0)); 1963 #endif // _LP64 1964 } else { 1965 Unimplemented(); 1966 } 1967 } 1968 1969 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1970 Assembler::Condition acond, ncond; 1971 switch (condition) { 1972 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1973 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1974 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1975 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1976 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1977 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1978 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1979 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1980 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1981 ShouldNotReachHere(); 1982 } 1983 1984 if (opr1->is_cpu_register()) { 1985 reg2reg(opr1, result); 1986 } else if (opr1->is_stack()) { 1987 stack2reg(opr1, result, result->type()); 1988 } else if (opr1->is_constant()) { 1989 const2reg(opr1, result, lir_patch_none, NULL); 1990 } else { 1991 ShouldNotReachHere(); 1992 } 1993 1994 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1995 // optimized version that does not require a branch 1996 if (opr2->is_single_cpu()) { 1997 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1998 __ cmov(ncond, result->as_register(), opr2->as_register()); 1999 } else if (opr2->is_double_cpu()) { 2000 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2001 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2002 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2003 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2004 } else if (opr2->is_single_stack()) { 2005 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2006 } else if (opr2->is_double_stack()) { 2007 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2008 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2009 } else { 2010 ShouldNotReachHere(); 2011 } 2012 2013 } else { 2014 Label skip; 2015 __ jcc (acond, skip); 2016 if (opr2->is_cpu_register()) { 2017 reg2reg(opr2, result); 2018 } else if (opr2->is_stack()) { 2019 stack2reg(opr2, result, result->type()); 2020 } else if (opr2->is_constant()) { 2021 const2reg(opr2, result, lir_patch_none, NULL); 2022 } else { 2023 ShouldNotReachHere(); 2024 } 2025 __ bind(skip); 2026 } 2027 } 2028 2029 2030 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2031 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2032 2033 if (left->is_single_cpu()) { 2034 assert(left == dest, "left and dest must be equal"); 2035 Register lreg = left->as_register(); 2036 2037 if (right->is_single_cpu()) { 2038 // cpu register - cpu register 2039 Register rreg = right->as_register(); 2040 switch (code) { 2041 case lir_add: __ addl (lreg, rreg); break; 2042 case lir_sub: __ subl (lreg, rreg); break; 2043 case lir_mul: __ imull(lreg, rreg); break; 2044 default: ShouldNotReachHere(); 2045 } 2046 2047 } else if (right->is_stack()) { 2048 // cpu register - stack 2049 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2050 switch (code) { 2051 case lir_add: __ addl(lreg, raddr); break; 2052 case lir_sub: __ subl(lreg, raddr); break; 2053 default: ShouldNotReachHere(); 2054 } 2055 2056 } else if (right->is_constant()) { 2057 // cpu register - constant 2058 jint c = right->as_constant_ptr()->as_jint(); 2059 switch (code) { 2060 case lir_add: { 2061 __ incrementl(lreg, c); 2062 break; 2063 } 2064 case lir_sub: { 2065 __ decrementl(lreg, c); 2066 break; 2067 } 2068 default: ShouldNotReachHere(); 2069 } 2070 2071 } else { 2072 ShouldNotReachHere(); 2073 } 2074 2075 } else if (left->is_double_cpu()) { 2076 assert(left == dest, "left and dest must be equal"); 2077 Register lreg_lo = left->as_register_lo(); 2078 Register lreg_hi = left->as_register_hi(); 2079 2080 if (right->is_double_cpu()) { 2081 // cpu register - cpu register 2082 Register rreg_lo = right->as_register_lo(); 2083 Register rreg_hi = right->as_register_hi(); 2084 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2085 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2086 switch (code) { 2087 case lir_add: 2088 __ addptr(lreg_lo, rreg_lo); 2089 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2090 break; 2091 case lir_sub: 2092 __ subptr(lreg_lo, rreg_lo); 2093 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2094 break; 2095 case lir_mul: 2096 #ifdef _LP64 2097 __ imulq(lreg_lo, rreg_lo); 2098 #else 2099 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2100 __ imull(lreg_hi, rreg_lo); 2101 __ imull(rreg_hi, lreg_lo); 2102 __ addl (rreg_hi, lreg_hi); 2103 __ mull (rreg_lo); 2104 __ addl (lreg_hi, rreg_hi); 2105 #endif // _LP64 2106 break; 2107 default: 2108 ShouldNotReachHere(); 2109 } 2110 2111 } else if (right->is_constant()) { 2112 // cpu register - constant 2113 #ifdef _LP64 2114 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2115 __ movptr(r10, (intptr_t) c); 2116 switch (code) { 2117 case lir_add: 2118 __ addptr(lreg_lo, r10); 2119 break; 2120 case lir_sub: 2121 __ subptr(lreg_lo, r10); 2122 break; 2123 default: 2124 ShouldNotReachHere(); 2125 } 2126 #else 2127 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2128 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2129 switch (code) { 2130 case lir_add: 2131 __ addptr(lreg_lo, c_lo); 2132 __ adcl(lreg_hi, c_hi); 2133 break; 2134 case lir_sub: 2135 __ subptr(lreg_lo, c_lo); 2136 __ sbbl(lreg_hi, c_hi); 2137 break; 2138 default: 2139 ShouldNotReachHere(); 2140 } 2141 #endif // _LP64 2142 2143 } else { 2144 ShouldNotReachHere(); 2145 } 2146 2147 } else if (left->is_single_xmm()) { 2148 assert(left == dest, "left and dest must be equal"); 2149 XMMRegister lreg = left->as_xmm_float_reg(); 2150 2151 if (right->is_single_xmm()) { 2152 XMMRegister rreg = right->as_xmm_float_reg(); 2153 switch (code) { 2154 case lir_add: __ addss(lreg, rreg); break; 2155 case lir_sub: __ subss(lreg, rreg); break; 2156 case lir_mul_strictfp: // fall through 2157 case lir_mul: __ mulss(lreg, rreg); break; 2158 case lir_div_strictfp: // fall through 2159 case lir_div: __ divss(lreg, rreg); break; 2160 default: ShouldNotReachHere(); 2161 } 2162 } else { 2163 Address raddr; 2164 if (right->is_single_stack()) { 2165 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2166 } else if (right->is_constant()) { 2167 // hack for now 2168 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2169 } else { 2170 ShouldNotReachHere(); 2171 } 2172 switch (code) { 2173 case lir_add: __ addss(lreg, raddr); break; 2174 case lir_sub: __ subss(lreg, raddr); break; 2175 case lir_mul_strictfp: // fall through 2176 case lir_mul: __ mulss(lreg, raddr); break; 2177 case lir_div_strictfp: // fall through 2178 case lir_div: __ divss(lreg, raddr); break; 2179 default: ShouldNotReachHere(); 2180 } 2181 } 2182 2183 } else if (left->is_double_xmm()) { 2184 assert(left == dest, "left and dest must be equal"); 2185 2186 XMMRegister lreg = left->as_xmm_double_reg(); 2187 if (right->is_double_xmm()) { 2188 XMMRegister rreg = right->as_xmm_double_reg(); 2189 switch (code) { 2190 case lir_add: __ addsd(lreg, rreg); break; 2191 case lir_sub: __ subsd(lreg, rreg); break; 2192 case lir_mul_strictfp: // fall through 2193 case lir_mul: __ mulsd(lreg, rreg); break; 2194 case lir_div_strictfp: // fall through 2195 case lir_div: __ divsd(lreg, rreg); break; 2196 default: ShouldNotReachHere(); 2197 } 2198 } else { 2199 Address raddr; 2200 if (right->is_double_stack()) { 2201 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2202 } else if (right->is_constant()) { 2203 // hack for now 2204 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2205 } else { 2206 ShouldNotReachHere(); 2207 } 2208 switch (code) { 2209 case lir_add: __ addsd(lreg, raddr); break; 2210 case lir_sub: __ subsd(lreg, raddr); break; 2211 case lir_mul_strictfp: // fall through 2212 case lir_mul: __ mulsd(lreg, raddr); break; 2213 case lir_div_strictfp: // fall through 2214 case lir_div: __ divsd(lreg, raddr); break; 2215 default: ShouldNotReachHere(); 2216 } 2217 } 2218 2219 } else if (left->is_single_fpu()) { 2220 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2221 2222 if (right->is_single_fpu()) { 2223 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2224 2225 } else { 2226 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2227 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2228 2229 Address raddr; 2230 if (right->is_single_stack()) { 2231 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2232 } else if (right->is_constant()) { 2233 address const_addr = float_constant(right->as_jfloat()); 2234 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2235 // hack for now 2236 raddr = __ as_Address(InternalAddress(const_addr)); 2237 } else { 2238 ShouldNotReachHere(); 2239 } 2240 2241 switch (code) { 2242 case lir_add: __ fadd_s(raddr); break; 2243 case lir_sub: __ fsub_s(raddr); break; 2244 case lir_mul_strictfp: // fall through 2245 case lir_mul: __ fmul_s(raddr); break; 2246 case lir_div_strictfp: // fall through 2247 case lir_div: __ fdiv_s(raddr); break; 2248 default: ShouldNotReachHere(); 2249 } 2250 } 2251 2252 } else if (left->is_double_fpu()) { 2253 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2254 2255 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2256 // Double values require special handling for strictfp mul/div on x86 2257 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2258 __ fmulp(left->fpu_regnrLo() + 1); 2259 } 2260 2261 if (right->is_double_fpu()) { 2262 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2263 2264 } else { 2265 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2266 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2267 2268 Address raddr; 2269 if (right->is_double_stack()) { 2270 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2271 } else if (right->is_constant()) { 2272 // hack for now 2273 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2274 } else { 2275 ShouldNotReachHere(); 2276 } 2277 2278 switch (code) { 2279 case lir_add: __ fadd_d(raddr); break; 2280 case lir_sub: __ fsub_d(raddr); break; 2281 case lir_mul_strictfp: // fall through 2282 case lir_mul: __ fmul_d(raddr); break; 2283 case lir_div_strictfp: // fall through 2284 case lir_div: __ fdiv_d(raddr); break; 2285 default: ShouldNotReachHere(); 2286 } 2287 } 2288 2289 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2290 // Double values require special handling for strictfp mul/div on x86 2291 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2292 __ fmulp(dest->fpu_regnrLo() + 1); 2293 } 2294 2295 } else if (left->is_single_stack() || left->is_address()) { 2296 assert(left == dest, "left and dest must be equal"); 2297 2298 Address laddr; 2299 if (left->is_single_stack()) { 2300 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2301 } else if (left->is_address()) { 2302 laddr = as_Address(left->as_address_ptr()); 2303 } else { 2304 ShouldNotReachHere(); 2305 } 2306 2307 if (right->is_single_cpu()) { 2308 Register rreg = right->as_register(); 2309 switch (code) { 2310 case lir_add: __ addl(laddr, rreg); break; 2311 case lir_sub: __ subl(laddr, rreg); break; 2312 default: ShouldNotReachHere(); 2313 } 2314 } else if (right->is_constant()) { 2315 jint c = right->as_constant_ptr()->as_jint(); 2316 switch (code) { 2317 case lir_add: { 2318 __ incrementl(laddr, c); 2319 break; 2320 } 2321 case lir_sub: { 2322 __ decrementl(laddr, c); 2323 break; 2324 } 2325 default: ShouldNotReachHere(); 2326 } 2327 } else { 2328 ShouldNotReachHere(); 2329 } 2330 2331 } else { 2332 ShouldNotReachHere(); 2333 } 2334 } 2335 2336 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2337 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2338 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2339 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2340 2341 bool left_is_tos = (left_index == 0); 2342 bool dest_is_tos = (dest_index == 0); 2343 int non_tos_index = (left_is_tos ? right_index : left_index); 2344 2345 switch (code) { 2346 case lir_add: 2347 if (pop_fpu_stack) __ faddp(non_tos_index); 2348 else if (dest_is_tos) __ fadd (non_tos_index); 2349 else __ fadda(non_tos_index); 2350 break; 2351 2352 case lir_sub: 2353 if (left_is_tos) { 2354 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2355 else if (dest_is_tos) __ fsub (non_tos_index); 2356 else __ fsubra(non_tos_index); 2357 } else { 2358 if (pop_fpu_stack) __ fsubp (non_tos_index); 2359 else if (dest_is_tos) __ fsubr (non_tos_index); 2360 else __ fsuba (non_tos_index); 2361 } 2362 break; 2363 2364 case lir_mul_strictfp: // fall through 2365 case lir_mul: 2366 if (pop_fpu_stack) __ fmulp(non_tos_index); 2367 else if (dest_is_tos) __ fmul (non_tos_index); 2368 else __ fmula(non_tos_index); 2369 break; 2370 2371 case lir_div_strictfp: // fall through 2372 case lir_div: 2373 if (left_is_tos) { 2374 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2375 else if (dest_is_tos) __ fdiv (non_tos_index); 2376 else __ fdivra(non_tos_index); 2377 } else { 2378 if (pop_fpu_stack) __ fdivp (non_tos_index); 2379 else if (dest_is_tos) __ fdivr (non_tos_index); 2380 else __ fdiva (non_tos_index); 2381 } 2382 break; 2383 2384 case lir_rem: 2385 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2386 __ fremr(noreg); 2387 break; 2388 2389 default: 2390 ShouldNotReachHere(); 2391 } 2392 } 2393 2394 2395 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2396 if (value->is_double_xmm()) { 2397 switch(code) { 2398 case lir_abs : 2399 { 2400 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2401 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2402 } 2403 __ andpd(dest->as_xmm_double_reg(), 2404 ExternalAddress((address)double_signmask_pool)); 2405 } 2406 break; 2407 2408 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2409 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2410 default : ShouldNotReachHere(); 2411 } 2412 2413 } else if (value->is_double_fpu()) { 2414 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2415 switch(code) { 2416 case lir_abs : __ fabs() ; break; 2417 case lir_sqrt : __ fsqrt(); break; 2418 default : ShouldNotReachHere(); 2419 } 2420 } else { 2421 Unimplemented(); 2422 } 2423 } 2424 2425 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2426 // assert(left->destroys_register(), "check"); 2427 if (left->is_single_cpu()) { 2428 Register reg = left->as_register(); 2429 if (right->is_constant()) { 2430 int val = right->as_constant_ptr()->as_jint(); 2431 switch (code) { 2432 case lir_logic_and: __ andl (reg, val); break; 2433 case lir_logic_or: __ orl (reg, val); break; 2434 case lir_logic_xor: __ xorl (reg, val); break; 2435 default: ShouldNotReachHere(); 2436 } 2437 } else if (right->is_stack()) { 2438 // added support for stack operands 2439 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2440 switch (code) { 2441 case lir_logic_and: __ andl (reg, raddr); break; 2442 case lir_logic_or: __ orl (reg, raddr); break; 2443 case lir_logic_xor: __ xorl (reg, raddr); break; 2444 default: ShouldNotReachHere(); 2445 } 2446 } else { 2447 Register rright = right->as_register(); 2448 switch (code) { 2449 case lir_logic_and: __ andptr (reg, rright); break; 2450 case lir_logic_or : __ orptr (reg, rright); break; 2451 case lir_logic_xor: __ xorptr (reg, rright); break; 2452 default: ShouldNotReachHere(); 2453 } 2454 } 2455 move_regs(reg, dst->as_register()); 2456 } else { 2457 Register l_lo = left->as_register_lo(); 2458 Register l_hi = left->as_register_hi(); 2459 if (right->is_constant()) { 2460 #ifdef _LP64 2461 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2462 switch (code) { 2463 case lir_logic_and: 2464 __ andq(l_lo, rscratch1); 2465 break; 2466 case lir_logic_or: 2467 __ orq(l_lo, rscratch1); 2468 break; 2469 case lir_logic_xor: 2470 __ xorq(l_lo, rscratch1); 2471 break; 2472 default: ShouldNotReachHere(); 2473 } 2474 #else 2475 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2476 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2477 switch (code) { 2478 case lir_logic_and: 2479 __ andl(l_lo, r_lo); 2480 __ andl(l_hi, r_hi); 2481 break; 2482 case lir_logic_or: 2483 __ orl(l_lo, r_lo); 2484 __ orl(l_hi, r_hi); 2485 break; 2486 case lir_logic_xor: 2487 __ xorl(l_lo, r_lo); 2488 __ xorl(l_hi, r_hi); 2489 break; 2490 default: ShouldNotReachHere(); 2491 } 2492 #endif // _LP64 2493 } else { 2494 #ifdef _LP64 2495 Register r_lo; 2496 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2497 r_lo = right->as_register(); 2498 } else { 2499 r_lo = right->as_register_lo(); 2500 } 2501 #else 2502 Register r_lo = right->as_register_lo(); 2503 Register r_hi = right->as_register_hi(); 2504 assert(l_lo != r_hi, "overwriting registers"); 2505 #endif 2506 switch (code) { 2507 case lir_logic_and: 2508 __ andptr(l_lo, r_lo); 2509 NOT_LP64(__ andptr(l_hi, r_hi);) 2510 break; 2511 case lir_logic_or: 2512 __ orptr(l_lo, r_lo); 2513 NOT_LP64(__ orptr(l_hi, r_hi);) 2514 break; 2515 case lir_logic_xor: 2516 __ xorptr(l_lo, r_lo); 2517 NOT_LP64(__ xorptr(l_hi, r_hi);) 2518 break; 2519 default: ShouldNotReachHere(); 2520 } 2521 } 2522 2523 Register dst_lo = dst->as_register_lo(); 2524 Register dst_hi = dst->as_register_hi(); 2525 2526 #ifdef _LP64 2527 move_regs(l_lo, dst_lo); 2528 #else 2529 if (dst_lo == l_hi) { 2530 assert(dst_hi != l_lo, "overwriting registers"); 2531 move_regs(l_hi, dst_hi); 2532 move_regs(l_lo, dst_lo); 2533 } else { 2534 assert(dst_lo != l_hi, "overwriting registers"); 2535 move_regs(l_lo, dst_lo); 2536 move_regs(l_hi, dst_hi); 2537 } 2538 #endif // _LP64 2539 } 2540 } 2541 2542 2543 // we assume that rax, and rdx can be overwritten 2544 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2545 2546 assert(left->is_single_cpu(), "left must be register"); 2547 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2548 assert(result->is_single_cpu(), "result must be register"); 2549 2550 // assert(left->destroys_register(), "check"); 2551 // assert(right->destroys_register(), "check"); 2552 2553 Register lreg = left->as_register(); 2554 Register dreg = result->as_register(); 2555 2556 if (right->is_constant()) { 2557 int divisor = right->as_constant_ptr()->as_jint(); 2558 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2559 if (code == lir_idiv) { 2560 assert(lreg == rax, "must be rax,"); 2561 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2562 __ cdql(); // sign extend into rdx:rax 2563 if (divisor == 2) { 2564 __ subl(lreg, rdx); 2565 } else { 2566 __ andl(rdx, divisor - 1); 2567 __ addl(lreg, rdx); 2568 } 2569 __ sarl(lreg, log2_intptr(divisor)); 2570 move_regs(lreg, dreg); 2571 } else if (code == lir_irem) { 2572 Label done; 2573 __ mov(dreg, lreg); 2574 __ andl(dreg, 0x80000000 | (divisor - 1)); 2575 __ jcc(Assembler::positive, done); 2576 __ decrement(dreg); 2577 __ orl(dreg, ~(divisor - 1)); 2578 __ increment(dreg); 2579 __ bind(done); 2580 } else { 2581 ShouldNotReachHere(); 2582 } 2583 } else { 2584 Register rreg = right->as_register(); 2585 assert(lreg == rax, "left register must be rax,"); 2586 assert(rreg != rdx, "right register must not be rdx"); 2587 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2588 2589 move_regs(lreg, rax); 2590 2591 int idivl_offset = __ corrected_idivl(rreg); 2592 if (ImplicitDiv0Checks) { 2593 add_debug_info_for_div0(idivl_offset, info); 2594 } 2595 if (code == lir_irem) { 2596 move_regs(rdx, dreg); // result is in rdx 2597 } else { 2598 move_regs(rax, dreg); 2599 } 2600 } 2601 } 2602 2603 2604 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2605 if (opr1->is_single_cpu()) { 2606 Register reg1 = opr1->as_register(); 2607 if (opr2->is_single_cpu()) { 2608 // cpu register - cpu register 2609 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2610 __ cmpoop(reg1, opr2->as_register()); 2611 } else { 2612 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2613 __ cmpl(reg1, opr2->as_register()); 2614 } 2615 } else if (opr2->is_stack()) { 2616 // cpu register - stack 2617 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2618 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2619 } else { 2620 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2621 } 2622 } else if (opr2->is_constant()) { 2623 // cpu register - constant 2624 LIR_Const* c = opr2->as_constant_ptr(); 2625 if (c->type() == T_INT) { 2626 __ cmpl(reg1, c->as_jint()); 2627 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2628 // In 64bit oops are single register 2629 jobject o = c->as_jobject(); 2630 if (o == NULL) { 2631 __ cmpptr(reg1, (int32_t)NULL_WORD); 2632 } else { 2633 __ cmpoop(reg1, o); 2634 } 2635 } else { 2636 fatal("unexpected type: %s", basictype_to_str(c->type())); 2637 } 2638 // cpu register - address 2639 } else if (opr2->is_address()) { 2640 if (op->info() != NULL) { 2641 add_debug_info_for_null_check_here(op->info()); 2642 } 2643 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2644 } else { 2645 ShouldNotReachHere(); 2646 } 2647 2648 } else if(opr1->is_double_cpu()) { 2649 Register xlo = opr1->as_register_lo(); 2650 Register xhi = opr1->as_register_hi(); 2651 if (opr2->is_double_cpu()) { 2652 #ifdef _LP64 2653 __ cmpptr(xlo, opr2->as_register_lo()); 2654 #else 2655 // cpu register - cpu register 2656 Register ylo = opr2->as_register_lo(); 2657 Register yhi = opr2->as_register_hi(); 2658 __ subl(xlo, ylo); 2659 __ sbbl(xhi, yhi); 2660 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2661 __ orl(xhi, xlo); 2662 } 2663 #endif // _LP64 2664 } else if (opr2->is_constant()) { 2665 // cpu register - constant 0 2666 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2667 #ifdef _LP64 2668 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2669 #else 2670 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2671 __ orl(xhi, xlo); 2672 #endif // _LP64 2673 } else { 2674 ShouldNotReachHere(); 2675 } 2676 2677 } else if (opr1->is_single_xmm()) { 2678 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2679 if (opr2->is_single_xmm()) { 2680 // xmm register - xmm register 2681 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2682 } else if (opr2->is_stack()) { 2683 // xmm register - stack 2684 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2685 } else if (opr2->is_constant()) { 2686 // xmm register - constant 2687 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2688 } else if (opr2->is_address()) { 2689 // xmm register - address 2690 if (op->info() != NULL) { 2691 add_debug_info_for_null_check_here(op->info()); 2692 } 2693 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2694 } else { 2695 ShouldNotReachHere(); 2696 } 2697 2698 } else if (opr1->is_double_xmm()) { 2699 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2700 if (opr2->is_double_xmm()) { 2701 // xmm register - xmm register 2702 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2703 } else if (opr2->is_stack()) { 2704 // xmm register - stack 2705 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2706 } else if (opr2->is_constant()) { 2707 // xmm register - constant 2708 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2709 } else if (opr2->is_address()) { 2710 // xmm register - address 2711 if (op->info() != NULL) { 2712 add_debug_info_for_null_check_here(op->info()); 2713 } 2714 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2715 } else { 2716 ShouldNotReachHere(); 2717 } 2718 2719 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2720 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2721 assert(opr2->is_fpu_register(), "both must be registers"); 2722 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2723 2724 } else if (opr1->is_address() && opr2->is_constant()) { 2725 LIR_Const* c = opr2->as_constant_ptr(); 2726 #ifdef _LP64 2727 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2728 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2729 __ movoop(rscratch1, c->as_jobject()); 2730 } 2731 #endif // LP64 2732 if (op->info() != NULL) { 2733 add_debug_info_for_null_check_here(op->info()); 2734 } 2735 // special case: address - constant 2736 LIR_Address* addr = opr1->as_address_ptr(); 2737 if (c->type() == T_INT) { 2738 __ cmpl(as_Address(addr), c->as_jint()); 2739 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2740 #ifdef _LP64 2741 // %%% Make this explode if addr isn't reachable until we figure out a 2742 // better strategy by giving noreg as the temp for as_Address 2743 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2744 #else 2745 __ cmpoop(as_Address(addr), c->as_jobject()); 2746 #endif // _LP64 2747 } else { 2748 ShouldNotReachHere(); 2749 } 2750 2751 } else { 2752 ShouldNotReachHere(); 2753 } 2754 } 2755 2756 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2757 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2758 if (left->is_single_xmm()) { 2759 assert(right->is_single_xmm(), "must match"); 2760 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2761 } else if (left->is_double_xmm()) { 2762 assert(right->is_double_xmm(), "must match"); 2763 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2764 2765 } else { 2766 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2767 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2768 2769 assert(left->fpu() == 0, "left must be on TOS"); 2770 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2771 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2772 } 2773 } else { 2774 assert(code == lir_cmp_l2i, "check"); 2775 #ifdef _LP64 2776 Label done; 2777 Register dest = dst->as_register(); 2778 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2779 __ movl(dest, -1); 2780 __ jccb(Assembler::less, done); 2781 __ set_byte_if_not_zero(dest); 2782 __ movzbl(dest, dest); 2783 __ bind(done); 2784 #else 2785 __ lcmp2int(left->as_register_hi(), 2786 left->as_register_lo(), 2787 right->as_register_hi(), 2788 right->as_register_lo()); 2789 move_regs(left->as_register_hi(), dst->as_register()); 2790 #endif // _LP64 2791 } 2792 } 2793 2794 2795 void LIR_Assembler::align_call(LIR_Code code) { 2796 if (os::is_MP()) { 2797 // make sure that the displacement word of the call ends up word aligned 2798 int offset = __ offset(); 2799 switch (code) { 2800 case lir_static_call: 2801 case lir_optvirtual_call: 2802 case lir_dynamic_call: 2803 offset += NativeCall::displacement_offset; 2804 break; 2805 case lir_icvirtual_call: 2806 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2807 break; 2808 case lir_virtual_call: // currently, sparc-specific for niagara 2809 default: ShouldNotReachHere(); 2810 } 2811 __ align(BytesPerWord, offset); 2812 } 2813 } 2814 2815 2816 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2817 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2818 "must be aligned"); 2819 __ call(AddressLiteral(op->addr(), rtype)); 2820 add_call_info(code_offset(), op->info()); 2821 } 2822 2823 2824 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2825 __ ic_call(op->addr()); 2826 add_call_info(code_offset(), op->info()); 2827 assert(!os::is_MP() || 2828 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2829 "must be aligned"); 2830 } 2831 2832 2833 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2834 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2835 ShouldNotReachHere(); 2836 } 2837 2838 2839 void LIR_Assembler::emit_static_call_stub() { 2840 address call_pc = __ pc(); 2841 address stub = __ start_a_stub(call_stub_size()); 2842 if (stub == NULL) { 2843 bailout("static call stub overflow"); 2844 return; 2845 } 2846 2847 int start = __ offset(); 2848 if (os::is_MP()) { 2849 // make sure that the displacement word of the call ends up word aligned 2850 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2851 } 2852 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2853 __ mov_metadata(rbx, (Metadata*)NULL); 2854 // must be set to -1 at code generation time 2855 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2856 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2857 __ jump(RuntimeAddress(__ pc())); 2858 2859 if (UseAOT) { 2860 // Trampoline to aot code 2861 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2862 #ifdef _LP64 2863 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2864 #else 2865 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2866 #endif 2867 __ jmp(rax); 2868 } 2869 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2870 __ end_a_stub(); 2871 } 2872 2873 2874 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2875 assert(exceptionOop->as_register() == rax, "must match"); 2876 assert(exceptionPC->as_register() == rdx, "must match"); 2877 2878 // exception object is not added to oop map by LinearScan 2879 // (LinearScan assumes that no oops are in fixed registers) 2880 info->add_register_oop(exceptionOop); 2881 Runtime1::StubID unwind_id; 2882 2883 // get current pc information 2884 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2885 int pc_for_athrow_offset = __ offset(); 2886 InternalAddress pc_for_athrow(__ pc()); 2887 __ lea(exceptionPC->as_register(), pc_for_athrow); 2888 add_call_info(pc_for_athrow_offset, info); // for exception handler 2889 2890 __ verify_not_null_oop(rax); 2891 // search an exception handler (rax: exception oop, rdx: throwing pc) 2892 if (compilation()->has_fpu_code()) { 2893 unwind_id = Runtime1::handle_exception_id; 2894 } else { 2895 unwind_id = Runtime1::handle_exception_nofpu_id; 2896 } 2897 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2898 2899 // enough room for two byte trap 2900 __ nop(); 2901 } 2902 2903 2904 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2905 assert(exceptionOop->as_register() == rax, "must match"); 2906 2907 __ jmp(_unwind_handler_entry); 2908 } 2909 2910 2911 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2912 2913 // optimized version for linear scan: 2914 // * count must be already in ECX (guaranteed by LinearScan) 2915 // * left and dest must be equal 2916 // * tmp must be unused 2917 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2918 assert(left == dest, "left and dest must be equal"); 2919 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2920 2921 if (left->is_single_cpu()) { 2922 Register value = left->as_register(); 2923 assert(value != SHIFT_count, "left cannot be ECX"); 2924 2925 switch (code) { 2926 case lir_shl: __ shll(value); break; 2927 case lir_shr: __ sarl(value); break; 2928 case lir_ushr: __ shrl(value); break; 2929 default: ShouldNotReachHere(); 2930 } 2931 } else if (left->is_double_cpu()) { 2932 Register lo = left->as_register_lo(); 2933 Register hi = left->as_register_hi(); 2934 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2935 #ifdef _LP64 2936 switch (code) { 2937 case lir_shl: __ shlptr(lo); break; 2938 case lir_shr: __ sarptr(lo); break; 2939 case lir_ushr: __ shrptr(lo); break; 2940 default: ShouldNotReachHere(); 2941 } 2942 #else 2943 2944 switch (code) { 2945 case lir_shl: __ lshl(hi, lo); break; 2946 case lir_shr: __ lshr(hi, lo, true); break; 2947 case lir_ushr: __ lshr(hi, lo, false); break; 2948 default: ShouldNotReachHere(); 2949 } 2950 #endif // LP64 2951 } else { 2952 ShouldNotReachHere(); 2953 } 2954 } 2955 2956 2957 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2958 if (dest->is_single_cpu()) { 2959 // first move left into dest so that left is not destroyed by the shift 2960 Register value = dest->as_register(); 2961 count = count & 0x1F; // Java spec 2962 2963 move_regs(left->as_register(), value); 2964 switch (code) { 2965 case lir_shl: __ shll(value, count); break; 2966 case lir_shr: __ sarl(value, count); break; 2967 case lir_ushr: __ shrl(value, count); break; 2968 default: ShouldNotReachHere(); 2969 } 2970 } else if (dest->is_double_cpu()) { 2971 #ifndef _LP64 2972 Unimplemented(); 2973 #else 2974 // first move left into dest so that left is not destroyed by the shift 2975 Register value = dest->as_register_lo(); 2976 count = count & 0x1F; // Java spec 2977 2978 move_regs(left->as_register_lo(), value); 2979 switch (code) { 2980 case lir_shl: __ shlptr(value, count); break; 2981 case lir_shr: __ sarptr(value, count); break; 2982 case lir_ushr: __ shrptr(value, count); break; 2983 default: ShouldNotReachHere(); 2984 } 2985 #endif // _LP64 2986 } else { 2987 ShouldNotReachHere(); 2988 } 2989 } 2990 2991 2992 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2993 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2994 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2995 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2996 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2997 } 2998 2999 3000 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3001 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3002 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3003 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3004 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3005 } 3006 3007 3008 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3009 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3010 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3011 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3012 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3013 } 3014 3015 3016 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3017 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3018 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3019 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3020 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3021 } 3022 3023 3024 // This code replaces a call to arraycopy; no exception may 3025 // be thrown in this code, they must be thrown in the System.arraycopy 3026 // activation frame; we could save some checks if this would not be the case 3027 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3028 ciArrayKlass* default_type = op->expected_type(); 3029 Register src = op->src()->as_register(); 3030 Register dst = op->dst()->as_register(); 3031 Register src_pos = op->src_pos()->as_register(); 3032 Register dst_pos = op->dst_pos()->as_register(); 3033 Register length = op->length()->as_register(); 3034 Register tmp = op->tmp()->as_register(); 3035 3036 CodeStub* stub = op->stub(); 3037 int flags = op->flags(); 3038 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3039 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3040 3041 // if we don't know anything, just go through the generic arraycopy 3042 if (default_type == NULL) { 3043 Label done; 3044 // save outgoing arguments on stack in case call to System.arraycopy is needed 3045 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3046 // for interpreter calling conventions. Now we have to do it in new style conventions. 3047 // For the moment until C1 gets the new register allocator I just force all the 3048 // args to the right place (except the register args) and then on the back side 3049 // reload the register args properly if we go slow path. Yuck 3050 3051 // These are proper for the calling convention 3052 store_parameter(length, 2); 3053 store_parameter(dst_pos, 1); 3054 store_parameter(dst, 0); 3055 3056 // these are just temporary placements until we need to reload 3057 store_parameter(src_pos, 3); 3058 store_parameter(src, 4); 3059 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3060 3061 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3062 3063 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3064 3065 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3066 #ifdef _LP64 3067 // The arguments are in java calling convention so we can trivially shift them to C 3068 // convention 3069 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3070 __ mov(c_rarg0, j_rarg0); 3071 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3072 __ mov(c_rarg1, j_rarg1); 3073 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3074 __ mov(c_rarg2, j_rarg2); 3075 assert_different_registers(c_rarg3, j_rarg4); 3076 __ mov(c_rarg3, j_rarg3); 3077 #ifdef _WIN64 3078 // Allocate abi space for args but be sure to keep stack aligned 3079 __ subptr(rsp, 6*wordSize); 3080 store_parameter(j_rarg4, 4); 3081 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3082 __ call(RuntimeAddress(C_entry)); 3083 } else { 3084 #ifndef PRODUCT 3085 if (PrintC1Statistics) { 3086 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3087 } 3088 #endif 3089 __ call(RuntimeAddress(copyfunc_addr)); 3090 } 3091 __ addptr(rsp, 6*wordSize); 3092 #else 3093 __ mov(c_rarg4, j_rarg4); 3094 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3095 __ call(RuntimeAddress(C_entry)); 3096 } else { 3097 #ifndef PRODUCT 3098 if (PrintC1Statistics) { 3099 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3100 } 3101 #endif 3102 __ call(RuntimeAddress(copyfunc_addr)); 3103 } 3104 #endif // _WIN64 3105 #else 3106 __ push(length); 3107 __ push(dst_pos); 3108 __ push(dst); 3109 __ push(src_pos); 3110 __ push(src); 3111 3112 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3113 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3114 } else { 3115 #ifndef PRODUCT 3116 if (PrintC1Statistics) { 3117 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3118 } 3119 #endif 3120 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3121 } 3122 3123 #endif // _LP64 3124 3125 __ cmpl(rax, 0); 3126 __ jcc(Assembler::equal, *stub->continuation()); 3127 3128 if (copyfunc_addr != NULL) { 3129 __ mov(tmp, rax); 3130 __ xorl(tmp, -1); 3131 } 3132 3133 // Reload values from the stack so they are where the stub 3134 // expects them. 3135 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3136 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3137 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3138 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3139 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3140 3141 if (copyfunc_addr != NULL) { 3142 __ subl(length, tmp); 3143 __ addl(src_pos, tmp); 3144 __ addl(dst_pos, tmp); 3145 } 3146 __ jmp(*stub->entry()); 3147 3148 __ bind(*stub->continuation()); 3149 return; 3150 } 3151 3152 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3153 3154 int elem_size = type2aelembytes(basic_type); 3155 Address::ScaleFactor scale; 3156 3157 switch (elem_size) { 3158 case 1 : 3159 scale = Address::times_1; 3160 break; 3161 case 2 : 3162 scale = Address::times_2; 3163 break; 3164 case 4 : 3165 scale = Address::times_4; 3166 break; 3167 case 8 : 3168 scale = Address::times_8; 3169 break; 3170 default: 3171 scale = Address::no_scale; 3172 ShouldNotReachHere(); 3173 } 3174 3175 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3176 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3177 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3178 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3179 3180 // length and pos's are all sign extended at this point on 64bit 3181 3182 // test for NULL 3183 if (flags & LIR_OpArrayCopy::src_null_check) { 3184 __ testptr(src, src); 3185 __ jcc(Assembler::zero, *stub->entry()); 3186 } 3187 if (flags & LIR_OpArrayCopy::dst_null_check) { 3188 __ testptr(dst, dst); 3189 __ jcc(Assembler::zero, *stub->entry()); 3190 } 3191 3192 // If the compiler was not able to prove that exact type of the source or the destination 3193 // of the arraycopy is an array type, check at runtime if the source or the destination is 3194 // an instance type. 3195 if (flags & LIR_OpArrayCopy::type_check) { 3196 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3197 __ load_klass(tmp, dst); 3198 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3199 __ jcc(Assembler::greaterEqual, *stub->entry()); 3200 } 3201 3202 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3203 __ load_klass(tmp, src); 3204 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3205 __ jcc(Assembler::greaterEqual, *stub->entry()); 3206 } 3207 } 3208 3209 // check if negative 3210 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3211 __ testl(src_pos, src_pos); 3212 __ jcc(Assembler::less, *stub->entry()); 3213 } 3214 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3215 __ testl(dst_pos, dst_pos); 3216 __ jcc(Assembler::less, *stub->entry()); 3217 } 3218 3219 if (flags & LIR_OpArrayCopy::src_range_check) { 3220 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3221 __ cmpl(tmp, src_length_addr); 3222 __ jcc(Assembler::above, *stub->entry()); 3223 } 3224 if (flags & LIR_OpArrayCopy::dst_range_check) { 3225 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3226 __ cmpl(tmp, dst_length_addr); 3227 __ jcc(Assembler::above, *stub->entry()); 3228 } 3229 3230 if (flags & LIR_OpArrayCopy::length_positive_check) { 3231 __ testl(length, length); 3232 __ jcc(Assembler::less, *stub->entry()); 3233 } 3234 3235 #ifdef _LP64 3236 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3237 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3238 #endif 3239 3240 if (flags & LIR_OpArrayCopy::type_check) { 3241 // We don't know the array types are compatible 3242 if (basic_type != T_OBJECT) { 3243 // Simple test for basic type arrays 3244 if (UseCompressedClassPointers) { 3245 __ movl(tmp, src_klass_addr); 3246 __ cmpl(tmp, dst_klass_addr); 3247 } else { 3248 __ movptr(tmp, src_klass_addr); 3249 __ cmpptr(tmp, dst_klass_addr); 3250 } 3251 __ jcc(Assembler::notEqual, *stub->entry()); 3252 } else { 3253 // For object arrays, if src is a sub class of dst then we can 3254 // safely do the copy. 3255 Label cont, slow; 3256 3257 __ push(src); 3258 __ push(dst); 3259 3260 __ load_klass(src, src); 3261 __ load_klass(dst, dst); 3262 3263 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3264 3265 __ push(src); 3266 __ push(dst); 3267 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3268 __ pop(dst); 3269 __ pop(src); 3270 3271 __ cmpl(src, 0); 3272 __ jcc(Assembler::notEqual, cont); 3273 3274 __ bind(slow); 3275 __ pop(dst); 3276 __ pop(src); 3277 3278 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3279 if (copyfunc_addr != NULL) { // use stub if available 3280 // src is not a sub class of dst so we have to do a 3281 // per-element check. 3282 3283 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3284 if ((flags & mask) != mask) { 3285 // Check that at least both of them object arrays. 3286 assert(flags & mask, "one of the two should be known to be an object array"); 3287 3288 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3289 __ load_klass(tmp, src); 3290 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3291 __ load_klass(tmp, dst); 3292 } 3293 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3294 Address klass_lh_addr(tmp, lh_offset); 3295 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3296 __ cmpl(klass_lh_addr, objArray_lh); 3297 __ jcc(Assembler::notEqual, *stub->entry()); 3298 } 3299 3300 // Spill because stubs can use any register they like and it's 3301 // easier to restore just those that we care about. 3302 store_parameter(dst, 0); 3303 store_parameter(dst_pos, 1); 3304 store_parameter(length, 2); 3305 store_parameter(src_pos, 3); 3306 store_parameter(src, 4); 3307 3308 #ifndef _LP64 3309 __ movptr(tmp, dst_klass_addr); 3310 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3311 __ push(tmp); 3312 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3313 __ push(tmp); 3314 __ push(length); 3315 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3316 __ push(tmp); 3317 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3318 __ push(tmp); 3319 3320 __ call_VM_leaf(copyfunc_addr, 5); 3321 #else 3322 __ movl2ptr(length, length); //higher 32bits must be null 3323 3324 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3325 assert_different_registers(c_rarg0, dst, dst_pos, length); 3326 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3327 assert_different_registers(c_rarg1, dst, length); 3328 3329 __ mov(c_rarg2, length); 3330 assert_different_registers(c_rarg2, dst); 3331 3332 #ifdef _WIN64 3333 // Allocate abi space for args but be sure to keep stack aligned 3334 __ subptr(rsp, 6*wordSize); 3335 __ load_klass(c_rarg3, dst); 3336 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3337 store_parameter(c_rarg3, 4); 3338 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3339 __ call(RuntimeAddress(copyfunc_addr)); 3340 __ addptr(rsp, 6*wordSize); 3341 #else 3342 __ load_klass(c_rarg4, dst); 3343 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3344 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3345 __ call(RuntimeAddress(copyfunc_addr)); 3346 #endif 3347 3348 #endif 3349 3350 #ifndef PRODUCT 3351 if (PrintC1Statistics) { 3352 Label failed; 3353 __ testl(rax, rax); 3354 __ jcc(Assembler::notZero, failed); 3355 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3356 __ bind(failed); 3357 } 3358 #endif 3359 3360 __ testl(rax, rax); 3361 __ jcc(Assembler::zero, *stub->continuation()); 3362 3363 #ifndef PRODUCT 3364 if (PrintC1Statistics) { 3365 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3366 } 3367 #endif 3368 3369 __ mov(tmp, rax); 3370 3371 __ xorl(tmp, -1); 3372 3373 // Restore previously spilled arguments 3374 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3375 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3376 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3377 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3378 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3379 3380 3381 __ subl(length, tmp); 3382 __ addl(src_pos, tmp); 3383 __ addl(dst_pos, tmp); 3384 } 3385 3386 __ jmp(*stub->entry()); 3387 3388 __ bind(cont); 3389 __ pop(dst); 3390 __ pop(src); 3391 } 3392 } 3393 3394 #ifdef ASSERT 3395 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3396 // Sanity check the known type with the incoming class. For the 3397 // primitive case the types must match exactly with src.klass and 3398 // dst.klass each exactly matching the default type. For the 3399 // object array case, if no type check is needed then either the 3400 // dst type is exactly the expected type and the src type is a 3401 // subtype which we can't check or src is the same array as dst 3402 // but not necessarily exactly of type default_type. 3403 Label known_ok, halt; 3404 __ mov_metadata(tmp, default_type->constant_encoding()); 3405 #ifdef _LP64 3406 if (UseCompressedClassPointers) { 3407 __ encode_klass_not_null(tmp); 3408 } 3409 #endif 3410 3411 if (basic_type != T_OBJECT) { 3412 3413 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3414 else __ cmpptr(tmp, dst_klass_addr); 3415 __ jcc(Assembler::notEqual, halt); 3416 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3417 else __ cmpptr(tmp, src_klass_addr); 3418 __ jcc(Assembler::equal, known_ok); 3419 } else { 3420 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3421 else __ cmpptr(tmp, dst_klass_addr); 3422 __ jcc(Assembler::equal, known_ok); 3423 __ cmpptr(src, dst); 3424 __ jcc(Assembler::equal, known_ok); 3425 } 3426 __ bind(halt); 3427 __ stop("incorrect type information in arraycopy"); 3428 __ bind(known_ok); 3429 } 3430 #endif 3431 3432 #ifndef PRODUCT 3433 if (PrintC1Statistics) { 3434 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3435 } 3436 #endif 3437 3438 #ifdef _LP64 3439 assert_different_registers(c_rarg0, dst, dst_pos, length); 3440 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3441 assert_different_registers(c_rarg1, length); 3442 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3443 __ mov(c_rarg2, length); 3444 3445 #else 3446 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3447 store_parameter(tmp, 0); 3448 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3449 store_parameter(tmp, 1); 3450 store_parameter(length, 2); 3451 #endif // _LP64 3452 3453 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3454 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3455 const char *name; 3456 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3457 __ call_VM_leaf(entry, 0); 3458 3459 __ bind(*stub->continuation()); 3460 } 3461 3462 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3463 assert(op->crc()->is_single_cpu(), "crc must be register"); 3464 assert(op->val()->is_single_cpu(), "byte value must be register"); 3465 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3466 Register crc = op->crc()->as_register(); 3467 Register val = op->val()->as_register(); 3468 Register res = op->result_opr()->as_register(); 3469 3470 assert_different_registers(val, crc, res); 3471 3472 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3473 __ notl(crc); // ~crc 3474 __ update_byte_crc32(crc, val, res); 3475 __ notl(crc); // ~crc 3476 __ mov(res, crc); 3477 } 3478 3479 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3480 Register obj = op->obj_opr()->as_register(); // may not be an oop 3481 Register hdr = op->hdr_opr()->as_register(); 3482 Register lock = op->lock_opr()->as_register(); 3483 if (!UseFastLocking) { 3484 __ jmp(*op->stub()->entry()); 3485 } else if (op->code() == lir_lock) { 3486 Register scratch = noreg; 3487 if (UseBiasedLocking) { 3488 scratch = op->scratch_opr()->as_register(); 3489 } 3490 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3491 // add debug info for NullPointerException only if one is possible 3492 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3493 if (op->info() != NULL) { 3494 add_debug_info_for_null_check(null_check_offset, op->info()); 3495 } 3496 // done 3497 } else if (op->code() == lir_unlock) { 3498 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3499 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3500 } else { 3501 Unimplemented(); 3502 } 3503 __ bind(*op->stub()->continuation()); 3504 } 3505 3506 3507 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3508 ciMethod* method = op->profiled_method(); 3509 int bci = op->profiled_bci(); 3510 ciMethod* callee = op->profiled_callee(); 3511 3512 // Update counter for all call types 3513 ciMethodData* md = method->method_data_or_null(); 3514 assert(md != NULL, "Sanity"); 3515 ciProfileData* data = md->bci_to_data(bci); 3516 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 3517 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3518 Register mdo = op->mdo()->as_register(); 3519 __ mov_metadata(mdo, md->constant_encoding()); 3520 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3521 // Perform additional virtual call profiling for invokevirtual and 3522 // invokeinterface bytecodes 3523 if (op->should_profile_receiver_type()) { 3524 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3525 Register recv = op->recv()->as_register(); 3526 assert_different_registers(mdo, recv); 3527 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3528 ciKlass* known_klass = op->known_holder(); 3529 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3530 // We know the type that will be seen at this call site; we can 3531 // statically update the MethodData* rather than needing to do 3532 // dynamic tests on the receiver type 3533 3534 // NOTE: we should probably put a lock around this search to 3535 // avoid collisions by concurrent compilations 3536 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3537 uint i; 3538 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3539 ciKlass* receiver = vc_data->receiver(i); 3540 if (known_klass->equals(receiver)) { 3541 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3542 __ addptr(data_addr, DataLayout::counter_increment); 3543 return; 3544 } 3545 } 3546 3547 // Receiver type not found in profile data; select an empty slot 3548 3549 // Note that this is less efficient than it should be because it 3550 // always does a write to the receiver part of the 3551 // VirtualCallData rather than just the first time 3552 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3553 ciKlass* receiver = vc_data->receiver(i); 3554 if (receiver == NULL) { 3555 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3556 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3557 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3558 __ addptr(data_addr, DataLayout::counter_increment); 3559 return; 3560 } 3561 } 3562 } else { 3563 __ load_klass(recv, recv); 3564 Label update_done; 3565 type_profile_helper(mdo, md, data, recv, &update_done); 3566 // Receiver did not match any saved receiver and there is no empty row for it. 3567 // Increment total counter to indicate polymorphic case. 3568 __ addptr(counter_addr, DataLayout::counter_increment); 3569 3570 __ bind(update_done); 3571 } 3572 } else { 3573 // Static call 3574 __ addptr(counter_addr, DataLayout::counter_increment); 3575 } 3576 } 3577 3578 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3579 Register obj = op->obj()->as_register(); 3580 Register tmp = op->tmp()->as_pointer_register(); 3581 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3582 ciKlass* exact_klass = op->exact_klass(); 3583 intptr_t current_klass = op->current_klass(); 3584 bool not_null = op->not_null(); 3585 bool no_conflict = op->no_conflict(); 3586 3587 Label update, next, none; 3588 3589 bool do_null = !not_null; 3590 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3591 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3592 3593 assert(do_null || do_update, "why are we here?"); 3594 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3595 3596 __ verify_oop(obj); 3597 3598 if (tmp != obj) { 3599 __ mov(tmp, obj); 3600 } 3601 if (do_null) { 3602 __ testptr(tmp, tmp); 3603 __ jccb(Assembler::notZero, update); 3604 if (!TypeEntries::was_null_seen(current_klass)) { 3605 __ orptr(mdo_addr, TypeEntries::null_seen); 3606 } 3607 if (do_update) { 3608 #ifndef ASSERT 3609 __ jmpb(next); 3610 } 3611 #else 3612 __ jmp(next); 3613 } 3614 } else { 3615 __ testptr(tmp, tmp); 3616 __ jccb(Assembler::notZero, update); 3617 __ stop("unexpect null obj"); 3618 #endif 3619 } 3620 3621 __ bind(update); 3622 3623 if (do_update) { 3624 #ifdef ASSERT 3625 if (exact_klass != NULL) { 3626 Label ok; 3627 __ load_klass(tmp, tmp); 3628 __ push(tmp); 3629 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3630 __ cmpptr(tmp, Address(rsp, 0)); 3631 __ jccb(Assembler::equal, ok); 3632 __ stop("exact klass and actual klass differ"); 3633 __ bind(ok); 3634 __ pop(tmp); 3635 } 3636 #endif 3637 if (!no_conflict) { 3638 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3639 if (exact_klass != NULL) { 3640 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3641 } else { 3642 __ load_klass(tmp, tmp); 3643 } 3644 3645 __ xorptr(tmp, mdo_addr); 3646 __ testptr(tmp, TypeEntries::type_klass_mask); 3647 // klass seen before, nothing to do. The unknown bit may have been 3648 // set already but no need to check. 3649 __ jccb(Assembler::zero, next); 3650 3651 __ testptr(tmp, TypeEntries::type_unknown); 3652 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3653 3654 if (TypeEntries::is_type_none(current_klass)) { 3655 __ cmpptr(mdo_addr, 0); 3656 __ jccb(Assembler::equal, none); 3657 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3658 __ jccb(Assembler::equal, none); 3659 // There is a chance that the checks above (re-reading profiling 3660 // data from memory) fail if another thread has just set the 3661 // profiling to this obj's klass 3662 __ xorptr(tmp, mdo_addr); 3663 __ testptr(tmp, TypeEntries::type_klass_mask); 3664 __ jccb(Assembler::zero, next); 3665 } 3666 } else { 3667 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3668 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3669 3670 __ movptr(tmp, mdo_addr); 3671 __ testptr(tmp, TypeEntries::type_unknown); 3672 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3673 } 3674 3675 // different than before. Cannot keep accurate profile. 3676 __ orptr(mdo_addr, TypeEntries::type_unknown); 3677 3678 if (TypeEntries::is_type_none(current_klass)) { 3679 __ jmpb(next); 3680 3681 __ bind(none); 3682 // first time here. Set profile type. 3683 __ movptr(mdo_addr, tmp); 3684 } 3685 } else { 3686 // There's a single possible klass at this profile point 3687 assert(exact_klass != NULL, "should be"); 3688 if (TypeEntries::is_type_none(current_klass)) { 3689 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3690 __ xorptr(tmp, mdo_addr); 3691 __ testptr(tmp, TypeEntries::type_klass_mask); 3692 #ifdef ASSERT 3693 __ jcc(Assembler::zero, next); 3694 3695 { 3696 Label ok; 3697 __ push(tmp); 3698 __ cmpptr(mdo_addr, 0); 3699 __ jcc(Assembler::equal, ok); 3700 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3701 __ jcc(Assembler::equal, ok); 3702 // may have been set by another thread 3703 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3704 __ xorptr(tmp, mdo_addr); 3705 __ testptr(tmp, TypeEntries::type_mask); 3706 __ jcc(Assembler::zero, ok); 3707 3708 __ stop("unexpected profiling mismatch"); 3709 __ bind(ok); 3710 __ pop(tmp); 3711 } 3712 #else 3713 __ jccb(Assembler::zero, next); 3714 #endif 3715 // first time here. Set profile type. 3716 __ movptr(mdo_addr, tmp); 3717 } else { 3718 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3719 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3720 3721 __ movptr(tmp, mdo_addr); 3722 __ testptr(tmp, TypeEntries::type_unknown); 3723 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3724 3725 __ orptr(mdo_addr, TypeEntries::type_unknown); 3726 } 3727 } 3728 3729 __ bind(next); 3730 } 3731 } 3732 3733 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3734 Unimplemented(); 3735 } 3736 3737 3738 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3739 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3740 } 3741 3742 3743 void LIR_Assembler::align_backward_branch_target() { 3744 __ align(BytesPerWord); 3745 } 3746 3747 3748 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3749 if (left->is_single_cpu()) { 3750 __ negl(left->as_register()); 3751 move_regs(left->as_register(), dest->as_register()); 3752 3753 } else if (left->is_double_cpu()) { 3754 Register lo = left->as_register_lo(); 3755 #ifdef _LP64 3756 Register dst = dest->as_register_lo(); 3757 __ movptr(dst, lo); 3758 __ negptr(dst); 3759 #else 3760 Register hi = left->as_register_hi(); 3761 __ lneg(hi, lo); 3762 if (dest->as_register_lo() == hi) { 3763 assert(dest->as_register_hi() != lo, "destroying register"); 3764 move_regs(hi, dest->as_register_hi()); 3765 move_regs(lo, dest->as_register_lo()); 3766 } else { 3767 move_regs(lo, dest->as_register_lo()); 3768 move_regs(hi, dest->as_register_hi()); 3769 } 3770 #endif // _LP64 3771 3772 } else if (dest->is_single_xmm()) { 3773 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3774 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3775 } 3776 if (UseAVX > 0) { 3777 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(), 3778 ExternalAddress((address)float_signflip_pool)); 3779 } else { 3780 __ xorps(dest->as_xmm_float_reg(), 3781 ExternalAddress((address)float_signflip_pool)); 3782 } 3783 } else if (dest->is_double_xmm()) { 3784 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3785 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3786 } 3787 if (UseAVX > 0) { 3788 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(), 3789 ExternalAddress((address)double_signflip_pool)); 3790 } else { 3791 __ xorpd(dest->as_xmm_double_reg(), 3792 ExternalAddress((address)double_signflip_pool)); 3793 } 3794 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3795 assert(left->fpu() == 0, "arg must be on TOS"); 3796 assert(dest->fpu() == 0, "dest must be TOS"); 3797 __ fchs(); 3798 3799 } else { 3800 ShouldNotReachHere(); 3801 } 3802 } 3803 3804 3805 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3806 assert(addr->is_address() && dest->is_register(), "check"); 3807 Register reg; 3808 reg = dest->as_pointer_register(); 3809 __ lea(reg, as_Address(addr->as_address_ptr())); 3810 } 3811 3812 3813 3814 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3815 assert(!tmp->is_valid(), "don't need temporary"); 3816 __ call(RuntimeAddress(dest)); 3817 if (info != NULL) { 3818 add_call_info_here(info); 3819 } 3820 } 3821 3822 3823 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3824 assert(type == T_LONG, "only for volatile long fields"); 3825 3826 if (info != NULL) { 3827 add_debug_info_for_null_check_here(info); 3828 } 3829 3830 if (src->is_double_xmm()) { 3831 if (dest->is_double_cpu()) { 3832 #ifdef _LP64 3833 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3834 #else 3835 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3836 __ psrlq(src->as_xmm_double_reg(), 32); 3837 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3838 #endif // _LP64 3839 } else if (dest->is_double_stack()) { 3840 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3841 } else if (dest->is_address()) { 3842 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3843 } else { 3844 ShouldNotReachHere(); 3845 } 3846 3847 } else if (dest->is_double_xmm()) { 3848 if (src->is_double_stack()) { 3849 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3850 } else if (src->is_address()) { 3851 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3852 } else { 3853 ShouldNotReachHere(); 3854 } 3855 3856 } else if (src->is_double_fpu()) { 3857 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3858 if (dest->is_double_stack()) { 3859 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3860 } else if (dest->is_address()) { 3861 __ fistp_d(as_Address(dest->as_address_ptr())); 3862 } else { 3863 ShouldNotReachHere(); 3864 } 3865 3866 } else if (dest->is_double_fpu()) { 3867 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3868 if (src->is_double_stack()) { 3869 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3870 } else if (src->is_address()) { 3871 __ fild_d(as_Address(src->as_address_ptr())); 3872 } else { 3873 ShouldNotReachHere(); 3874 } 3875 } else { 3876 ShouldNotReachHere(); 3877 } 3878 } 3879 3880 #ifdef ASSERT 3881 // emit run-time assertion 3882 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3883 assert(op->code() == lir_assert, "must be"); 3884 3885 if (op->in_opr1()->is_valid()) { 3886 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3887 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3888 } else { 3889 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3890 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3891 } 3892 3893 Label ok; 3894 if (op->condition() != lir_cond_always) { 3895 Assembler::Condition acond = Assembler::zero; 3896 switch (op->condition()) { 3897 case lir_cond_equal: acond = Assembler::equal; break; 3898 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3899 case lir_cond_less: acond = Assembler::less; break; 3900 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3901 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3902 case lir_cond_greater: acond = Assembler::greater; break; 3903 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3904 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3905 default: ShouldNotReachHere(); 3906 } 3907 __ jcc(acond, ok); 3908 } 3909 if (op->halt()) { 3910 const char* str = __ code_string(op->msg()); 3911 __ stop(str); 3912 } else { 3913 breakpoint(); 3914 } 3915 __ bind(ok); 3916 } 3917 #endif 3918 3919 void LIR_Assembler::membar() { 3920 // QQQ sparc TSO uses this, 3921 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3922 } 3923 3924 void LIR_Assembler::membar_acquire() { 3925 // No x86 machines currently require load fences 3926 } 3927 3928 void LIR_Assembler::membar_release() { 3929 // No x86 machines currently require store fences 3930 } 3931 3932 void LIR_Assembler::membar_loadload() { 3933 // no-op 3934 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3935 } 3936 3937 void LIR_Assembler::membar_storestore() { 3938 // no-op 3939 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3940 } 3941 3942 void LIR_Assembler::membar_loadstore() { 3943 // no-op 3944 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3945 } 3946 3947 void LIR_Assembler::membar_storeload() { 3948 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3949 } 3950 3951 void LIR_Assembler::on_spin_wait() { 3952 __ pause (); 3953 } 3954 3955 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3956 assert(result_reg->is_register(), "check"); 3957 #ifdef _LP64 3958 // __ get_thread(result_reg->as_register_lo()); 3959 __ mov(result_reg->as_register(), r15_thread); 3960 #else 3961 __ get_thread(result_reg->as_register()); 3962 #endif // _LP64 3963 } 3964 3965 3966 void LIR_Assembler::peephole(LIR_List*) { 3967 // do nothing for now 3968 } 3969 3970 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3971 assert(data == dest, "xchg/xadd uses only 2 operands"); 3972 3973 if (data->type() == T_INT) { 3974 if (code == lir_xadd) { 3975 if (os::is_MP()) { 3976 __ lock(); 3977 } 3978 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 3979 } else { 3980 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 3981 } 3982 } else if (data->is_oop()) { 3983 assert (code == lir_xchg, "xadd for oops"); 3984 Register obj = data->as_register(); 3985 #ifdef _LP64 3986 if (UseCompressedOops) { 3987 __ encode_heap_oop(obj); 3988 __ xchgl(obj, as_Address(src->as_address_ptr())); 3989 __ decode_heap_oop(obj); 3990 } else { 3991 __ xchgptr(obj, as_Address(src->as_address_ptr())); 3992 } 3993 #else 3994 __ xchgl(obj, as_Address(src->as_address_ptr())); 3995 #endif 3996 } else if (data->type() == T_LONG) { 3997 #ifdef _LP64 3998 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 3999 if (code == lir_xadd) { 4000 if (os::is_MP()) { 4001 __ lock(); 4002 } 4003 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4004 } else { 4005 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4006 } 4007 #else 4008 ShouldNotReachHere(); 4009 #endif 4010 } else { 4011 ShouldNotReachHere(); 4012 } 4013 } 4014 4015 #undef __