1 /*
   2  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef SHARE_VM_OPTO_REGMASK_HPP
  26 #define SHARE_VM_OPTO_REGMASK_HPP
  27 
  28 #include "code/vmreg.hpp"
  29 #include "opto/optoreg.hpp"
  30 
  31 // Some fun naming (textual) substitutions:
  32 //
  33 // RegMask::get_low_elem() ==> RegMask::find_first_elem()
  34 // RegMask::Special        ==> RegMask::Empty
  35 // RegMask::_flags         ==> RegMask::is_AllStack()
  36 // RegMask::operator<<=()  ==> RegMask::Insert()
  37 // RegMask::operator>>=()  ==> RegMask::Remove()
  38 // RegMask::Union()        ==> RegMask::OR
  39 // RegMask::Inter()        ==> RegMask::AND
  40 //
  41 // OptoRegister::RegName   ==> OptoReg::Name
  42 //
  43 // OptoReg::stack0()       ==> _last_Mach_Reg  or ZERO in core version
  44 //
  45 // numregs in chaitin      ==> proper degree in chaitin
  46 
  47 //-------------Non-zero bit search methods used by RegMask---------------------
  48 // Find lowest 1, or return 32 if empty
  49 int find_lowest_bit( uint32_t mask );
  50 // Find highest 1, or return 32 if empty
  51 int find_hihghest_bit( uint32_t mask );
  52 
  53 //------------------------------RegMask----------------------------------------
  54 // The ADL file describes how to print the machine-specific registers, as well
  55 // as any notion of register classes.  We provide a register mask, which is
  56 // just a collection of Register numbers.
  57 
  58 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
  59 // RM_SIZE is the size of a register mask in words.
  60 // FORALL_BODY replicates a BODY macro once per word in the register mask.
  61 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
  62 // However, it means the ADLC can redefine the unroll macro and all loops
  63 // over register masks will be unrolled by the correct amount.
  64 
  65 class RegMask {
  66   union {
  67     double _dummy_force_double_alignment[RM_SIZE>>1];
  68     // Array of Register Mask bits.  This array is large enough to cover
  69     // all the machine registers and all parameters that need to be passed
  70     // on the stack (stack registers) up to some interesting limit.  Methods
  71     // that need more parameters will NOT be compiled.  On Intel, the limit
  72     // is something like 90+ parameters.
  73     int _A[RM_SIZE];
  74   };
  75 
  76   enum {
  77     _WordBits    = BitsPerInt,
  78     _LogWordBits = LogBitsPerInt,
  79     _RM_SIZE     = RM_SIZE   // local constant, imported, then hidden by #undef
  80   };
  81 
  82 public:
  83   enum { CHUNK_SIZE = RM_SIZE*_WordBits };
  84 
  85   // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
  86   // Also, consider the maximum alignment size for a normally allocated
  87   // value.  Since we allocate register pairs but not register quads (at
  88   // present), this alignment is SlotsPerLong (== 2).  A normally
  89   // aligned allocated register is either a single register, or a pair
  90   // of adjacent registers, the lower-numbered being even.
  91   // See also is_aligned_Pairs() below, and the padding added before
  92   // Matcher::_new_SP to keep allocated pairs aligned properly.
  93   // If we ever go to quad-word allocations, SlotsPerQuad will become
  94   // the controlling alignment constraint.  Note that this alignment
  95   // requirement is internal to the allocator, and independent of any
  96   // particular platform.
  97   enum { SlotsPerLong = 2,
  98          SlotsPerVecS = 1,
  99          SlotsPerVecD = 2,
 100          SlotsPerVecX = 4,
 101          SlotsPerVecY = 8,
 102          SlotsPerVecZ = 16 };
 103 
 104   // A constructor only used by the ADLC output.  All mask fields are filled
 105   // in directly.  Calls to this look something like RM(1,2,3,4);
 106   RegMask(
 107 #   define BODY(I) int a##I,
 108     FORALL_BODY
 109 #   undef BODY
 110     int dummy = 0 ) {
 111 #   define BODY(I) _A[I] = a##I;
 112     FORALL_BODY
 113 #   undef BODY
 114   }
 115 
 116   // Handy copying constructor
 117   RegMask( RegMask *rm ) {
 118 #   define BODY(I) _A[I] = rm->_A[I];
 119     FORALL_BODY
 120 #   undef BODY
 121   }
 122 
 123   // Construct an empty mask
 124   RegMask( ) { Clear(); }
 125 
 126   // Construct a mask with a single bit
 127   RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
 128 
 129   // Check for register being in mask
 130   int Member( OptoReg::Name reg ) const {
 131     assert( reg < CHUNK_SIZE, "" );
 132     return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
 133   }
 134 
 135   // The last bit in the register mask indicates that the mask should repeat
 136   // indefinitely with ONE bits.  Returns TRUE if mask is infinite or
 137   // unbounded in size.  Returns FALSE if mask is finite size.
 138   int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
 139 
 140   // Work around an -xO3 optimization problme in WS6U1. The old way:
 141   //   void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
 142   // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
 143   // follows an Insert() loop, like the one found in init_spill_mask(). Using
 144   // Insert() instead works because the index into _A in computed instead of
 145   // constant.  See bug 4665841.
 146   void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
 147 
 148   // Test for being a not-empty mask.
 149   int is_NotEmpty( ) const {
 150     int tmp = 0;
 151 #   define BODY(I) tmp |= _A[I];
 152     FORALL_BODY
 153 #   undef BODY
 154     return tmp;
 155   }
 156 
 157   // Find lowest-numbered register from mask, or BAD if mask is empty.
 158   OptoReg::Name find_first_elem() const {
 159     int base, bits;
 160 #   define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
 161     FORALL_BODY
 162 #   undef BODY
 163       { base = OptoReg::Bad; bits = 1<<0; }
 164     return OptoReg::Name(base + find_lowest_bit(bits));
 165   }
 166   // Get highest-numbered register from mask, or BAD if mask is empty.
 167   OptoReg::Name find_last_elem() const {
 168     int base, bits;
 169 #   define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
 170     FORALL_BODY
 171 #   undef BODY
 172       { base = OptoReg::Bad; bits = 1<<0; }
 173     return OptoReg::Name(base + find_hihghest_bit(bits));
 174   }
 175 
 176   // Find the lowest-numbered register pair in the mask.  Return the
 177   // HIGHEST register number in the pair, or BAD if no pairs.
 178   // Assert that the mask contains only bit pairs.
 179   OptoReg::Name find_first_pair() const;
 180 
 181   // Clear out partial bits; leave only aligned adjacent bit pairs.
 182   void clear_to_pairs();
 183   // Smear out partial bits; leave only aligned adjacent bit pairs.
 184   void smear_to_pairs();
 185   // Verify that the mask contains only aligned adjacent bit pairs
 186   void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
 187   // Test that the mask contains only aligned adjacent bit pairs
 188   bool is_aligned_pairs() const;
 189 
 190   // mask is a pair of misaligned registers
 191   bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
 192   // Test for single register
 193   int is_bound1() const;
 194   // Test for a single adjacent pair
 195   int is_bound_pair() const;
 196   // Test for a single adjacent set of ideal register's size.
 197   int is_bound(uint ireg) const {
 198     if (is_vector(ireg)) {
 199       if (is_bound_set(num_registers(ireg)))
 200         return true;
 201     } else if (is_bound1() || is_bound_pair()) {
 202       return true;
 203     }
 204     return false;
 205   }
 206 
 207   // Find the lowest-numbered register set in the mask.  Return the
 208   // HIGHEST register number in the set, or BAD if no sets.
 209   // Assert that the mask contains only bit sets.
 210   OptoReg::Name find_first_set(const int size) const;
 211 
 212   // Clear out partial bits; leave only aligned adjacent bit sets of size.
 213   void clear_to_sets(const int size);
 214   // Smear out partial bits to aligned adjacent bit sets.
 215   void smear_to_sets(const int size);
 216   // Verify that the mask contains only aligned adjacent bit sets
 217   void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
 218   // Test that the mask contains only aligned adjacent bit sets
 219   bool is_aligned_sets(const int size) const;
 220 
 221   // mask is a set of misaligned registers
 222   bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
 223 
 224   // Test for a single adjacent set
 225   int is_bound_set(const int size) const;
 226 
 227   static bool is_vector(uint ireg);
 228   static int num_registers(uint ireg);
 229 
 230   // Fast overlap test.  Non-zero if any registers in common.
 231   int overlap( const RegMask &rm ) const {
 232     return
 233 #   define BODY(I) (_A[I] & rm._A[I]) |
 234     FORALL_BODY
 235 #   undef BODY
 236     0 ;
 237   }
 238 
 239   // Special test for register pressure based splitting
 240   // UP means register only, Register plus stack, or stack only is DOWN
 241   bool is_UP() const;
 242 
 243   // Clear a register mask
 244   void Clear( ) {
 245 #   define BODY(I) _A[I] = 0;
 246     FORALL_BODY
 247 #   undef BODY
 248   }
 249 
 250   // Fill a register mask with 1's
 251   void Set_All( ) {
 252 #   define BODY(I) _A[I] = -1;
 253     FORALL_BODY
 254 #   undef BODY
 255   }
 256 
 257   // Insert register into mask
 258   void Insert( OptoReg::Name reg ) {
 259     assert( reg < CHUNK_SIZE, "" );
 260     _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
 261   }
 262 
 263   // Remove register from mask
 264   void Remove( OptoReg::Name reg ) {
 265     assert( reg < CHUNK_SIZE, "" );
 266     _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
 267   }
 268 
 269   // OR 'rm' into 'this'
 270   void OR( const RegMask &rm ) {
 271 #   define BODY(I) this->_A[I] |= rm._A[I];
 272     FORALL_BODY
 273 #   undef BODY
 274   }
 275 
 276   // AND 'rm' into 'this'
 277   void AND( const RegMask &rm ) {
 278 #   define BODY(I) this->_A[I] &= rm._A[I];
 279     FORALL_BODY
 280 #   undef BODY
 281   }
 282 
 283   // Subtract 'rm' from 'this'
 284   void SUBTRACT( const RegMask &rm ) {
 285 #   define BODY(I) _A[I] &= ~rm._A[I];
 286     FORALL_BODY
 287 #   undef BODY
 288   }
 289 
 290   // Compute size of register mask: number of bits
 291   uint Size() const;
 292 
 293 #ifndef PRODUCT
 294   void print() const { dump(); }
 295   void dump(outputStream *st = tty) const; // Print a mask
 296 #endif
 297 
 298   static const RegMask Empty;   // Common empty mask
 299 
 300   static bool can_represent(OptoReg::Name reg) {
 301     // NOTE: -1 in computation reflects the usage of the last
 302     //       bit of the regmask as an infinite stack flag and
 303     //       -7 is to keep mask aligned for largest value (VecZ).
 304     return (int)reg < (int)(CHUNK_SIZE-1);
 305   }
 306   static bool can_represent_arg(OptoReg::Name reg) {
 307     // NOTE: -SlotsPerVecZ in computation reflects the need
 308     //       to keep mask aligned for largest value (VecZ).
 309     return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecZ);
 310   }
 311 };
 312 
 313 // Do not use this constant directly in client code!
 314 #undef RM_SIZE
 315 
 316 #endif // SHARE_VM_OPTO_REGMASK_HPP