1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableBarrierSet.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/interfaceSupport.inline.hpp"
39 #include "runtime/jniHandles.inline.hpp"
40 #include "runtime/safepointMechanism.inline.hpp"
41 #include "runtime/sharedRuntime.hpp"
42
43 #define __ _masm->
44
45
46 //------------------------------------------------------------
47
48
49 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
50 if (opr->is_constant()) {
51 LIR_Const* constant = opr->as_constant_ptr();
52 switch (constant->type()) {
53 case T_INT: {
54 jint value = constant->as_jint();
55 return Assembler::is_simm13(value);
56 }
57
58 default:
59 return false;
60 }
61 }
62 return false;
63 }
64
65
66 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
67 switch (op->code()) {
68 case lir_null_check:
69 return true;
70
71
72 case lir_add:
73 case lir_ushr:
74 case lir_shr:
75 case lir_shl:
76 // integer shifts and adds are always one instruction
77 return op->result_opr()->is_single_cpu();
78
79
80 case lir_move: {
81 LIR_Op1* op1 = op->as_Op1();
82 LIR_Opr src = op1->in_opr();
83 LIR_Opr dst = op1->result_opr();
84
85 if (src == dst) {
86 NEEDS_CLEANUP;
87 // this works around a problem where moves with the same src and dst
88 // end up in the delay slot and then the assembler swallows the mov
89 // since it has no effect and then it complains because the delay slot
90 // is empty. returning false stops the optimizer from putting this in
91 // the delay slot
92 return false;
93 }
94
95 // don't put moves involving oops into the delay slot since the VerifyOops code
96 // will make it much larger than a single instruction.
97 if (VerifyOops) {
98 return false;
99 }
100
101 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
102 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
103 return false;
104 }
105
106 if (UseCompressedOops) {
107 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
108 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
109 }
110
111 if (UseCompressedClassPointers) {
112 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
113 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
114 }
115
116 if (dst->is_register()) {
117 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
118 return !PatchALot;
119 } else if (src->is_single_stack()) {
120 return true;
121 }
122 }
123
124 if (src->is_register()) {
125 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
126 return !PatchALot;
127 } else if (dst->is_single_stack()) {
128 return true;
129 }
130 }
131
132 if (dst->is_register() &&
133 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
134 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
135 return true;
136 }
137
138 return false;
139 }
140
141 default:
142 return false;
143 }
144 ShouldNotReachHere();
145 }
146
147
148 LIR_Opr LIR_Assembler::receiverOpr() {
149 return FrameMap::O0_oop_opr;
150 }
151
152
153 LIR_Opr LIR_Assembler::osrBufferPointer() {
154 return FrameMap::I0_opr;
155 }
156
157
158 int LIR_Assembler::initial_frame_size_in_bytes() const {
159 return in_bytes(frame_map()->framesize_in_bytes());
160 }
161
162
163 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
164 // we fetch the class of the receiver (O0) and compare it with the cached class.
165 // If they do not match we jump to slow case.
166 int LIR_Assembler::check_icache() {
167 int offset = __ offset();
168 __ inline_cache_check(O0, G5_inline_cache_reg);
169 return offset;
170 }
171
172
173 void LIR_Assembler::osr_entry() {
174 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
175 //
176 // 1. Create a new compiled activation.
177 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
178 // at the osr_bci; it is not initialized.
179 // 3. Jump to the continuation address in compiled code to resume execution.
180
181 // OSR entry point
182 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
183 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
184 ValueStack* entry_state = osr_entry->end()->state();
185 int number_of_locks = entry_state->locks_size();
186
187 // Create a frame for the compiled activation.
188 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
189
190 // OSR buffer is
191 //
192 // locals[nlocals-1..0]
193 // monitors[number_of_locks-1..0]
194 //
195 // locals is a direct copy of the interpreter frame so in the osr buffer
196 // so first slot in the local array is the last local from the interpreter
197 // and last slot is local[0] (receiver) from the interpreter
198 //
199 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
200 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
201 // in the interpreter frame (the method lock if a sync method)
202
203 // Initialize monitors in the compiled activation.
204 // I0: pointer to osr buffer
205 //
206 // All other registers are dead at this point and the locals will be
207 // copied into place by code emitted in the IR.
208
209 Register OSR_buf = osrBufferPointer()->as_register();
210 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
211 int monitor_offset = BytesPerWord * method()->max_locals() +
212 (2 * BytesPerWord) * (number_of_locks - 1);
213 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
214 // the OSR buffer using 2 word entries: first the lock and then
215 // the oop.
216 for (int i = 0; i < number_of_locks; i++) {
217 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
218 #ifdef ASSERT
219 // verify the interpreter's monitor has a non-null object
220 {
221 Label L;
222 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
223 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
224 __ stop("locked object is NULL");
225 __ bind(L);
226 }
227 #endif // ASSERT
228 // Copy the lock field into the compiled activation.
229 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
230 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
231 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
232 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
233 }
234 }
235 }
236
237
238 // --------------------------------------------------------------------------------------------
239
240 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
241 if (!GenerateSynchronizationCode) return;
242
243 Register obj_reg = obj_opr->as_register();
244 Register lock_reg = lock_opr->as_register();
245
246 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
247 Register reg = mon_addr.base();
248 int offset = mon_addr.disp();
249 // compute pointer to BasicLock
250 if (mon_addr.is_simm13()) {
251 __ add(reg, offset, lock_reg);
252 }
253 else {
254 __ set(offset, lock_reg);
255 __ add(reg, lock_reg, lock_reg);
256 }
257 // unlock object
258 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
259 // _slow_case_stubs->append(slow_case);
260 // temporary fix: must be created after exceptionhandler, therefore as call stub
261 _slow_case_stubs->append(slow_case);
262 if (UseFastLocking) {
263 // try inlined fast unlocking first, revert to slow locking if it fails
264 // note: lock_reg points to the displaced header since the displaced header offset is 0!
265 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
266 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
267 } else {
268 // always do slow unlocking
269 // note: the slow unlocking code could be inlined here, however if we use
270 // slow unlocking, speed doesn't matter anyway and this solution is
271 // simpler and requires less duplicated code - additionally, the
272 // slow unlocking code is the same in either case which simplifies
273 // debugging
274 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
275 __ delayed()->nop();
276 }
277 // done
278 __ bind(*slow_case->continuation());
279 }
280
281
282 int LIR_Assembler::emit_exception_handler() {
283 // if the last instruction is a call (typically to do a throw which
284 // is coming at the end after block reordering) the return address
285 // must still point into the code area in order to avoid assertion
286 // failures when searching for the corresponding bci => add a nop
287 // (was bug 5/14/1999 - gri)
288 __ nop();
289
290 // generate code for exception handler
291 ciMethod* method = compilation()->method();
292
293 address handler_base = __ start_a_stub(exception_handler_size());
294
295 if (handler_base == NULL) {
296 // not enough space left for the handler
297 bailout("exception handler overflow");
298 return -1;
299 }
300
301 int offset = code_offset();
302
303 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
304 __ delayed()->nop();
305 __ should_not_reach_here();
306 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
307 __ end_a_stub();
308
309 return offset;
310 }
311
312
313 // Emit the code to remove the frame from the stack in the exception
314 // unwind path.
315 int LIR_Assembler::emit_unwind_handler() {
316 #ifndef PRODUCT
317 if (CommentedAssembly) {
318 _masm->block_comment("Unwind handler");
319 }
320 #endif
321
322 int offset = code_offset();
323
324 // Fetch the exception from TLS and clear out exception related thread state
325 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
326 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
327 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
328
329 __ bind(_unwind_handler_entry);
330 __ verify_not_null_oop(O0);
331 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
332 __ mov(O0, I0); // Preserve the exception
333 }
334
335 // Preform needed unlocking
336 MonitorExitStub* stub = NULL;
337 if (method()->is_synchronized()) {
338 monitor_address(0, FrameMap::I1_opr);
339 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
340 __ unlock_object(I3, I2, I1, *stub->entry());
341 __ bind(*stub->continuation());
342 }
343
344 if (compilation()->env()->dtrace_method_probes()) {
345 __ mov(G2_thread, O0);
346 __ save_thread(I1); // need to preserve thread in G2 across
347 // runtime call
348 metadata2reg(method()->constant_encoding(), O1);
349 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
350 __ delayed()->nop();
351 __ restore_thread(I1);
352 }
353
354 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
355 __ mov(I0, O0); // Restore the exception
356 }
357
358 // dispatch to the unwind logic
359 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
360 __ delayed()->nop();
361
362 // Emit the slow path assembly
363 if (stub != NULL) {
364 stub->emit_code(this);
365 }
366
367 return offset;
368 }
369
370
371 int LIR_Assembler::emit_deopt_handler() {
372 // if the last instruction is a call (typically to do a throw which
373 // is coming at the end after block reordering) the return address
374 // must still point into the code area in order to avoid assertion
375 // failures when searching for the corresponding bci => add a nop
376 // (was bug 5/14/1999 - gri)
377 __ nop();
378
379 // generate code for deopt handler
380 ciMethod* method = compilation()->method();
381 address handler_base = __ start_a_stub(deopt_handler_size());
382 if (handler_base == NULL) {
383 // not enough space left for the handler
384 bailout("deopt handler overflow");
385 return -1;
386 }
387
388 int offset = code_offset();
389 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
390 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
391 __ delayed()->nop();
392 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
393 __ end_a_stub();
394
395 return offset;
396 }
397
398
399 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
400 if (o == NULL) {
401 __ set(NULL_WORD, reg);
402 } else {
403 #ifdef ASSERT
404 {
405 ThreadInVMfromNative tiv(JavaThread::current());
406 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
407 }
408 #endif
409 int oop_index = __ oop_recorder()->find_index(o);
410 RelocationHolder rspec = oop_Relocation::spec(oop_index);
411 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
412 }
413 }
414
415
416 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
417 // Allocate a new index in table to hold the object once it's been patched
418 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
419 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
420
421 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
422 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
423 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
424 // NULL will be dynamically patched later and the patched value may be large. We must
425 // therefore generate the sethi/add as a placeholders
426 __ patchable_set(addrlit, reg);
427
428 patching_epilog(patch, lir_patch_normal, reg, info);
429 }
430
431
432 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
433 __ set_metadata_constant(o, reg);
434 }
435
436 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
437 // Allocate a new index in table to hold the klass once it's been patched
438 int index = __ oop_recorder()->allocate_metadata_index(NULL);
439 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
440 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
441 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
442 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
443 // NULL will be dynamically patched later and the patched value may be large. We must
444 // therefore generate the sethi/add as a placeholders
445 __ patchable_set(addrlit, reg);
446
447 patching_epilog(patch, lir_patch_normal, reg, info);
448 }
449
450 void LIR_Assembler::emit_op3(LIR_Op3* op) {
451 switch (op->code()) {
452 case lir_idiv:
453 case lir_irem: // Both idiv & irem are handled after the switch (below).
454 break;
455 case lir_fmaf:
456 __ fmadd(FloatRegisterImpl::S,
457 op->in_opr1()->as_float_reg(),
458 op->in_opr2()->as_float_reg(),
459 op->in_opr3()->as_float_reg(),
460 op->result_opr()->as_float_reg());
461 return;
462 case lir_fmad:
463 __ fmadd(FloatRegisterImpl::D,
464 op->in_opr1()->as_double_reg(),
465 op->in_opr2()->as_double_reg(),
466 op->in_opr3()->as_double_reg(),
467 op->result_opr()->as_double_reg());
468 return;
469 default:
470 ShouldNotReachHere();
471 break;
472 }
473
474 // Handle idiv & irem:
475
476 Register Rdividend = op->in_opr1()->as_register();
477 Register Rdivisor = noreg;
478 Register Rscratch = op->in_opr3()->as_register();
479 Register Rresult = op->result_opr()->as_register();
480 int divisor = -1;
481
482 if (op->in_opr2()->is_register()) {
483 Rdivisor = op->in_opr2()->as_register();
484 } else {
485 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
486 assert(Assembler::is_simm13(divisor), "can only handle simm13");
487 }
488
489 assert(Rdividend != Rscratch, "");
490 assert(Rdivisor != Rscratch, "");
491 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
492
493 if (Rdivisor == noreg && is_power_of_2(divisor)) {
494 // convert division by a power of two into some shifts and logical operations
495 if (op->code() == lir_idiv) {
496 if (divisor == 2) {
497 __ srl(Rdividend, 31, Rscratch);
498 } else {
499 __ sra(Rdividend, 31, Rscratch);
500 __ and3(Rscratch, divisor - 1, Rscratch);
501 }
502 __ add(Rdividend, Rscratch, Rscratch);
503 __ sra(Rscratch, log2_intptr(divisor), Rresult);
504 return;
505 } else {
506 if (divisor == 2) {
507 __ srl(Rdividend, 31, Rscratch);
508 } else {
509 __ sra(Rdividend, 31, Rscratch);
510 __ and3(Rscratch, divisor - 1,Rscratch);
511 }
512 __ add(Rdividend, Rscratch, Rscratch);
513 __ andn(Rscratch, divisor - 1,Rscratch);
514 __ sub(Rdividend, Rscratch, Rresult);
515 return;
516 }
517 }
518
519 __ sra(Rdividend, 31, Rscratch);
520 __ wry(Rscratch);
521
522 add_debug_info_for_div0_here(op->info());
523
524 if (Rdivisor != noreg) {
525 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
526 } else {
527 assert(Assembler::is_simm13(divisor), "can only handle simm13");
528 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
529 }
530
531 Label skip;
532 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
533 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
534 __ bind(skip);
535
536 if (op->code() == lir_irem) {
537 if (Rdivisor != noreg) {
538 __ smul(Rscratch, Rdivisor, Rscratch);
539 } else {
540 __ smul(Rscratch, divisor, Rscratch);
541 }
542 __ sub(Rdividend, Rscratch, Rresult);
543 }
544 }
545
546
547 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
548 #ifdef ASSERT
549 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
550 if (op->block() != NULL) _branch_target_blocks.append(op->block());
551 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
552 #endif
553 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
554
555 if (op->cond() == lir_cond_always) {
556 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
557 } else if (op->code() == lir_cond_float_branch) {
558 assert(op->ublock() != NULL, "must have unordered successor");
559 bool is_unordered = (op->ublock() == op->block());
560 Assembler::Condition acond;
561 switch (op->cond()) {
562 case lir_cond_equal: acond = Assembler::f_equal; break;
563 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
564 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
565 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
566 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
567 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
568 default : ShouldNotReachHere();
569 }
570 __ fb( acond, false, Assembler::pn, *(op->label()));
571 } else {
572 assert (op->code() == lir_branch, "just checking");
573
574 Assembler::Condition acond;
575 switch (op->cond()) {
576 case lir_cond_equal: acond = Assembler::equal; break;
577 case lir_cond_notEqual: acond = Assembler::notEqual; break;
578 case lir_cond_less: acond = Assembler::less; break;
579 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
580 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
581 case lir_cond_greater: acond = Assembler::greater; break;
582 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
583 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
584 default: ShouldNotReachHere();
585 };
586
587 // sparc has different condition codes for testing 32-bit
588 // vs. 64-bit values. We could always test xcc is we could
589 // guarantee that 32-bit loads always sign extended but that isn't
590 // true and since sign extension isn't free, it would impose a
591 // slight cost.
592 if (op->type() == T_INT) {
593 __ br(acond, false, Assembler::pn, *(op->label()));
594 } else
595 __ brx(acond, false, Assembler::pn, *(op->label()));
596 }
597 // The peephole pass fills the delay slot
598 }
599
600
601 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
602 Bytecodes::Code code = op->bytecode();
603 LIR_Opr dst = op->result_opr();
604
605 switch(code) {
606 case Bytecodes::_i2l: {
607 Register rlo = dst->as_register_lo();
608 Register rhi = dst->as_register_hi();
609 Register rval = op->in_opr()->as_register();
610 __ sra(rval, 0, rlo);
611 break;
612 }
613 case Bytecodes::_i2d:
614 case Bytecodes::_i2f: {
615 bool is_double = (code == Bytecodes::_i2d);
616 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
617 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
618 FloatRegister rsrc = op->in_opr()->as_float_reg();
619 if (rsrc != rdst) {
620 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
621 }
622 __ fitof(w, rdst, rdst);
623 break;
624 }
625 case Bytecodes::_f2i:{
626 FloatRegister rsrc = op->in_opr()->as_float_reg();
627 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
628 Label L;
629 // result must be 0 if value is NaN; test by comparing value to itself
630 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
631 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
632 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
633 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
634 // move integer result from float register to int register
635 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
636 __ bind (L);
637 break;
638 }
639 case Bytecodes::_l2i: {
640 Register rlo = op->in_opr()->as_register_lo();
641 Register rhi = op->in_opr()->as_register_hi();
642 Register rdst = dst->as_register();
643 __ sra(rlo, 0, rdst);
644 break;
645 }
646 case Bytecodes::_d2f:
647 case Bytecodes::_f2d: {
648 bool is_double = (code == Bytecodes::_f2d);
649 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
650 LIR_Opr val = op->in_opr();
651 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
652 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
653 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
654 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
655 __ ftof(vw, dw, rval, rdst);
656 break;
657 }
658 case Bytecodes::_i2s:
659 case Bytecodes::_i2b: {
660 Register rval = op->in_opr()->as_register();
661 Register rdst = dst->as_register();
662 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
663 __ sll (rval, shift, rdst);
664 __ sra (rdst, shift, rdst);
665 break;
666 }
667 case Bytecodes::_i2c: {
668 Register rval = op->in_opr()->as_register();
669 Register rdst = dst->as_register();
670 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
671 __ sll (rval, shift, rdst);
672 __ srl (rdst, shift, rdst);
673 break;
674 }
675
676 default: ShouldNotReachHere();
677 }
678 }
679
680
681 void LIR_Assembler::align_call(LIR_Code) {
682 // do nothing since all instructions are word aligned on sparc
683 }
684
685
686 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
687 __ call(op->addr(), rtype);
688 // The peephole pass fills the delay slot, add_call_info is done in
689 // LIR_Assembler::emit_delay.
690 }
691
692
693 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
694 __ ic_call(op->addr(), false);
695 // The peephole pass fills the delay slot, add_call_info is done in
696 // LIR_Assembler::emit_delay.
697 }
698
699
700 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
701 add_debug_info_for_null_check_here(op->info());
702 __ load_klass(O0, G3_scratch);
703 if (Assembler::is_simm13(op->vtable_offset())) {
704 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
705 } else {
706 // This will generate 2 instructions
707 __ set(op->vtable_offset(), G5_method);
708 // ld_ptr, set_hi, set
709 __ ld_ptr(G3_scratch, G5_method, G5_method);
710 }
711 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
712 __ callr(G3_scratch, G0);
713 // the peephole pass fills the delay slot
714 }
715
716 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
717 int store_offset;
718 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
719 assert(base != O7, "destroying register");
720 assert(!unaligned, "can't handle this");
721 // for offsets larger than a simm13 we setup the offset in O7
722 __ set(offset, O7);
723 store_offset = store(from_reg, base, O7, type, wide);
724 } else {
725 if (type == T_ARRAY || type == T_OBJECT) {
726 __ verify_oop(from_reg->as_register());
727 }
728 store_offset = code_offset();
729 switch (type) {
730 case T_BOOLEAN: // fall through
731 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
732 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
733 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
734 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
735 case T_LONG :
736 if (unaligned || PatchALot) {
737 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
738 assert(G3_scratch != base, "can't handle this");
739 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
740 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
741 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
742 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
743 } else {
744 __ stx(from_reg->as_register_lo(), base, offset);
745 }
746 break;
747 case T_ADDRESS:
748 case T_METADATA:
749 __ st_ptr(from_reg->as_register(), base, offset);
750 break;
751 case T_ARRAY : // fall through
752 case T_OBJECT:
753 {
754 if (UseCompressedOops && !wide) {
755 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
756 store_offset = code_offset();
757 __ stw(G3_scratch, base, offset);
758 } else {
759 __ st_ptr(from_reg->as_register(), base, offset);
760 }
761 break;
762 }
763
764 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
765 case T_DOUBLE:
766 {
767 FloatRegister reg = from_reg->as_double_reg();
768 // split unaligned stores
769 if (unaligned || PatchALot) {
770 assert(Assembler::is_simm13(offset + 4), "must be");
771 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
772 __ stf(FloatRegisterImpl::S, reg, base, offset);
773 } else {
774 __ stf(FloatRegisterImpl::D, reg, base, offset);
775 }
776 break;
777 }
778 default : ShouldNotReachHere();
779 }
780 }
781 return store_offset;
782 }
783
784
785 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
786 if (type == T_ARRAY || type == T_OBJECT) {
787 __ verify_oop(from_reg->as_register());
788 }
789 int store_offset = code_offset();
790 switch (type) {
791 case T_BOOLEAN: // fall through
792 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
793 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
794 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
795 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
796 case T_LONG :
797 __ stx(from_reg->as_register_lo(), base, disp);
798 break;
799 case T_ADDRESS:
800 __ st_ptr(from_reg->as_register(), base, disp);
801 break;
802 case T_ARRAY : // fall through
803 case T_OBJECT:
804 {
805 if (UseCompressedOops && !wide) {
806 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
807 store_offset = code_offset();
808 __ stw(G3_scratch, base, disp);
809 } else {
810 __ st_ptr(from_reg->as_register(), base, disp);
811 }
812 break;
813 }
814 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
815 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
816 default : ShouldNotReachHere();
817 }
818 return store_offset;
819 }
820
821
822 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
823 int load_offset;
824 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
825 assert(base != O7, "destroying register");
826 assert(!unaligned, "can't handle this");
827 // for offsets larger than a simm13 we setup the offset in O7
828 __ set(offset, O7);
829 load_offset = load(base, O7, to_reg, type, wide);
830 } else {
831 load_offset = code_offset();
832 switch(type) {
833 case T_BOOLEAN: // fall through
834 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
835 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
836 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
837 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
838 case T_LONG :
839 if (!unaligned && !PatchALot) {
840 __ ldx(base, offset, to_reg->as_register_lo());
841 } else {
842 assert(base != to_reg->as_register_lo(), "can't handle this");
843 assert(O7 != to_reg->as_register_lo(), "can't handle this");
844 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
845 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
846 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
847 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
848 }
849 break;
850 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
851 case T_ADDRESS:
852 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
853 __ lduw(base, offset, to_reg->as_register());
854 __ decode_klass_not_null(to_reg->as_register());
855 } else
856 {
857 __ ld_ptr(base, offset, to_reg->as_register());
858 }
859 break;
860 case T_ARRAY : // fall through
861 case T_OBJECT:
862 {
863 if (UseCompressedOops && !wide) {
864 __ lduw(base, offset, to_reg->as_register());
865 __ decode_heap_oop(to_reg->as_register());
866 } else {
867 __ ld_ptr(base, offset, to_reg->as_register());
868 }
869 break;
870 }
871 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
872 case T_DOUBLE:
873 {
874 FloatRegister reg = to_reg->as_double_reg();
875 // split unaligned loads
876 if (unaligned || PatchALot) {
877 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
878 __ ldf(FloatRegisterImpl::S, base, offset, reg);
879 } else {
880 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
881 }
882 break;
883 }
884 default : ShouldNotReachHere();
885 }
886 if (type == T_ARRAY || type == T_OBJECT) {
887 __ verify_oop(to_reg->as_register());
888 }
889 }
890 return load_offset;
891 }
892
893
894 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
895 int load_offset = code_offset();
896 switch(type) {
897 case T_BOOLEAN: // fall through
898 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
899 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
900 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
901 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
902 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
903 case T_ARRAY : // fall through
904 case T_OBJECT:
905 {
906 if (UseCompressedOops && !wide) {
907 __ lduw(base, disp, to_reg->as_register());
908 __ decode_heap_oop(to_reg->as_register());
909 } else {
910 __ ld_ptr(base, disp, to_reg->as_register());
911 }
912 break;
913 }
914 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
915 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
916 case T_LONG :
917 __ ldx(base, disp, to_reg->as_register_lo());
918 break;
919 default : ShouldNotReachHere();
920 }
921 if (type == T_ARRAY || type == T_OBJECT) {
922 __ verify_oop(to_reg->as_register());
923 }
924 return load_offset;
925 }
926
927 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
928 LIR_Const* c = src->as_constant_ptr();
929 switch (c->type()) {
930 case T_INT:
931 case T_FLOAT: {
932 Register src_reg = O7;
933 int value = c->as_jint_bits();
934 if (value == 0) {
935 src_reg = G0;
936 } else {
937 __ set(value, O7);
938 }
939 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
940 __ stw(src_reg, addr.base(), addr.disp());
941 break;
942 }
943 case T_ADDRESS: {
944 Register src_reg = O7;
945 int value = c->as_jint_bits();
946 if (value == 0) {
947 src_reg = G0;
948 } else {
949 __ set(value, O7);
950 }
951 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
952 __ st_ptr(src_reg, addr.base(), addr.disp());
953 break;
954 }
955 case T_OBJECT: {
956 Register src_reg = O7;
957 jobject2reg(c->as_jobject(), src_reg);
958 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
959 __ st_ptr(src_reg, addr.base(), addr.disp());
960 break;
961 }
962 case T_LONG:
963 case T_DOUBLE: {
964 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
965
966 Register tmp = O7;
967 int value_lo = c->as_jint_lo_bits();
968 if (value_lo == 0) {
969 tmp = G0;
970 } else {
971 __ set(value_lo, O7);
972 }
973 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
974 int value_hi = c->as_jint_hi_bits();
975 if (value_hi == 0) {
976 tmp = G0;
977 } else {
978 __ set(value_hi, O7);
979 }
980 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
981 break;
982 }
983 default:
984 Unimplemented();
985 }
986 }
987
988
989 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
990 LIR_Const* c = src->as_constant_ptr();
991 LIR_Address* addr = dest->as_address_ptr();
992 Register base = addr->base()->as_pointer_register();
993 int offset = -1;
994
995 switch (c->type()) {
996 case T_FLOAT: type = T_INT; // Float constants are stored by int store instructions.
997 case T_INT:
998 case T_ADDRESS: {
999 LIR_Opr tmp = FrameMap::O7_opr;
1000 int value = c->as_jint_bits();
1001 if (value == 0) {
1002 tmp = FrameMap::G0_opr;
1003 } else if (Assembler::is_simm13(value)) {
1004 __ set(value, O7);
1005 }
1006 if (addr->index()->is_valid()) {
1007 assert(addr->disp() == 0, "must be zero");
1008 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1009 } else {
1010 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1011 offset = store(tmp, base, addr->disp(), type, wide, false);
1012 }
1013 break;
1014 }
1015 case T_LONG:
1016 case T_DOUBLE: {
1017 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1018 assert(Assembler::is_simm13(addr->disp()) &&
1019 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1020
1021 LIR_Opr tmp = FrameMap::O7_opr;
1022 int value_lo = c->as_jint_lo_bits();
1023 if (value_lo == 0) {
1024 tmp = FrameMap::G0_opr;
1025 } else {
1026 __ set(value_lo, O7);
1027 }
1028 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1029 int value_hi = c->as_jint_hi_bits();
1030 if (value_hi == 0) {
1031 tmp = FrameMap::G0_opr;
1032 } else {
1033 __ set(value_hi, O7);
1034 }
1035 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1036 break;
1037 }
1038 case T_OBJECT: {
1039 jobject obj = c->as_jobject();
1040 LIR_Opr tmp;
1041 if (obj == NULL) {
1042 tmp = FrameMap::G0_opr;
1043 } else {
1044 tmp = FrameMap::O7_opr;
1045 jobject2reg(c->as_jobject(), O7);
1046 }
1047 // handle either reg+reg or reg+disp address
1048 if (addr->index()->is_valid()) {
1049 assert(addr->disp() == 0, "must be zero");
1050 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1051 } else {
1052 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1053 offset = store(tmp, base, addr->disp(), type, wide, false);
1054 }
1055
1056 break;
1057 }
1058 default:
1059 Unimplemented();
1060 }
1061 if (info != NULL) {
1062 assert(offset != -1, "offset should've been set");
1063 add_debug_info_for_null_check(offset, info);
1064 }
1065 }
1066
1067
1068 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1069 LIR_Const* c = src->as_constant_ptr();
1070 LIR_Opr to_reg = dest;
1071
1072 switch (c->type()) {
1073 case T_INT:
1074 case T_ADDRESS:
1075 {
1076 jint con = c->as_jint();
1077 if (to_reg->is_single_cpu()) {
1078 assert(patch_code == lir_patch_none, "no patching handled here");
1079 __ set(con, to_reg->as_register());
1080 } else {
1081 ShouldNotReachHere();
1082 assert(to_reg->is_single_fpu(), "wrong register kind");
1083
1084 __ set(con, O7);
1085 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1086 __ st(O7, temp_slot);
1087 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1088 }
1089 }
1090 break;
1091
1092 case T_LONG:
1093 {
1094 jlong con = c->as_jlong();
1095
1096 if (to_reg->is_double_cpu()) {
1097 __ set(con, to_reg->as_register_lo());
1098 } else if (to_reg->is_single_cpu()) {
1099 __ set(con, to_reg->as_register());
1100 } else {
1101 ShouldNotReachHere();
1102 assert(to_reg->is_double_fpu(), "wrong register kind");
1103 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1104 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1105 __ set(low(con), O7);
1106 __ st(O7, temp_slot_lo);
1107 __ set(high(con), O7);
1108 __ st(O7, temp_slot_hi);
1109 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1110 }
1111 }
1112 break;
1113
1114 case T_OBJECT:
1115 {
1116 if (patch_code == lir_patch_none) {
1117 jobject2reg(c->as_jobject(), to_reg->as_register());
1118 } else {
1119 jobject2reg_with_patching(to_reg->as_register(), info);
1120 }
1121 }
1122 break;
1123
1124 case T_METADATA:
1125 {
1126 if (patch_code == lir_patch_none) {
1127 metadata2reg(c->as_metadata(), to_reg->as_register());
1128 } else {
1129 klass2reg_with_patching(to_reg->as_register(), info);
1130 }
1131 }
1132 break;
1133
1134 case T_FLOAT:
1135 {
1136 address const_addr = __ float_constant(c->as_jfloat());
1137 if (const_addr == NULL) {
1138 bailout("const section overflow");
1139 break;
1140 }
1141 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1142 AddressLiteral const_addrlit(const_addr, rspec);
1143 if (to_reg->is_single_fpu()) {
1144 __ patchable_sethi(const_addrlit, O7);
1145 __ relocate(rspec);
1146 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1147
1148 } else {
1149 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1150
1151 __ set(const_addrlit, O7);
1152 __ ld(O7, 0, to_reg->as_register());
1153 }
1154 }
1155 break;
1156
1157 case T_DOUBLE:
1158 {
1159 address const_addr = __ double_constant(c->as_jdouble());
1160 if (const_addr == NULL) {
1161 bailout("const section overflow");
1162 break;
1163 }
1164 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1165
1166 if (to_reg->is_double_fpu()) {
1167 AddressLiteral const_addrlit(const_addr, rspec);
1168 __ patchable_sethi(const_addrlit, O7);
1169 __ relocate(rspec);
1170 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1171 } else {
1172 assert(to_reg->is_double_cpu(), "Must be a long register.");
1173 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1174 }
1175
1176 }
1177 break;
1178
1179 default:
1180 ShouldNotReachHere();
1181 }
1182 }
1183
1184 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1185 Register reg = addr->base()->as_pointer_register();
1186 LIR_Opr index = addr->index();
1187 if (index->is_illegal()) {
1188 return Address(reg, addr->disp());
1189 } else {
1190 assert (addr->disp() == 0, "unsupported address mode");
1191 return Address(reg, index->as_pointer_register());
1192 }
1193 }
1194
1195
1196 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1197 switch (type) {
1198 case T_INT:
1199 case T_FLOAT: {
1200 Register tmp = O7;
1201 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1202 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1203 __ lduw(from.base(), from.disp(), tmp);
1204 __ stw(tmp, to.base(), to.disp());
1205 break;
1206 }
1207 case T_ADDRESS:
1208 case T_OBJECT: {
1209 Register tmp = O7;
1210 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1211 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1212 __ ld_ptr(from.base(), from.disp(), tmp);
1213 __ st_ptr(tmp, to.base(), to.disp());
1214 break;
1215 }
1216 case T_LONG:
1217 case T_DOUBLE: {
1218 Register tmp = O7;
1219 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1220 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1221 __ lduw(from.base(), from.disp(), tmp);
1222 __ stw(tmp, to.base(), to.disp());
1223 __ lduw(from.base(), from.disp() + 4, tmp);
1224 __ stw(tmp, to.base(), to.disp() + 4);
1225 break;
1226 }
1227
1228 default:
1229 ShouldNotReachHere();
1230 }
1231 }
1232
1233
1234 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1235 Address base = as_Address(addr);
1236 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1237 }
1238
1239
1240 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1241 Address base = as_Address(addr);
1242 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1243 }
1244
1245
1246 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1247 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1248
1249 assert(type != T_METADATA, "load of metadata ptr not supported");
1250 LIR_Address* addr = src_opr->as_address_ptr();
1251 LIR_Opr to_reg = dest;
1252
1253 Register src = addr->base()->as_pointer_register();
1254 Register disp_reg = noreg;
1255 int disp_value = addr->disp();
1256 bool needs_patching = (patch_code != lir_patch_none);
1257
1258 if (addr->base()->type() == T_OBJECT) {
1259 __ verify_oop(src);
1260 }
1261
1262 PatchingStub* patch = NULL;
1263 if (needs_patching) {
1264 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1265 assert(!to_reg->is_double_cpu() ||
1266 patch_code == lir_patch_none ||
1267 patch_code == lir_patch_normal, "patching doesn't match register");
1268 }
1269
1270 if (addr->index()->is_illegal()) {
1271 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1272 if (needs_patching) {
1273 __ patchable_set(0, O7);
1274 } else {
1275 __ set(disp_value, O7);
1276 }
1277 disp_reg = O7;
1278 }
1279 } else if (unaligned || PatchALot) {
1280 __ add(src, addr->index()->as_pointer_register(), O7);
1281 src = O7;
1282 } else {
1283 disp_reg = addr->index()->as_pointer_register();
1284 assert(disp_value == 0, "can't handle 3 operand addresses");
1285 }
1286
1287 // remember the offset of the load. The patching_epilog must be done
1288 // before the call to add_debug_info, otherwise the PcDescs don't get
1289 // entered in increasing order.
1290 int offset = code_offset();
1291
1292 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1293 if (disp_reg == noreg) {
1294 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1295 } else {
1296 assert(!unaligned, "can't handle this");
1297 offset = load(src, disp_reg, to_reg, type, wide);
1298 }
1299
1300 if (patch != NULL) {
1301 patching_epilog(patch, patch_code, src, info);
1302 }
1303 if (info != NULL) add_debug_info_for_null_check(offset, info);
1304 }
1305
1306
1307 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1308 Address addr;
1309 if (src->is_single_word()) {
1310 addr = frame_map()->address_for_slot(src->single_stack_ix());
1311 } else if (src->is_double_word()) {
1312 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1313 }
1314
1315 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1316 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1317 }
1318
1319
1320 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1321 Address addr;
1322 if (dest->is_single_word()) {
1323 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1324 } else if (dest->is_double_word()) {
1325 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1326 }
1327 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1328 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1329 }
1330
1331
1332 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1333 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1334 if (from_reg->is_double_fpu()) {
1335 // double to double moves
1336 assert(to_reg->is_double_fpu(), "should match");
1337 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1338 } else {
1339 // float to float moves
1340 assert(to_reg->is_single_fpu(), "should match");
1341 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1342 }
1343 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1344 if (from_reg->is_double_cpu()) {
1345 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1346 } else if (to_reg->is_double_cpu()) {
1347 // int to int moves
1348 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1349 } else {
1350 // int to int moves
1351 __ mov(from_reg->as_register(), to_reg->as_register());
1352 }
1353 } else {
1354 ShouldNotReachHere();
1355 }
1356 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1357 __ verify_oop(to_reg->as_register());
1358 }
1359 }
1360
1361 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1362 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1363 bool wide, bool unaligned) {
1364 assert(type != T_METADATA, "store of metadata ptr not supported");
1365 LIR_Address* addr = dest->as_address_ptr();
1366
1367 Register src = addr->base()->as_pointer_register();
1368 Register disp_reg = noreg;
1369 int disp_value = addr->disp();
1370 bool needs_patching = (patch_code != lir_patch_none);
1371
1372 if (addr->base()->is_oop_register()) {
1373 __ verify_oop(src);
1374 }
1375
1376 PatchingStub* patch = NULL;
1377 if (needs_patching) {
1378 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1379 assert(!from_reg->is_double_cpu() ||
1380 patch_code == lir_patch_none ||
1381 patch_code == lir_patch_normal, "patching doesn't match register");
1382 }
1383
1384 if (addr->index()->is_illegal()) {
1385 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1386 if (needs_patching) {
1387 __ patchable_set(0, O7);
1388 } else {
1389 __ set(disp_value, O7);
1390 }
1391 disp_reg = O7;
1392 }
1393 } else if (unaligned || PatchALot) {
1394 __ add(src, addr->index()->as_pointer_register(), O7);
1395 src = O7;
1396 } else {
1397 disp_reg = addr->index()->as_pointer_register();
1398 assert(disp_value == 0, "can't handle 3 operand addresses");
1399 }
1400
1401 // remember the offset of the store. The patching_epilog must be done
1402 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1403 // entered in increasing order.
1404 int offset;
1405
1406 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1407 if (disp_reg == noreg) {
1408 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1409 } else {
1410 assert(!unaligned, "can't handle this");
1411 offset = store(from_reg, src, disp_reg, type, wide);
1412 }
1413
1414 if (patch != NULL) {
1415 patching_epilog(patch, patch_code, src, info);
1416 }
1417
1418 if (info != NULL) add_debug_info_for_null_check(offset, info);
1419 }
1420
1421
1422 void LIR_Assembler::return_op(LIR_Opr result) {
1423 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1424 __ reserved_stack_check();
1425 }
1426 if (SafepointMechanism::uses_thread_local_poll()) {
1427 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0);
1428 } else {
1429 __ set((intptr_t)os::get_polling_page(), L0);
1430 }
1431 __ relocate(relocInfo::poll_return_type);
1432 __ ld_ptr(L0, 0, G0);
1433 __ ret();
1434 __ delayed()->restore();
1435 }
1436
1437
1438 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1439 if (SafepointMechanism::uses_thread_local_poll()) {
1440 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), tmp->as_register());
1441 } else {
1442 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1443 }
1444 if (info != NULL) {
1445 add_debug_info_for_branch(info);
1446 }
1447 int offset = __ offset();
1448
1449 __ relocate(relocInfo::poll_type);
1450 __ ld_ptr(tmp->as_register(), 0, G0);
1451 return offset;
1452 }
1453
1454
1455 void LIR_Assembler::emit_static_call_stub() {
1456 address call_pc = __ pc();
1457 address stub = __ start_a_stub(call_stub_size());
1458 if (stub == NULL) {
1459 bailout("static call stub overflow");
1460 return;
1461 }
1462
1463 int start = __ offset();
1464 __ relocate(static_stub_Relocation::spec(call_pc));
1465
1466 __ set_metadata(NULL, G5);
1467 // must be set to -1 at code generation time
1468 AddressLiteral addrlit(-1);
1469 __ jump_to(addrlit, G3);
1470 __ delayed()->nop();
1471
1472 assert(__ offset() - start <= call_stub_size(), "stub too big");
1473 __ end_a_stub();
1474 }
1475
1476
1477 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1478 if (opr1->is_single_fpu()) {
1479 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1480 } else if (opr1->is_double_fpu()) {
1481 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1482 } else if (opr1->is_single_cpu()) {
1483 if (opr2->is_constant()) {
1484 switch (opr2->as_constant_ptr()->type()) {
1485 case T_INT:
1486 { jint con = opr2->as_constant_ptr()->as_jint();
1487 if (Assembler::is_simm13(con)) {
1488 __ cmp(opr1->as_register(), con);
1489 } else {
1490 __ set(con, O7);
1491 __ cmp(opr1->as_register(), O7);
1492 }
1493 }
1494 break;
1495
1496 case T_OBJECT:
1497 // there are only equal/notequal comparisions on objects
1498 { jobject con = opr2->as_constant_ptr()->as_jobject();
1499 if (con == NULL) {
1500 __ cmp(opr1->as_register(), 0);
1501 } else {
1502 jobject2reg(con, O7);
1503 __ cmp(opr1->as_register(), O7);
1504 }
1505 }
1506 break;
1507
1508 default:
1509 ShouldNotReachHere();
1510 break;
1511 }
1512 } else {
1513 if (opr2->is_address()) {
1514 LIR_Address * addr = opr2->as_address_ptr();
1515 BasicType type = addr->type();
1516 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1517 else __ ld(as_Address(addr), O7);
1518 __ cmp(opr1->as_register(), O7);
1519 } else {
1520 __ cmp(opr1->as_register(), opr2->as_register());
1521 }
1522 }
1523 } else if (opr1->is_double_cpu()) {
1524 Register xlo = opr1->as_register_lo();
1525 Register xhi = opr1->as_register_hi();
1526 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1527 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1528 __ orcc(xhi, G0, G0);
1529 } else if (opr2->is_register()) {
1530 Register ylo = opr2->as_register_lo();
1531 Register yhi = opr2->as_register_hi();
1532 __ cmp(xlo, ylo);
1533 } else {
1534 ShouldNotReachHere();
1535 }
1536 } else if (opr1->is_address()) {
1537 LIR_Address * addr = opr1->as_address_ptr();
1538 BasicType type = addr->type();
1539 assert (opr2->is_constant(), "Checking");
1540 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1541 else __ ld(as_Address(addr), O7);
1542 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1543 } else {
1544 ShouldNotReachHere();
1545 }
1546 }
1547
1548
1549 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1550 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1551 bool is_unordered_less = (code == lir_ucmp_fd2i);
1552 if (left->is_single_fpu()) {
1553 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1554 } else if (left->is_double_fpu()) {
1555 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1556 } else {
1557 ShouldNotReachHere();
1558 }
1559 } else if (code == lir_cmp_l2i) {
1560 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1561 } else {
1562 ShouldNotReachHere();
1563 }
1564 }
1565
1566
1567 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1568 Assembler::Condition acond;
1569 switch (condition) {
1570 case lir_cond_equal: acond = Assembler::equal; break;
1571 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1572 case lir_cond_less: acond = Assembler::less; break;
1573 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1574 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1575 case lir_cond_greater: acond = Assembler::greater; break;
1576 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1577 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1578 default: ShouldNotReachHere();
1579 };
1580
1581 if (opr1->is_constant() && opr1->type() == T_INT) {
1582 Register dest = result->as_register();
1583 // load up first part of constant before branch
1584 // and do the rest in the delay slot.
1585 if (!Assembler::is_simm13(opr1->as_jint())) {
1586 __ sethi(opr1->as_jint(), dest);
1587 }
1588 } else if (opr1->is_constant()) {
1589 const2reg(opr1, result, lir_patch_none, NULL);
1590 } else if (opr1->is_register()) {
1591 reg2reg(opr1, result);
1592 } else if (opr1->is_stack()) {
1593 stack2reg(opr1, result, result->type());
1594 } else {
1595 ShouldNotReachHere();
1596 }
1597 Label skip;
1598 if (type == T_INT) {
1599 __ br(acond, false, Assembler::pt, skip);
1600 } else {
1601 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1602 }
1603 if (opr1->is_constant() && opr1->type() == T_INT) {
1604 Register dest = result->as_register();
1605 if (Assembler::is_simm13(opr1->as_jint())) {
1606 __ delayed()->or3(G0, opr1->as_jint(), dest);
1607 } else {
1608 // the sethi has been done above, so just put in the low 10 bits
1609 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1610 }
1611 } else {
1612 // can't do anything useful in the delay slot
1613 __ delayed()->nop();
1614 }
1615 if (opr2->is_constant()) {
1616 const2reg(opr2, result, lir_patch_none, NULL);
1617 } else if (opr2->is_register()) {
1618 reg2reg(opr2, result);
1619 } else if (opr2->is_stack()) {
1620 stack2reg(opr2, result, result->type());
1621 } else {
1622 ShouldNotReachHere();
1623 }
1624 __ bind(skip);
1625 }
1626
1627
1628 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1629 assert(info == NULL, "unused on this code path");
1630 assert(left->is_register(), "wrong items state");
1631 assert(dest->is_register(), "wrong items state");
1632
1633 if (right->is_register()) {
1634 if (dest->is_float_kind()) {
1635
1636 FloatRegister lreg, rreg, res;
1637 FloatRegisterImpl::Width w;
1638 if (right->is_single_fpu()) {
1639 w = FloatRegisterImpl::S;
1640 lreg = left->as_float_reg();
1641 rreg = right->as_float_reg();
1642 res = dest->as_float_reg();
1643 } else {
1644 w = FloatRegisterImpl::D;
1645 lreg = left->as_double_reg();
1646 rreg = right->as_double_reg();
1647 res = dest->as_double_reg();
1648 }
1649
1650 switch (code) {
1651 case lir_add: __ fadd(w, lreg, rreg, res); break;
1652 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1653 case lir_mul: // fall through
1654 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1655 case lir_div: // fall through
1656 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1657 default: ShouldNotReachHere();
1658 }
1659
1660 } else if (dest->is_double_cpu()) {
1661 Register dst_lo = dest->as_register_lo();
1662 Register op1_lo = left->as_pointer_register();
1663 Register op2_lo = right->as_pointer_register();
1664
1665 switch (code) {
1666 case lir_add:
1667 __ add(op1_lo, op2_lo, dst_lo);
1668 break;
1669
1670 case lir_sub:
1671 __ sub(op1_lo, op2_lo, dst_lo);
1672 break;
1673
1674 default: ShouldNotReachHere();
1675 }
1676 } else {
1677 assert (right->is_single_cpu(), "Just Checking");
1678
1679 Register lreg = left->as_register();
1680 Register res = dest->as_register();
1681 Register rreg = right->as_register();
1682 switch (code) {
1683 case lir_add: __ add (lreg, rreg, res); break;
1684 case lir_sub: __ sub (lreg, rreg, res); break;
1685 case lir_mul: __ mulx (lreg, rreg, res); break;
1686 default: ShouldNotReachHere();
1687 }
1688 }
1689 } else {
1690 assert (right->is_constant(), "must be constant");
1691
1692 if (dest->is_single_cpu()) {
1693 Register lreg = left->as_register();
1694 Register res = dest->as_register();
1695 int simm13 = right->as_constant_ptr()->as_jint();
1696
1697 switch (code) {
1698 case lir_add: __ add (lreg, simm13, res); break;
1699 case lir_sub: __ sub (lreg, simm13, res); break;
1700 case lir_mul: __ mulx (lreg, simm13, res); break;
1701 default: ShouldNotReachHere();
1702 }
1703 } else {
1704 Register lreg = left->as_pointer_register();
1705 Register res = dest->as_register_lo();
1706 long con = right->as_constant_ptr()->as_jlong();
1707 assert(Assembler::is_simm13(con), "must be simm13");
1708
1709 switch (code) {
1710 case lir_add: __ add (lreg, (int)con, res); break;
1711 case lir_sub: __ sub (lreg, (int)con, res); break;
1712 case lir_mul: __ mulx (lreg, (int)con, res); break;
1713 default: ShouldNotReachHere();
1714 }
1715 }
1716 }
1717 }
1718
1719
1720 void LIR_Assembler::fpop() {
1721 // do nothing
1722 }
1723
1724
1725 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1726 switch (code) {
1727 case lir_tan: {
1728 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1729 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1730 break;
1731 }
1732 case lir_sqrt: {
1733 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1734 FloatRegister src_reg = value->as_double_reg();
1735 FloatRegister dst_reg = dest->as_double_reg();
1736 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1737 break;
1738 }
1739 case lir_abs: {
1740 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1741 FloatRegister src_reg = value->as_double_reg();
1742 FloatRegister dst_reg = dest->as_double_reg();
1743 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1744 break;
1745 }
1746 default: {
1747 ShouldNotReachHere();
1748 break;
1749 }
1750 }
1751 }
1752
1753
1754 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1755 if (right->is_constant()) {
1756 if (dest->is_single_cpu()) {
1757 int simm13 = right->as_constant_ptr()->as_jint();
1758 switch (code) {
1759 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1760 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1761 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1762 default: ShouldNotReachHere();
1763 }
1764 } else {
1765 long c = right->as_constant_ptr()->as_jlong();
1766 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1767 int simm13 = (int)c;
1768 switch (code) {
1769 case lir_logic_and:
1770 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1771 break;
1772
1773 case lir_logic_or:
1774 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1775 break;
1776
1777 case lir_logic_xor:
1778 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1779 break;
1780
1781 default: ShouldNotReachHere();
1782 }
1783 }
1784 } else {
1785 assert(right->is_register(), "right should be in register");
1786
1787 if (dest->is_single_cpu()) {
1788 switch (code) {
1789 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1790 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1791 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1792 default: ShouldNotReachHere();
1793 }
1794 } else {
1795 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1796 left->as_register_lo();
1797 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1798 right->as_register_lo();
1799
1800 switch (code) {
1801 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1802 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1803 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1804 default: ShouldNotReachHere();
1805 }
1806 }
1807 }
1808 }
1809
1810
1811 int LIR_Assembler::shift_amount(BasicType t) {
1812 int elem_size = type2aelembytes(t);
1813 switch (elem_size) {
1814 case 1 : return 0;
1815 case 2 : return 1;
1816 case 4 : return 2;
1817 case 8 : return 3;
1818 }
1819 ShouldNotReachHere();
1820 return -1;
1821 }
1822
1823
1824 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1825 assert(exceptionOop->as_register() == Oexception, "should match");
1826 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1827
1828 info->add_register_oop(exceptionOop);
1829
1830 // reuse the debug info from the safepoint poll for the throw op itself
1831 address pc_for_athrow = __ pc();
1832 int pc_for_athrow_offset = __ offset();
1833 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1834 __ set(pc_for_athrow, Oissuing_pc, rspec);
1835 add_call_info(pc_for_athrow_offset, info); // for exception handler
1836
1837 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1838 __ delayed()->nop();
1839 }
1840
1841
1842 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1843 assert(exceptionOop->as_register() == Oexception, "should match");
1844
1845 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1846 __ delayed()->nop();
1847 }
1848
1849 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1850 Register src = op->src()->as_register();
1851 Register dst = op->dst()->as_register();
1852 Register src_pos = op->src_pos()->as_register();
1853 Register dst_pos = op->dst_pos()->as_register();
1854 Register length = op->length()->as_register();
1855 Register tmp = op->tmp()->as_register();
1856 Register tmp2 = O7;
1857
1858 int flags = op->flags();
1859 ciArrayKlass* default_type = op->expected_type();
1860 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1861 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1862
1863 // higher 32bits must be null
1864 __ sra(dst_pos, 0, dst_pos);
1865 __ sra(src_pos, 0, src_pos);
1866 __ sra(length, 0, length);
1867
1868 // set up the arraycopy stub information
1869 ArrayCopyStub* stub = op->stub();
1870
1871 // always do stub if no type information is available. it's ok if
1872 // the known type isn't loaded since the code sanity checks
1873 // in debug mode and the type isn't required when we know the exact type
1874 // also check that the type is an array type.
1875 if (op->expected_type() == NULL) {
1876 __ mov(src, O0);
1877 __ mov(src_pos, O1);
1878 __ mov(dst, O2);
1879 __ mov(dst_pos, O3);
1880 __ mov(length, O4);
1881 address copyfunc_addr = StubRoutines::generic_arraycopy();
1882
1883 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1884 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1885 } else {
1886 #ifndef PRODUCT
1887 if (PrintC1Statistics) {
1888 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1889 __ inc_counter(counter, G1, G3);
1890 }
1891 #endif
1892 __ call_VM_leaf(tmp, copyfunc_addr);
1893 }
1894
1895 if (copyfunc_addr != NULL) {
1896 __ xor3(O0, -1, tmp);
1897 __ sub(length, tmp, length);
1898 __ add(src_pos, tmp, src_pos);
1899 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1900 __ delayed()->add(dst_pos, tmp, dst_pos);
1901 } else {
1902 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1903 __ delayed()->nop();
1904 }
1905 __ bind(*stub->continuation());
1906 return;
1907 }
1908
1909 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1910
1911 // make sure src and dst are non-null and load array length
1912 if (flags & LIR_OpArrayCopy::src_null_check) {
1913 __ tst(src);
1914 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1915 __ delayed()->nop();
1916 }
1917
1918 if (flags & LIR_OpArrayCopy::dst_null_check) {
1919 __ tst(dst);
1920 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1921 __ delayed()->nop();
1922 }
1923
1924 // If the compiler was not able to prove that exact type of the source or the destination
1925 // of the arraycopy is an array type, check at runtime if the source or the destination is
1926 // an instance type.
1927 if (flags & LIR_OpArrayCopy::type_check) {
1928 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
1929 __ load_klass(dst, tmp);
1930 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1931 __ cmp(tmp2, Klass::_lh_neutral_value);
1932 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1933 __ delayed()->nop();
1934 }
1935
1936 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
1937 __ load_klass(src, tmp);
1938 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1939 __ cmp(tmp2, Klass::_lh_neutral_value);
1940 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1941 __ delayed()->nop();
1942 }
1943 }
1944
1945 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1946 // test src_pos register
1947 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1948 __ delayed()->nop();
1949 }
1950
1951 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1952 // test dst_pos register
1953 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1954 __ delayed()->nop();
1955 }
1956
1957 if (flags & LIR_OpArrayCopy::length_positive_check) {
1958 // make sure length isn't negative
1959 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1960 __ delayed()->nop();
1961 }
1962
1963 if (flags & LIR_OpArrayCopy::src_range_check) {
1964 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1965 __ add(length, src_pos, tmp);
1966 __ cmp(tmp2, tmp);
1967 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1968 __ delayed()->nop();
1969 }
1970
1971 if (flags & LIR_OpArrayCopy::dst_range_check) {
1972 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1973 __ add(length, dst_pos, tmp);
1974 __ cmp(tmp2, tmp);
1975 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1976 __ delayed()->nop();
1977 }
1978
1979 int shift = shift_amount(basic_type);
1980
1981 if (flags & LIR_OpArrayCopy::type_check) {
1982 // We don't know the array types are compatible
1983 if (basic_type != T_OBJECT) {
1984 // Simple test for basic type arrays
1985 if (UseCompressedClassPointers) {
1986 // We don't need decode because we just need to compare
1987 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1988 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1989 __ cmp(tmp, tmp2);
1990 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1991 } else {
1992 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1993 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1994 __ cmp(tmp, tmp2);
1995 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1996 }
1997 __ delayed()->nop();
1998 } else {
1999 // For object arrays, if src is a sub class of dst then we can
2000 // safely do the copy.
2001 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2002
2003 Label cont, slow;
2004 assert_different_registers(tmp, tmp2, G3, G1);
2005
2006 __ load_klass(src, G3);
2007 __ load_klass(dst, G1);
2008
2009 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2010
2011 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2012 __ delayed()->nop();
2013
2014 __ cmp(G3, 0);
2015 if (copyfunc_addr != NULL) { // use stub if available
2016 // src is not a sub class of dst so we have to do a
2017 // per-element check.
2018 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2019 __ delayed()->nop();
2020
2021 __ bind(slow);
2022
2023 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2024 if ((flags & mask) != mask) {
2025 // Check that at least both of them object arrays.
2026 assert(flags & mask, "one of the two should be known to be an object array");
2027
2028 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2029 __ load_klass(src, tmp);
2030 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2031 __ load_klass(dst, tmp);
2032 }
2033 int lh_offset = in_bytes(Klass::layout_helper_offset());
2034
2035 __ lduw(tmp, lh_offset, tmp2);
2036
2037 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2038 __ set(objArray_lh, tmp);
2039 __ cmp(tmp, tmp2);
2040 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2041 __ delayed()->nop();
2042 }
2043
2044 Register src_ptr = O0;
2045 Register dst_ptr = O1;
2046 Register len = O2;
2047 Register chk_off = O3;
2048 Register super_k = O4;
2049
2050 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2051 if (shift == 0) {
2052 __ add(src_ptr, src_pos, src_ptr);
2053 } else {
2054 __ sll(src_pos, shift, tmp);
2055 __ add(src_ptr, tmp, src_ptr);
2056 }
2057
2058 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2059 if (shift == 0) {
2060 __ add(dst_ptr, dst_pos, dst_ptr);
2061 } else {
2062 __ sll(dst_pos, shift, tmp);
2063 __ add(dst_ptr, tmp, dst_ptr);
2064 }
2065 __ mov(length, len);
2066 __ load_klass(dst, tmp);
2067
2068 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2069 __ ld_ptr(tmp, ek_offset, super_k);
2070
2071 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2072 __ lduw(super_k, sco_offset, chk_off);
2073
2074 __ call_VM_leaf(tmp, copyfunc_addr);
2075
2076 #ifndef PRODUCT
2077 if (PrintC1Statistics) {
2078 Label failed;
2079 __ br_notnull_short(O0, Assembler::pn, failed);
2080 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2081 __ bind(failed);
2082 }
2083 #endif
2084
2085 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2086 __ delayed()->xor3(O0, -1, tmp);
2087
2088 #ifndef PRODUCT
2089 if (PrintC1Statistics) {
2090 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2091 }
2092 #endif
2093
2094 __ sub(length, tmp, length);
2095 __ add(src_pos, tmp, src_pos);
2096 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2097 __ delayed()->add(dst_pos, tmp, dst_pos);
2098
2099 __ bind(cont);
2100 } else {
2101 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2102 __ delayed()->nop();
2103 __ bind(cont);
2104 }
2105 }
2106 }
2107
2108 #ifdef ASSERT
2109 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2110 // Sanity check the known type with the incoming class. For the
2111 // primitive case the types must match exactly with src.klass and
2112 // dst.klass each exactly matching the default type. For the
2113 // object array case, if no type check is needed then either the
2114 // dst type is exactly the expected type and the src type is a
2115 // subtype which we can't check or src is the same array as dst
2116 // but not necessarily exactly of type default_type.
2117 Label known_ok, halt;
2118 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2119 if (UseCompressedClassPointers) {
2120 // tmp holds the default type. It currently comes uncompressed after the
2121 // load of a constant, so encode it.
2122 __ encode_klass_not_null(tmp);
2123 // load the raw value of the dst klass, since we will be comparing
2124 // uncompressed values directly.
2125 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2126 if (basic_type != T_OBJECT) {
2127 __ cmp(tmp, tmp2);
2128 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2129 // load the raw value of the src klass.
2130 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2131 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2132 } else {
2133 __ cmp(tmp, tmp2);
2134 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2135 __ delayed()->cmp(src, dst);
2136 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2137 __ delayed()->nop();
2138 }
2139 } else {
2140 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2141 if (basic_type != T_OBJECT) {
2142 __ cmp(tmp, tmp2);
2143 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2144 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2145 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2146 } else {
2147 __ cmp(tmp, tmp2);
2148 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2149 __ delayed()->cmp(src, dst);
2150 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2151 __ delayed()->nop();
2152 }
2153 }
2154 __ bind(halt);
2155 __ stop("incorrect type information in arraycopy");
2156 __ bind(known_ok);
2157 }
2158 #endif
2159
2160 #ifndef PRODUCT
2161 if (PrintC1Statistics) {
2162 address counter = Runtime1::arraycopy_count_address(basic_type);
2163 __ inc_counter(counter, G1, G3);
2164 }
2165 #endif
2166
2167 Register src_ptr = O0;
2168 Register dst_ptr = O1;
2169 Register len = O2;
2170
2171 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2172 if (shift == 0) {
2173 __ add(src_ptr, src_pos, src_ptr);
2174 } else {
2175 __ sll(src_pos, shift, tmp);
2176 __ add(src_ptr, tmp, src_ptr);
2177 }
2178
2179 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2180 if (shift == 0) {
2181 __ add(dst_ptr, dst_pos, dst_ptr);
2182 } else {
2183 __ sll(dst_pos, shift, tmp);
2184 __ add(dst_ptr, tmp, dst_ptr);
2185 }
2186
2187 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2188 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2189 const char *name;
2190 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2191
2192 // arraycopy stubs takes a length in number of elements, so don't scale it.
2193 __ mov(length, len);
2194 __ call_VM_leaf(tmp, entry);
2195
2196 __ bind(*stub->continuation());
2197 }
2198
2199
2200 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2201 if (dest->is_single_cpu()) {
2202 if (left->type() == T_OBJECT) {
2203 switch (code) {
2204 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2205 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2206 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2207 default: ShouldNotReachHere();
2208 }
2209 } else
2210 switch (code) {
2211 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2212 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2213 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2214 default: ShouldNotReachHere();
2215 }
2216 } else {
2217 switch (code) {
2218 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2219 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2220 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2221 default: ShouldNotReachHere();
2222 }
2223 }
2224 }
2225
2226
2227 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2228 if (left->type() == T_OBJECT) {
2229 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2230 Register l = left->as_register();
2231 Register d = dest->as_register_lo();
2232 switch (code) {
2233 case lir_shl: __ sllx (l, count, d); break;
2234 case lir_shr: __ srax (l, count, d); break;
2235 case lir_ushr: __ srlx (l, count, d); break;
2236 default: ShouldNotReachHere();
2237 }
2238 return;
2239 }
2240
2241 if (dest->is_single_cpu()) {
2242 count = count & 0x1F; // Java spec
2243 switch (code) {
2244 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2245 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2246 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2247 default: ShouldNotReachHere();
2248 }
2249 } else if (dest->is_double_cpu()) {
2250 count = count & 63; // Java spec
2251 switch (code) {
2252 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2253 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2254 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2255 default: ShouldNotReachHere();
2256 }
2257 } else {
2258 ShouldNotReachHere();
2259 }
2260 }
2261
2262
2263 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2264 assert(op->tmp1()->as_register() == G1 &&
2265 op->tmp2()->as_register() == G3 &&
2266 op->tmp3()->as_register() == G4 &&
2267 op->obj()->as_register() == O0 &&
2268 op->klass()->as_register() == G5, "must be");
2269 if (op->init_check()) {
2270 add_debug_info_for_null_check_here(op->stub()->info());
2271 __ ldub(op->klass()->as_register(),
2272 in_bytes(InstanceKlass::init_state_offset()),
2273 op->tmp1()->as_register());
2274 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2275 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2276 __ delayed()->nop();
2277 }
2278 __ allocate_object(op->obj()->as_register(),
2279 op->tmp1()->as_register(),
2280 op->tmp2()->as_register(),
2281 op->tmp3()->as_register(),
2282 op->header_size(),
2283 op->object_size(),
2284 op->klass()->as_register(),
2285 *op->stub()->entry());
2286 __ bind(*op->stub()->continuation());
2287 __ verify_oop(op->obj()->as_register());
2288 }
2289
2290
2291 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2292 assert(op->tmp1()->as_register() == G1 &&
2293 op->tmp2()->as_register() == G3 &&
2294 op->tmp3()->as_register() == G4 &&
2295 op->tmp4()->as_register() == O1 &&
2296 op->klass()->as_register() == G5, "must be");
2297
2298 __ signx(op->len()->as_register());
2299 if (UseSlowPath ||
2300 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2301 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2302 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2303 __ delayed()->nop();
2304 } else {
2305 __ allocate_array(op->obj()->as_register(),
2306 op->len()->as_register(),
2307 op->tmp1()->as_register(),
2308 op->tmp2()->as_register(),
2309 op->tmp3()->as_register(),
2310 arrayOopDesc::header_size(op->type()),
2311 type2aelembytes(op->type()),
2312 op->klass()->as_register(),
2313 *op->stub()->entry());
2314 }
2315 __ bind(*op->stub()->continuation());
2316 }
2317
2318
2319 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2320 ciMethodData *md, ciProfileData *data,
2321 Register recv, Register tmp1, Label* update_done) {
2322 uint i;
2323 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2324 Label next_test;
2325 // See if the receiver is receiver[n].
2326 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2327 mdo_offset_bias);
2328 __ ld_ptr(receiver_addr, tmp1);
2329 __ verify_klass_ptr(tmp1);
2330 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2331 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2332 mdo_offset_bias);
2333 __ ld_ptr(data_addr, tmp1);
2334 __ add(tmp1, DataLayout::counter_increment, tmp1);
2335 __ st_ptr(tmp1, data_addr);
2336 __ ba(*update_done);
2337 __ delayed()->nop();
2338 __ bind(next_test);
2339 }
2340
2341 // Didn't find receiver; find next empty slot and fill it in
2342 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2343 Label next_test;
2344 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2345 mdo_offset_bias);
2346 __ ld_ptr(recv_addr, tmp1);
2347 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2348 __ st_ptr(recv, recv_addr);
2349 __ set(DataLayout::counter_increment, tmp1);
2350 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2351 mdo_offset_bias);
2352 __ ba(*update_done);
2353 __ delayed()->nop();
2354 __ bind(next_test);
2355 }
2356 }
2357
2358
2359 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2360 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2361 md = method->method_data_or_null();
2362 assert(md != NULL, "Sanity");
2363 data = md->bci_to_data(bci);
2364 assert(data != NULL, "need data for checkcast");
2365 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2366 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2367 // The offset is large so bias the mdo by the base of the slot so
2368 // that the ld can use simm13s to reference the slots of the data
2369 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2370 }
2371 }
2372
2373 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2374 // we always need a stub for the failure case.
2375 CodeStub* stub = op->stub();
2376 Register obj = op->object()->as_register();
2377 Register k_RInfo = op->tmp1()->as_register();
2378 Register klass_RInfo = op->tmp2()->as_register();
2379 Register dst = op->result_opr()->as_register();
2380 Register Rtmp1 = op->tmp3()->as_register();
2381 ciKlass* k = op->klass();
2382
2383
2384 if (obj == k_RInfo) {
2385 k_RInfo = klass_RInfo;
2386 klass_RInfo = obj;
2387 }
2388
2389 ciMethodData* md;
2390 ciProfileData* data;
2391 int mdo_offset_bias = 0;
2392 if (op->should_profile()) {
2393 ciMethod* method = op->profiled_method();
2394 assert(method != NULL, "Should have method");
2395 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2396
2397 Label not_null;
2398 __ br_notnull_short(obj, Assembler::pn, not_null);
2399 Register mdo = k_RInfo;
2400 Register data_val = Rtmp1;
2401 metadata2reg(md->constant_encoding(), mdo);
2402 if (mdo_offset_bias > 0) {
2403 __ set(mdo_offset_bias, data_val);
2404 __ add(mdo, data_val, mdo);
2405 }
2406 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2407 __ ldub(flags_addr, data_val);
2408 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2409 __ stb(data_val, flags_addr);
2410 __ ba(*obj_is_null);
2411 __ delayed()->nop();
2412 __ bind(not_null);
2413 } else {
2414 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2415 __ delayed()->nop();
2416 }
2417
2418 Label profile_cast_failure, profile_cast_success;
2419 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2420 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2421
2422 // patching may screw with our temporaries on sparc,
2423 // so let's do it before loading the class
2424 if (k->is_loaded()) {
2425 metadata2reg(k->constant_encoding(), k_RInfo);
2426 } else {
2427 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2428 }
2429 assert(obj != k_RInfo, "must be different");
2430
2431 // get object class
2432 // not a safepoint as obj null check happens earlier
2433 __ load_klass(obj, klass_RInfo);
2434 if (op->fast_check()) {
2435 assert_different_registers(klass_RInfo, k_RInfo);
2436 __ cmp(k_RInfo, klass_RInfo);
2437 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2438 __ delayed()->nop();
2439 } else {
2440 bool need_slow_path = true;
2441 if (k->is_loaded()) {
2442 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2443 need_slow_path = false;
2444 // perform the fast part of the checking logic
2445 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2446 (need_slow_path ? success_target : NULL),
2447 failure_target, NULL,
2448 RegisterOrConstant(k->super_check_offset()));
2449 } else {
2450 // perform the fast part of the checking logic
2451 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2452 failure_target, NULL);
2453 }
2454 if (need_slow_path) {
2455 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2456 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2457 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2458 __ delayed()->nop();
2459 __ cmp(G3, 0);
2460 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2461 __ delayed()->nop();
2462 // Fall through to success case
2463 }
2464 }
2465
2466 if (op->should_profile()) {
2467 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2468 assert_different_registers(obj, mdo, recv, tmp1);
2469 __ bind(profile_cast_success);
2470 metadata2reg(md->constant_encoding(), mdo);
2471 if (mdo_offset_bias > 0) {
2472 __ set(mdo_offset_bias, tmp1);
2473 __ add(mdo, tmp1, mdo);
2474 }
2475 __ load_klass(obj, recv);
2476 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2477 // Jump over the failure case
2478 __ ba(*success);
2479 __ delayed()->nop();
2480 // Cast failure case
2481 __ bind(profile_cast_failure);
2482 metadata2reg(md->constant_encoding(), mdo);
2483 if (mdo_offset_bias > 0) {
2484 __ set(mdo_offset_bias, tmp1);
2485 __ add(mdo, tmp1, mdo);
2486 }
2487 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2488 __ ld_ptr(data_addr, tmp1);
2489 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2490 __ st_ptr(tmp1, data_addr);
2491 __ ba(*failure);
2492 __ delayed()->nop();
2493 }
2494 __ ba(*success);
2495 __ delayed()->nop();
2496 }
2497
2498 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2499 LIR_Code code = op->code();
2500 if (code == lir_store_check) {
2501 Register value = op->object()->as_register();
2502 Register array = op->array()->as_register();
2503 Register k_RInfo = op->tmp1()->as_register();
2504 Register klass_RInfo = op->tmp2()->as_register();
2505 Register Rtmp1 = op->tmp3()->as_register();
2506
2507 __ verify_oop(value);
2508 CodeStub* stub = op->stub();
2509 // check if it needs to be profiled
2510 ciMethodData* md;
2511 ciProfileData* data;
2512 int mdo_offset_bias = 0;
2513 if (op->should_profile()) {
2514 ciMethod* method = op->profiled_method();
2515 assert(method != NULL, "Should have method");
2516 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2517 }
2518 Label profile_cast_success, profile_cast_failure, done;
2519 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2520 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2521
2522 if (op->should_profile()) {
2523 Label not_null;
2524 __ br_notnull_short(value, Assembler::pn, not_null);
2525 Register mdo = k_RInfo;
2526 Register data_val = Rtmp1;
2527 metadata2reg(md->constant_encoding(), mdo);
2528 if (mdo_offset_bias > 0) {
2529 __ set(mdo_offset_bias, data_val);
2530 __ add(mdo, data_val, mdo);
2531 }
2532 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2533 __ ldub(flags_addr, data_val);
2534 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2535 __ stb(data_val, flags_addr);
2536 __ ba_short(done);
2537 __ bind(not_null);
2538 } else {
2539 __ br_null_short(value, Assembler::pn, done);
2540 }
2541 add_debug_info_for_null_check_here(op->info_for_exception());
2542 __ load_klass(array, k_RInfo);
2543 __ load_klass(value, klass_RInfo);
2544
2545 // get instance klass
2546 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2547 // perform the fast part of the checking logic
2548 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2549
2550 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2551 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2552 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2553 __ delayed()->nop();
2554 __ cmp(G3, 0);
2555 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2556 __ delayed()->nop();
2557 // fall through to the success case
2558
2559 if (op->should_profile()) {
2560 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2561 assert_different_registers(value, mdo, recv, tmp1);
2562 __ bind(profile_cast_success);
2563 metadata2reg(md->constant_encoding(), mdo);
2564 if (mdo_offset_bias > 0) {
2565 __ set(mdo_offset_bias, tmp1);
2566 __ add(mdo, tmp1, mdo);
2567 }
2568 __ load_klass(value, recv);
2569 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2570 __ ba_short(done);
2571 // Cast failure case
2572 __ bind(profile_cast_failure);
2573 metadata2reg(md->constant_encoding(), mdo);
2574 if (mdo_offset_bias > 0) {
2575 __ set(mdo_offset_bias, tmp1);
2576 __ add(mdo, tmp1, mdo);
2577 }
2578 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2579 __ ld_ptr(data_addr, tmp1);
2580 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2581 __ st_ptr(tmp1, data_addr);
2582 __ ba(*stub->entry());
2583 __ delayed()->nop();
2584 }
2585 __ bind(done);
2586 } else if (code == lir_checkcast) {
2587 Register obj = op->object()->as_register();
2588 Register dst = op->result_opr()->as_register();
2589 Label success;
2590 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2591 __ bind(success);
2592 __ mov(obj, dst);
2593 } else if (code == lir_instanceof) {
2594 Register obj = op->object()->as_register();
2595 Register dst = op->result_opr()->as_register();
2596 Label success, failure, done;
2597 emit_typecheck_helper(op, &success, &failure, &failure);
2598 __ bind(failure);
2599 __ set(0, dst);
2600 __ ba_short(done);
2601 __ bind(success);
2602 __ set(1, dst);
2603 __ bind(done);
2604 } else {
2605 ShouldNotReachHere();
2606 }
2607
2608 }
2609
2610
2611 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2612 if (op->code() == lir_cas_long) {
2613 assert(VM_Version::supports_cx8(), "wrong machine");
2614 Register addr = op->addr()->as_pointer_register();
2615 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2616 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2617 Register new_value_lo = op->new_value()->as_register_lo();
2618 Register new_value_hi = op->new_value()->as_register_hi();
2619 Register t1 = op->tmp1()->as_register();
2620 Register t2 = op->tmp2()->as_register();
2621 __ mov(cmp_value_lo, t1);
2622 __ mov(new_value_lo, t2);
2623 // perform the compare and swap operation
2624 __ casx(addr, t1, t2);
2625 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2626 // overwritten with the original value in "addr" and will be equal to t1.
2627 __ cmp(t1, t2);
2628 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2629 Register addr = op->addr()->as_pointer_register();
2630 Register cmp_value = op->cmp_value()->as_register();
2631 Register new_value = op->new_value()->as_register();
2632 Register t1 = op->tmp1()->as_register();
2633 Register t2 = op->tmp2()->as_register();
2634 __ mov(cmp_value, t1);
2635 __ mov(new_value, t2);
2636 if (op->code() == lir_cas_obj) {
2637 if (UseCompressedOops) {
2638 __ encode_heap_oop(t1);
2639 __ encode_heap_oop(t2);
2640 __ cas(addr, t1, t2);
2641 } else {
2642 __ cas_ptr(addr, t1, t2);
2643 }
2644 } else {
2645 __ cas(addr, t1, t2);
2646 }
2647 __ cmp(t1, t2);
2648 } else {
2649 Unimplemented();
2650 }
2651 }
2652
2653 void LIR_Assembler::set_24bit_FPU() {
2654 Unimplemented();
2655 }
2656
2657
2658 void LIR_Assembler::reset_FPU() {
2659 Unimplemented();
2660 }
2661
2662
2663 void LIR_Assembler::breakpoint() {
2664 __ breakpoint_trap();
2665 }
2666
2667
2668 void LIR_Assembler::push(LIR_Opr opr) {
2669 Unimplemented();
2670 }
2671
2672
2673 void LIR_Assembler::pop(LIR_Opr opr) {
2674 Unimplemented();
2675 }
2676
2677
2678 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2679 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2680 Register dst = dst_opr->as_register();
2681 Register reg = mon_addr.base();
2682 int offset = mon_addr.disp();
2683 // compute pointer to BasicLock
2684 if (mon_addr.is_simm13()) {
2685 __ add(reg, offset, dst);
2686 } else {
2687 __ set(offset, dst);
2688 __ add(dst, reg, dst);
2689 }
2690 }
2691
2692 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2693 assert(op->crc()->is_single_cpu(), "crc must be register");
2694 assert(op->val()->is_single_cpu(), "byte value must be register");
2695 assert(op->result_opr()->is_single_cpu(), "result must be register");
2696 Register crc = op->crc()->as_register();
2697 Register val = op->val()->as_register();
2698 Register table = op->result_opr()->as_register();
2699 Register res = op->result_opr()->as_register();
2700
2701 assert_different_registers(val, crc, table);
2702
2703 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2704 __ not1(crc);
2705 __ clruwu(crc);
2706 __ update_byte_crc32(crc, val, table);
2707 __ not1(crc);
2708
2709 __ mov(crc, res);
2710 }
2711
2712 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2713 Register obj = op->obj_opr()->as_register();
2714 Register hdr = op->hdr_opr()->as_register();
2715 Register lock = op->lock_opr()->as_register();
2716
2717 // obj may not be an oop
2718 if (op->code() == lir_lock) {
2719 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2720 if (UseFastLocking) {
2721 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2722 // add debug info for NullPointerException only if one is possible
2723 if (op->info() != NULL) {
2724 add_debug_info_for_null_check_here(op->info());
2725 }
2726 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2727 } else {
2728 // always do slow locking
2729 // note: the slow locking code could be inlined here, however if we use
2730 // slow locking, speed doesn't matter anyway and this solution is
2731 // simpler and requires less duplicated code - additionally, the
2732 // slow locking code is the same in either case which simplifies
2733 // debugging
2734 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2735 __ delayed()->nop();
2736 }
2737 } else {
2738 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2739 if (UseFastLocking) {
2740 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2741 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2742 } else {
2743 // always do slow unlocking
2744 // note: the slow unlocking code could be inlined here, however if we use
2745 // slow unlocking, speed doesn't matter anyway and this solution is
2746 // simpler and requires less duplicated code - additionally, the
2747 // slow unlocking code is the same in either case which simplifies
2748 // debugging
2749 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2750 __ delayed()->nop();
2751 }
2752 }
2753 __ bind(*op->stub()->continuation());
2754 }
2755
2756
2757 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2758 ciMethod* method = op->profiled_method();
2759 int bci = op->profiled_bci();
2760 ciMethod* callee = op->profiled_callee();
2761
2762 // Update counter for all call types
2763 ciMethodData* md = method->method_data_or_null();
2764 assert(md != NULL, "Sanity");
2765 ciProfileData* data = md->bci_to_data(bci);
2766 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2767 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2768 Register mdo = op->mdo()->as_register();
2769 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2770 Register tmp1 = op->tmp1()->as_register_lo();
2771 metadata2reg(md->constant_encoding(), mdo);
2772 int mdo_offset_bias = 0;
2773 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2774 data->size_in_bytes())) {
2775 // The offset is large so bias the mdo by the base of the slot so
2776 // that the ld can use simm13s to reference the slots of the data
2777 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2778 __ set(mdo_offset_bias, O7);
2779 __ add(mdo, O7, mdo);
2780 }
2781
2782 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2783 // Perform additional virtual call profiling for invokevirtual and
2784 // invokeinterface bytecodes
2785 if (op->should_profile_receiver_type()) {
2786 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2787 Register recv = op->recv()->as_register();
2788 assert_different_registers(mdo, tmp1, recv);
2789 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2790 ciKlass* known_klass = op->known_holder();
2791 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2792 // We know the type that will be seen at this call site; we can
2793 // statically update the MethodData* rather than needing to do
2794 // dynamic tests on the receiver type
2795
2796 // NOTE: we should probably put a lock around this search to
2797 // avoid collisions by concurrent compilations
2798 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2799 uint i;
2800 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2801 ciKlass* receiver = vc_data->receiver(i);
2802 if (known_klass->equals(receiver)) {
2803 Address data_addr(mdo, md->byte_offset_of_slot(data,
2804 VirtualCallData::receiver_count_offset(i)) -
2805 mdo_offset_bias);
2806 __ ld_ptr(data_addr, tmp1);
2807 __ add(tmp1, DataLayout::counter_increment, tmp1);
2808 __ st_ptr(tmp1, data_addr);
2809 return;
2810 }
2811 }
2812
2813 // Receiver type not found in profile data; select an empty slot
2814
2815 // Note that this is less efficient than it should be because it
2816 // always does a write to the receiver part of the
2817 // VirtualCallData rather than just the first time
2818 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2819 ciKlass* receiver = vc_data->receiver(i);
2820 if (receiver == NULL) {
2821 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2822 mdo_offset_bias);
2823 metadata2reg(known_klass->constant_encoding(), tmp1);
2824 __ st_ptr(tmp1, recv_addr);
2825 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2826 mdo_offset_bias);
2827 __ ld_ptr(data_addr, tmp1);
2828 __ add(tmp1, DataLayout::counter_increment, tmp1);
2829 __ st_ptr(tmp1, data_addr);
2830 return;
2831 }
2832 }
2833 } else {
2834 __ load_klass(recv, recv);
2835 Label update_done;
2836 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2837 // Receiver did not match any saved receiver and there is no empty row for it.
2838 // Increment total counter to indicate polymorphic case.
2839 __ ld_ptr(counter_addr, tmp1);
2840 __ add(tmp1, DataLayout::counter_increment, tmp1);
2841 __ st_ptr(tmp1, counter_addr);
2842
2843 __ bind(update_done);
2844 }
2845 } else {
2846 // Static call
2847 __ ld_ptr(counter_addr, tmp1);
2848 __ add(tmp1, DataLayout::counter_increment, tmp1);
2849 __ st_ptr(tmp1, counter_addr);
2850 }
2851 }
2852
2853 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2854 Register obj = op->obj()->as_register();
2855 Register tmp1 = op->tmp()->as_pointer_register();
2856 Register tmp2 = G1;
2857 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2858 ciKlass* exact_klass = op->exact_klass();
2859 intptr_t current_klass = op->current_klass();
2860 bool not_null = op->not_null();
2861 bool no_conflict = op->no_conflict();
2862
2863 Label update, next, none;
2864
2865 bool do_null = !not_null;
2866 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2867 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2868
2869 assert(do_null || do_update, "why are we here?");
2870 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2871
2872 __ verify_oop(obj);
2873
2874 if (tmp1 != obj) {
2875 __ mov(obj, tmp1);
2876 }
2877 if (do_null) {
2878 __ br_notnull_short(tmp1, Assembler::pt, update);
2879 if (!TypeEntries::was_null_seen(current_klass)) {
2880 __ ld_ptr(mdo_addr, tmp1);
2881 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2882 __ st_ptr(tmp1, mdo_addr);
2883 }
2884 if (do_update) {
2885 __ ba(next);
2886 __ delayed()->nop();
2887 }
2888 #ifdef ASSERT
2889 } else {
2890 __ br_notnull_short(tmp1, Assembler::pt, update);
2891 __ stop("unexpect null obj");
2892 #endif
2893 }
2894
2895 __ bind(update);
2896
2897 if (do_update) {
2898 #ifdef ASSERT
2899 if (exact_klass != NULL) {
2900 Label ok;
2901 __ load_klass(tmp1, tmp1);
2902 metadata2reg(exact_klass->constant_encoding(), tmp2);
2903 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
2904 __ stop("exact klass and actual klass differ");
2905 __ bind(ok);
2906 }
2907 #endif
2908
2909 Label do_update;
2910 __ ld_ptr(mdo_addr, tmp2);
2911
2912 if (!no_conflict) {
2913 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2914 if (exact_klass != NULL) {
2915 metadata2reg(exact_klass->constant_encoding(), tmp1);
2916 } else {
2917 __ load_klass(tmp1, tmp1);
2918 }
2919
2920 __ xor3(tmp1, tmp2, tmp1);
2921 __ btst(TypeEntries::type_klass_mask, tmp1);
2922 // klass seen before, nothing to do. The unknown bit may have been
2923 // set already but no need to check.
2924 __ brx(Assembler::zero, false, Assembler::pt, next);
2925 __ delayed()->
2926
2927 btst(TypeEntries::type_unknown, tmp1);
2928 // already unknown. Nothing to do anymore.
2929 __ brx(Assembler::notZero, false, Assembler::pt, next);
2930
2931 if (TypeEntries::is_type_none(current_klass)) {
2932 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2933 __ brx(Assembler::zero, true, Assembler::pt, do_update);
2934 // first time here. Set profile type.
2935 __ delayed()->or3(tmp2, tmp1, tmp2);
2936 } else {
2937 __ delayed()->nop();
2938 }
2939 } else {
2940 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2941 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2942
2943 __ btst(TypeEntries::type_unknown, tmp2);
2944 // already unknown. Nothing to do anymore.
2945 __ brx(Assembler::notZero, false, Assembler::pt, next);
2946 __ delayed()->nop();
2947 }
2948
2949 // different than before. Cannot keep accurate profile.
2950 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
2951 } else {
2952 // There's a single possible klass at this profile point
2953 assert(exact_klass != NULL, "should be");
2954 if (TypeEntries::is_type_none(current_klass)) {
2955 metadata2reg(exact_klass->constant_encoding(), tmp1);
2956 __ xor3(tmp1, tmp2, tmp1);
2957 __ btst(TypeEntries::type_klass_mask, tmp1);
2958 __ brx(Assembler::zero, false, Assembler::pt, next);
2959 #ifdef ASSERT
2960
2961 {
2962 Label ok;
2963 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2964 __ brx(Assembler::zero, true, Assembler::pt, ok);
2965 __ delayed()->nop();
2966
2967 __ stop("unexpected profiling mismatch");
2968 __ bind(ok);
2969 }
2970 // first time here. Set profile type.
2971 __ or3(tmp2, tmp1, tmp2);
2972 #else
2973 // first time here. Set profile type.
2974 __ delayed()->or3(tmp2, tmp1, tmp2);
2975 #endif
2976
2977 } else {
2978 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2979 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2980
2981 // already unknown. Nothing to do anymore.
2982 __ btst(TypeEntries::type_unknown, tmp2);
2983 __ brx(Assembler::notZero, false, Assembler::pt, next);
2984 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
2985 }
2986 }
2987
2988 __ bind(do_update);
2989 __ st_ptr(tmp2, mdo_addr);
2990
2991 __ bind(next);
2992 }
2993 }
2994
2995 void LIR_Assembler::align_backward_branch_target() {
2996 __ align(OptoLoopAlignment);
2997 }
2998
2999
3000 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3001 // make sure we are expecting a delay
3002 // this has the side effect of clearing the delay state
3003 // so we can use _masm instead of _masm->delayed() to do the
3004 // code generation.
3005 __ delayed();
3006
3007 // make sure we only emit one instruction
3008 int offset = code_offset();
3009 op->delay_op()->emit_code(this);
3010 #ifdef ASSERT
3011 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3012 op->delay_op()->print();
3013 }
3014 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3015 "only one instruction can go in a delay slot");
3016 #endif
3017
3018 // we may also be emitting the call info for the instruction
3019 // which we are the delay slot of.
3020 CodeEmitInfo* call_info = op->call_info();
3021 if (call_info) {
3022 add_call_info(code_offset(), call_info);
3023 }
3024
3025 if (VerifyStackAtCalls) {
3026 _masm->sub(FP, SP, O7);
3027 _masm->cmp(O7, initial_frame_size_in_bytes());
3028 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3029 }
3030 }
3031
3032
3033 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3034 assert(left->is_register(), "can only handle registers");
3035
3036 if (left->is_single_cpu()) {
3037 __ neg(left->as_register(), dest->as_register());
3038 } else if (left->is_single_fpu()) {
3039 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3040 } else if (left->is_double_fpu()) {
3041 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3042 } else {
3043 assert (left->is_double_cpu(), "Must be a long");
3044 Register Rlow = left->as_register_lo();
3045 Register Rhi = left->as_register_hi();
3046 __ sub(G0, Rlow, dest->as_register_lo());
3047 }
3048 }
3049
3050
3051 void LIR_Assembler::fxch(int i) {
3052 Unimplemented();
3053 }
3054
3055 void LIR_Assembler::fld(int i) {
3056 Unimplemented();
3057 }
3058
3059 void LIR_Assembler::ffree(int i) {
3060 Unimplemented();
3061 }
3062
3063 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3064 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3065
3066 // if tmp is invalid, then the function being called doesn't destroy the thread
3067 if (tmp->is_valid()) {
3068 __ save_thread(tmp->as_pointer_register());
3069 }
3070 __ call(dest, relocInfo::runtime_call_type);
3071 __ delayed()->nop();
3072 if (info != NULL) {
3073 add_call_info_here(info);
3074 }
3075 if (tmp->is_valid()) {
3076 __ restore_thread(tmp->as_pointer_register());
3077 }
3078
3079 #ifdef ASSERT
3080 __ verify_thread();
3081 #endif // ASSERT
3082 }
3083
3084
3085 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3086 ShouldNotReachHere();
3087
3088 NEEDS_CLEANUP;
3089 if (type == T_LONG) {
3090 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3091
3092 // (extended to allow indexed as well as constant displaced for JSR-166)
3093 Register idx = noreg; // contains either constant offset or index
3094
3095 int disp = mem_addr->disp();
3096 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3097 if (!Assembler::is_simm13(disp)) {
3098 idx = O7;
3099 __ set(disp, idx);
3100 }
3101 } else {
3102 assert(disp == 0, "not both indexed and disp");
3103 idx = mem_addr->index()->as_register();
3104 }
3105
3106 int null_check_offset = -1;
3107
3108 Register base = mem_addr->base()->as_register();
3109 if (src->is_register() && dest->is_address()) {
3110 // G4 is high half, G5 is low half
3111 // clear the top bits of G5, and scale up G4
3112 __ srl (src->as_register_lo(), 0, G5);
3113 __ sllx(src->as_register_hi(), 32, G4);
3114 // combine the two halves into the 64 bits of G4
3115 __ or3(G4, G5, G4);
3116 null_check_offset = __ offset();
3117 if (idx == noreg) {
3118 __ stx(G4, base, disp);
3119 } else {
3120 __ stx(G4, base, idx);
3121 }
3122 } else if (src->is_address() && dest->is_register()) {
3123 null_check_offset = __ offset();
3124 if (idx == noreg) {
3125 __ ldx(base, disp, G5);
3126 } else {
3127 __ ldx(base, idx, G5);
3128 }
3129 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3130 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3131 } else {
3132 Unimplemented();
3133 }
3134 if (info != NULL) {
3135 add_debug_info_for_null_check(null_check_offset, info);
3136 }
3137
3138 } else {
3139 // use normal move for all other volatiles since they don't need
3140 // special handling to remain atomic.
3141 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3142 }
3143 }
3144
3145 void LIR_Assembler::membar() {
3146 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3147 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3148 }
3149
3150 void LIR_Assembler::membar_acquire() {
3151 // no-op on TSO
3152 }
3153
3154 void LIR_Assembler::membar_release() {
3155 // no-op on TSO
3156 }
3157
3158 void LIR_Assembler::membar_loadload() {
3159 // no-op
3160 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3161 }
3162
3163 void LIR_Assembler::membar_storestore() {
3164 // no-op
3165 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3166 }
3167
3168 void LIR_Assembler::membar_loadstore() {
3169 // no-op
3170 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3171 }
3172
3173 void LIR_Assembler::membar_storeload() {
3174 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3175 }
3176
3177 void LIR_Assembler::on_spin_wait() {
3178 Unimplemented();
3179 }
3180
3181 // Pack two sequential registers containing 32 bit values
3182 // into a single 64 bit register.
3183 // src and src->successor() are packed into dst
3184 // src and dst may be the same register.
3185 // Note: src is destroyed
3186 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3187 Register rs = src->as_register();
3188 Register rd = dst->as_register_lo();
3189 __ sllx(rs, 32, rs);
3190 __ srl(rs->successor(), 0, rs->successor());
3191 __ or3(rs, rs->successor(), rd);
3192 }
3193
3194 // Unpack a 64 bit value in a register into
3195 // two sequential registers.
3196 // src is unpacked into dst and dst->successor()
3197 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3198 Register rs = src->as_register_lo();
3199 Register rd = dst->as_register_hi();
3200 assert_different_registers(rs, rd, rd->successor());
3201 __ srlx(rs, 32, rd);
3202 __ srl (rs, 0, rd->successor());
3203 }
3204
3205 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3206 const LIR_Address* addr = addr_opr->as_address_ptr();
3207 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3208 const Register dest_reg = dest->as_pointer_register();
3209 const Register base_reg = addr->base()->as_pointer_register();
3210
3211 if (Assembler::is_simm13(addr->disp())) {
3212 if (addr->index()->is_valid()) {
3213 const Register index_reg = addr->index()->as_pointer_register();
3214 assert(index_reg != G3_scratch, "invariant");
3215 __ add(base_reg, addr->disp(), G3_scratch);
3216 __ add(index_reg, G3_scratch, dest_reg);
3217 } else {
3218 __ add(base_reg, addr->disp(), dest_reg);
3219 }
3220 } else {
3221 __ set(addr->disp(), G3_scratch);
3222 if (addr->index()->is_valid()) {
3223 const Register index_reg = addr->index()->as_pointer_register();
3224 assert(index_reg != G3_scratch, "invariant");
3225 __ add(index_reg, G3_scratch, G3_scratch);
3226 }
3227 __ add(base_reg, G3_scratch, dest_reg);
3228 }
3229 }
3230
3231
3232 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3233 assert(result_reg->is_register(), "check");
3234 __ mov(G2_thread, result_reg->as_register());
3235 }
3236
3237 #ifdef ASSERT
3238 // emit run-time assertion
3239 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3240 assert(op->code() == lir_assert, "must be");
3241
3242 if (op->in_opr1()->is_valid()) {
3243 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3244 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3245 } else {
3246 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3247 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3248 }
3249
3250 Label ok;
3251 if (op->condition() != lir_cond_always) {
3252 Assembler::Condition acond;
3253 switch (op->condition()) {
3254 case lir_cond_equal: acond = Assembler::equal; break;
3255 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3256 case lir_cond_less: acond = Assembler::less; break;
3257 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3258 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3259 case lir_cond_greater: acond = Assembler::greater; break;
3260 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3261 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3262 default: ShouldNotReachHere();
3263 };
3264 __ br(acond, false, Assembler::pt, ok);
3265 __ delayed()->nop();
3266 }
3267 if (op->halt()) {
3268 const char* str = __ code_string(op->msg());
3269 __ stop(str);
3270 } else {
3271 breakpoint();
3272 }
3273 __ bind(ok);
3274 }
3275 #endif
3276
3277 void LIR_Assembler::peephole(LIR_List* lir) {
3278 LIR_OpList* inst = lir->instructions_list();
3279 for (int i = 0; i < inst->length(); i++) {
3280 LIR_Op* op = inst->at(i);
3281 switch (op->code()) {
3282 case lir_cond_float_branch:
3283 case lir_branch: {
3284 LIR_OpBranch* branch = op->as_OpBranch();
3285 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3286 LIR_Op* delay_op = NULL;
3287 // we'd like to be able to pull following instructions into
3288 // this slot but we don't know enough to do it safely yet so
3289 // only optimize block to block control flow.
3290 if (LIRFillDelaySlots && branch->block()) {
3291 LIR_Op* prev = inst->at(i - 1);
3292 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3293 // swap previous instruction into delay slot
3294 inst->at_put(i - 1, op);
3295 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3296 #ifndef PRODUCT
3297 if (LIRTracePeephole) {
3298 tty->print_cr("delayed");
3299 inst->at(i - 1)->print();
3300 inst->at(i)->print();
3301 tty->cr();
3302 }
3303 #endif
3304 continue;
3305 }
3306 }
3307
3308 if (!delay_op) {
3309 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3310 }
3311 inst->insert_before(i + 1, delay_op);
3312 break;
3313 }
3314 case lir_static_call:
3315 case lir_virtual_call:
3316 case lir_icvirtual_call:
3317 case lir_optvirtual_call:
3318 case lir_dynamic_call: {
3319 LIR_Op* prev = inst->at(i - 1);
3320 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3321 (op->code() != lir_virtual_call ||
3322 !prev->result_opr()->is_single_cpu() ||
3323 prev->result_opr()->as_register() != O0) &&
3324 LIR_Assembler::is_single_instruction(prev)) {
3325 // Only moves without info can be put into the delay slot.
3326 // Also don't allow the setup of the receiver in the delay
3327 // slot for vtable calls.
3328 inst->at_put(i - 1, op);
3329 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3330 #ifndef PRODUCT
3331 if (LIRTracePeephole) {
3332 tty->print_cr("delayed");
3333 inst->at(i - 1)->print();
3334 inst->at(i)->print();
3335 tty->cr();
3336 }
3337 #endif
3338 } else {
3339 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3340 inst->insert_before(i + 1, delay_op);
3341 i++;
3342 }
3343 break;
3344 }
3345 }
3346 }
3347 }
3348
3349 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3350 LIR_Address* addr = src->as_address_ptr();
3351
3352 assert(data == dest, "swap uses only 2 operands");
3353 assert (code == lir_xchg, "no xadd on sparc");
3354
3355 if (data->type() == T_INT) {
3356 __ swap(as_Address(addr), data->as_register());
3357 } else if (data->is_oop()) {
3358 Register obj = data->as_register();
3359 Register narrow = tmp->as_register();
3360 assert(UseCompressedOops, "swap is 32bit only");
3361 __ encode_heap_oop(obj, narrow);
3362 __ swap(as_Address(addr), narrow);
3363 __ decode_heap_oop(narrow, obj);
3364 } else {
3365 ShouldNotReachHere();
3366 }
3367 }
3368
3369 #undef __