1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableBarrierSet.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/interfaceSupport.inline.hpp"
40 #include "runtime/jniHandles.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 #define __ _masm->
45
46
47 //------------------------------------------------------------
48
49
50 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
51 if (opr->is_constant()) {
52 LIR_Const* constant = opr->as_constant_ptr();
53 switch (constant->type()) {
54 case T_INT: {
55 jint value = constant->as_jint();
56 return Assembler::is_simm13(value);
57 }
58
59 default:
60 return false;
61 }
62 }
63 return false;
64 }
65
66
67 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
68 switch (op->code()) {
69 case lir_null_check:
70 return true;
71
72
73 case lir_add:
74 case lir_ushr:
75 case lir_shr:
76 case lir_shl:
77 // integer shifts and adds are always one instruction
78 return op->result_opr()->is_single_cpu();
79
80
81 case lir_move: {
82 LIR_Op1* op1 = op->as_Op1();
83 LIR_Opr src = op1->in_opr();
84 LIR_Opr dst = op1->result_opr();
85
86 if (src == dst) {
87 NEEDS_CLEANUP;
88 // this works around a problem where moves with the same src and dst
89 // end up in the delay slot and then the assembler swallows the mov
90 // since it has no effect and then it complains because the delay slot
91 // is empty. returning false stops the optimizer from putting this in
92 // the delay slot
93 return false;
94 }
95
96 // don't put moves involving oops into the delay slot since the VerifyOops code
97 // will make it much larger than a single instruction.
98 if (VerifyOops) {
99 return false;
100 }
101
102 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
103 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
104 return false;
105 }
106
107 if (UseCompressedOops) {
108 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
109 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
110 }
111
112 if (UseCompressedClassPointers) {
113 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
114 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
115 }
116
117 if (dst->is_register()) {
118 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
119 return !PatchALot;
120 } else if (src->is_single_stack()) {
121 return true;
122 }
123 }
124
125 if (src->is_register()) {
126 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
127 return !PatchALot;
128 } else if (dst->is_single_stack()) {
129 return true;
130 }
131 }
132
133 if (dst->is_register() &&
134 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
135 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
136 return true;
137 }
138
139 return false;
140 }
141
142 default:
143 return false;
144 }
145 ShouldNotReachHere();
146 }
147
148
149 LIR_Opr LIR_Assembler::receiverOpr() {
150 return FrameMap::O0_oop_opr;
151 }
152
153
154 LIR_Opr LIR_Assembler::osrBufferPointer() {
155 return FrameMap::I0_opr;
156 }
157
158
159 int LIR_Assembler::initial_frame_size_in_bytes() const {
160 return in_bytes(frame_map()->framesize_in_bytes());
161 }
162
163
164 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
165 // we fetch the class of the receiver (O0) and compare it with the cached class.
166 // If they do not match we jump to slow case.
167 int LIR_Assembler::check_icache() {
168 int offset = __ offset();
169 __ inline_cache_check(O0, G5_inline_cache_reg);
170 return offset;
171 }
172
173
174 void LIR_Assembler::osr_entry() {
175 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
176 //
177 // 1. Create a new compiled activation.
178 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
179 // at the osr_bci; it is not initialized.
180 // 3. Jump to the continuation address in compiled code to resume execution.
181
182 // OSR entry point
183 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
184 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
185 ValueStack* entry_state = osr_entry->end()->state();
186 int number_of_locks = entry_state->locks_size();
187
188 // Create a frame for the compiled activation.
189 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
190
191 // OSR buffer is
192 //
193 // locals[nlocals-1..0]
194 // monitors[number_of_locks-1..0]
195 //
196 // locals is a direct copy of the interpreter frame so in the osr buffer
197 // so first slot in the local array is the last local from the interpreter
198 // and last slot is local[0] (receiver) from the interpreter
199 //
200 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
201 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
202 // in the interpreter frame (the method lock if a sync method)
203
204 // Initialize monitors in the compiled activation.
205 // I0: pointer to osr buffer
206 //
207 // All other registers are dead at this point and the locals will be
208 // copied into place by code emitted in the IR.
209
210 Register OSR_buf = osrBufferPointer()->as_register();
211 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
212 int monitor_offset = BytesPerWord * method()->max_locals() +
213 (2 * BytesPerWord) * (number_of_locks - 1);
214 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
215 // the OSR buffer using 2 word entries: first the lock and then
216 // the oop.
217 for (int i = 0; i < number_of_locks; i++) {
218 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
219 #ifdef ASSERT
220 // verify the interpreter's monitor has a non-null object
221 {
222 Label L;
223 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
224 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
225 __ stop("locked object is NULL");
226 __ bind(L);
227 }
228 #endif // ASSERT
229 // Copy the lock field into the compiled activation.
230 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
231 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
232 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
233 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
234 }
235 }
236 }
237
238
239 // --------------------------------------------------------------------------------------------
240
241 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
242 if (!GenerateSynchronizationCode) return;
243
244 Register obj_reg = obj_opr->as_register();
245 Register lock_reg = lock_opr->as_register();
246
247 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
248 Register reg = mon_addr.base();
249 int offset = mon_addr.disp();
250 // compute pointer to BasicLock
251 if (mon_addr.is_simm13()) {
252 __ add(reg, offset, lock_reg);
253 }
254 else {
255 __ set(offset, lock_reg);
256 __ add(reg, lock_reg, lock_reg);
257 }
258 // unlock object
259 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
260 // _slow_case_stubs->append(slow_case);
261 // temporary fix: must be created after exceptionhandler, therefore as call stub
262 _slow_case_stubs->append(slow_case);
263 if (UseFastLocking) {
264 // try inlined fast unlocking first, revert to slow locking if it fails
265 // note: lock_reg points to the displaced header since the displaced header offset is 0!
266 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
267 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
268 } else {
269 // always do slow unlocking
270 // note: the slow unlocking code could be inlined here, however if we use
271 // slow unlocking, speed doesn't matter anyway and this solution is
272 // simpler and requires less duplicated code - additionally, the
273 // slow unlocking code is the same in either case which simplifies
274 // debugging
275 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
276 __ delayed()->nop();
277 }
278 // done
279 __ bind(*slow_case->continuation());
280 }
281
282
283 int LIR_Assembler::emit_exception_handler() {
284 // if the last instruction is a call (typically to do a throw which
285 // is coming at the end after block reordering) the return address
286 // must still point into the code area in order to avoid assertion
287 // failures when searching for the corresponding bci => add a nop
288 // (was bug 5/14/1999 - gri)
289 __ nop();
290
291 // generate code for exception handler
292 ciMethod* method = compilation()->method();
293
294 address handler_base = __ start_a_stub(exception_handler_size());
295
296 if (handler_base == NULL) {
297 // not enough space left for the handler
298 bailout("exception handler overflow");
299 return -1;
300 }
301
302 int offset = code_offset();
303
304 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
305 __ delayed()->nop();
306 __ should_not_reach_here();
307 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
308 __ end_a_stub();
309
310 return offset;
311 }
312
313
314 // Emit the code to remove the frame from the stack in the exception
315 // unwind path.
316 int LIR_Assembler::emit_unwind_handler() {
317 #ifndef PRODUCT
318 if (CommentedAssembly) {
319 _masm->block_comment("Unwind handler");
320 }
321 #endif
322
323 int offset = code_offset();
324
325 // Fetch the exception from TLS and clear out exception related thread state
326 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
327 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
328 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
329
330 __ bind(_unwind_handler_entry);
331 __ verify_not_null_oop(O0);
332 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
333 __ mov(O0, I0); // Preserve the exception
334 }
335
336 // Preform needed unlocking
337 MonitorExitStub* stub = NULL;
338 if (method()->is_synchronized()) {
339 monitor_address(0, FrameMap::I1_opr);
340 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
341 __ unlock_object(I3, I2, I1, *stub->entry());
342 __ bind(*stub->continuation());
343 }
344
345 if (compilation()->env()->dtrace_method_probes()) {
346 __ mov(G2_thread, O0);
347 __ save_thread(I1); // need to preserve thread in G2 across
348 // runtime call
349 metadata2reg(method()->constant_encoding(), O1);
350 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
351 __ delayed()->nop();
352 __ restore_thread(I1);
353 }
354
355 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
356 __ mov(I0, O0); // Restore the exception
357 }
358
359 // dispatch to the unwind logic
360 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
361 __ delayed()->nop();
362
363 // Emit the slow path assembly
364 if (stub != NULL) {
365 stub->emit_code(this);
366 }
367
368 return offset;
369 }
370
371
372 int LIR_Assembler::emit_deopt_handler() {
373 // if the last instruction is a call (typically to do a throw which
374 // is coming at the end after block reordering) the return address
375 // must still point into the code area in order to avoid assertion
376 // failures when searching for the corresponding bci => add a nop
377 // (was bug 5/14/1999 - gri)
378 __ nop();
379
380 // generate code for deopt handler
381 ciMethod* method = compilation()->method();
382 address handler_base = __ start_a_stub(deopt_handler_size());
383 if (handler_base == NULL) {
384 // not enough space left for the handler
385 bailout("deopt handler overflow");
386 return -1;
387 }
388
389 int offset = code_offset();
390 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
391 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
392 __ delayed()->nop();
393 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
394 __ end_a_stub();
395
396 return offset;
397 }
398
399
400 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
401 if (o == NULL) {
402 __ set(NULL_WORD, reg);
403 } else {
404 #ifdef ASSERT
405 {
406 ThreadInVMfromNative tiv(JavaThread::current());
407 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
408 }
409 #endif
410 int oop_index = __ oop_recorder()->find_index(o);
411 RelocationHolder rspec = oop_Relocation::spec(oop_index);
412 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
413 }
414 }
415
416
417 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
418 // Allocate a new index in table to hold the object once it's been patched
419 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
420 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
421
422 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
423 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
424 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
425 // NULL will be dynamically patched later and the patched value may be large. We must
426 // therefore generate the sethi/add as a placeholders
427 __ patchable_set(addrlit, reg);
428
429 patching_epilog(patch, lir_patch_normal, reg, info);
430 }
431
432
433 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
434 __ set_metadata_constant(o, reg);
435 }
436
437 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
438 // Allocate a new index in table to hold the klass once it's been patched
439 int index = __ oop_recorder()->allocate_metadata_index(NULL);
440 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
441 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
442 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
443 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
444 // NULL will be dynamically patched later and the patched value may be large. We must
445 // therefore generate the sethi/add as a placeholders
446 __ patchable_set(addrlit, reg);
447
448 patching_epilog(patch, lir_patch_normal, reg, info);
449 }
450
451 void LIR_Assembler::emit_op3(LIR_Op3* op) {
452 switch (op->code()) {
453 case lir_idiv:
454 case lir_irem: // Both idiv & irem are handled after the switch (below).
455 break;
456 case lir_fmaf:
457 __ fmadd(FloatRegisterImpl::S,
458 op->in_opr1()->as_float_reg(),
459 op->in_opr2()->as_float_reg(),
460 op->in_opr3()->as_float_reg(),
461 op->result_opr()->as_float_reg());
462 return;
463 case lir_fmad:
464 __ fmadd(FloatRegisterImpl::D,
465 op->in_opr1()->as_double_reg(),
466 op->in_opr2()->as_double_reg(),
467 op->in_opr3()->as_double_reg(),
468 op->result_opr()->as_double_reg());
469 return;
470 default:
471 ShouldNotReachHere();
472 break;
473 }
474
475 // Handle idiv & irem:
476
477 Register Rdividend = op->in_opr1()->as_register();
478 Register Rdivisor = noreg;
479 Register Rscratch = op->in_opr3()->as_register();
480 Register Rresult = op->result_opr()->as_register();
481 int divisor = -1;
482
483 if (op->in_opr2()->is_register()) {
484 Rdivisor = op->in_opr2()->as_register();
485 } else {
486 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
487 assert(Assembler::is_simm13(divisor), "can only handle simm13");
488 }
489
490 assert(Rdividend != Rscratch, "");
491 assert(Rdivisor != Rscratch, "");
492 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
493
494 if (Rdivisor == noreg && is_power_of_2(divisor)) {
495 // convert division by a power of two into some shifts and logical operations
496 if (op->code() == lir_idiv) {
497 if (divisor == 2) {
498 __ srl(Rdividend, 31, Rscratch);
499 } else {
500 __ sra(Rdividend, 31, Rscratch);
501 __ and3(Rscratch, divisor - 1, Rscratch);
502 }
503 __ add(Rdividend, Rscratch, Rscratch);
504 __ sra(Rscratch, log2_intptr(divisor), Rresult);
505 return;
506 } else {
507 if (divisor == 2) {
508 __ srl(Rdividend, 31, Rscratch);
509 } else {
510 __ sra(Rdividend, 31, Rscratch);
511 __ and3(Rscratch, divisor - 1,Rscratch);
512 }
513 __ add(Rdividend, Rscratch, Rscratch);
514 __ andn(Rscratch, divisor - 1,Rscratch);
515 __ sub(Rdividend, Rscratch, Rresult);
516 return;
517 }
518 }
519
520 __ sra(Rdividend, 31, Rscratch);
521 __ wry(Rscratch);
522
523 add_debug_info_for_div0_here(op->info());
524
525 if (Rdivisor != noreg) {
526 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
527 } else {
528 assert(Assembler::is_simm13(divisor), "can only handle simm13");
529 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
530 }
531
532 Label skip;
533 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
534 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
535 __ bind(skip);
536
537 if (op->code() == lir_irem) {
538 if (Rdivisor != noreg) {
539 __ smul(Rscratch, Rdivisor, Rscratch);
540 } else {
541 __ smul(Rscratch, divisor, Rscratch);
542 }
543 __ sub(Rdividend, Rscratch, Rresult);
544 }
545 }
546
547
548 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
549 #ifdef ASSERT
550 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
551 if (op->block() != NULL) _branch_target_blocks.append(op->block());
552 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
553 #endif
554 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
555
556 if (op->cond() == lir_cond_always) {
557 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
558 } else if (op->code() == lir_cond_float_branch) {
559 assert(op->ublock() != NULL, "must have unordered successor");
560 bool is_unordered = (op->ublock() == op->block());
561 Assembler::Condition acond;
562 switch (op->cond()) {
563 case lir_cond_equal: acond = Assembler::f_equal; break;
564 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
565 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
566 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
567 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
568 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
569 default : ShouldNotReachHere();
570 }
571 __ fb( acond, false, Assembler::pn, *(op->label()));
572 } else {
573 assert (op->code() == lir_branch, "just checking");
574
575 Assembler::Condition acond;
576 switch (op->cond()) {
577 case lir_cond_equal: acond = Assembler::equal; break;
578 case lir_cond_notEqual: acond = Assembler::notEqual; break;
579 case lir_cond_less: acond = Assembler::less; break;
580 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
581 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
582 case lir_cond_greater: acond = Assembler::greater; break;
583 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
584 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
585 default: ShouldNotReachHere();
586 };
587
588 // sparc has different condition codes for testing 32-bit
589 // vs. 64-bit values. We could always test xcc is we could
590 // guarantee that 32-bit loads always sign extended but that isn't
591 // true and since sign extension isn't free, it would impose a
592 // slight cost.
593 if (op->type() == T_INT) {
594 __ br(acond, false, Assembler::pn, *(op->label()));
595 } else
596 __ brx(acond, false, Assembler::pn, *(op->label()));
597 }
598 // The peephole pass fills the delay slot
599 }
600
601
602 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
603 Bytecodes::Code code = op->bytecode();
604 LIR_Opr dst = op->result_opr();
605
606 switch(code) {
607 case Bytecodes::_i2l: {
608 Register rlo = dst->as_register_lo();
609 Register rhi = dst->as_register_hi();
610 Register rval = op->in_opr()->as_register();
611 __ sra(rval, 0, rlo);
612 break;
613 }
614 case Bytecodes::_i2d:
615 case Bytecodes::_i2f: {
616 bool is_double = (code == Bytecodes::_i2d);
617 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
618 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
619 FloatRegister rsrc = op->in_opr()->as_float_reg();
620 if (rsrc != rdst) {
621 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
622 }
623 __ fitof(w, rdst, rdst);
624 break;
625 }
626 case Bytecodes::_f2i:{
627 FloatRegister rsrc = op->in_opr()->as_float_reg();
628 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
629 Label L;
630 // result must be 0 if value is NaN; test by comparing value to itself
631 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
632 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
633 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
634 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
635 // move integer result from float register to int register
636 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
637 __ bind (L);
638 break;
639 }
640 case Bytecodes::_l2i: {
641 Register rlo = op->in_opr()->as_register_lo();
642 Register rhi = op->in_opr()->as_register_hi();
643 Register rdst = dst->as_register();
644 __ sra(rlo, 0, rdst);
645 break;
646 }
647 case Bytecodes::_d2f:
648 case Bytecodes::_f2d: {
649 bool is_double = (code == Bytecodes::_f2d);
650 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
651 LIR_Opr val = op->in_opr();
652 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
653 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
654 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
655 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
656 __ ftof(vw, dw, rval, rdst);
657 break;
658 }
659 case Bytecodes::_i2s:
660 case Bytecodes::_i2b: {
661 Register rval = op->in_opr()->as_register();
662 Register rdst = dst->as_register();
663 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
664 __ sll (rval, shift, rdst);
665 __ sra (rdst, shift, rdst);
666 break;
667 }
668 case Bytecodes::_i2c: {
669 Register rval = op->in_opr()->as_register();
670 Register rdst = dst->as_register();
671 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
672 __ sll (rval, shift, rdst);
673 __ srl (rdst, shift, rdst);
674 break;
675 }
676
677 default: ShouldNotReachHere();
678 }
679 }
680
681
682 void LIR_Assembler::align_call(LIR_Code) {
683 // do nothing since all instructions are word aligned on sparc
684 }
685
686
687 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
688 __ call(op->addr(), rtype);
689 // The peephole pass fills the delay slot, add_call_info is done in
690 // LIR_Assembler::emit_delay.
691 }
692
693
694 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
695 __ ic_call(op->addr(), false);
696 // The peephole pass fills the delay slot, add_call_info is done in
697 // LIR_Assembler::emit_delay.
698 }
699
700
701 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
702 add_debug_info_for_null_check_here(op->info());
703 __ load_klass(O0, G3_scratch);
704 if (Assembler::is_simm13(op->vtable_offset())) {
705 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
706 } else {
707 // This will generate 2 instructions
708 __ set(op->vtable_offset(), G5_method);
709 // ld_ptr, set_hi, set
710 __ ld_ptr(G3_scratch, G5_method, G5_method);
711 }
712 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
713 __ callr(G3_scratch, G0);
714 // the peephole pass fills the delay slot
715 }
716
717 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
718 int store_offset;
719 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
720 assert(base != O7, "destroying register");
721 assert(!unaligned, "can't handle this");
722 // for offsets larger than a simm13 we setup the offset in O7
723 __ set(offset, O7);
724 store_offset = store(from_reg, base, O7, type, wide);
725 } else {
726 if (type == T_ARRAY || type == T_OBJECT) {
727 __ verify_oop(from_reg->as_register());
728 }
729 store_offset = code_offset();
730 switch (type) {
731 case T_BOOLEAN: // fall through
732 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
733 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
734 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
735 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
736 case T_LONG :
737 if (unaligned || PatchALot) {
738 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
739 assert(G3_scratch != base, "can't handle this");
740 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
741 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
742 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
743 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
744 } else {
745 __ stx(from_reg->as_register_lo(), base, offset);
746 }
747 break;
748 case T_ADDRESS:
749 case T_METADATA:
750 __ st_ptr(from_reg->as_register(), base, offset);
751 break;
752 case T_ARRAY : // fall through
753 case T_OBJECT:
754 {
755 if (UseCompressedOops && !wide) {
756 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
757 store_offset = code_offset();
758 __ stw(G3_scratch, base, offset);
759 } else {
760 __ st_ptr(from_reg->as_register(), base, offset);
761 }
762 break;
763 }
764
765 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
766 case T_DOUBLE:
767 {
768 FloatRegister reg = from_reg->as_double_reg();
769 // split unaligned stores
770 if (unaligned || PatchALot) {
771 assert(Assembler::is_simm13(offset + 4), "must be");
772 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
773 __ stf(FloatRegisterImpl::S, reg, base, offset);
774 } else {
775 __ stf(FloatRegisterImpl::D, reg, base, offset);
776 }
777 break;
778 }
779 default : ShouldNotReachHere();
780 }
781 }
782 return store_offset;
783 }
784
785
786 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
787 if (type == T_ARRAY || type == T_OBJECT) {
788 __ verify_oop(from_reg->as_register());
789 }
790 int store_offset = code_offset();
791 switch (type) {
792 case T_BOOLEAN: // fall through
793 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
794 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
795 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
796 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
797 case T_LONG :
798 __ stx(from_reg->as_register_lo(), base, disp);
799 break;
800 case T_ADDRESS:
801 __ st_ptr(from_reg->as_register(), base, disp);
802 break;
803 case T_ARRAY : // fall through
804 case T_OBJECT:
805 {
806 if (UseCompressedOops && !wide) {
807 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
808 store_offset = code_offset();
809 __ stw(G3_scratch, base, disp);
810 } else {
811 __ st_ptr(from_reg->as_register(), base, disp);
812 }
813 break;
814 }
815 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
816 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
817 default : ShouldNotReachHere();
818 }
819 return store_offset;
820 }
821
822
823 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
824 int load_offset;
825 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
826 assert(base != O7, "destroying register");
827 assert(!unaligned, "can't handle this");
828 // for offsets larger than a simm13 we setup the offset in O7
829 __ set(offset, O7);
830 load_offset = load(base, O7, to_reg, type, wide);
831 } else {
832 load_offset = code_offset();
833 switch(type) {
834 case T_BOOLEAN: // fall through
835 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
836 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
837 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
838 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
839 case T_LONG :
840 if (!unaligned && !PatchALot) {
841 __ ldx(base, offset, to_reg->as_register_lo());
842 } else {
843 assert(base != to_reg->as_register_lo(), "can't handle this");
844 assert(O7 != to_reg->as_register_lo(), "can't handle this");
845 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
846 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
847 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
848 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
849 }
850 break;
851 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
852 case T_ADDRESS:
853 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
854 __ lduw(base, offset, to_reg->as_register());
855 __ decode_klass_not_null(to_reg->as_register());
856 } else
857 {
858 __ ld_ptr(base, offset, to_reg->as_register());
859 }
860 break;
861 case T_ARRAY : // fall through
862 case T_OBJECT:
863 {
864 if (UseCompressedOops && !wide) {
865 __ lduw(base, offset, to_reg->as_register());
866 __ decode_heap_oop(to_reg->as_register());
867 } else {
868 __ ld_ptr(base, offset, to_reg->as_register());
869 }
870 break;
871 }
872 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
873 case T_DOUBLE:
874 {
875 FloatRegister reg = to_reg->as_double_reg();
876 // split unaligned loads
877 if (unaligned || PatchALot) {
878 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
879 __ ldf(FloatRegisterImpl::S, base, offset, reg);
880 } else {
881 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
882 }
883 break;
884 }
885 default : ShouldNotReachHere();
886 }
887 if (type == T_ARRAY || type == T_OBJECT) {
888 __ verify_oop(to_reg->as_register());
889 }
890 }
891 return load_offset;
892 }
893
894
895 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
896 int load_offset = code_offset();
897 switch(type) {
898 case T_BOOLEAN: // fall through
899 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
900 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
901 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
902 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
903 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
904 case T_ARRAY : // fall through
905 case T_OBJECT:
906 {
907 if (UseCompressedOops && !wide) {
908 __ lduw(base, disp, to_reg->as_register());
909 __ decode_heap_oop(to_reg->as_register());
910 } else {
911 __ ld_ptr(base, disp, to_reg->as_register());
912 }
913 break;
914 }
915 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
916 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
917 case T_LONG :
918 __ ldx(base, disp, to_reg->as_register_lo());
919 break;
920 default : ShouldNotReachHere();
921 }
922 if (type == T_ARRAY || type == T_OBJECT) {
923 __ verify_oop(to_reg->as_register());
924 }
925 return load_offset;
926 }
927
928 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
929 LIR_Const* c = src->as_constant_ptr();
930 switch (c->type()) {
931 case T_INT:
932 case T_FLOAT: {
933 Register src_reg = O7;
934 int value = c->as_jint_bits();
935 if (value == 0) {
936 src_reg = G0;
937 } else {
938 __ set(value, O7);
939 }
940 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
941 __ stw(src_reg, addr.base(), addr.disp());
942 break;
943 }
944 case T_ADDRESS: {
945 Register src_reg = O7;
946 int value = c->as_jint_bits();
947 if (value == 0) {
948 src_reg = G0;
949 } else {
950 __ set(value, O7);
951 }
952 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
953 __ st_ptr(src_reg, addr.base(), addr.disp());
954 break;
955 }
956 case T_OBJECT: {
957 Register src_reg = O7;
958 jobject2reg(c->as_jobject(), src_reg);
959 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
960 __ st_ptr(src_reg, addr.base(), addr.disp());
961 break;
962 }
963 case T_LONG:
964 case T_DOUBLE: {
965 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
966
967 Register tmp = O7;
968 int value_lo = c->as_jint_lo_bits();
969 if (value_lo == 0) {
970 tmp = G0;
971 } else {
972 __ set(value_lo, O7);
973 }
974 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
975 int value_hi = c->as_jint_hi_bits();
976 if (value_hi == 0) {
977 tmp = G0;
978 } else {
979 __ set(value_hi, O7);
980 }
981 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
982 break;
983 }
984 default:
985 Unimplemented();
986 }
987 }
988
989
990 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
991 LIR_Const* c = src->as_constant_ptr();
992 LIR_Address* addr = dest->as_address_ptr();
993 Register base = addr->base()->as_pointer_register();
994 int offset = -1;
995
996 switch (c->type()) {
997 case T_FLOAT: type = T_INT; // Float constants are stored by int store instructions.
998 case T_INT:
999 case T_ADDRESS: {
1000 LIR_Opr tmp = FrameMap::O7_opr;
1001 int value = c->as_jint_bits();
1002 if (value == 0) {
1003 tmp = FrameMap::G0_opr;
1004 } else if (Assembler::is_simm13(value)) {
1005 __ set(value, O7);
1006 }
1007 if (addr->index()->is_valid()) {
1008 assert(addr->disp() == 0, "must be zero");
1009 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1010 } else {
1011 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1012 offset = store(tmp, base, addr->disp(), type, wide, false);
1013 }
1014 break;
1015 }
1016 case T_LONG:
1017 case T_DOUBLE: {
1018 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1019 assert(Assembler::is_simm13(addr->disp()) &&
1020 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1021
1022 LIR_Opr tmp = FrameMap::O7_opr;
1023 int value_lo = c->as_jint_lo_bits();
1024 if (value_lo == 0) {
1025 tmp = FrameMap::G0_opr;
1026 } else {
1027 __ set(value_lo, O7);
1028 }
1029 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1030 int value_hi = c->as_jint_hi_bits();
1031 if (value_hi == 0) {
1032 tmp = FrameMap::G0_opr;
1033 } else {
1034 __ set(value_hi, O7);
1035 }
1036 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1037 break;
1038 }
1039 case T_OBJECT: {
1040 jobject obj = c->as_jobject();
1041 LIR_Opr tmp;
1042 if (obj == NULL) {
1043 tmp = FrameMap::G0_opr;
1044 } else {
1045 tmp = FrameMap::O7_opr;
1046 jobject2reg(c->as_jobject(), O7);
1047 }
1048 // handle either reg+reg or reg+disp address
1049 if (addr->index()->is_valid()) {
1050 assert(addr->disp() == 0, "must be zero");
1051 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1052 } else {
1053 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1054 offset = store(tmp, base, addr->disp(), type, wide, false);
1055 }
1056
1057 break;
1058 }
1059 default:
1060 Unimplemented();
1061 }
1062 if (info != NULL) {
1063 assert(offset != -1, "offset should've been set");
1064 add_debug_info_for_null_check(offset, info);
1065 }
1066 }
1067
1068
1069 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1070 LIR_Const* c = src->as_constant_ptr();
1071 LIR_Opr to_reg = dest;
1072
1073 switch (c->type()) {
1074 case T_INT:
1075 case T_ADDRESS:
1076 {
1077 jint con = c->as_jint();
1078 if (to_reg->is_single_cpu()) {
1079 assert(patch_code == lir_patch_none, "no patching handled here");
1080 __ set(con, to_reg->as_register());
1081 } else {
1082 ShouldNotReachHere();
1083 assert(to_reg->is_single_fpu(), "wrong register kind");
1084
1085 __ set(con, O7);
1086 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1087 __ st(O7, temp_slot);
1088 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1089 }
1090 }
1091 break;
1092
1093 case T_LONG:
1094 {
1095 jlong con = c->as_jlong();
1096
1097 if (to_reg->is_double_cpu()) {
1098 __ set(con, to_reg->as_register_lo());
1099 } else if (to_reg->is_single_cpu()) {
1100 __ set(con, to_reg->as_register());
1101 } else {
1102 ShouldNotReachHere();
1103 assert(to_reg->is_double_fpu(), "wrong register kind");
1104 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1105 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1106 __ set(low(con), O7);
1107 __ st(O7, temp_slot_lo);
1108 __ set(high(con), O7);
1109 __ st(O7, temp_slot_hi);
1110 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1111 }
1112 }
1113 break;
1114
1115 case T_OBJECT:
1116 {
1117 if (patch_code == lir_patch_none) {
1118 jobject2reg(c->as_jobject(), to_reg->as_register());
1119 } else {
1120 jobject2reg_with_patching(to_reg->as_register(), info);
1121 }
1122 }
1123 break;
1124
1125 case T_METADATA:
1126 {
1127 if (patch_code == lir_patch_none) {
1128 metadata2reg(c->as_metadata(), to_reg->as_register());
1129 } else {
1130 klass2reg_with_patching(to_reg->as_register(), info);
1131 }
1132 }
1133 break;
1134
1135 case T_FLOAT:
1136 {
1137 address const_addr = __ float_constant(c->as_jfloat());
1138 if (const_addr == NULL) {
1139 bailout("const section overflow");
1140 break;
1141 }
1142 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1143 AddressLiteral const_addrlit(const_addr, rspec);
1144 if (to_reg->is_single_fpu()) {
1145 __ patchable_sethi(const_addrlit, O7);
1146 __ relocate(rspec);
1147 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1148
1149 } else {
1150 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1151
1152 __ set(const_addrlit, O7);
1153 __ ld(O7, 0, to_reg->as_register());
1154 }
1155 }
1156 break;
1157
1158 case T_DOUBLE:
1159 {
1160 address const_addr = __ double_constant(c->as_jdouble());
1161 if (const_addr == NULL) {
1162 bailout("const section overflow");
1163 break;
1164 }
1165 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1166
1167 if (to_reg->is_double_fpu()) {
1168 AddressLiteral const_addrlit(const_addr, rspec);
1169 __ patchable_sethi(const_addrlit, O7);
1170 __ relocate(rspec);
1171 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1172 } else {
1173 assert(to_reg->is_double_cpu(), "Must be a long register.");
1174 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1175 }
1176
1177 }
1178 break;
1179
1180 default:
1181 ShouldNotReachHere();
1182 }
1183 }
1184
1185 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1186 Register reg = addr->base()->as_pointer_register();
1187 LIR_Opr index = addr->index();
1188 if (index->is_illegal()) {
1189 return Address(reg, addr->disp());
1190 } else {
1191 assert (addr->disp() == 0, "unsupported address mode");
1192 return Address(reg, index->as_pointer_register());
1193 }
1194 }
1195
1196
1197 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1198 switch (type) {
1199 case T_INT:
1200 case T_FLOAT: {
1201 Register tmp = O7;
1202 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1203 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1204 __ lduw(from.base(), from.disp(), tmp);
1205 __ stw(tmp, to.base(), to.disp());
1206 break;
1207 }
1208 case T_ADDRESS:
1209 case T_OBJECT: {
1210 Register tmp = O7;
1211 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1212 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1213 __ ld_ptr(from.base(), from.disp(), tmp);
1214 __ st_ptr(tmp, to.base(), to.disp());
1215 break;
1216 }
1217 case T_LONG:
1218 case T_DOUBLE: {
1219 Register tmp = O7;
1220 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1221 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1222 __ lduw(from.base(), from.disp(), tmp);
1223 __ stw(tmp, to.base(), to.disp());
1224 __ lduw(from.base(), from.disp() + 4, tmp);
1225 __ stw(tmp, to.base(), to.disp() + 4);
1226 break;
1227 }
1228
1229 default:
1230 ShouldNotReachHere();
1231 }
1232 }
1233
1234
1235 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1236 Address base = as_Address(addr);
1237 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1238 }
1239
1240
1241 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1242 Address base = as_Address(addr);
1243 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1244 }
1245
1246
1247 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1248 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1249
1250 assert(type != T_METADATA, "load of metadata ptr not supported");
1251 LIR_Address* addr = src_opr->as_address_ptr();
1252 LIR_Opr to_reg = dest;
1253
1254 Register src = addr->base()->as_pointer_register();
1255 Register disp_reg = noreg;
1256 int disp_value = addr->disp();
1257 bool needs_patching = (patch_code != lir_patch_none);
1258
1259 if (addr->base()->type() == T_OBJECT) {
1260 __ verify_oop(src);
1261 }
1262
1263 PatchingStub* patch = NULL;
1264 if (needs_patching) {
1265 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1266 assert(!to_reg->is_double_cpu() ||
1267 patch_code == lir_patch_none ||
1268 patch_code == lir_patch_normal, "patching doesn't match register");
1269 }
1270
1271 if (addr->index()->is_illegal()) {
1272 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1273 if (needs_patching) {
1274 __ patchable_set(0, O7);
1275 } else {
1276 __ set(disp_value, O7);
1277 }
1278 disp_reg = O7;
1279 }
1280 } else if (unaligned || PatchALot) {
1281 __ add(src, addr->index()->as_pointer_register(), O7);
1282 src = O7;
1283 } else {
1284 disp_reg = addr->index()->as_pointer_register();
1285 assert(disp_value == 0, "can't handle 3 operand addresses");
1286 }
1287
1288 // remember the offset of the load. The patching_epilog must be done
1289 // before the call to add_debug_info, otherwise the PcDescs don't get
1290 // entered in increasing order.
1291 int offset = code_offset();
1292
1293 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1294 if (disp_reg == noreg) {
1295 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1296 } else {
1297 assert(!unaligned, "can't handle this");
1298 offset = load(src, disp_reg, to_reg, type, wide);
1299 }
1300
1301 if (patch != NULL) {
1302 patching_epilog(patch, patch_code, src, info);
1303 }
1304 if (info != NULL) add_debug_info_for_null_check(offset, info);
1305 }
1306
1307
1308 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1309 Address addr;
1310 if (src->is_single_word()) {
1311 addr = frame_map()->address_for_slot(src->single_stack_ix());
1312 } else if (src->is_double_word()) {
1313 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1314 }
1315
1316 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1317 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1318 }
1319
1320
1321 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1322 Address addr;
1323 if (dest->is_single_word()) {
1324 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1325 } else if (dest->is_double_word()) {
1326 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1327 }
1328 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1329 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1330 }
1331
1332
1333 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1334 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1335 if (from_reg->is_double_fpu()) {
1336 // double to double moves
1337 assert(to_reg->is_double_fpu(), "should match");
1338 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1339 } else {
1340 // float to float moves
1341 assert(to_reg->is_single_fpu(), "should match");
1342 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1343 }
1344 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1345 if (from_reg->is_double_cpu()) {
1346 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1347 } else if (to_reg->is_double_cpu()) {
1348 // int to int moves
1349 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1350 } else {
1351 // int to int moves
1352 __ mov(from_reg->as_register(), to_reg->as_register());
1353 }
1354 } else {
1355 ShouldNotReachHere();
1356 }
1357 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1358 __ verify_oop(to_reg->as_register());
1359 }
1360 }
1361
1362 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1363 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1364 bool wide, bool unaligned) {
1365 assert(type != T_METADATA, "store of metadata ptr not supported");
1366 LIR_Address* addr = dest->as_address_ptr();
1367
1368 Register src = addr->base()->as_pointer_register();
1369 Register disp_reg = noreg;
1370 int disp_value = addr->disp();
1371 bool needs_patching = (patch_code != lir_patch_none);
1372
1373 if (addr->base()->is_oop_register()) {
1374 __ verify_oop(src);
1375 }
1376
1377 PatchingStub* patch = NULL;
1378 if (needs_patching) {
1379 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1380 assert(!from_reg->is_double_cpu() ||
1381 patch_code == lir_patch_none ||
1382 patch_code == lir_patch_normal, "patching doesn't match register");
1383 }
1384
1385 if (addr->index()->is_illegal()) {
1386 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1387 if (needs_patching) {
1388 __ patchable_set(0, O7);
1389 } else {
1390 __ set(disp_value, O7);
1391 }
1392 disp_reg = O7;
1393 }
1394 } else if (unaligned || PatchALot) {
1395 __ add(src, addr->index()->as_pointer_register(), O7);
1396 src = O7;
1397 } else {
1398 disp_reg = addr->index()->as_pointer_register();
1399 assert(disp_value == 0, "can't handle 3 operand addresses");
1400 }
1401
1402 // remember the offset of the store. The patching_epilog must be done
1403 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1404 // entered in increasing order.
1405 int offset;
1406
1407 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1408 if (disp_reg == noreg) {
1409 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1410 } else {
1411 assert(!unaligned, "can't handle this");
1412 offset = store(from_reg, src, disp_reg, type, wide);
1413 }
1414
1415 if (patch != NULL) {
1416 patching_epilog(patch, patch_code, src, info);
1417 }
1418
1419 if (info != NULL) add_debug_info_for_null_check(offset, info);
1420 }
1421
1422
1423 void LIR_Assembler::return_op(LIR_Opr result) {
1424 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1425 __ reserved_stack_check();
1426 }
1427 if (SafepointMechanism::uses_thread_local_poll()) {
1428 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0);
1429 } else {
1430 __ set((intptr_t)os::get_polling_page(), L0);
1431 }
1432 __ relocate(relocInfo::poll_return_type);
1433 __ ld_ptr(L0, 0, G0);
1434 __ ret();
1435 __ delayed()->restore();
1436 }
1437
1438
1439 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1440 if (SafepointMechanism::uses_thread_local_poll()) {
1441 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), tmp->as_register());
1442 } else {
1443 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1444 }
1445 if (info != NULL) {
1446 add_debug_info_for_branch(info);
1447 }
1448 int offset = __ offset();
1449
1450 __ relocate(relocInfo::poll_type);
1451 __ ld_ptr(tmp->as_register(), 0, G0);
1452 return offset;
1453 }
1454
1455
1456 void LIR_Assembler::emit_static_call_stub() {
1457 address call_pc = __ pc();
1458 address stub = __ start_a_stub(call_stub_size());
1459 if (stub == NULL) {
1460 bailout("static call stub overflow");
1461 return;
1462 }
1463
1464 int start = __ offset();
1465 __ relocate(static_stub_Relocation::spec(call_pc));
1466
1467 __ set_metadata(NULL, G5);
1468 // must be set to -1 at code generation time
1469 AddressLiteral addrlit(-1);
1470 __ jump_to(addrlit, G3);
1471 __ delayed()->nop();
1472
1473 assert(__ offset() - start <= call_stub_size(), "stub too big");
1474 __ end_a_stub();
1475 }
1476
1477
1478 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1479 if (opr1->is_single_fpu()) {
1480 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1481 } else if (opr1->is_double_fpu()) {
1482 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1483 } else if (opr1->is_single_cpu()) {
1484 if (opr2->is_constant()) {
1485 switch (opr2->as_constant_ptr()->type()) {
1486 case T_INT:
1487 { jint con = opr2->as_constant_ptr()->as_jint();
1488 if (Assembler::is_simm13(con)) {
1489 __ cmp(opr1->as_register(), con);
1490 } else {
1491 __ set(con, O7);
1492 __ cmp(opr1->as_register(), O7);
1493 }
1494 }
1495 break;
1496
1497 case T_OBJECT:
1498 // there are only equal/notequal comparisions on objects
1499 { jobject con = opr2->as_constant_ptr()->as_jobject();
1500 if (con == NULL) {
1501 __ cmp(opr1->as_register(), 0);
1502 } else {
1503 jobject2reg(con, O7);
1504 __ cmp(opr1->as_register(), O7);
1505 }
1506 }
1507 break;
1508
1509 default:
1510 ShouldNotReachHere();
1511 break;
1512 }
1513 } else {
1514 if (opr2->is_address()) {
1515 LIR_Address * addr = opr2->as_address_ptr();
1516 BasicType type = addr->type();
1517 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1518 else __ ld(as_Address(addr), O7);
1519 __ cmp(opr1->as_register(), O7);
1520 } else {
1521 __ cmp(opr1->as_register(), opr2->as_register());
1522 }
1523 }
1524 } else if (opr1->is_double_cpu()) {
1525 Register xlo = opr1->as_register_lo();
1526 Register xhi = opr1->as_register_hi();
1527 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1528 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1529 __ orcc(xhi, G0, G0);
1530 } else if (opr2->is_register()) {
1531 Register ylo = opr2->as_register_lo();
1532 Register yhi = opr2->as_register_hi();
1533 __ cmp(xlo, ylo);
1534 } else {
1535 ShouldNotReachHere();
1536 }
1537 } else if (opr1->is_address()) {
1538 LIR_Address * addr = opr1->as_address_ptr();
1539 BasicType type = addr->type();
1540 assert (opr2->is_constant(), "Checking");
1541 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1542 else __ ld(as_Address(addr), O7);
1543 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1544 } else {
1545 ShouldNotReachHere();
1546 }
1547 }
1548
1549
1550 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1551 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1552 bool is_unordered_less = (code == lir_ucmp_fd2i);
1553 if (left->is_single_fpu()) {
1554 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1555 } else if (left->is_double_fpu()) {
1556 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1557 } else {
1558 ShouldNotReachHere();
1559 }
1560 } else if (code == lir_cmp_l2i) {
1561 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1562 } else {
1563 ShouldNotReachHere();
1564 }
1565 }
1566
1567
1568 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1569 Assembler::Condition acond;
1570 switch (condition) {
1571 case lir_cond_equal: acond = Assembler::equal; break;
1572 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1573 case lir_cond_less: acond = Assembler::less; break;
1574 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1575 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1576 case lir_cond_greater: acond = Assembler::greater; break;
1577 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1578 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1579 default: ShouldNotReachHere();
1580 };
1581
1582 if (opr1->is_constant() && opr1->type() == T_INT) {
1583 Register dest = result->as_register();
1584 // load up first part of constant before branch
1585 // and do the rest in the delay slot.
1586 if (!Assembler::is_simm13(opr1->as_jint())) {
1587 __ sethi(opr1->as_jint(), dest);
1588 }
1589 } else if (opr1->is_constant()) {
1590 const2reg(opr1, result, lir_patch_none, NULL);
1591 } else if (opr1->is_register()) {
1592 reg2reg(opr1, result);
1593 } else if (opr1->is_stack()) {
1594 stack2reg(opr1, result, result->type());
1595 } else {
1596 ShouldNotReachHere();
1597 }
1598 Label skip;
1599 if (type == T_INT) {
1600 __ br(acond, false, Assembler::pt, skip);
1601 } else {
1602 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1603 }
1604 if (opr1->is_constant() && opr1->type() == T_INT) {
1605 Register dest = result->as_register();
1606 if (Assembler::is_simm13(opr1->as_jint())) {
1607 __ delayed()->or3(G0, opr1->as_jint(), dest);
1608 } else {
1609 // the sethi has been done above, so just put in the low 10 bits
1610 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1611 }
1612 } else {
1613 // can't do anything useful in the delay slot
1614 __ delayed()->nop();
1615 }
1616 if (opr2->is_constant()) {
1617 const2reg(opr2, result, lir_patch_none, NULL);
1618 } else if (opr2->is_register()) {
1619 reg2reg(opr2, result);
1620 } else if (opr2->is_stack()) {
1621 stack2reg(opr2, result, result->type());
1622 } else {
1623 ShouldNotReachHere();
1624 }
1625 __ bind(skip);
1626 }
1627
1628
1629 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1630 assert(info == NULL, "unused on this code path");
1631 assert(left->is_register(), "wrong items state");
1632 assert(dest->is_register(), "wrong items state");
1633
1634 if (right->is_register()) {
1635 if (dest->is_float_kind()) {
1636
1637 FloatRegister lreg, rreg, res;
1638 FloatRegisterImpl::Width w;
1639 if (right->is_single_fpu()) {
1640 w = FloatRegisterImpl::S;
1641 lreg = left->as_float_reg();
1642 rreg = right->as_float_reg();
1643 res = dest->as_float_reg();
1644 } else {
1645 w = FloatRegisterImpl::D;
1646 lreg = left->as_double_reg();
1647 rreg = right->as_double_reg();
1648 res = dest->as_double_reg();
1649 }
1650
1651 switch (code) {
1652 case lir_add: __ fadd(w, lreg, rreg, res); break;
1653 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1654 case lir_mul: // fall through
1655 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1656 case lir_div: // fall through
1657 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1658 default: ShouldNotReachHere();
1659 }
1660
1661 } else if (dest->is_double_cpu()) {
1662 Register dst_lo = dest->as_register_lo();
1663 Register op1_lo = left->as_pointer_register();
1664 Register op2_lo = right->as_pointer_register();
1665
1666 switch (code) {
1667 case lir_add:
1668 __ add(op1_lo, op2_lo, dst_lo);
1669 break;
1670
1671 case lir_sub:
1672 __ sub(op1_lo, op2_lo, dst_lo);
1673 break;
1674
1675 default: ShouldNotReachHere();
1676 }
1677 } else {
1678 assert (right->is_single_cpu(), "Just Checking");
1679
1680 Register lreg = left->as_register();
1681 Register res = dest->as_register();
1682 Register rreg = right->as_register();
1683 switch (code) {
1684 case lir_add: __ add (lreg, rreg, res); break;
1685 case lir_sub: __ sub (lreg, rreg, res); break;
1686 case lir_mul: __ mulx (lreg, rreg, res); break;
1687 default: ShouldNotReachHere();
1688 }
1689 }
1690 } else {
1691 assert (right->is_constant(), "must be constant");
1692
1693 if (dest->is_single_cpu()) {
1694 Register lreg = left->as_register();
1695 Register res = dest->as_register();
1696 int simm13 = right->as_constant_ptr()->as_jint();
1697
1698 switch (code) {
1699 case lir_add: __ add (lreg, simm13, res); break;
1700 case lir_sub: __ sub (lreg, simm13, res); break;
1701 case lir_mul: __ mulx (lreg, simm13, res); break;
1702 default: ShouldNotReachHere();
1703 }
1704 } else {
1705 Register lreg = left->as_pointer_register();
1706 Register res = dest->as_register_lo();
1707 long con = right->as_constant_ptr()->as_jlong();
1708 assert(Assembler::is_simm13(con), "must be simm13");
1709
1710 switch (code) {
1711 case lir_add: __ add (lreg, (int)con, res); break;
1712 case lir_sub: __ sub (lreg, (int)con, res); break;
1713 case lir_mul: __ mulx (lreg, (int)con, res); break;
1714 default: ShouldNotReachHere();
1715 }
1716 }
1717 }
1718 }
1719
1720
1721 void LIR_Assembler::fpop() {
1722 // do nothing
1723 }
1724
1725
1726 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1727 switch (code) {
1728 case lir_tan: {
1729 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1730 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1731 break;
1732 }
1733 case lir_sqrt: {
1734 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1735 FloatRegister src_reg = value->as_double_reg();
1736 FloatRegister dst_reg = dest->as_double_reg();
1737 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1738 break;
1739 }
1740 case lir_abs: {
1741 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1742 FloatRegister src_reg = value->as_double_reg();
1743 FloatRegister dst_reg = dest->as_double_reg();
1744 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1745 break;
1746 }
1747 default: {
1748 ShouldNotReachHere();
1749 break;
1750 }
1751 }
1752 }
1753
1754
1755 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1756 if (right->is_constant()) {
1757 if (dest->is_single_cpu()) {
1758 int simm13 = right->as_constant_ptr()->as_jint();
1759 switch (code) {
1760 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1761 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1762 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1763 default: ShouldNotReachHere();
1764 }
1765 } else {
1766 long c = right->as_constant_ptr()->as_jlong();
1767 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1768 int simm13 = (int)c;
1769 switch (code) {
1770 case lir_logic_and:
1771 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1772 break;
1773
1774 case lir_logic_or:
1775 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1776 break;
1777
1778 case lir_logic_xor:
1779 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1780 break;
1781
1782 default: ShouldNotReachHere();
1783 }
1784 }
1785 } else {
1786 assert(right->is_register(), "right should be in register");
1787
1788 if (dest->is_single_cpu()) {
1789 switch (code) {
1790 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1791 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1792 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1793 default: ShouldNotReachHere();
1794 }
1795 } else {
1796 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1797 left->as_register_lo();
1798 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1799 right->as_register_lo();
1800
1801 switch (code) {
1802 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1803 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1804 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1805 default: ShouldNotReachHere();
1806 }
1807 }
1808 }
1809 }
1810
1811
1812 int LIR_Assembler::shift_amount(BasicType t) {
1813 int elem_size = type2aelembytes(t);
1814 switch (elem_size) {
1815 case 1 : return 0;
1816 case 2 : return 1;
1817 case 4 : return 2;
1818 case 8 : return 3;
1819 }
1820 ShouldNotReachHere();
1821 return -1;
1822 }
1823
1824
1825 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1826 assert(exceptionOop->as_register() == Oexception, "should match");
1827 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1828
1829 info->add_register_oop(exceptionOop);
1830
1831 // reuse the debug info from the safepoint poll for the throw op itself
1832 address pc_for_athrow = __ pc();
1833 int pc_for_athrow_offset = __ offset();
1834 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1835 __ set(pc_for_athrow, Oissuing_pc, rspec);
1836 add_call_info(pc_for_athrow_offset, info); // for exception handler
1837
1838 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1839 __ delayed()->nop();
1840 }
1841
1842
1843 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1844 assert(exceptionOop->as_register() == Oexception, "should match");
1845
1846 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1847 __ delayed()->nop();
1848 }
1849
1850 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1851 Register src = op->src()->as_register();
1852 Register dst = op->dst()->as_register();
1853 Register src_pos = op->src_pos()->as_register();
1854 Register dst_pos = op->dst_pos()->as_register();
1855 Register length = op->length()->as_register();
1856 Register tmp = op->tmp()->as_register();
1857 Register tmp2 = O7;
1858
1859 int flags = op->flags();
1860 ciArrayKlass* default_type = op->expected_type();
1861 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1862 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1863
1864 // higher 32bits must be null
1865 __ sra(dst_pos, 0, dst_pos);
1866 __ sra(src_pos, 0, src_pos);
1867 __ sra(length, 0, length);
1868
1869 // set up the arraycopy stub information
1870 ArrayCopyStub* stub = op->stub();
1871
1872 // always do stub if no type information is available. it's ok if
1873 // the known type isn't loaded since the code sanity checks
1874 // in debug mode and the type isn't required when we know the exact type
1875 // also check that the type is an array type.
1876 if (op->expected_type() == NULL) {
1877 __ mov(src, O0);
1878 __ mov(src_pos, O1);
1879 __ mov(dst, O2);
1880 __ mov(dst_pos, O3);
1881 __ mov(length, O4);
1882 address copyfunc_addr = StubRoutines::generic_arraycopy();
1883
1884 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1885 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1886 } else {
1887 #ifndef PRODUCT
1888 if (PrintC1Statistics) {
1889 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1890 __ inc_counter(counter, G1, G3);
1891 }
1892 #endif
1893 __ call_VM_leaf(tmp, copyfunc_addr);
1894 }
1895
1896 if (copyfunc_addr != NULL) {
1897 __ xor3(O0, -1, tmp);
1898 __ sub(length, tmp, length);
1899 __ add(src_pos, tmp, src_pos);
1900 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1901 __ delayed()->add(dst_pos, tmp, dst_pos);
1902 } else {
1903 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1904 __ delayed()->nop();
1905 }
1906 __ bind(*stub->continuation());
1907 return;
1908 }
1909
1910 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1911
1912 // make sure src and dst are non-null and load array length
1913 if (flags & LIR_OpArrayCopy::src_null_check) {
1914 __ tst(src);
1915 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1916 __ delayed()->nop();
1917 }
1918
1919 if (flags & LIR_OpArrayCopy::dst_null_check) {
1920 __ tst(dst);
1921 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1922 __ delayed()->nop();
1923 }
1924
1925 // If the compiler was not able to prove that exact type of the source or the destination
1926 // of the arraycopy is an array type, check at runtime if the source or the destination is
1927 // an instance type.
1928 if (flags & LIR_OpArrayCopy::type_check) {
1929 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
1930 __ load_klass(dst, tmp);
1931 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1932 __ cmp(tmp2, Klass::_lh_neutral_value);
1933 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1934 __ delayed()->nop();
1935 }
1936
1937 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
1938 __ load_klass(src, tmp);
1939 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1940 __ cmp(tmp2, Klass::_lh_neutral_value);
1941 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1942 __ delayed()->nop();
1943 }
1944 }
1945
1946 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1947 // test src_pos register
1948 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1949 __ delayed()->nop();
1950 }
1951
1952 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1953 // test dst_pos register
1954 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1955 __ delayed()->nop();
1956 }
1957
1958 if (flags & LIR_OpArrayCopy::length_positive_check) {
1959 // make sure length isn't negative
1960 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1961 __ delayed()->nop();
1962 }
1963
1964 if (flags & LIR_OpArrayCopy::src_range_check) {
1965 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1966 __ add(length, src_pos, tmp);
1967 __ cmp(tmp2, tmp);
1968 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1969 __ delayed()->nop();
1970 }
1971
1972 if (flags & LIR_OpArrayCopy::dst_range_check) {
1973 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1974 __ add(length, dst_pos, tmp);
1975 __ cmp(tmp2, tmp);
1976 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1977 __ delayed()->nop();
1978 }
1979
1980 int shift = shift_amount(basic_type);
1981
1982 if (flags & LIR_OpArrayCopy::type_check) {
1983 // We don't know the array types are compatible
1984 if (basic_type != T_OBJECT) {
1985 // Simple test for basic type arrays
1986 if (UseCompressedClassPointers) {
1987 // We don't need decode because we just need to compare
1988 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1989 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1990 __ cmp(tmp, tmp2);
1991 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1992 } else {
1993 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1994 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1995 __ cmp(tmp, tmp2);
1996 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1997 }
1998 __ delayed()->nop();
1999 } else {
2000 // For object arrays, if src is a sub class of dst then we can
2001 // safely do the copy.
2002 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2003
2004 Label cont, slow;
2005 assert_different_registers(tmp, tmp2, G3, G1);
2006
2007 __ load_klass(src, G3);
2008 __ load_klass(dst, G1);
2009
2010 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2011
2012 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2013 __ delayed()->nop();
2014
2015 __ cmp(G3, 0);
2016 if (copyfunc_addr != NULL) { // use stub if available
2017 // src is not a sub class of dst so we have to do a
2018 // per-element check.
2019 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2020 __ delayed()->nop();
2021
2022 __ bind(slow);
2023
2024 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2025 if ((flags & mask) != mask) {
2026 // Check that at least both of them object arrays.
2027 assert(flags & mask, "one of the two should be known to be an object array");
2028
2029 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2030 __ load_klass(src, tmp);
2031 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2032 __ load_klass(dst, tmp);
2033 }
2034 int lh_offset = in_bytes(Klass::layout_helper_offset());
2035
2036 __ lduw(tmp, lh_offset, tmp2);
2037
2038 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2039 __ set(objArray_lh, tmp);
2040 __ cmp(tmp, tmp2);
2041 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2042 __ delayed()->nop();
2043 }
2044
2045 Register src_ptr = O0;
2046 Register dst_ptr = O1;
2047 Register len = O2;
2048 Register chk_off = O3;
2049 Register super_k = O4;
2050
2051 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2052 if (shift == 0) {
2053 __ add(src_ptr, src_pos, src_ptr);
2054 } else {
2055 __ sll(src_pos, shift, tmp);
2056 __ add(src_ptr, tmp, src_ptr);
2057 }
2058
2059 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2060 if (shift == 0) {
2061 __ add(dst_ptr, dst_pos, dst_ptr);
2062 } else {
2063 __ sll(dst_pos, shift, tmp);
2064 __ add(dst_ptr, tmp, dst_ptr);
2065 }
2066 __ mov(length, len);
2067 __ load_klass(dst, tmp);
2068
2069 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2070 __ ld_ptr(tmp, ek_offset, super_k);
2071
2072 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2073 __ lduw(super_k, sco_offset, chk_off);
2074
2075 __ call_VM_leaf(tmp, copyfunc_addr);
2076
2077 #ifndef PRODUCT
2078 if (PrintC1Statistics) {
2079 Label failed;
2080 __ br_notnull_short(O0, Assembler::pn, failed);
2081 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2082 __ bind(failed);
2083 }
2084 #endif
2085
2086 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2087 __ delayed()->xor3(O0, -1, tmp);
2088
2089 #ifndef PRODUCT
2090 if (PrintC1Statistics) {
2091 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2092 }
2093 #endif
2094
2095 __ sub(length, tmp, length);
2096 __ add(src_pos, tmp, src_pos);
2097 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2098 __ delayed()->add(dst_pos, tmp, dst_pos);
2099
2100 __ bind(cont);
2101 } else {
2102 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2103 __ delayed()->nop();
2104 __ bind(cont);
2105 }
2106 }
2107 }
2108
2109 #ifdef ASSERT
2110 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2111 // Sanity check the known type with the incoming class. For the
2112 // primitive case the types must match exactly with src.klass and
2113 // dst.klass each exactly matching the default type. For the
2114 // object array case, if no type check is needed then either the
2115 // dst type is exactly the expected type and the src type is a
2116 // subtype which we can't check or src is the same array as dst
2117 // but not necessarily exactly of type default_type.
2118 Label known_ok, halt;
2119 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2120 if (UseCompressedClassPointers) {
2121 // tmp holds the default type. It currently comes uncompressed after the
2122 // load of a constant, so encode it.
2123 __ encode_klass_not_null(tmp);
2124 // load the raw value of the dst klass, since we will be comparing
2125 // uncompressed values directly.
2126 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2127 if (basic_type != T_OBJECT) {
2128 __ cmp(tmp, tmp2);
2129 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2130 // load the raw value of the src klass.
2131 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2132 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2133 } else {
2134 __ cmp(tmp, tmp2);
2135 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2136 __ delayed()->cmp(src, dst);
2137 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2138 __ delayed()->nop();
2139 }
2140 } else {
2141 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2142 if (basic_type != T_OBJECT) {
2143 __ cmp(tmp, tmp2);
2144 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2145 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2146 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2147 } else {
2148 __ cmp(tmp, tmp2);
2149 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2150 __ delayed()->cmp(src, dst);
2151 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2152 __ delayed()->nop();
2153 }
2154 }
2155 __ bind(halt);
2156 __ stop("incorrect type information in arraycopy");
2157 __ bind(known_ok);
2158 }
2159 #endif
2160
2161 #ifndef PRODUCT
2162 if (PrintC1Statistics) {
2163 address counter = Runtime1::arraycopy_count_address(basic_type);
2164 __ inc_counter(counter, G1, G3);
2165 }
2166 #endif
2167
2168 Register src_ptr = O0;
2169 Register dst_ptr = O1;
2170 Register len = O2;
2171
2172 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2173 if (shift == 0) {
2174 __ add(src_ptr, src_pos, src_ptr);
2175 } else {
2176 __ sll(src_pos, shift, tmp);
2177 __ add(src_ptr, tmp, src_ptr);
2178 }
2179
2180 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2181 if (shift == 0) {
2182 __ add(dst_ptr, dst_pos, dst_ptr);
2183 } else {
2184 __ sll(dst_pos, shift, tmp);
2185 __ add(dst_ptr, tmp, dst_ptr);
2186 }
2187
2188 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2189 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2190 const char *name;
2191 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2192
2193 // arraycopy stubs takes a length in number of elements, so don't scale it.
2194 __ mov(length, len);
2195 __ call_VM_leaf(tmp, entry);
2196
2197 __ bind(*stub->continuation());
2198 }
2199
2200
2201 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2202 if (dest->is_single_cpu()) {
2203 if (left->type() == T_OBJECT) {
2204 switch (code) {
2205 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2206 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2207 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2208 default: ShouldNotReachHere();
2209 }
2210 } else
2211 switch (code) {
2212 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2213 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2214 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2215 default: ShouldNotReachHere();
2216 }
2217 } else {
2218 switch (code) {
2219 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2220 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2221 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2222 default: ShouldNotReachHere();
2223 }
2224 }
2225 }
2226
2227
2228 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2229 if (left->type() == T_OBJECT) {
2230 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2231 Register l = left->as_register();
2232 Register d = dest->as_register_lo();
2233 switch (code) {
2234 case lir_shl: __ sllx (l, count, d); break;
2235 case lir_shr: __ srax (l, count, d); break;
2236 case lir_ushr: __ srlx (l, count, d); break;
2237 default: ShouldNotReachHere();
2238 }
2239 return;
2240 }
2241
2242 if (dest->is_single_cpu()) {
2243 count = count & 0x1F; // Java spec
2244 switch (code) {
2245 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2246 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2247 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2248 default: ShouldNotReachHere();
2249 }
2250 } else if (dest->is_double_cpu()) {
2251 count = count & 63; // Java spec
2252 switch (code) {
2253 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2254 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2255 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2256 default: ShouldNotReachHere();
2257 }
2258 } else {
2259 ShouldNotReachHere();
2260 }
2261 }
2262
2263
2264 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2265 assert(op->tmp1()->as_register() == G1 &&
2266 op->tmp2()->as_register() == G3 &&
2267 op->tmp3()->as_register() == G4 &&
2268 op->obj()->as_register() == O0 &&
2269 op->klass()->as_register() == G5, "must be");
2270 if (op->init_check()) {
2271 add_debug_info_for_null_check_here(op->stub()->info());
2272 __ ldub(op->klass()->as_register(),
2273 in_bytes(InstanceKlass::init_state_offset()),
2274 op->tmp1()->as_register());
2275 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2276 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2277 __ delayed()->nop();
2278 }
2279 __ allocate_object(op->obj()->as_register(),
2280 op->tmp1()->as_register(),
2281 op->tmp2()->as_register(),
2282 op->tmp3()->as_register(),
2283 op->header_size(),
2284 op->object_size(),
2285 op->klass()->as_register(),
2286 *op->stub()->entry());
2287 __ bind(*op->stub()->continuation());
2288 __ verify_oop(op->obj()->as_register());
2289 }
2290
2291
2292 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2293 assert(op->tmp1()->as_register() == G1 &&
2294 op->tmp2()->as_register() == G3 &&
2295 op->tmp3()->as_register() == G4 &&
2296 op->tmp4()->as_register() == O1 &&
2297 op->klass()->as_register() == G5, "must be");
2298
2299 __ signx(op->len()->as_register());
2300 if (UseSlowPath ||
2301 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2302 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2303 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2304 __ delayed()->nop();
2305 } else {
2306 __ allocate_array(op->obj()->as_register(),
2307 op->len()->as_register(),
2308 op->tmp1()->as_register(),
2309 op->tmp2()->as_register(),
2310 op->tmp3()->as_register(),
2311 arrayOopDesc::header_size(op->type()),
2312 type2aelembytes(op->type()),
2313 op->klass()->as_register(),
2314 *op->stub()->entry());
2315 }
2316 __ bind(*op->stub()->continuation());
2317 }
2318
2319
2320 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2321 ciMethodData *md, ciProfileData *data,
2322 Register recv, Register tmp1, Label* update_done) {
2323 uint i;
2324 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2325 Label next_test;
2326 // See if the receiver is receiver[n].
2327 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2328 mdo_offset_bias);
2329 __ ld_ptr(receiver_addr, tmp1);
2330 __ verify_klass_ptr(tmp1);
2331 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2332 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2333 mdo_offset_bias);
2334 __ ld_ptr(data_addr, tmp1);
2335 __ add(tmp1, DataLayout::counter_increment, tmp1);
2336 __ st_ptr(tmp1, data_addr);
2337 __ ba(*update_done);
2338 __ delayed()->nop();
2339 __ bind(next_test);
2340 }
2341
2342 // Didn't find receiver; find next empty slot and fill it in
2343 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2344 Label next_test;
2345 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2346 mdo_offset_bias);
2347 __ ld_ptr(recv_addr, tmp1);
2348 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2349 __ st_ptr(recv, recv_addr);
2350 __ set(DataLayout::counter_increment, tmp1);
2351 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2352 mdo_offset_bias);
2353 __ ba(*update_done);
2354 __ delayed()->nop();
2355 __ bind(next_test);
2356 }
2357 }
2358
2359
2360 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2361 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2362 md = method->method_data_or_null();
2363 assert(md != NULL, "Sanity");
2364 data = md->bci_to_data(bci);
2365 assert(data != NULL, "need data for checkcast");
2366 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2367 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2368 // The offset is large so bias the mdo by the base of the slot so
2369 // that the ld can use simm13s to reference the slots of the data
2370 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2371 }
2372 }
2373
2374 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2375 // we always need a stub for the failure case.
2376 CodeStub* stub = op->stub();
2377 Register obj = op->object()->as_register();
2378 Register k_RInfo = op->tmp1()->as_register();
2379 Register klass_RInfo = op->tmp2()->as_register();
2380 Register dst = op->result_opr()->as_register();
2381 Register Rtmp1 = op->tmp3()->as_register();
2382 ciKlass* k = op->klass();
2383
2384
2385 if (obj == k_RInfo) {
2386 k_RInfo = klass_RInfo;
2387 klass_RInfo = obj;
2388 }
2389
2390 ciMethodData* md;
2391 ciProfileData* data;
2392 int mdo_offset_bias = 0;
2393 if (op->should_profile()) {
2394 ciMethod* method = op->profiled_method();
2395 assert(method != NULL, "Should have method");
2396 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2397
2398 Label not_null;
2399 __ br_notnull_short(obj, Assembler::pn, not_null);
2400 Register mdo = k_RInfo;
2401 Register data_val = Rtmp1;
2402 metadata2reg(md->constant_encoding(), mdo);
2403 if (mdo_offset_bias > 0) {
2404 __ set(mdo_offset_bias, data_val);
2405 __ add(mdo, data_val, mdo);
2406 }
2407 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2408 __ ldub(flags_addr, data_val);
2409 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2410 __ stb(data_val, flags_addr);
2411 __ ba(*obj_is_null);
2412 __ delayed()->nop();
2413 __ bind(not_null);
2414 } else {
2415 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2416 __ delayed()->nop();
2417 }
2418
2419 Label profile_cast_failure, profile_cast_success;
2420 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2421 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2422
2423 // patching may screw with our temporaries on sparc,
2424 // so let's do it before loading the class
2425 if (k->is_loaded()) {
2426 metadata2reg(k->constant_encoding(), k_RInfo);
2427 } else {
2428 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2429 }
2430 assert(obj != k_RInfo, "must be different");
2431
2432 // get object class
2433 // not a safepoint as obj null check happens earlier
2434 __ load_klass(obj, klass_RInfo);
2435 if (op->fast_check()) {
2436 assert_different_registers(klass_RInfo, k_RInfo);
2437 __ cmp(k_RInfo, klass_RInfo);
2438 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2439 __ delayed()->nop();
2440 } else {
2441 bool need_slow_path = true;
2442 if (k->is_loaded()) {
2443 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2444 need_slow_path = false;
2445 // perform the fast part of the checking logic
2446 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2447 (need_slow_path ? success_target : NULL),
2448 failure_target, NULL,
2449 RegisterOrConstant(k->super_check_offset()));
2450 } else {
2451 // perform the fast part of the checking logic
2452 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2453 failure_target, NULL);
2454 }
2455 if (need_slow_path) {
2456 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2457 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2458 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2459 __ delayed()->nop();
2460 __ cmp(G3, 0);
2461 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2462 __ delayed()->nop();
2463 // Fall through to success case
2464 }
2465 }
2466
2467 if (op->should_profile()) {
2468 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2469 assert_different_registers(obj, mdo, recv, tmp1);
2470 __ bind(profile_cast_success);
2471 metadata2reg(md->constant_encoding(), mdo);
2472 if (mdo_offset_bias > 0) {
2473 __ set(mdo_offset_bias, tmp1);
2474 __ add(mdo, tmp1, mdo);
2475 }
2476 __ load_klass(obj, recv);
2477 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2478 // Jump over the failure case
2479 __ ba(*success);
2480 __ delayed()->nop();
2481 // Cast failure case
2482 __ bind(profile_cast_failure);
2483 metadata2reg(md->constant_encoding(), mdo);
2484 if (mdo_offset_bias > 0) {
2485 __ set(mdo_offset_bias, tmp1);
2486 __ add(mdo, tmp1, mdo);
2487 }
2488 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2489 __ ld_ptr(data_addr, tmp1);
2490 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2491 __ st_ptr(tmp1, data_addr);
2492 __ ba(*failure);
2493 __ delayed()->nop();
2494 }
2495 __ ba(*success);
2496 __ delayed()->nop();
2497 }
2498
2499 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2500 LIR_Code code = op->code();
2501 if (code == lir_store_check) {
2502 Register value = op->object()->as_register();
2503 Register array = op->array()->as_register();
2504 Register k_RInfo = op->tmp1()->as_register();
2505 Register klass_RInfo = op->tmp2()->as_register();
2506 Register Rtmp1 = op->tmp3()->as_register();
2507
2508 __ verify_oop(value);
2509 CodeStub* stub = op->stub();
2510 // check if it needs to be profiled
2511 ciMethodData* md;
2512 ciProfileData* data;
2513 int mdo_offset_bias = 0;
2514 if (op->should_profile()) {
2515 ciMethod* method = op->profiled_method();
2516 assert(method != NULL, "Should have method");
2517 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2518 }
2519 Label profile_cast_success, profile_cast_failure, done;
2520 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2521 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2522
2523 if (op->should_profile()) {
2524 Label not_null;
2525 __ br_notnull_short(value, Assembler::pn, not_null);
2526 Register mdo = k_RInfo;
2527 Register data_val = Rtmp1;
2528 metadata2reg(md->constant_encoding(), mdo);
2529 if (mdo_offset_bias > 0) {
2530 __ set(mdo_offset_bias, data_val);
2531 __ add(mdo, data_val, mdo);
2532 }
2533 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2534 __ ldub(flags_addr, data_val);
2535 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2536 __ stb(data_val, flags_addr);
2537 __ ba_short(done);
2538 __ bind(not_null);
2539 } else {
2540 __ br_null_short(value, Assembler::pn, done);
2541 }
2542 add_debug_info_for_null_check_here(op->info_for_exception());
2543 __ load_klass(array, k_RInfo);
2544 __ load_klass(value, klass_RInfo);
2545
2546 // get instance klass
2547 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2548 // perform the fast part of the checking logic
2549 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2550
2551 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2552 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2553 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2554 __ delayed()->nop();
2555 __ cmp(G3, 0);
2556 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2557 __ delayed()->nop();
2558 // fall through to the success case
2559
2560 if (op->should_profile()) {
2561 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2562 assert_different_registers(value, mdo, recv, tmp1);
2563 __ bind(profile_cast_success);
2564 metadata2reg(md->constant_encoding(), mdo);
2565 if (mdo_offset_bias > 0) {
2566 __ set(mdo_offset_bias, tmp1);
2567 __ add(mdo, tmp1, mdo);
2568 }
2569 __ load_klass(value, recv);
2570 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2571 __ ba_short(done);
2572 // Cast failure case
2573 __ bind(profile_cast_failure);
2574 metadata2reg(md->constant_encoding(), mdo);
2575 if (mdo_offset_bias > 0) {
2576 __ set(mdo_offset_bias, tmp1);
2577 __ add(mdo, tmp1, mdo);
2578 }
2579 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2580 __ ld_ptr(data_addr, tmp1);
2581 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2582 __ st_ptr(tmp1, data_addr);
2583 __ ba(*stub->entry());
2584 __ delayed()->nop();
2585 }
2586 __ bind(done);
2587 } else if (code == lir_checkcast) {
2588 Register obj = op->object()->as_register();
2589 Register dst = op->result_opr()->as_register();
2590 Label success;
2591 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2592 __ bind(success);
2593 __ mov(obj, dst);
2594 } else if (code == lir_instanceof) {
2595 Register obj = op->object()->as_register();
2596 Register dst = op->result_opr()->as_register();
2597 Label success, failure, done;
2598 emit_typecheck_helper(op, &success, &failure, &failure);
2599 __ bind(failure);
2600 __ set(0, dst);
2601 __ ba_short(done);
2602 __ bind(success);
2603 __ set(1, dst);
2604 __ bind(done);
2605 } else {
2606 ShouldNotReachHere();
2607 }
2608
2609 }
2610
2611
2612 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2613 if (op->code() == lir_cas_long) {
2614 assert(VM_Version::supports_cx8(), "wrong machine");
2615 Register addr = op->addr()->as_pointer_register();
2616 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2617 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2618 Register new_value_lo = op->new_value()->as_register_lo();
2619 Register new_value_hi = op->new_value()->as_register_hi();
2620 Register t1 = op->tmp1()->as_register();
2621 Register t2 = op->tmp2()->as_register();
2622 __ mov(cmp_value_lo, t1);
2623 __ mov(new_value_lo, t2);
2624 // perform the compare and swap operation
2625 __ casx(addr, t1, t2);
2626 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2627 // overwritten with the original value in "addr" and will be equal to t1.
2628 __ cmp(t1, t2);
2629 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2630 Register addr = op->addr()->as_pointer_register();
2631 Register cmp_value = op->cmp_value()->as_register();
2632 Register new_value = op->new_value()->as_register();
2633 Register t1 = op->tmp1()->as_register();
2634 Register t2 = op->tmp2()->as_register();
2635 __ mov(cmp_value, t1);
2636 __ mov(new_value, t2);
2637 if (op->code() == lir_cas_obj) {
2638 if (UseCompressedOops) {
2639 __ encode_heap_oop(t1);
2640 __ encode_heap_oop(t2);
2641 __ cas(addr, t1, t2);
2642 } else {
2643 __ cas_ptr(addr, t1, t2);
2644 }
2645 } else {
2646 __ cas(addr, t1, t2);
2647 }
2648 __ cmp(t1, t2);
2649 } else {
2650 Unimplemented();
2651 }
2652 }
2653
2654 void LIR_Assembler::set_24bit_FPU() {
2655 Unimplemented();
2656 }
2657
2658
2659 void LIR_Assembler::reset_FPU() {
2660 Unimplemented();
2661 }
2662
2663
2664 void LIR_Assembler::breakpoint() {
2665 __ breakpoint_trap();
2666 }
2667
2668
2669 void LIR_Assembler::push(LIR_Opr opr) {
2670 Unimplemented();
2671 }
2672
2673
2674 void LIR_Assembler::pop(LIR_Opr opr) {
2675 Unimplemented();
2676 }
2677
2678
2679 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2680 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2681 Register dst = dst_opr->as_register();
2682 Register reg = mon_addr.base();
2683 int offset = mon_addr.disp();
2684 // compute pointer to BasicLock
2685 if (mon_addr.is_simm13()) {
2686 __ add(reg, offset, dst);
2687 } else {
2688 __ set(offset, dst);
2689 __ add(dst, reg, dst);
2690 }
2691 }
2692
2693 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2694 assert(op->crc()->is_single_cpu(), "crc must be register");
2695 assert(op->val()->is_single_cpu(), "byte value must be register");
2696 assert(op->result_opr()->is_single_cpu(), "result must be register");
2697 Register crc = op->crc()->as_register();
2698 Register val = op->val()->as_register();
2699 Register table = op->result_opr()->as_register();
2700 Register res = op->result_opr()->as_register();
2701
2702 assert_different_registers(val, crc, table);
2703
2704 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2705 __ not1(crc);
2706 __ clruwu(crc);
2707 __ update_byte_crc32(crc, val, table);
2708 __ not1(crc);
2709
2710 __ mov(crc, res);
2711 }
2712
2713 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2714 Register obj = op->obj_opr()->as_register();
2715 Register hdr = op->hdr_opr()->as_register();
2716 Register lock = op->lock_opr()->as_register();
2717
2718 // obj may not be an oop
2719 if (op->code() == lir_lock) {
2720 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2721 if (UseFastLocking) {
2722 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2723 // add debug info for NullPointerException only if one is possible
2724 if (op->info() != NULL) {
2725 add_debug_info_for_null_check_here(op->info());
2726 }
2727 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2728 } else {
2729 // always do slow locking
2730 // note: the slow locking code could be inlined here, however if we use
2731 // slow locking, speed doesn't matter anyway and this solution is
2732 // simpler and requires less duplicated code - additionally, the
2733 // slow locking code is the same in either case which simplifies
2734 // debugging
2735 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2736 __ delayed()->nop();
2737 }
2738 } else {
2739 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2740 if (UseFastLocking) {
2741 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2742 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2743 } else {
2744 // always do slow unlocking
2745 // note: the slow unlocking code could be inlined here, however if we use
2746 // slow unlocking, speed doesn't matter anyway and this solution is
2747 // simpler and requires less duplicated code - additionally, the
2748 // slow unlocking code is the same in either case which simplifies
2749 // debugging
2750 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2751 __ delayed()->nop();
2752 }
2753 }
2754 __ bind(*op->stub()->continuation());
2755 }
2756
2757
2758 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2759 ciMethod* method = op->profiled_method();
2760 int bci = op->profiled_bci();
2761 ciMethod* callee = op->profiled_callee();
2762
2763 // Update counter for all call types
2764 ciMethodData* md = method->method_data_or_null();
2765 assert(md != NULL, "Sanity");
2766 ciProfileData* data = md->bci_to_data(bci);
2767 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2768 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2769 Register mdo = op->mdo()->as_register();
2770 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2771 Register tmp1 = op->tmp1()->as_register_lo();
2772 metadata2reg(md->constant_encoding(), mdo);
2773 int mdo_offset_bias = 0;
2774 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2775 data->size_in_bytes())) {
2776 // The offset is large so bias the mdo by the base of the slot so
2777 // that the ld can use simm13s to reference the slots of the data
2778 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2779 __ set(mdo_offset_bias, O7);
2780 __ add(mdo, O7, mdo);
2781 }
2782
2783 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2784 // Perform additional virtual call profiling for invokevirtual and
2785 // invokeinterface bytecodes
2786 if (op->should_profile_receiver_type()) {
2787 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2788 Register recv = op->recv()->as_register();
2789 assert_different_registers(mdo, tmp1, recv);
2790 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2791 ciKlass* known_klass = op->known_holder();
2792 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2793 // We know the type that will be seen at this call site; we can
2794 // statically update the MethodData* rather than needing to do
2795 // dynamic tests on the receiver type
2796
2797 // NOTE: we should probably put a lock around this search to
2798 // avoid collisions by concurrent compilations
2799 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2800 uint i;
2801 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2802 ciKlass* receiver = vc_data->receiver(i);
2803 if (known_klass->equals(receiver)) {
2804 Address data_addr(mdo, md->byte_offset_of_slot(data,
2805 VirtualCallData::receiver_count_offset(i)) -
2806 mdo_offset_bias);
2807 __ ld_ptr(data_addr, tmp1);
2808 __ add(tmp1, DataLayout::counter_increment, tmp1);
2809 __ st_ptr(tmp1, data_addr);
2810 return;
2811 }
2812 }
2813
2814 // Receiver type not found in profile data; select an empty slot
2815
2816 // Note that this is less efficient than it should be because it
2817 // always does a write to the receiver part of the
2818 // VirtualCallData rather than just the first time
2819 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2820 ciKlass* receiver = vc_data->receiver(i);
2821 if (receiver == NULL) {
2822 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2823 mdo_offset_bias);
2824 metadata2reg(known_klass->constant_encoding(), tmp1);
2825 __ st_ptr(tmp1, recv_addr);
2826 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2827 mdo_offset_bias);
2828 __ ld_ptr(data_addr, tmp1);
2829 __ add(tmp1, DataLayout::counter_increment, tmp1);
2830 __ st_ptr(tmp1, data_addr);
2831 return;
2832 }
2833 }
2834 } else {
2835 __ load_klass(recv, recv);
2836 Label update_done;
2837 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2838 // Receiver did not match any saved receiver and there is no empty row for it.
2839 // Increment total counter to indicate polymorphic case.
2840 __ ld_ptr(counter_addr, tmp1);
2841 __ add(tmp1, DataLayout::counter_increment, tmp1);
2842 __ st_ptr(tmp1, counter_addr);
2843
2844 __ bind(update_done);
2845 }
2846 } else {
2847 // Static call
2848 __ ld_ptr(counter_addr, tmp1);
2849 __ add(tmp1, DataLayout::counter_increment, tmp1);
2850 __ st_ptr(tmp1, counter_addr);
2851 }
2852 }
2853
2854 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2855 Register obj = op->obj()->as_register();
2856 Register tmp1 = op->tmp()->as_pointer_register();
2857 Register tmp2 = G1;
2858 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2859 ciKlass* exact_klass = op->exact_klass();
2860 intptr_t current_klass = op->current_klass();
2861 bool not_null = op->not_null();
2862 bool no_conflict = op->no_conflict();
2863
2864 Label update, next, none;
2865
2866 bool do_null = !not_null;
2867 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2868 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2869
2870 assert(do_null || do_update, "why are we here?");
2871 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2872
2873 __ verify_oop(obj);
2874
2875 if (tmp1 != obj) {
2876 __ mov(obj, tmp1);
2877 }
2878 if (do_null) {
2879 __ br_notnull_short(tmp1, Assembler::pt, update);
2880 if (!TypeEntries::was_null_seen(current_klass)) {
2881 __ ld_ptr(mdo_addr, tmp1);
2882 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2883 __ st_ptr(tmp1, mdo_addr);
2884 }
2885 if (do_update) {
2886 __ ba(next);
2887 __ delayed()->nop();
2888 }
2889 #ifdef ASSERT
2890 } else {
2891 __ br_notnull_short(tmp1, Assembler::pt, update);
2892 __ stop("unexpect null obj");
2893 #endif
2894 }
2895
2896 __ bind(update);
2897
2898 if (do_update) {
2899 #ifdef ASSERT
2900 if (exact_klass != NULL) {
2901 Label ok;
2902 __ load_klass(tmp1, tmp1);
2903 metadata2reg(exact_klass->constant_encoding(), tmp2);
2904 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
2905 __ stop("exact klass and actual klass differ");
2906 __ bind(ok);
2907 }
2908 #endif
2909
2910 Label do_update;
2911 __ ld_ptr(mdo_addr, tmp2);
2912
2913 if (!no_conflict) {
2914 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2915 if (exact_klass != NULL) {
2916 metadata2reg(exact_klass->constant_encoding(), tmp1);
2917 } else {
2918 __ load_klass(tmp1, tmp1);
2919 }
2920
2921 __ xor3(tmp1, tmp2, tmp1);
2922 __ btst(TypeEntries::type_klass_mask, tmp1);
2923 // klass seen before, nothing to do. The unknown bit may have been
2924 // set already but no need to check.
2925 __ brx(Assembler::zero, false, Assembler::pt, next);
2926 __ delayed()->
2927
2928 btst(TypeEntries::type_unknown, tmp1);
2929 // already unknown. Nothing to do anymore.
2930 __ brx(Assembler::notZero, false, Assembler::pt, next);
2931
2932 if (TypeEntries::is_type_none(current_klass)) {
2933 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2934 __ brx(Assembler::zero, true, Assembler::pt, do_update);
2935 // first time here. Set profile type.
2936 __ delayed()->or3(tmp2, tmp1, tmp2);
2937 } else {
2938 __ delayed()->nop();
2939 }
2940 } else {
2941 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2942 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2943
2944 __ btst(TypeEntries::type_unknown, tmp2);
2945 // already unknown. Nothing to do anymore.
2946 __ brx(Assembler::notZero, false, Assembler::pt, next);
2947 __ delayed()->nop();
2948 }
2949
2950 // different than before. Cannot keep accurate profile.
2951 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
2952 } else {
2953 // There's a single possible klass at this profile point
2954 assert(exact_klass != NULL, "should be");
2955 if (TypeEntries::is_type_none(current_klass)) {
2956 metadata2reg(exact_klass->constant_encoding(), tmp1);
2957 __ xor3(tmp1, tmp2, tmp1);
2958 __ btst(TypeEntries::type_klass_mask, tmp1);
2959 __ brx(Assembler::zero, false, Assembler::pt, next);
2960 #ifdef ASSERT
2961
2962 {
2963 Label ok;
2964 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2965 __ brx(Assembler::zero, true, Assembler::pt, ok);
2966 __ delayed()->nop();
2967
2968 __ stop("unexpected profiling mismatch");
2969 __ bind(ok);
2970 }
2971 // first time here. Set profile type.
2972 __ or3(tmp2, tmp1, tmp2);
2973 #else
2974 // first time here. Set profile type.
2975 __ delayed()->or3(tmp2, tmp1, tmp2);
2976 #endif
2977
2978 } else {
2979 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2980 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2981
2982 // already unknown. Nothing to do anymore.
2983 __ btst(TypeEntries::type_unknown, tmp2);
2984 __ brx(Assembler::notZero, false, Assembler::pt, next);
2985 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
2986 }
2987 }
2988
2989 __ bind(do_update);
2990 __ st_ptr(tmp2, mdo_addr);
2991
2992 __ bind(next);
2993 }
2994 }
2995
2996 void LIR_Assembler::align_backward_branch_target() {
2997 __ align(OptoLoopAlignment);
2998 }
2999
3000
3001 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3002 // make sure we are expecting a delay
3003 // this has the side effect of clearing the delay state
3004 // so we can use _masm instead of _masm->delayed() to do the
3005 // code generation.
3006 __ delayed();
3007
3008 // make sure we only emit one instruction
3009 int offset = code_offset();
3010 op->delay_op()->emit_code(this);
3011 #ifdef ASSERT
3012 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3013 op->delay_op()->print();
3014 }
3015 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3016 "only one instruction can go in a delay slot");
3017 #endif
3018
3019 // we may also be emitting the call info for the instruction
3020 // which we are the delay slot of.
3021 CodeEmitInfo* call_info = op->call_info();
3022 if (call_info) {
3023 add_call_info(code_offset(), call_info);
3024 }
3025
3026 if (VerifyStackAtCalls) {
3027 _masm->sub(FP, SP, O7);
3028 _masm->cmp(O7, initial_frame_size_in_bytes());
3029 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3030 }
3031 }
3032
3033
3034 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3035 assert(left->is_register(), "can only handle registers");
3036
3037 if (left->is_single_cpu()) {
3038 __ neg(left->as_register(), dest->as_register());
3039 } else if (left->is_single_fpu()) {
3040 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3041 } else if (left->is_double_fpu()) {
3042 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3043 } else {
3044 assert (left->is_double_cpu(), "Must be a long");
3045 Register Rlow = left->as_register_lo();
3046 Register Rhi = left->as_register_hi();
3047 __ sub(G0, Rlow, dest->as_register_lo());
3048 }
3049 }
3050
3051
3052 void LIR_Assembler::fxch(int i) {
3053 Unimplemented();
3054 }
3055
3056 void LIR_Assembler::fld(int i) {
3057 Unimplemented();
3058 }
3059
3060 void LIR_Assembler::ffree(int i) {
3061 Unimplemented();
3062 }
3063
3064 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3065 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3066
3067 // if tmp is invalid, then the function being called doesn't destroy the thread
3068 if (tmp->is_valid()) {
3069 __ save_thread(tmp->as_pointer_register());
3070 }
3071 __ call(dest, relocInfo::runtime_call_type);
3072 __ delayed()->nop();
3073 if (info != NULL) {
3074 add_call_info_here(info);
3075 }
3076 if (tmp->is_valid()) {
3077 __ restore_thread(tmp->as_pointer_register());
3078 }
3079
3080 #ifdef ASSERT
3081 __ verify_thread();
3082 #endif // ASSERT
3083 }
3084
3085
3086 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3087 ShouldNotReachHere();
3088
3089 NEEDS_CLEANUP;
3090 if (type == T_LONG) {
3091 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3092
3093 // (extended to allow indexed as well as constant displaced for JSR-166)
3094 Register idx = noreg; // contains either constant offset or index
3095
3096 int disp = mem_addr->disp();
3097 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3098 if (!Assembler::is_simm13(disp)) {
3099 idx = O7;
3100 __ set(disp, idx);
3101 }
3102 } else {
3103 assert(disp == 0, "not both indexed and disp");
3104 idx = mem_addr->index()->as_register();
3105 }
3106
3107 int null_check_offset = -1;
3108
3109 Register base = mem_addr->base()->as_register();
3110 if (src->is_register() && dest->is_address()) {
3111 // G4 is high half, G5 is low half
3112 // clear the top bits of G5, and scale up G4
3113 __ srl (src->as_register_lo(), 0, G5);
3114 __ sllx(src->as_register_hi(), 32, G4);
3115 // combine the two halves into the 64 bits of G4
3116 __ or3(G4, G5, G4);
3117 null_check_offset = __ offset();
3118 if (idx == noreg) {
3119 __ stx(G4, base, disp);
3120 } else {
3121 __ stx(G4, base, idx);
3122 }
3123 } else if (src->is_address() && dest->is_register()) {
3124 null_check_offset = __ offset();
3125 if (idx == noreg) {
3126 __ ldx(base, disp, G5);
3127 } else {
3128 __ ldx(base, idx, G5);
3129 }
3130 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3131 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3132 } else {
3133 Unimplemented();
3134 }
3135 if (info != NULL) {
3136 add_debug_info_for_null_check(null_check_offset, info);
3137 }
3138
3139 } else {
3140 // use normal move for all other volatiles since they don't need
3141 // special handling to remain atomic.
3142 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3143 }
3144 }
3145
3146 void LIR_Assembler::membar() {
3147 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3148 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3149 }
3150
3151 void LIR_Assembler::membar_acquire() {
3152 // no-op on TSO
3153 }
3154
3155 void LIR_Assembler::membar_release() {
3156 // no-op on TSO
3157 }
3158
3159 void LIR_Assembler::membar_loadload() {
3160 // no-op
3161 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3162 }
3163
3164 void LIR_Assembler::membar_storestore() {
3165 // no-op
3166 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3167 }
3168
3169 void LIR_Assembler::membar_loadstore() {
3170 // no-op
3171 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3172 }
3173
3174 void LIR_Assembler::membar_storeload() {
3175 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3176 }
3177
3178 void LIR_Assembler::on_spin_wait() {
3179 Unimplemented();
3180 }
3181
3182 // Pack two sequential registers containing 32 bit values
3183 // into a single 64 bit register.
3184 // src and src->successor() are packed into dst
3185 // src and dst may be the same register.
3186 // Note: src is destroyed
3187 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3188 Register rs = src->as_register();
3189 Register rd = dst->as_register_lo();
3190 __ sllx(rs, 32, rs);
3191 __ srl(rs->successor(), 0, rs->successor());
3192 __ or3(rs, rs->successor(), rd);
3193 }
3194
3195 // Unpack a 64 bit value in a register into
3196 // two sequential registers.
3197 // src is unpacked into dst and dst->successor()
3198 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3199 Register rs = src->as_register_lo();
3200 Register rd = dst->as_register_hi();
3201 assert_different_registers(rs, rd, rd->successor());
3202 __ srlx(rs, 32, rd);
3203 __ srl (rs, 0, rd->successor());
3204 }
3205
3206 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3207 const LIR_Address* addr = addr_opr->as_address_ptr();
3208 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3209 const Register dest_reg = dest->as_pointer_register();
3210 const Register base_reg = addr->base()->as_pointer_register();
3211
3212 if (Assembler::is_simm13(addr->disp())) {
3213 if (addr->index()->is_valid()) {
3214 const Register index_reg = addr->index()->as_pointer_register();
3215 assert(index_reg != G3_scratch, "invariant");
3216 __ add(base_reg, addr->disp(), G3_scratch);
3217 __ add(index_reg, G3_scratch, dest_reg);
3218 } else {
3219 __ add(base_reg, addr->disp(), dest_reg);
3220 }
3221 } else {
3222 __ set(addr->disp(), G3_scratch);
3223 if (addr->index()->is_valid()) {
3224 const Register index_reg = addr->index()->as_pointer_register();
3225 assert(index_reg != G3_scratch, "invariant");
3226 __ add(index_reg, G3_scratch, G3_scratch);
3227 }
3228 __ add(base_reg, G3_scratch, dest_reg);
3229 }
3230 }
3231
3232
3233 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3234 assert(result_reg->is_register(), "check");
3235 __ mov(G2_thread, result_reg->as_register());
3236 }
3237
3238 #ifdef ASSERT
3239 // emit run-time assertion
3240 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3241 assert(op->code() == lir_assert, "must be");
3242
3243 if (op->in_opr1()->is_valid()) {
3244 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3245 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3246 } else {
3247 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3248 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3249 }
3250
3251 Label ok;
3252 if (op->condition() != lir_cond_always) {
3253 Assembler::Condition acond;
3254 switch (op->condition()) {
3255 case lir_cond_equal: acond = Assembler::equal; break;
3256 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3257 case lir_cond_less: acond = Assembler::less; break;
3258 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3259 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3260 case lir_cond_greater: acond = Assembler::greater; break;
3261 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3262 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3263 default: ShouldNotReachHere();
3264 };
3265 __ br(acond, false, Assembler::pt, ok);
3266 __ delayed()->nop();
3267 }
3268 if (op->halt()) {
3269 const char* str = __ code_string(op->msg());
3270 __ stop(str);
3271 } else {
3272 breakpoint();
3273 }
3274 __ bind(ok);
3275 }
3276 #endif
3277
3278 void LIR_Assembler::peephole(LIR_List* lir) {
3279 LIR_OpList* inst = lir->instructions_list();
3280 for (int i = 0; i < inst->length(); i++) {
3281 LIR_Op* op = inst->at(i);
3282 switch (op->code()) {
3283 case lir_cond_float_branch:
3284 case lir_branch: {
3285 LIR_OpBranch* branch = op->as_OpBranch();
3286 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3287 LIR_Op* delay_op = NULL;
3288 // we'd like to be able to pull following instructions into
3289 // this slot but we don't know enough to do it safely yet so
3290 // only optimize block to block control flow.
3291 if (LIRFillDelaySlots && branch->block()) {
3292 LIR_Op* prev = inst->at(i - 1);
3293 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3294 // swap previous instruction into delay slot
3295 inst->at_put(i - 1, op);
3296 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3297 #ifndef PRODUCT
3298 if (LIRTracePeephole) {
3299 tty->print_cr("delayed");
3300 inst->at(i - 1)->print();
3301 inst->at(i)->print();
3302 tty->cr();
3303 }
3304 #endif
3305 continue;
3306 }
3307 }
3308
3309 if (!delay_op) {
3310 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3311 }
3312 inst->insert_before(i + 1, delay_op);
3313 break;
3314 }
3315 case lir_static_call:
3316 case lir_virtual_call:
3317 case lir_icvirtual_call:
3318 case lir_optvirtual_call:
3319 case lir_dynamic_call: {
3320 LIR_Op* prev = inst->at(i - 1);
3321 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3322 (op->code() != lir_virtual_call ||
3323 !prev->result_opr()->is_single_cpu() ||
3324 prev->result_opr()->as_register() != O0) &&
3325 LIR_Assembler::is_single_instruction(prev)) {
3326 // Only moves without info can be put into the delay slot.
3327 // Also don't allow the setup of the receiver in the delay
3328 // slot for vtable calls.
3329 inst->at_put(i - 1, op);
3330 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3331 #ifndef PRODUCT
3332 if (LIRTracePeephole) {
3333 tty->print_cr("delayed");
3334 inst->at(i - 1)->print();
3335 inst->at(i)->print();
3336 tty->cr();
3337 }
3338 #endif
3339 } else {
3340 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3341 inst->insert_before(i + 1, delay_op);
3342 i++;
3343 }
3344 break;
3345 }
3346 }
3347 }
3348 }
3349
3350 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3351 LIR_Address* addr = src->as_address_ptr();
3352
3353 assert(data == dest, "swap uses only 2 operands");
3354 assert (code == lir_xchg, "no xadd on sparc");
3355
3356 if (data->type() == T_INT) {
3357 __ swap(as_Address(addr), data->as_register());
3358 } else if (data->is_oop()) {
3359 Register obj = data->as_register();
3360 Register narrow = tmp->as_register();
3361 assert(UseCompressedOops, "swap is 32bit only");
3362 __ encode_heap_oop(obj, narrow);
3363 __ swap(as_Address(addr), narrow);
3364 __ decode_heap_oop(narrow, obj);
3365 } else {
3366 ShouldNotReachHere();
3367 }
3368 }
3369
3370 #undef __