1 /*
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   7  * under the terms of the GNU General Public License version 2 only, as
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  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
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  25 
  26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_HPP
  27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_HPP
  28 
  29 #include "runtime/orderAccess.hpp"
  30 
  31 // Compiler version last used for testing: xlc 12
  32 // Please update this information when this file changes
  33 
  34 // Implementation of class OrderAccess.
  35 
  36 //
  37 // Machine barrier instructions:
  38 //
  39 // - sync            Two-way memory barrier, aka fence.
  40 // - lwsync          orders  Store|Store,
  41 //                            Load|Store,
  42 //                            Load|Load,
  43 //                   but not Store|Load
  44 // - eieio           orders  Store|Store
  45 // - isync           Invalidates speculatively executed instructions,
  46 //                   but isync may complete before storage accesses
  47 //                   associated with instructions preceding isync have
  48 //                   been performed.
  49 //
  50 // Semantic barrier instructions:
  51 // (as defined in orderAccess.hpp)
  52 //
  53 // - release         orders Store|Store,       (maps to lwsync)
  54 //                           Load|Store
  55 // - acquire         orders  Load|Store,       (maps to lwsync)
  56 //                           Load|Load
  57 // - fence           orders Store|Store,       (maps to sync)
  58 //                           Load|Store,
  59 //                           Load|Load,
  60 //                          Store|Load
  61 //
  62 
  63 #define inlasm_sync()     __asm__ __volatile__ ("sync"   : : : "memory");
  64 #define inlasm_lwsync()   __asm__ __volatile__ ("lwsync" : : : "memory");
  65 #define inlasm_eieio()    __asm__ __volatile__ ("eieio"  : : : "memory");
  66 #define inlasm_isync()    __asm__ __volatile__ ("isync"  : : : "memory");
  67 // Use twi-isync for load_acquire (faster than lwsync).
  68 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
  69 // #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
  70 #define inlasm_acquire_reg(X) inlasm_lwsync();
  71 
  72 inline void OrderAccess::loadload()   { inlasm_lwsync(); }
  73 inline void OrderAccess::storestore() { inlasm_lwsync(); }
  74 inline void OrderAccess::loadstore()  { inlasm_lwsync(); }
  75 inline void OrderAccess::storeload()  { inlasm_sync();   }
  76 
  77 inline void OrderAccess::acquire()    { inlasm_lwsync(); }
  78 inline void OrderAccess::release()    { inlasm_lwsync(); }
  79 inline void OrderAccess::fence()      { inlasm_sync();   }
  80 
  81 template<size_t byte_size>
  82 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE>
  83 {
  84   template <typename T>
  85   T operator()(const volatile T* p) const { register T t = Atomic::load(p); inlasm_acquire_reg(t); return t; }
  86 };
  87 
  88 #undef inlasm_sync
  89 #undef inlasm_lwsync
  90 #undef inlasm_eieio
  91 #undef inlasm_isync
  92 
  93 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_HPP