6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
  27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
  28 
  29 #include "runtime/orderAccess.hpp"
  30 
  31 // Compiler version last used for testing: xlc 12
  32 // Please update this information when this file changes
  33 
  34 // Implementation of class OrderAccess.
  35 
  36 //
  37 // Machine barrier instructions:
  38 //
  39 // - sync            Two-way memory barrier, aka fence.
  40 // - lwsync          orders  Store|Store,
  41 //                            Load|Store,
  42 //                            Load|Load,
  43 //                   but not Store|Load
  44 // - eieio           orders  Store|Store
  45 // - isync           Invalidates speculatively executed instructions,
  46 //                   but isync may complete before storage accesses
  47 //                   associated with instructions preceding isync have

  73 inline void OrderAccess::storestore() { inlasm_lwsync(); }
  74 inline void OrderAccess::loadstore()  { inlasm_lwsync(); }
  75 inline void OrderAccess::storeload()  { inlasm_sync();   }
  76 
  77 inline void OrderAccess::acquire()    { inlasm_lwsync(); }
  78 inline void OrderAccess::release()    { inlasm_lwsync(); }
  79 inline void OrderAccess::fence()      { inlasm_sync();   }
  80 
  81 template<size_t byte_size>
  82 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE>
  83 {
  84   template <typename T>
  85   T operator()(const volatile T* p) const { register T t = Atomic::load(p); inlasm_acquire_reg(t); return t; }
  86 };
  87 
  88 #undef inlasm_sync
  89 #undef inlasm_lwsync
  90 #undef inlasm_eieio
  91 #undef inlasm_isync
  92 
  93 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP

   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_HPP
  27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_HPP
  28 
  29 #include "runtime/orderAccess.hpp"
  30 
  31 // Compiler version last used for testing: xlc 12
  32 // Please update this information when this file changes
  33 
  34 // Implementation of class OrderAccess.
  35 
  36 //
  37 // Machine barrier instructions:
  38 //
  39 // - sync            Two-way memory barrier, aka fence.
  40 // - lwsync          orders  Store|Store,
  41 //                            Load|Store,
  42 //                            Load|Load,
  43 //                   but not Store|Load
  44 // - eieio           orders  Store|Store
  45 // - isync           Invalidates speculatively executed instructions,
  46 //                   but isync may complete before storage accesses
  47 //                   associated with instructions preceding isync have

  73 inline void OrderAccess::storestore() { inlasm_lwsync(); }
  74 inline void OrderAccess::loadstore()  { inlasm_lwsync(); }
  75 inline void OrderAccess::storeload()  { inlasm_sync();   }
  76 
  77 inline void OrderAccess::acquire()    { inlasm_lwsync(); }
  78 inline void OrderAccess::release()    { inlasm_lwsync(); }
  79 inline void OrderAccess::fence()      { inlasm_sync();   }
  80 
  81 template<size_t byte_size>
  82 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE>
  83 {
  84   template <typename T>
  85   T operator()(const volatile T* p) const { register T t = Atomic::load(p); inlasm_acquire_reg(t); return t; }
  86 };
  87 
  88 #undef inlasm_sync
  89 #undef inlasm_lwsync
  90 #undef inlasm_eieio
  91 #undef inlasm_isync
  92 
  93 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_HPP