src/hotspot/os_cpu/bsd_x86/orderAccess_bsd_x86.hpp

*** 20,35 ****
   * or visit www.oracle.com if you need additional information or have any
   * questions.
   *
   */
  
! #ifndef OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
! #define OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
  
  #include "runtime/atomic.hpp"
  #include "runtime/orderAccess.hpp"
- #include "runtime/os.hpp"
  
  // Compiler version last used for testing: clang 5.1
  // Please update this information when this file changes
  
  // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
--- 20,34 ----
   * or visit www.oracle.com if you need additional information or have any
   * questions.
   *
   */
  
! #ifndef OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_HPP
! #define OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_HPP
  
  #include "runtime/atomic.hpp"
  #include "runtime/orderAccess.hpp"
  
  // Compiler version last used for testing: clang 5.1
  // Please update this information when this file changes
  
  // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
*** 50,67 ****
  
  inline void OrderAccess::acquire()    { compiler_barrier(); }
  inline void OrderAccess::release()    { compiler_barrier(); }
  
  inline void OrderAccess::fence() {
-   if (os::is_MP()) {
      // always use locked addl since mfence is sometimes expensive
  #ifdef AMD64
      __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
  #else
      __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
  #endif
-   }
    compiler_barrier();
  }
  
  template<>
  struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE>
--- 49,64 ----
*** 111,116 ****
                        : "memory");
    }
  };
  #endif // AMD64
  
! #endif // OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
--- 108,113 ----
                        : "memory");
    }
  };
  #endif // AMD64
  
! #endif // OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_HPP