5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
26 #define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
27
28 #include "runtime/orderAccess.hpp"
29 #include "runtime/os.hpp"
30 #include "vm_version_arm.hpp"
31
32 // Implementation of class OrderAccess.
33 // - we define the high level barriers below and use the general
34 // implementation in orderAccess.inline.hpp, with customizations
35 // on AARCH64 via the specialized_* template functions
36
37 // Memory Ordering on ARM is weak.
38 //
39 // Implement all 4 memory ordering barriers by DMB, since it is a
40 // lighter version of DSB.
41 // dmb_sy implies full system shareability domain. RD/WR access type.
42 // dmb_st implies full system shareability domain. WR only access type.
43 //
44 // NOP on < ARMv6 (MP not supported)
45 //
46 // Non mcr instructions can be used if we build for armv7 or higher arch
47 // __asm__ __volatile__ ("dmb" : : : "memory");
48 // __asm__ __volatile__ ("dsb" : : : "memory");
49 //
50 // inline void _OrderAccess_dsb() {
51 // volatile intptr_t dummy = 0;
52 // if (os::is_MP()) {
53 // __asm__ volatile (
54 // "mcr p15, 0, %0, c7, c10, 4"
227 : [ptr] "r" (p), [val] "r" (v)
228 : "memory");
229 }
230 };
231
232 template<>
233 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE>
234 {
235 template <typename T>
236 void operator()(T v, volatile T* p) const {
237 __asm__ volatile(
238 "stlr %[val], [%[ptr]]"
239 :
240 : [ptr] "r" (p), [val] "r" (v)
241 : "memory");
242 }
243 };
244
245 #endif // AARCH64
246
247 #endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
|
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_HPP
26 #define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_HPP
27
28 #include "runtime/orderAccess.hpp"
29 #include "runtime/os.hpp"
30 #include "vm_version_arm.hpp"
31
32 // Implementation of class OrderAccess.
33 // - we define the high level barriers below and use the general
34 // implementation in orderAccess.hpp, with customizations
35 // on AARCH64 via the specialized_* template functions
36
37 // Memory Ordering on ARM is weak.
38 //
39 // Implement all 4 memory ordering barriers by DMB, since it is a
40 // lighter version of DSB.
41 // dmb_sy implies full system shareability domain. RD/WR access type.
42 // dmb_st implies full system shareability domain. WR only access type.
43 //
44 // NOP on < ARMv6 (MP not supported)
45 //
46 // Non mcr instructions can be used if we build for armv7 or higher arch
47 // __asm__ __volatile__ ("dmb" : : : "memory");
48 // __asm__ __volatile__ ("dsb" : : : "memory");
49 //
50 // inline void _OrderAccess_dsb() {
51 // volatile intptr_t dummy = 0;
52 // if (os::is_MP()) {
53 // __asm__ volatile (
54 // "mcr p15, 0, %0, c7, c10, 4"
227 : [ptr] "r" (p), [val] "r" (v)
228 : "memory");
229 }
230 };
231
232 template<>
233 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE>
234 {
235 template <typename T>
236 void operator()(T v, volatile T* p) const {
237 __asm__ volatile(
238 "stlr %[val], [%[ptr]]"
239 :
240 : [ptr] "r" (p), [val] "r" (v)
241 : "memory");
242 }
243 };
244
245 #endif // AARCH64
246
247 #endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_HPP
|