1 /* 2 * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP 27 #define OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP 28 29 #include "runtime/orderAccess.hpp" 30 #include "vm_version_s390.hpp" 31 32 // Implementation of class OrderAccess. 33 34 // 35 // machine barrier instructions: 36 // 37 // - z_sync two-way memory barrier, aka fence 38 // 39 // semantic barrier instructions: 40 // (as defined in orderAccess.hpp) 41 // 42 // - z_release orders Store|Store, (maps to compiler barrier) 43 // Load|Store 44 // - z_acquire orders Load|Store, (maps to compiler barrier) 45 // Load|Load 46 // - z_fence orders Store|Store, (maps to z_sync) 47 // Load|Store, 48 // Load|Load, 49 // Store|Load 50 // 51 52 53 // Only load-after-store-order is not guaranteed on z/Architecture, i.e. only 'fence' 54 // is needed. 55 56 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions. 57 #define inlasm_compiler_barrier() __asm__ volatile ("" : : : "memory"); 58 // "bcr 15, 0" is used as two way memory barrier. 59 #define inlasm_zarch_sync() __asm__ __volatile__ ("bcr 15, 0" : : : "memory"); 60 61 // Release and acquire are empty on z/Architecture, but potential 62 // optimizations of gcc must be forbidden by OrderAccess::release and 63 // OrderAccess::acquire. 64 #define inlasm_zarch_release() inlasm_compiler_barrier() 65 #define inlasm_zarch_acquire() inlasm_compiler_barrier() 66 #define inlasm_zarch_fence() inlasm_zarch_sync() 67 68 inline void OrderAccess::loadload() { inlasm_compiler_barrier(); } 69 inline void OrderAccess::storestore() { inlasm_compiler_barrier(); } 70 inline void OrderAccess::loadstore() { inlasm_compiler_barrier(); } 71 inline void OrderAccess::storeload() { inlasm_zarch_sync(); } 72 73 inline void OrderAccess::acquire() { inlasm_zarch_acquire(); } 74 inline void OrderAccess::release() { inlasm_zarch_release(); } 75 inline void OrderAccess::fence() { inlasm_zarch_sync(); } 76 77 template<size_t byte_size> 78 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE> 79 { 80 template <typename T> 81 T operator()(const volatile T* p) const { register T t = *p; inlasm_zarch_acquire(); return t; } 82 }; 83 84 #undef inlasm_compiler_barrier 85 #undef inlasm_zarch_sync 86 #undef inlasm_zarch_release 87 #undef inlasm_zarch_acquire 88 #undef inlasm_zarch_fence 89 90 #endif // OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP