1 //
2 // Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr;
952 instr = (Assembler::ldst_op << 30)
953 | (dst_enc << 25)
954 | (primary << 19)
955 | (src1_enc << 14);
956
957 uint index = src2_enc;
958 int disp = disp32;
959
960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
961 disp += STACK_BIAS;
962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
963 if (!Assembler::is_simm13(disp)) {
964 ra->C->record_method_not_compilable("unable to handle large constant offsets");
965 return;
966 }
967 }
968
969 // We should have a compiler bailout here rather than a guarantee.
970 // Better yet would be some mechanism to handle variable-size matches correctly.
971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rtype);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 // If this does safepoint polling, then do it here
1298 if(do_polling() && ra_->C->is_method_compilation()) {
1299 AddressLiteral polling_page(os::get_polling_page());
1300 __ sethi(polling_page, L0);
1301 __ relocate(relocInfo::poll_return_type);
1302 __ ld_ptr(L0, 0, G0);
1303 }
1304
1305 // If this is a return, then stuff the restore in the delay slot
1306 if(do_polling()) {
1307 if (UseCBCond && !ra_->C->is_method_compilation()) {
1308 // Insert extra padding for the case when the epilogue is preceded by
1309 // a cbcond jump, which can't be followed by a CTI instruction
1310 __ nop();
1311 }
1312 __ ret();
1313 __ delayed()->restore();
1314 } else {
1315 __ restore();
1316 }
1317 }
1318
1319 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1320 return MachNode::size(ra_);
1321 }
1322
1323 int MachEpilogNode::reloc() const {
1324 return 16; // a large enough number
1325 }
1326
1327 const Pipeline * MachEpilogNode::pipeline() const {
1328 return MachNode::pipeline_class();
1329 }
1330
1331 int MachEpilogNode::safepoint_offset() const {
1332 assert( do_polling(), "no return for this epilog node");
1333 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1334 }
1335
1336 //=============================================================================
1337
1338 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1339 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1340 static enum RC rc_class( OptoReg::Name reg ) {
1341 if( !OptoReg::is_valid(reg) ) return rc_bad;
1342 if (OptoReg::is_stack(reg)) return rc_stack;
1343 VMReg r = OptoReg::as_VMReg(reg);
1344 if (r->is_Register()) return rc_int;
1345 assert(r->is_FloatRegister(), "must be");
1346 return rc_float;
1347 }
1348
1349 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1350 if (cbuf) {
1351 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1352 }
1353 #ifndef PRODUCT
1354 else if (!do_size) {
1355 if (size != 0) st->print("\n\t");
1356 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1357 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1358 }
1359 #endif
1360 return size+4;
1361 }
1362
1363 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1364 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1365 #ifndef PRODUCT
1366 else if( !do_size ) {
1367 if( size != 0 ) st->print("\n\t");
1368 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1369 }
1370 #endif
1371 return size+4;
1372 }
1373
1374 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1375 PhaseRegAlloc *ra_,
1376 bool do_size,
1377 outputStream* st ) const {
1378 // Get registers to move
1379 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1380 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1381 OptoReg::Name dst_second = ra_->get_reg_second(this );
1382 OptoReg::Name dst_first = ra_->get_reg_first(this );
1383
1384 enum RC src_second_rc = rc_class(src_second);
1385 enum RC src_first_rc = rc_class(src_first);
1386 enum RC dst_second_rc = rc_class(dst_second);
1387 enum RC dst_first_rc = rc_class(dst_first);
1388
1389 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1390
1391 // Generate spill code!
1392 int size = 0;
1393
1394 if( src_first == dst_first && src_second == dst_second )
1395 return size; // Self copy, no move
1396
1397 // --------------------------------------
1398 // Check for mem-mem move. Load into unused float registers and fall into
1399 // the float-store case.
1400 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1401 int offset = ra_->reg2offset(src_first);
1402 // Further check for aligned-adjacent pair, so we can use a double load
1403 if( (src_first&1)==0 && src_first+1 == src_second ) {
1404 src_second = OptoReg::Name(R_F31_num);
1405 src_second_rc = rc_float;
1406 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1407 } else {
1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1409 }
1410 src_first = OptoReg::Name(R_F30_num);
1411 src_first_rc = rc_float;
1412 }
1413
1414 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1415 int offset = ra_->reg2offset(src_second);
1416 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1417 src_second = OptoReg::Name(R_F31_num);
1418 src_second_rc = rc_float;
1419 }
1420
1421 // --------------------------------------
1422 // Check for float->int copy; requires a trip through memory
1423 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1424 int offset = frame::register_save_words*wordSize;
1425 if (cbuf) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1427 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1428 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1429 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1430 }
1431 #ifndef PRODUCT
1432 else if (!do_size) {
1433 if (size != 0) st->print("\n\t");
1434 st->print( "SUB R_SP,16,R_SP\n");
1435 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1436 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1437 st->print("\tADD R_SP,16,R_SP\n");
1438 }
1439 #endif
1440 size += 16;
1441 }
1442
1443 // Check for float->int copy on T4
1444 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1445 // Further check for aligned-adjacent pair, so we can use a double move
1446 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1447 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1448 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1449 }
1450 // Check for int->float copy on T4
1451 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1452 // Further check for aligned-adjacent pair, so we can use a double move
1453 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1454 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1455 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1456 }
1457
1458 // --------------------------------------
1459 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1460 // In such cases, I have to do the big-endian swap. For aligned targets, the
1461 // hardware does the flop for me. Doubles are always aligned, so no problem
1462 // there. Misaligned sources only come from native-long-returns (handled
1463 // special below).
1464 #ifndef _LP64
1465 if( src_first_rc == rc_int && // source is already big-endian
1466 src_second_rc != rc_bad && // 64-bit move
1467 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1468 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1469 // Do the big-endian flop.
1470 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1471 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1472 }
1473 #endif
1474
1475 // --------------------------------------
1476 // Check for integer reg-reg copy
1477 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1478 #ifndef _LP64
1479 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1480 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1481 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1482 // operand contains the least significant word of the 64-bit value and vice versa.
1483 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1484 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1485 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1486 if( cbuf ) {
1487 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1488 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1489 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1490 #ifndef PRODUCT
1491 } else if( !do_size ) {
1492 if( size != 0 ) st->print("\n\t");
1493 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1494 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1495 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1496 #endif
1497 }
1498 return size+12;
1499 }
1500 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1501 // returning a long value in I0/I1
1502 // a SpillCopy must be able to target a return instruction's reg_class
1503 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1504 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1505 // operand contains the least significant word of the 64-bit value and vice versa.
1506 OptoReg::Name tdest = dst_first;
1507
1508 if (src_first == dst_first) {
1509 tdest = OptoReg::Name(R_O7_num);
1510 size += 4;
1511 }
1512
1513 if( cbuf ) {
1514 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1515 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1516 // ShrL_reg_imm6
1517 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1518 // ShrR_reg_imm6 src, 0, dst
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1520 if (tdest != dst_first) {
1521 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1522 }
1523 }
1524 #ifndef PRODUCT
1525 else if( !do_size ) {
1526 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1527 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1528 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1529 if (tdest != dst_first) {
1530 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1531 }
1532 }
1533 #endif // PRODUCT
1534 return size+8;
1535 }
1536 #endif // !_LP64
1537 // Else normal reg-reg copy
1538 assert( src_second != dst_first, "smashed second before evacuating it" );
1539 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1540 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1541 // This moves an aligned adjacent pair.
1542 // See if we are done.
1543 if( src_first+1 == src_second && dst_first+1 == dst_second )
1544 return size;
1545 }
1546
1547 // Check for integer store
1548 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1549 int offset = ra_->reg2offset(dst_first);
1550 // Further check for aligned-adjacent pair, so we can use a double store
1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1552 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1553 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1554 }
1555
1556 // Check for integer load
1557 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1558 int offset = ra_->reg2offset(src_first);
1559 // Further check for aligned-adjacent pair, so we can use a double load
1560 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1561 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1562 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1563 }
1564
1565 // Check for float reg-reg copy
1566 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1567 // Further check for aligned-adjacent pair, so we can use a double move
1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1569 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1570 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1571 }
1572
1573 // Check for float store
1574 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1575 int offset = ra_->reg2offset(dst_first);
1576 // Further check for aligned-adjacent pair, so we can use a double store
1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1578 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1579 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1580 }
1581
1582 // Check for float load
1583 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1584 int offset = ra_->reg2offset(src_first);
1585 // Further check for aligned-adjacent pair, so we can use a double load
1586 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1587 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1588 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1589 }
1590
1591 // --------------------------------------------------------------------
1592 // Check for hi bits still needing moving. Only happens for misaligned
1593 // arguments to native calls.
1594 if( src_second == dst_second )
1595 return size; // Self copy; no move
1596 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1597
1598 #ifndef _LP64
1599 // In the LP64 build, all registers can be moved as aligned/adjacent
1600 // pairs, so there's never any need to move the high bits separately.
1601 // The 32-bit builds have to deal with the 32-bit ABI which can force
1602 // all sorts of silly alignment problems.
1603
1604 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1605 // 32-bits of a 64-bit register, but are needed in low bits of another
1606 // register (else it's a hi-bits-to-hi-bits copy which should have
1607 // happened already as part of a 64-bit move)
1608 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1609 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1610 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1611 // Shift src_second down to dst_second's low bits.
1612 if( cbuf ) {
1613 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1614 #ifndef PRODUCT
1615 } else if( !do_size ) {
1616 if( size != 0 ) st->print("\n\t");
1617 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1618 #endif
1619 }
1620 return size+4;
1621 }
1622
1623 // Check for high word integer store. Must down-shift the hi bits
1624 // into a temp register, then fall into the case of storing int bits.
1625 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1626 // Shift src_second down to dst_second's low bits.
1627 if( cbuf ) {
1628 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1629 #ifndef PRODUCT
1630 } else if( !do_size ) {
1631 if( size != 0 ) st->print("\n\t");
1632 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1633 #endif
1634 }
1635 size+=4;
1636 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1637 }
1638
1639 // Check for high word integer load
1640 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1641 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1642
1643 // Check for high word integer store
1644 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1645 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1646
1647 // Check for high word float store
1648 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1650
1651 #endif // !_LP64
1652
1653 Unimplemented();
1654 }
1655
1656 #ifndef PRODUCT
1657 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 implementation( NULL, ra_, false, st );
1659 }
1660 #endif
1661
1662 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1663 implementation( &cbuf, ra_, false, NULL );
1664 }
1665
1666 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1667 return implementation( NULL, ra_, true, NULL );
1668 }
1669
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1673 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1674 }
1675 #endif
1676
1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1678 MacroAssembler _masm(&cbuf);
1679 for(int i = 0; i < _count; i += 1) {
1680 __ nop();
1681 }
1682 }
1683
1684 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1685 return 4 * _count;
1686 }
1687
1688
1689 //=============================================================================
1690 #ifndef PRODUCT
1691 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1692 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1693 int reg = ra_->get_reg_first(this);
1694 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1695 }
1696 #endif
1697
1698 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1699 MacroAssembler _masm(&cbuf);
1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1701 int reg = ra_->get_encode(this);
1702
1703 if (Assembler::is_simm13(offset)) {
1704 __ add(SP, offset, reg_to_register_object(reg));
1705 } else {
1706 __ set(offset, O7);
1707 __ add(SP, O7, reg_to_register_object(reg));
1708 }
1709 }
1710
1711 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1712 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1713 assert(ra_ == ra_->C->regalloc(), "sanity");
1714 return ra_->C->scratch_emit_size(this);
1715 }
1716
1717 //=============================================================================
1718 #ifndef PRODUCT
1719 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1720 st->print_cr("\nUEP:");
1721 #ifdef _LP64
1722 if (UseCompressedClassPointers) {
1723 assert(Universe::heap() != NULL, "java heap should be initialized");
1724 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1725 if (Universe::narrow_klass_base() != 0) {
1726 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1727 if (Universe::narrow_klass_shift() != 0) {
1728 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1729 }
1730 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1731 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1732 } else {
1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1734 }
1735 } else {
1736 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1737 }
1738 st->print_cr("\tCMP R_G5,R_G3" );
1739 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1740 #else // _LP64
1741 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1742 st->print_cr("\tCMP R_G5,R_G3" );
1743 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1744 #endif // _LP64
1745 }
1746 #endif
1747
1748 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1749 MacroAssembler _masm(&cbuf);
1750 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1751 Register temp_reg = G3;
1752 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1753
1754 // Load klass from receiver
1755 __ load_klass(O0, temp_reg);
1756 // Compare against expected klass
1757 __ cmp(temp_reg, G5_ic_reg);
1758 // Branch to miss code, checks xcc or icc depending
1759 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1760 }
1761
1762 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1763 return MachNode::size(ra_);
1764 }
1765
1766
1767 //=============================================================================
1768
1769
1770 // Emit exception handler code.
1771 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1772 Register temp_reg = G3;
1773 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1774 MacroAssembler _masm(&cbuf);
1775
1776 address base = __ start_a_stub(size_exception_handler());
1777 if (base == NULL) {
1778 ciEnv::current()->record_failure("CodeCache is full");
1779 return 0; // CodeBuffer::expand failed
1780 }
1781
1782 int offset = __ offset();
1783
1784 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1785 __ delayed()->nop();
1786
1787 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1788
1789 __ end_a_stub();
1790
1791 return offset;
1792 }
1793
1794 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1795 // Can't use any of the current frame's registers as we may have deopted
1796 // at a poll and everything (including G3) can be live.
1797 Register temp_reg = L0;
1798 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1799 MacroAssembler _masm(&cbuf);
1800
1801 address base = __ start_a_stub(size_deopt_handler());
1802 if (base == NULL) {
1803 ciEnv::current()->record_failure("CodeCache is full");
1804 return 0; // CodeBuffer::expand failed
1805 }
1806
1807 int offset = __ offset();
1808 __ save_frame(0);
1809 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1810 __ delayed()->restore();
1811
1812 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1813
1814 __ end_a_stub();
1815 return offset;
1816
1817 }
1818
1819 // Given a register encoding, produce a Integer Register object
1820 static Register reg_to_register_object(int register_encoding) {
1821 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1822 return as_Register(register_encoding);
1823 }
1824
1825 // Given a register encoding, produce a single-precision Float Register object
1826 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1827 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1828 return as_SingleFloatRegister(register_encoding);
1829 }
1830
1831 // Given a register encoding, produce a double-precision Float Register object
1832 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1833 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1834 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1835 return as_DoubleFloatRegister(register_encoding);
1836 }
1837
1838 const bool Matcher::match_rule_supported(int opcode) {
1839 if (!has_match_rule(opcode))
1840 return false;
1841
1842 switch (opcode) {
1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 int Matcher::regnum_to_fpu_offset(int regnum) {
1864 return regnum - 32; // The FP registers are in the second chunk
1865 }
1866
1867 #ifdef ASSERT
1868 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1869 #endif
1870
1871 // Vector width in bytes
1872 const int Matcher::vector_width_in_bytes(BasicType bt) {
1873 assert(MaxVectorSize == 8, "");
1874 return 8;
1875 }
1876
1877 // Vector ideal reg
1878 const int Matcher::vector_ideal_reg(int size) {
1879 assert(MaxVectorSize == 8, "");
1880 return Op_RegD;
1881 }
1882
1883 const int Matcher::vector_shift_count_ideal_reg(int size) {
1884 fatal("vector shift is not supported");
1885 return Node::NotAMachineReg;
1886 }
1887
1888 // Limits on vector size (number of elements) loaded into vector.
1889 const int Matcher::max_vector_size(const BasicType bt) {
1890 assert(is_java_primitive(bt), "only primitive type vectors");
1891 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1892 }
1893
1894 const int Matcher::min_vector_size(const BasicType bt) {
1895 return max_vector_size(bt); // Same as max.
1896 }
1897
1898 // SPARC doesn't support misaligned vectors store/load.
1899 const bool Matcher::misaligned_vectors_ok() {
1900 return false;
1901 }
1902
1903 // Current (2013) SPARC platforms need to read original key
1904 // to construct decryption expanded key
1905 const bool Matcher::pass_original_key_for_aes() {
1906 return true;
1907 }
1908
1909 // USII supports fxtof through the whole range of number, USIII doesn't
1910 const bool Matcher::convL2FSupported(void) {
1911 return VM_Version::has_fast_fxtof();
1912 }
1913
1914 // Is this branch offset short enough that a short branch can be used?
1915 //
1916 // NOTE: If the platform does not provide any short branch variants, then
1917 // this method should return false for offset 0.
1918 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1919 // The passed offset is relative to address of the branch.
1920 // Don't need to adjust the offset.
1921 return UseCBCond && Assembler::is_simm12(offset);
1922 }
1923
1924 const bool Matcher::isSimpleConstant64(jlong value) {
1925 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1926 // Depends on optimizations in MacroAssembler::setx.
1927 int hi = (int)(value >> 32);
1928 int lo = (int)(value & ~0);
1929 return (hi == 0) || (hi == -1) || (lo == 0);
1930 }
1931
1932 // No scaling for the parameter the ClearArray node.
1933 const bool Matcher::init_array_count_is_in_bytes = true;
1934
1935 // Threshold size for cleararray.
1936 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1937
1938 // No additional cost for CMOVL.
1939 const int Matcher::long_cmove_cost() { return 0; }
1940
1941 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1942 const int Matcher::float_cmove_cost() {
1943 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1944 }
1945
1946 // Does the CPU require late expand (see block.cpp for description of late expand)?
1947 const bool Matcher::require_postalloc_expand = false;
1948
1949 // Should the Matcher clone shifts on addressing modes, expecting them to
1950 // be subsumed into complex addressing expressions or compute them into
1951 // registers? True for Intel but false for most RISCs
1952 const bool Matcher::clone_shift_expressions = false;
1953
1954 // Do we need to mask the count passed to shift instructions or does
1955 // the cpu only look at the lower 5/6 bits anyway?
1956 const bool Matcher::need_masked_shift_count = false;
1957
1958 bool Matcher::narrow_oop_use_complex_address() {
1959 NOT_LP64(ShouldNotCallThis());
1960 assert(UseCompressedOops, "only for compressed oops code");
1961 return false;
1962 }
1963
1964 bool Matcher::narrow_klass_use_complex_address() {
1965 NOT_LP64(ShouldNotCallThis());
1966 assert(UseCompressedClassPointers, "only for compressed klass code");
1967 return false;
1968 }
1969
1970 // Is it better to copy float constants, or load them directly from memory?
1971 // Intel can load a float constant from a direct address, requiring no
1972 // extra registers. Most RISCs will have to materialize an address into a
1973 // register first, so they would do better to copy the constant from stack.
1974 const bool Matcher::rematerialize_float_constants = false;
1975
1976 // If CPU can load and store mis-aligned doubles directly then no fixup is
1977 // needed. Else we split the double into 2 integer pieces and move it
1978 // piece-by-piece. Only happens when passing doubles into C code as the
1979 // Java calling convention forces doubles to be aligned.
1980 #ifdef _LP64
1981 const bool Matcher::misaligned_doubles_ok = true;
1982 #else
1983 const bool Matcher::misaligned_doubles_ok = false;
1984 #endif
1985
1986 // No-op on SPARC.
1987 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1988 }
1989
1990 // Advertise here if the CPU requires explicit rounding operations
1991 // to implement the UseStrictFP mode.
1992 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1993
1994 // Are floats converted to double when stored to stack during deoptimization?
1995 // Sparc does not handle callee-save floats.
1996 bool Matcher::float_in_double() { return false; }
1997
1998 // Do ints take an entire long register or just half?
1999 // Note that we if-def off of _LP64.
2000 // The relevant question is how the int is callee-saved. In _LP64
2001 // the whole long is written but de-opt'ing will have to extract
2002 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2003 #ifdef _LP64
2004 const bool Matcher::int_in_long = true;
2005 #else
2006 const bool Matcher::int_in_long = false;
2007 #endif
2008
2009 // Return whether or not this register is ever used as an argument. This
2010 // function is used on startup to build the trampoline stubs in generateOptoStub.
2011 // Registers not mentioned will be killed by the VM call in the trampoline, and
2012 // arguments in those registers not be available to the callee.
2013 bool Matcher::can_be_java_arg( int reg ) {
2014 // Standard sparc 6 args in registers
2015 if( reg == R_I0_num ||
2016 reg == R_I1_num ||
2017 reg == R_I2_num ||
2018 reg == R_I3_num ||
2019 reg == R_I4_num ||
2020 reg == R_I5_num ) return true;
2021 #ifdef _LP64
2022 // 64-bit builds can pass 64-bit pointers and longs in
2023 // the high I registers
2024 if( reg == R_I0H_num ||
2025 reg == R_I1H_num ||
2026 reg == R_I2H_num ||
2027 reg == R_I3H_num ||
2028 reg == R_I4H_num ||
2029 reg == R_I5H_num ) return true;
2030
2031 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2032 return true;
2033 }
2034
2035 #else
2036 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2037 // Longs cannot be passed in O regs, because O regs become I regs
2038 // after a 'save' and I regs get their high bits chopped off on
2039 // interrupt.
2040 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2041 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2042 #endif
2043 // A few float args in registers
2044 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2045
2046 return false;
2047 }
2048
2049 bool Matcher::is_spillable_arg( int reg ) {
2050 return can_be_java_arg(reg);
2051 }
2052
2053 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2054 // Use hardware SDIVX instruction when it is
2055 // faster than a code which use multiply.
2056 return VM_Version::has_fast_idiv();
2057 }
2058
2059 // Register for DIVI projection of divmodI
2060 RegMask Matcher::divI_proj_mask() {
2061 ShouldNotReachHere();
2062 return RegMask();
2063 }
2064
2065 // Register for MODI projection of divmodI
2066 RegMask Matcher::modI_proj_mask() {
2067 ShouldNotReachHere();
2068 return RegMask();
2069 }
2070
2071 // Register for DIVL projection of divmodL
2072 RegMask Matcher::divL_proj_mask() {
2073 ShouldNotReachHere();
2074 return RegMask();
2075 }
2076
2077 // Register for MODL projection of divmodL
2078 RegMask Matcher::modL_proj_mask() {
2079 ShouldNotReachHere();
2080 return RegMask();
2081 }
2082
2083 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2084 return L7_REGP_mask();
2085 }
2086
2087 %}
2088
2089
2090 // The intptr_t operand types, defined by textual substitution.
2091 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2092 #ifdef _LP64
2093 #define immX immL
2094 #define immX13 immL13
2095 #define immX13m7 immL13m7
2096 #define iRegX iRegL
2097 #define g1RegX g1RegL
2098 #else
2099 #define immX immI
2100 #define immX13 immI13
2101 #define immX13m7 immI13m7
2102 #define iRegX iRegI
2103 #define g1RegX g1RegI
2104 #endif
2105
2106 //----------ENCODING BLOCK-----------------------------------------------------
2107 // This block specifies the encoding classes used by the compiler to output
2108 // byte streams. Encoding classes are parameterized macros used by
2109 // Machine Instruction Nodes in order to generate the bit encoding of the
2110 // instruction. Operands specify their base encoding interface with the
2111 // interface keyword. There are currently supported four interfaces,
2112 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2113 // operand to generate a function which returns its register number when
2114 // queried. CONST_INTER causes an operand to generate a function which
2115 // returns the value of the constant when queried. MEMORY_INTER causes an
2116 // operand to generate four functions which return the Base Register, the
2117 // Index Register, the Scale Value, and the Offset Value of the operand when
2118 // queried. COND_INTER causes an operand to generate six functions which
2119 // return the encoding code (ie - encoding bits for the instruction)
2120 // associated with each basic boolean condition for a conditional instruction.
2121 //
2122 // Instructions specify two basic values for encoding. Again, a function
2123 // is available to check if the constant displacement is an oop. They use the
2124 // ins_encode keyword to specify their encoding classes (which must be
2125 // a sequence of enc_class names, and their parameters, specified in
2126 // the encoding block), and they use the
2127 // opcode keyword to specify, in order, their primary, secondary, and
2128 // tertiary opcode. Only the opcode sections which a particular instruction
2129 // needs for encoding need to be specified.
2130 encode %{
2131 enc_class enc_untested %{
2132 #ifdef ASSERT
2133 MacroAssembler _masm(&cbuf);
2134 __ untested("encoding");
2135 #endif
2136 %}
2137
2138 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2139 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2140 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2141 %}
2142
2143 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2144 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2145 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2146 %}
2147
2148 enc_class form3_mem_prefetch_read( memory mem ) %{
2149 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2150 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2151 %}
2152
2153 enc_class form3_mem_prefetch_write( memory mem ) %{
2154 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2155 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2156 %}
2157
2158 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2159 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2160 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2161 guarantee($mem$$index == R_G0_enc, "double index?");
2162 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2163 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2164 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2165 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2166 %}
2167
2168 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2169 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2170 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2171 guarantee($mem$$index == R_G0_enc, "double index?");
2172 // Load long with 2 instructions
2173 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2174 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2175 %}
2176
2177 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2178 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2179 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2180 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2181 %}
2182
2183 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2184 // Encode a reg-reg copy. If it is useless, then empty encoding.
2185 if( $rs2$$reg != $rd$$reg )
2186 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2187 %}
2188
2189 // Target lo half of long
2190 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2191 // Encode a reg-reg copy. If it is useless, then empty encoding.
2192 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2193 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2194 %}
2195
2196 // Source lo half of long
2197 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2198 // Encode a reg-reg copy. If it is useless, then empty encoding.
2199 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2200 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2201 %}
2202
2203 // Target hi half of long
2204 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2205 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2206 %}
2207
2208 // Source lo half of long, and leave it sign extended.
2209 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2210 // Sign extend low half
2211 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2212 %}
2213
2214 // Source hi half of long, and leave it sign extended.
2215 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2216 // Shift high half to low half
2217 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2218 %}
2219
2220 // Source hi half of long
2221 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2222 // Encode a reg-reg copy. If it is useless, then empty encoding.
2223 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2224 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2225 %}
2226
2227 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2228 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2229 %}
2230
2231 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2232 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2233 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2234 %}
2235
2236 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2237 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2238 // clear if nothing else is happening
2239 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2240 // blt,a,pn done
2241 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2242 // mov dst,-1 in delay slot
2243 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2244 %}
2245
2246 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2247 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2248 %}
2249
2250 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2251 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2252 %}
2253
2254 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2255 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2256 %}
2257
2258 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2259 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2260 %}
2261
2262 enc_class move_return_pc_to_o1() %{
2263 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2264 %}
2265
2266 #ifdef _LP64
2267 /* %%% merge with enc_to_bool */
2268 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2269 MacroAssembler _masm(&cbuf);
2270
2271 Register src_reg = reg_to_register_object($src$$reg);
2272 Register dst_reg = reg_to_register_object($dst$$reg);
2273 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2274 %}
2275 #endif
2276
2277 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2278 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2279 MacroAssembler _masm(&cbuf);
2280
2281 Register p_reg = reg_to_register_object($p$$reg);
2282 Register q_reg = reg_to_register_object($q$$reg);
2283 Register y_reg = reg_to_register_object($y$$reg);
2284 Register tmp_reg = reg_to_register_object($tmp$$reg);
2285
2286 __ subcc( p_reg, q_reg, p_reg );
2287 __ add ( p_reg, y_reg, tmp_reg );
2288 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2289 %}
2290
2291 enc_class form_d2i_helper(regD src, regF dst) %{
2292 // fcmp %fcc0,$src,$src
2293 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2294 // branch %fcc0 not-nan, predict taken
2295 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2296 // fdtoi $src,$dst
2297 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2298 // fitos $dst,$dst (if nan)
2299 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2300 // clear $dst (if nan)
2301 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2302 // carry on here...
2303 %}
2304
2305 enc_class form_d2l_helper(regD src, regD dst) %{
2306 // fcmp %fcc0,$src,$src check for NAN
2307 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2308 // branch %fcc0 not-nan, predict taken
2309 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2310 // fdtox $src,$dst convert in delay slot
2311 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2312 // fxtod $dst,$dst (if nan)
2313 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2314 // clear $dst (if nan)
2315 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2316 // carry on here...
2317 %}
2318
2319 enc_class form_f2i_helper(regF src, regF dst) %{
2320 // fcmps %fcc0,$src,$src
2321 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2322 // branch %fcc0 not-nan, predict taken
2323 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2324 // fstoi $src,$dst
2325 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2326 // fitos $dst,$dst (if nan)
2327 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2328 // clear $dst (if nan)
2329 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2330 // carry on here...
2331 %}
2332
2333 enc_class form_f2l_helper(regF src, regD dst) %{
2334 // fcmps %fcc0,$src,$src
2335 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2336 // branch %fcc0 not-nan, predict taken
2337 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2338 // fstox $src,$dst
2339 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2340 // fxtod $dst,$dst (if nan)
2341 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2342 // clear $dst (if nan)
2343 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2344 // carry on here...
2345 %}
2346
2347 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2348 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2349 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2350 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2351
2352 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2353
2354 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2355 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2356
2357 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2358 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2359 %}
2360
2361 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2362 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2363 %}
2364
2365 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2366 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2367 %}
2368
2369 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2370 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2371 %}
2372
2373 enc_class form3_convI2F(regF rs2, regF rd) %{
2374 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2375 %}
2376
2377 // Encloding class for traceable jumps
2378 enc_class form_jmpl(g3RegP dest) %{
2379 emit_jmpl(cbuf, $dest$$reg);
2380 %}
2381
2382 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2383 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2384 %}
2385
2386 enc_class form2_nop() %{
2387 emit_nop(cbuf);
2388 %}
2389
2390 enc_class form2_illtrap() %{
2391 emit_illtrap(cbuf);
2392 %}
2393
2394
2395 // Compare longs and convert into -1, 0, 1.
2396 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2397 // CMP $src1,$src2
2398 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2399 // blt,a,pn done
2400 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2401 // mov dst,-1 in delay slot
2402 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2403 // bgt,a,pn done
2404 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2405 // mov dst,1 in delay slot
2406 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2407 // CLR $dst
2408 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2409 %}
2410
2411 enc_class enc_PartialSubtypeCheck() %{
2412 MacroAssembler _masm(&cbuf);
2413 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2414 __ delayed()->nop();
2415 %}
2416
2417 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2418 MacroAssembler _masm(&cbuf);
2419 Label* L = $labl$$label;
2420 Assembler::Predict predict_taken =
2421 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2422
2423 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2424 __ delayed()->nop();
2425 %}
2426
2427 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2428 MacroAssembler _masm(&cbuf);
2429 Label* L = $labl$$label;
2430 Assembler::Predict predict_taken =
2431 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2432
2433 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2434 __ delayed()->nop();
2435 %}
2436
2437 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2438 int op = (Assembler::arith_op << 30) |
2439 ($dst$$reg << 25) |
2440 (Assembler::movcc_op3 << 19) |
2441 (1 << 18) | // cc2 bit for 'icc'
2442 ($cmp$$cmpcode << 14) |
2443 (0 << 13) | // select register move
2444 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2445 ($src$$reg << 0);
2446 cbuf.insts()->emit_int32(op);
2447 %}
2448
2449 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2450 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2451 int op = (Assembler::arith_op << 30) |
2452 ($dst$$reg << 25) |
2453 (Assembler::movcc_op3 << 19) |
2454 (1 << 18) | // cc2 bit for 'icc'
2455 ($cmp$$cmpcode << 14) |
2456 (1 << 13) | // select immediate move
2457 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2458 (simm11 << 0);
2459 cbuf.insts()->emit_int32(op);
2460 %}
2461
2462 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2463 int op = (Assembler::arith_op << 30) |
2464 ($dst$$reg << 25) |
2465 (Assembler::movcc_op3 << 19) |
2466 (0 << 18) | // cc2 bit for 'fccX'
2467 ($cmp$$cmpcode << 14) |
2468 (0 << 13) | // select register move
2469 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2470 ($src$$reg << 0);
2471 cbuf.insts()->emit_int32(op);
2472 %}
2473
2474 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2475 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2476 int op = (Assembler::arith_op << 30) |
2477 ($dst$$reg << 25) |
2478 (Assembler::movcc_op3 << 19) |
2479 (0 << 18) | // cc2 bit for 'fccX'
2480 ($cmp$$cmpcode << 14) |
2481 (1 << 13) | // select immediate move
2482 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2483 (simm11 << 0);
2484 cbuf.insts()->emit_int32(op);
2485 %}
2486
2487 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2488 int op = (Assembler::arith_op << 30) |
2489 ($dst$$reg << 25) |
2490 (Assembler::fpop2_op3 << 19) |
2491 (0 << 18) |
2492 ($cmp$$cmpcode << 14) |
2493 (1 << 13) | // select register move
2494 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2495 ($primary << 5) | // select single, double or quad
2496 ($src$$reg << 0);
2497 cbuf.insts()->emit_int32(op);
2498 %}
2499
2500 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2501 int op = (Assembler::arith_op << 30) |
2502 ($dst$$reg << 25) |
2503 (Assembler::fpop2_op3 << 19) |
2504 (0 << 18) |
2505 ($cmp$$cmpcode << 14) |
2506 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2507 ($primary << 5) | // select single, double or quad
2508 ($src$$reg << 0);
2509 cbuf.insts()->emit_int32(op);
2510 %}
2511
2512 // Used by the MIN/MAX encodings. Same as a CMOV, but
2513 // the condition comes from opcode-field instead of an argument.
2514 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2515 int op = (Assembler::arith_op << 30) |
2516 ($dst$$reg << 25) |
2517 (Assembler::movcc_op3 << 19) |
2518 (1 << 18) | // cc2 bit for 'icc'
2519 ($primary << 14) |
2520 (0 << 13) | // select register move
2521 (0 << 11) | // cc1, cc0 bits for 'icc'
2522 ($src$$reg << 0);
2523 cbuf.insts()->emit_int32(op);
2524 %}
2525
2526 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2527 int op = (Assembler::arith_op << 30) |
2528 ($dst$$reg << 25) |
2529 (Assembler::movcc_op3 << 19) |
2530 (6 << 16) | // cc2 bit for 'xcc'
2531 ($primary << 14) |
2532 (0 << 13) | // select register move
2533 (0 << 11) | // cc1, cc0 bits for 'icc'
2534 ($src$$reg << 0);
2535 cbuf.insts()->emit_int32(op);
2536 %}
2537
2538 enc_class Set13( immI13 src, iRegI rd ) %{
2539 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2540 %}
2541
2542 enc_class SetHi22( immI src, iRegI rd ) %{
2543 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2544 %}
2545
2546 enc_class Set32( immI src, iRegI rd ) %{
2547 MacroAssembler _masm(&cbuf);
2548 __ set($src$$constant, reg_to_register_object($rd$$reg));
2549 %}
2550
2551 enc_class call_epilog %{
2552 if( VerifyStackAtCalls ) {
2553 MacroAssembler _masm(&cbuf);
2554 int framesize = ra_->C->frame_size_in_bytes();
2555 Register temp_reg = G3;
2556 __ add(SP, framesize, temp_reg);
2557 __ cmp(temp_reg, FP);
2558 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2559 }
2560 %}
2561
2562 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2563 // to G1 so the register allocator will not have to deal with the misaligned register
2564 // pair.
2565 enc_class adjust_long_from_native_call %{
2566 #ifndef _LP64
2567 if (returns_long()) {
2568 // sllx O0,32,O0
2569 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2570 // srl O1,0,O1
2571 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2572 // or O0,O1,G1
2573 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2574 }
2575 #endif
2576 %}
2577
2578 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2579 // CALL directly to the runtime
2580 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2581 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2582 /*preserve_g2=*/true);
2583 %}
2584
2585 enc_class preserve_SP %{
2586 MacroAssembler _masm(&cbuf);
2587 __ mov(SP, L7_mh_SP_save);
2588 %}
2589
2590 enc_class restore_SP %{
2591 MacroAssembler _masm(&cbuf);
2592 __ mov(L7_mh_SP_save, SP);
2593 %}
2594
2595 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2596 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2597 // who we intended to call.
2598 if (!_method) {
2599 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2600 } else if (_optimized_virtual) {
2601 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2602 } else {
2603 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2604 }
2605 if (_method) { // Emit stub for static call.
2606 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2607 // Stub does not fit into scratch buffer if TraceJumps is enabled
2608 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2609 ciEnv::current()->record_failure("CodeCache is full");
2610 return;
2611 }
2612 }
2613 %}
2614
2615 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2616 MacroAssembler _masm(&cbuf);
2617 __ set_inst_mark();
2618 int vtable_index = this->_vtable_index;
2619 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2620 if (vtable_index < 0) {
2621 // must be invalid_vtable_index, not nonvirtual_vtable_index
2622 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2623 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2624 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2625 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2626 __ ic_call((address)$meth$$method);
2627 } else {
2628 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2629 // Just go thru the vtable
2630 // get receiver klass (receiver already checked for non-null)
2631 // If we end up going thru a c2i adapter interpreter expects method in G5
2632 int off = __ offset();
2633 __ load_klass(O0, G3_scratch);
2634 int klass_load_size;
2635 if (UseCompressedClassPointers) {
2636 assert(Universe::heap() != NULL, "java heap should be initialized");
2637 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2638 } else {
2639 klass_load_size = 1*BytesPerInstWord;
2640 }
2641 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2642 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2643 if (Assembler::is_simm13(v_off)) {
2644 __ ld_ptr(G3, v_off, G5_method);
2645 } else {
2646 // Generate 2 instructions
2647 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2648 __ or3(G5_method, v_off & 0x3ff, G5_method);
2649 // ld_ptr, set_hi, set
2650 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2651 "Unexpected instruction size(s)");
2652 __ ld_ptr(G3, G5_method, G5_method);
2653 }
2654 // NOTE: for vtable dispatches, the vtable entry will never be null.
2655 // However it may very well end up in handle_wrong_method if the
2656 // method is abstract for the particular class.
2657 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2658 // jump to target (either compiled code or c2iadapter)
2659 __ jmpl(G3_scratch, G0, O7);
2660 __ delayed()->nop();
2661 }
2662 %}
2663
2664 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2665 MacroAssembler _masm(&cbuf);
2666
2667 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2668 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2669 // we might be calling a C2I adapter which needs it.
2670
2671 assert(temp_reg != G5_ic_reg, "conflicting registers");
2672 // Load nmethod
2673 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2674
2675 // CALL to compiled java, indirect the contents of G3
2676 __ set_inst_mark();
2677 __ callr(temp_reg, G0);
2678 __ delayed()->nop();
2679 %}
2680
2681 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2682 MacroAssembler _masm(&cbuf);
2683 Register Rdividend = reg_to_register_object($src1$$reg);
2684 Register Rdivisor = reg_to_register_object($src2$$reg);
2685 Register Rresult = reg_to_register_object($dst$$reg);
2686
2687 __ sra(Rdivisor, 0, Rdivisor);
2688 __ sra(Rdividend, 0, Rdividend);
2689 __ sdivx(Rdividend, Rdivisor, Rresult);
2690 %}
2691
2692 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2693 MacroAssembler _masm(&cbuf);
2694
2695 Register Rdividend = reg_to_register_object($src1$$reg);
2696 int divisor = $imm$$constant;
2697 Register Rresult = reg_to_register_object($dst$$reg);
2698
2699 __ sra(Rdividend, 0, Rdividend);
2700 __ sdivx(Rdividend, divisor, Rresult);
2701 %}
2702
2703 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2704 MacroAssembler _masm(&cbuf);
2705 Register Rsrc1 = reg_to_register_object($src1$$reg);
2706 Register Rsrc2 = reg_to_register_object($src2$$reg);
2707 Register Rdst = reg_to_register_object($dst$$reg);
2708
2709 __ sra( Rsrc1, 0, Rsrc1 );
2710 __ sra( Rsrc2, 0, Rsrc2 );
2711 __ mulx( Rsrc1, Rsrc2, Rdst );
2712 __ srlx( Rdst, 32, Rdst );
2713 %}
2714
2715 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2716 MacroAssembler _masm(&cbuf);
2717 Register Rdividend = reg_to_register_object($src1$$reg);
2718 Register Rdivisor = reg_to_register_object($src2$$reg);
2719 Register Rresult = reg_to_register_object($dst$$reg);
2720 Register Rscratch = reg_to_register_object($scratch$$reg);
2721
2722 assert(Rdividend != Rscratch, "");
2723 assert(Rdivisor != Rscratch, "");
2724
2725 __ sra(Rdividend, 0, Rdividend);
2726 __ sra(Rdivisor, 0, Rdivisor);
2727 __ sdivx(Rdividend, Rdivisor, Rscratch);
2728 __ mulx(Rscratch, Rdivisor, Rscratch);
2729 __ sub(Rdividend, Rscratch, Rresult);
2730 %}
2731
2732 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2733 MacroAssembler _masm(&cbuf);
2734
2735 Register Rdividend = reg_to_register_object($src1$$reg);
2736 int divisor = $imm$$constant;
2737 Register Rresult = reg_to_register_object($dst$$reg);
2738 Register Rscratch = reg_to_register_object($scratch$$reg);
2739
2740 assert(Rdividend != Rscratch, "");
2741
2742 __ sra(Rdividend, 0, Rdividend);
2743 __ sdivx(Rdividend, divisor, Rscratch);
2744 __ mulx(Rscratch, divisor, Rscratch);
2745 __ sub(Rdividend, Rscratch, Rresult);
2746 %}
2747
2748 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2749 MacroAssembler _masm(&cbuf);
2750
2751 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2752 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2753
2754 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2755 %}
2756
2757 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2758 MacroAssembler _masm(&cbuf);
2759
2760 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2761 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2762
2763 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2764 %}
2765
2766 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2767 MacroAssembler _masm(&cbuf);
2768
2769 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2770 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2771
2772 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2773 %}
2774
2775 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2776 MacroAssembler _masm(&cbuf);
2777
2778 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2779 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2780
2781 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2782 %}
2783
2784 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2785 MacroAssembler _masm(&cbuf);
2786
2787 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2788 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2789
2790 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2791 %}
2792
2793 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2794 MacroAssembler _masm(&cbuf);
2795
2796 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2797 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2798
2799 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2800 %}
2801
2802 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2803 MacroAssembler _masm(&cbuf);
2804
2805 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2806 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2807
2808 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2809 %}
2810
2811 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2812 MacroAssembler _masm(&cbuf);
2813
2814 Register Roop = reg_to_register_object($oop$$reg);
2815 Register Rbox = reg_to_register_object($box$$reg);
2816 Register Rscratch = reg_to_register_object($scratch$$reg);
2817 Register Rmark = reg_to_register_object($scratch2$$reg);
2818
2819 assert(Roop != Rscratch, "");
2820 assert(Roop != Rmark, "");
2821 assert(Rbox != Rscratch, "");
2822 assert(Rbox != Rmark, "");
2823
2824 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2825 %}
2826
2827 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2828 MacroAssembler _masm(&cbuf);
2829
2830 Register Roop = reg_to_register_object($oop$$reg);
2831 Register Rbox = reg_to_register_object($box$$reg);
2832 Register Rscratch = reg_to_register_object($scratch$$reg);
2833 Register Rmark = reg_to_register_object($scratch2$$reg);
2834
2835 assert(Roop != Rscratch, "");
2836 assert(Roop != Rmark, "");
2837 assert(Rbox != Rscratch, "");
2838 assert(Rbox != Rmark, "");
2839
2840 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2841 %}
2842
2843 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2844 MacroAssembler _masm(&cbuf);
2845 Register Rmem = reg_to_register_object($mem$$reg);
2846 Register Rold = reg_to_register_object($old$$reg);
2847 Register Rnew = reg_to_register_object($new$$reg);
2848
2849 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2850 __ cmp( Rold, Rnew );
2851 %}
2852
2853 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2854 Register Rmem = reg_to_register_object($mem$$reg);
2855 Register Rold = reg_to_register_object($old$$reg);
2856 Register Rnew = reg_to_register_object($new$$reg);
2857
2858 MacroAssembler _masm(&cbuf);
2859 __ mov(Rnew, O7);
2860 __ casx(Rmem, Rold, O7);
2861 __ cmp( Rold, O7 );
2862 %}
2863
2864 // raw int cas, used for compareAndSwap
2865 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2866 Register Rmem = reg_to_register_object($mem$$reg);
2867 Register Rold = reg_to_register_object($old$$reg);
2868 Register Rnew = reg_to_register_object($new$$reg);
2869
2870 MacroAssembler _masm(&cbuf);
2871 __ mov(Rnew, O7);
2872 __ cas(Rmem, Rold, O7);
2873 __ cmp( Rold, O7 );
2874 %}
2875
2876 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2877 Register Rres = reg_to_register_object($res$$reg);
2878
2879 MacroAssembler _masm(&cbuf);
2880 __ mov(1, Rres);
2881 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2882 %}
2883
2884 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2885 Register Rres = reg_to_register_object($res$$reg);
2886
2887 MacroAssembler _masm(&cbuf);
2888 __ mov(1, Rres);
2889 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2890 %}
2891
2892 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2893 MacroAssembler _masm(&cbuf);
2894 Register Rdst = reg_to_register_object($dst$$reg);
2895 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2896 : reg_to_DoubleFloatRegister_object($src1$$reg);
2897 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2898 : reg_to_DoubleFloatRegister_object($src2$$reg);
2899
2900 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2901 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2902 %}
2903
2904
2905 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2906 Label Ldone, Lloop;
2907 MacroAssembler _masm(&cbuf);
2908
2909 Register str1_reg = reg_to_register_object($str1$$reg);
2910 Register str2_reg = reg_to_register_object($str2$$reg);
2911 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2912 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2913 Register result_reg = reg_to_register_object($result$$reg);
2914
2915 assert(result_reg != str1_reg &&
2916 result_reg != str2_reg &&
2917 result_reg != cnt1_reg &&
2918 result_reg != cnt2_reg ,
2919 "need different registers");
2920
2921 // Compute the minimum of the string lengths(str1_reg) and the
2922 // difference of the string lengths (stack)
2923
2924 // See if the lengths are different, and calculate min in str1_reg.
2925 // Stash diff in O7 in case we need it for a tie-breaker.
2926 Label Lskip;
2927 __ subcc(cnt1_reg, cnt2_reg, O7);
2928 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2929 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2930 // cnt2 is shorter, so use its count:
2931 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2932 __ bind(Lskip);
2933
2934 // reallocate cnt1_reg, cnt2_reg, result_reg
2935 // Note: limit_reg holds the string length pre-scaled by 2
2936 Register limit_reg = cnt1_reg;
2937 Register chr2_reg = cnt2_reg;
2938 Register chr1_reg = result_reg;
2939 // str{12} are the base pointers
2940
2941 // Is the minimum length zero?
2942 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2943 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2944 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2945
2946 // Load first characters
2947 __ lduh(str1_reg, 0, chr1_reg);
2948 __ lduh(str2_reg, 0, chr2_reg);
2949
2950 // Compare first characters
2951 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2952 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2953 assert(chr1_reg == result_reg, "result must be pre-placed");
2954 __ delayed()->nop();
2955
2956 {
2957 // Check after comparing first character to see if strings are equivalent
2958 Label LSkip2;
2959 // Check if the strings start at same location
2960 __ cmp(str1_reg, str2_reg);
2961 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2962 __ delayed()->nop();
2963
2964 // Check if the length difference is zero (in O7)
2965 __ cmp(G0, O7);
2966 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2967 __ delayed()->mov(G0, result_reg); // result is zero
2968
2969 // Strings might not be equal
2970 __ bind(LSkip2);
2971 }
2972
2973 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2974 __ signx(limit_reg);
2975
2976 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2977 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2978 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2979
2980 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2981 __ add(str1_reg, limit_reg, str1_reg);
2982 __ add(str2_reg, limit_reg, str2_reg);
2983 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2984
2985 // Compare the rest of the characters
2986 __ lduh(str1_reg, limit_reg, chr1_reg);
2987 __ bind(Lloop);
2988 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2989 __ lduh(str2_reg, limit_reg, chr2_reg);
2990 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2991 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2992 assert(chr1_reg == result_reg, "result must be pre-placed");
2993 __ delayed()->inccc(limit_reg, sizeof(jchar));
2994 // annul LDUH if branch is not taken to prevent access past end of string
2995 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2996 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2997
2998 // If strings are equal up to min length, return the length difference.
2999 __ mov(O7, result_reg);
3000
3001 // Otherwise, return the difference between the first mismatched chars.
3002 __ bind(Ldone);
3003 %}
3004
3005 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
3006 Label Lchar, Lchar_loop, Ldone;
3007 MacroAssembler _masm(&cbuf);
3008
3009 Register str1_reg = reg_to_register_object($str1$$reg);
3010 Register str2_reg = reg_to_register_object($str2$$reg);
3011 Register cnt_reg = reg_to_register_object($cnt$$reg);
3012 Register tmp1_reg = O7;
3013 Register result_reg = reg_to_register_object($result$$reg);
3014
3015 assert(result_reg != str1_reg &&
3016 result_reg != str2_reg &&
3017 result_reg != cnt_reg &&
3018 result_reg != tmp1_reg ,
3019 "need different registers");
3020
3021 __ cmp(str1_reg, str2_reg); //same char[] ?
3022 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3023 __ delayed()->add(G0, 1, result_reg);
3024
3025 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3026 __ delayed()->add(G0, 1, result_reg); // count == 0
3027
3028 //rename registers
3029 Register limit_reg = cnt_reg;
3030 Register chr1_reg = result_reg;
3031 Register chr2_reg = tmp1_reg;
3032
3033 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
3034 __ signx(limit_reg);
3035
3036 //check for alignment and position the pointers to the ends
3037 __ or3(str1_reg, str2_reg, chr1_reg);
3038 __ andcc(chr1_reg, 0x3, chr1_reg);
3039 // notZero means at least one not 4-byte aligned.
3040 // We could optimize the case when both arrays are not aligned
3041 // but it is not frequent case and it requires additional checks.
3042 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3043 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3044
3045 // Compare char[] arrays aligned to 4 bytes.
3046 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3047 chr1_reg, chr2_reg, Ldone);
3048 __ ba(Ldone);
3049 __ delayed()->add(G0, 1, result_reg);
3050
3051 // char by char compare
3052 __ bind(Lchar);
3053 __ add(str1_reg, limit_reg, str1_reg);
3054 __ add(str2_reg, limit_reg, str2_reg);
3055 __ neg(limit_reg); //negate count
3056
3057 __ lduh(str1_reg, limit_reg, chr1_reg);
3058 // Lchar_loop
3059 __ bind(Lchar_loop);
3060 __ lduh(str2_reg, limit_reg, chr2_reg);
3061 __ cmp(chr1_reg, chr2_reg);
3062 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3063 __ delayed()->mov(G0, result_reg); //not equal
3064 __ inccc(limit_reg, sizeof(jchar));
3065 // annul LDUH if branch is not taken to prevent access past end of string
3066 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3067 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3068
3069 __ add(G0, 1, result_reg); //equal
3070
3071 __ bind(Ldone);
3072 %}
3073
3074 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3075 Label Lvector, Ldone, Lloop;
3076 MacroAssembler _masm(&cbuf);
3077
3078 Register ary1_reg = reg_to_register_object($ary1$$reg);
3079 Register ary2_reg = reg_to_register_object($ary2$$reg);
3080 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3081 Register tmp2_reg = O7;
3082 Register result_reg = reg_to_register_object($result$$reg);
3083
3084 int length_offset = arrayOopDesc::length_offset_in_bytes();
3085 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3086
3087 // return true if the same array
3088 __ cmp(ary1_reg, ary2_reg);
3089 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3090 __ delayed()->add(G0, 1, result_reg); // equal
3091
3092 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3093 __ delayed()->mov(G0, result_reg); // not equal
3094
3095 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3096 __ delayed()->mov(G0, result_reg); // not equal
3097
3098 //load the lengths of arrays
3099 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3100 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3101
3102 // return false if the two arrays are not equal length
3103 __ cmp(tmp1_reg, tmp2_reg);
3104 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3105 __ delayed()->mov(G0, result_reg); // not equal
3106
3107 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3108 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3109
3110 // load array addresses
3111 __ add(ary1_reg, base_offset, ary1_reg);
3112 __ add(ary2_reg, base_offset, ary2_reg);
3113
3114 // renaming registers
3115 Register chr1_reg = result_reg; // for characters in ary1
3116 Register chr2_reg = tmp2_reg; // for characters in ary2
3117 Register limit_reg = tmp1_reg; // length
3118
3119 // set byte count
3120 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3121
3122 // Compare char[] arrays aligned to 4 bytes.
3123 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3124 chr1_reg, chr2_reg, Ldone);
3125 __ add(G0, 1, result_reg); // equals
3126
3127 __ bind(Ldone);
3128 %}
3129
3130 enc_class enc_rethrow() %{
3131 cbuf.set_insts_mark();
3132 Register temp_reg = G3;
3133 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3134 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3135 MacroAssembler _masm(&cbuf);
3136 #ifdef ASSERT
3137 __ save_frame(0);
3138 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3139 __ sethi(last_rethrow_addrlit, L1);
3140 Address addr(L1, last_rethrow_addrlit.low10());
3141 __ rdpc(L2);
3142 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3143 __ st_ptr(L2, addr);
3144 __ restore();
3145 #endif
3146 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3147 __ delayed()->nop();
3148 %}
3149
3150 enc_class emit_mem_nop() %{
3151 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3152 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3153 %}
3154
3155 enc_class emit_fadd_nop() %{
3156 // Generates the instruction FMOVS f31,f31
3157 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3158 %}
3159
3160 enc_class emit_br_nop() %{
3161 // Generates the instruction BPN,PN .
3162 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3163 %}
3164
3165 enc_class enc_membar_acquire %{
3166 MacroAssembler _masm(&cbuf);
3167 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3168 %}
3169
3170 enc_class enc_membar_release %{
3171 MacroAssembler _masm(&cbuf);
3172 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3173 %}
3174
3175 enc_class enc_membar_volatile %{
3176 MacroAssembler _masm(&cbuf);
3177 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3178 %}
3179
3180 %}
3181
3182 //----------FRAME--------------------------------------------------------------
3183 // Definition of frame structure and management information.
3184 //
3185 // S T A C K L A Y O U T Allocators stack-slot number
3186 // | (to get allocators register number
3187 // G Owned by | | v add VMRegImpl::stack0)
3188 // r CALLER | |
3189 // o | +--------+ pad to even-align allocators stack-slot
3190 // w V | pad0 | numbers; owned by CALLER
3191 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3192 // h ^ | in | 5
3193 // | | args | 4 Holes in incoming args owned by SELF
3194 // | | | | 3
3195 // | | +--------+
3196 // V | | old out| Empty on Intel, window on Sparc
3197 // | old |preserve| Must be even aligned.
3198 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3199 // | | in | 3 area for Intel ret address
3200 // Owned by |preserve| Empty on Sparc.
3201 // SELF +--------+
3202 // | | pad2 | 2 pad to align old SP
3203 // | +--------+ 1
3204 // | | locks | 0
3205 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3206 // | | pad1 | 11 pad to align new SP
3207 // | +--------+
3208 // | | | 10
3209 // | | spills | 9 spills
3210 // V | | 8 (pad0 slot for callee)
3211 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3212 // ^ | out | 7
3213 // | | args | 6 Holes in outgoing args owned by CALLEE
3214 // Owned by +--------+
3215 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3216 // | new |preserve| Must be even-aligned.
3217 // | SP-+--------+----> Matcher::_new_SP, even aligned
3218 // | | |
3219 //
3220 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3221 // known from SELF's arguments and the Java calling convention.
3222 // Region 6-7 is determined per call site.
3223 // Note 2: If the calling convention leaves holes in the incoming argument
3224 // area, those holes are owned by SELF. Holes in the outgoing area
3225 // are owned by the CALLEE. Holes should not be nessecary in the
3226 // incoming area, as the Java calling convention is completely under
3227 // the control of the AD file. Doubles can be sorted and packed to
3228 // avoid holes. Holes in the outgoing arguments may be necessary for
3229 // varargs C calling conventions.
3230 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3231 // even aligned with pad0 as needed.
3232 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3233 // region 6-11 is even aligned; it may be padded out more so that
3234 // the region from SP to FP meets the minimum stack alignment.
3235
3236 frame %{
3237 // What direction does stack grow in (assumed to be same for native & Java)
3238 stack_direction(TOWARDS_LOW);
3239
3240 // These two registers define part of the calling convention
3241 // between compiled code and the interpreter.
3242 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3243 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3244
3245 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3246 cisc_spilling_operand_name(indOffset);
3247
3248 // Number of stack slots consumed by a Monitor enter
3249 #ifdef _LP64
3250 sync_stack_slots(2);
3251 #else
3252 sync_stack_slots(1);
3253 #endif
3254
3255 // Compiled code's Frame Pointer
3256 frame_pointer(R_SP);
3257
3258 // Stack alignment requirement
3259 stack_alignment(StackAlignmentInBytes);
3260 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3261 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3262
3263 // Number of stack slots between incoming argument block and the start of
3264 // a new frame. The PROLOG must add this many slots to the stack. The
3265 // EPILOG must remove this many slots.
3266 in_preserve_stack_slots(0);
3267
3268 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3269 // for calls to C. Supports the var-args backing area for register parms.
3270 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3271 #ifdef _LP64
3272 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3273 varargs_C_out_slots_killed(12);
3274 #else
3275 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3276 varargs_C_out_slots_killed( 7);
3277 #endif
3278
3279 // The after-PROLOG location of the return address. Location of
3280 // return address specifies a type (REG or STACK) and a number
3281 // representing the register number (i.e. - use a register name) or
3282 // stack slot.
3283 return_addr(REG R_I7); // Ret Addr is in register I7
3284
3285 // Body of function which returns an OptoRegs array locating
3286 // arguments either in registers or in stack slots for calling
3287 // java
3288 calling_convention %{
3289 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3290
3291 %}
3292
3293 // Body of function which returns an OptoRegs array locating
3294 // arguments either in registers or in stack slots for calling
3295 // C.
3296 c_calling_convention %{
3297 // This is obviously always outgoing
3298 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3299 %}
3300
3301 // Location of native (C/C++) and interpreter return values. This is specified to
3302 // be the same as Java. In the 32-bit VM, long values are actually returned from
3303 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3304 // to and from the register pairs is done by the appropriate call and epilog
3305 // opcodes. This simplifies the register allocator.
3306 c_return_value %{
3307 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3308 #ifdef _LP64
3309 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3310 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3311 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3312 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3313 #else // !_LP64
3314 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3315 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3316 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3317 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3318 #endif
3319 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3320 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3321 %}
3322
3323 // Location of compiled Java return values. Same as C
3324 return_value %{
3325 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3326 #ifdef _LP64
3327 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3328 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3329 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3330 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3331 #else // !_LP64
3332 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3333 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3334 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3335 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3336 #endif
3337 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3338 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3339 %}
3340
3341 %}
3342
3343
3344 //----------ATTRIBUTES---------------------------------------------------------
3345 //----------Operand Attributes-------------------------------------------------
3346 op_attrib op_cost(1); // Required cost attribute
3347
3348 //----------Instruction Attributes---------------------------------------------
3349 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3350 ins_attrib ins_size(32); // Required size attribute (in bits)
3351
3352 // avoid_back_to_back attribute is an expression that must return
3353 // one of the following values defined in MachNode:
3354 // AVOID_NONE - instruction can be placed anywhere
3355 // AVOID_BEFORE - instruction cannot be placed after an
3356 // instruction with MachNode::AVOID_AFTER
3357 // AVOID_AFTER - the next instruction cannot be the one
3358 // with MachNode::AVOID_BEFORE
3359 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3360 // the same time
3361 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3362
3363 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3364 // non-matching short branch variant of some
3365 // long branch?
3366
3367 //----------OPERANDS-----------------------------------------------------------
3368 // Operand definitions must precede instruction definitions for correct parsing
3369 // in the ADLC because operands constitute user defined types which are used in
3370 // instruction definitions.
3371
3372 //----------Simple Operands----------------------------------------------------
3373 // Immediate Operands
3374 // Integer Immediate: 32-bit
3375 operand immI() %{
3376 match(ConI);
3377
3378 op_cost(0);
3379 // formats are generated automatically for constants and base registers
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Integer Immediate: 0-bit
3385 operand immI0() %{
3386 predicate(n->get_int() == 0);
3387 match(ConI);
3388 op_cost(0);
3389
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Integer Immediate: 5-bit
3395 operand immI5() %{
3396 predicate(Assembler::is_simm5(n->get_int()));
3397 match(ConI);
3398 op_cost(0);
3399 format %{ %}
3400 interface(CONST_INTER);
3401 %}
3402
3403 // Integer Immediate: 8-bit
3404 operand immI8() %{
3405 predicate(Assembler::is_simm8(n->get_int()));
3406 match(ConI);
3407 op_cost(0);
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3411
3412 // Integer Immediate: the value 10
3413 operand immI10() %{
3414 predicate(n->get_int() == 10);
3415 match(ConI);
3416 op_cost(0);
3417
3418 format %{ %}
3419 interface(CONST_INTER);
3420 %}
3421
3422 // Integer Immediate: 11-bit
3423 operand immI11() %{
3424 predicate(Assembler::is_simm11(n->get_int()));
3425 match(ConI);
3426 op_cost(0);
3427 format %{ %}
3428 interface(CONST_INTER);
3429 %}
3430
3431 // Integer Immediate: 13-bit
3432 operand immI13() %{
3433 predicate(Assembler::is_simm13(n->get_int()));
3434 match(ConI);
3435 op_cost(0);
3436
3437 format %{ %}
3438 interface(CONST_INTER);
3439 %}
3440
3441 // Integer Immediate: 13-bit minus 7
3442 operand immI13m7() %{
3443 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3444 match(ConI);
3445 op_cost(0);
3446
3447 format %{ %}
3448 interface(CONST_INTER);
3449 %}
3450
3451 // Integer Immediate: 16-bit
3452 operand immI16() %{
3453 predicate(Assembler::is_simm16(n->get_int()));
3454 match(ConI);
3455 op_cost(0);
3456 format %{ %}
3457 interface(CONST_INTER);
3458 %}
3459
3460 // Integer Immediate: the values 1-31
3461 operand immI_1_31() %{
3462 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3463 match(ConI);
3464 op_cost(0);
3465
3466 format %{ %}
3467 interface(CONST_INTER);
3468 %}
3469
3470 // Integer Immediate: the values 32-63
3471 operand immI_32_63() %{
3472 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3473 match(ConI);
3474 op_cost(0);
3475
3476 format %{ %}
3477 interface(CONST_INTER);
3478 %}
3479
3480 // Immediates for special shifts (sign extend)
3481
3482 // Integer Immediate: the value 16
3483 operand immI_16() %{
3484 predicate(n->get_int() == 16);
3485 match(ConI);
3486 op_cost(0);
3487
3488 format %{ %}
3489 interface(CONST_INTER);
3490 %}
3491
3492 // Integer Immediate: the value 24
3493 operand immI_24() %{
3494 predicate(n->get_int() == 24);
3495 match(ConI);
3496 op_cost(0);
3497
3498 format %{ %}
3499 interface(CONST_INTER);
3500 %}
3501 // Integer Immediate: the value 255
3502 operand immI_255() %{
3503 predicate( n->get_int() == 255 );
3504 match(ConI);
3505 op_cost(0);
3506
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 // Integer Immediate: the value 65535
3512 operand immI_65535() %{
3513 predicate(n->get_int() == 65535);
3514 match(ConI);
3515 op_cost(0);
3516
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 // Integer Immediate: the values 0-31
3522 operand immU5() %{
3523 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3524 match(ConI);
3525 op_cost(0);
3526
3527 format %{ %}
3528 interface(CONST_INTER);
3529 %}
3530
3531 // Integer Immediate: 6-bit
3532 operand immU6() %{
3533 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3534 match(ConI);
3535 op_cost(0);
3536 format %{ %}
3537 interface(CONST_INTER);
3538 %}
3539
3540 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3541 operand immU12() %{
3542 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3543 match(ConI);
3544 op_cost(0);
3545
3546 format %{ %}
3547 interface(CONST_INTER);
3548 %}
3549
3550 // Integer Immediate non-negative
3551 operand immU31()
3552 %{
3553 predicate(n->get_int() >= 0);
3554 match(ConI);
3555
3556 op_cost(0);
3557 format %{ %}
3558 interface(CONST_INTER);
3559 %}
3560
3561 // Long Immediate: the value FF
3562 operand immL_FF() %{
3563 predicate( n->get_long() == 0xFFL );
3564 match(ConL);
3565 op_cost(0);
3566
3567 format %{ %}
3568 interface(CONST_INTER);
3569 %}
3570
3571 // Long Immediate: the value FFFF
3572 operand immL_FFFF() %{
3573 predicate( n->get_long() == 0xFFFFL );
3574 match(ConL);
3575 op_cost(0);
3576
3577 format %{ %}
3578 interface(CONST_INTER);
3579 %}
3580
3581 // Pointer Immediate: 32 or 64-bit
3582 operand immP() %{
3583 match(ConP);
3584
3585 op_cost(5);
3586 // formats are generated automatically for constants and base registers
3587 format %{ %}
3588 interface(CONST_INTER);
3589 %}
3590
3591 #ifdef _LP64
3592 // Pointer Immediate: 64-bit
3593 operand immP_set() %{
3594 predicate(!VM_Version::is_niagara_plus());
3595 match(ConP);
3596
3597 op_cost(5);
3598 // formats are generated automatically for constants and base registers
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3602
3603 // Pointer Immediate: 64-bit
3604 // From Niagara2 processors on a load should be better than materializing.
3605 operand immP_load() %{
3606 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3607 match(ConP);
3608
3609 op_cost(5);
3610 // formats are generated automatically for constants and base registers
3611 format %{ %}
3612 interface(CONST_INTER);
3613 %}
3614
3615 // Pointer Immediate: 64-bit
3616 operand immP_no_oop_cheap() %{
3617 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3618 match(ConP);
3619
3620 op_cost(5);
3621 // formats are generated automatically for constants and base registers
3622 format %{ %}
3623 interface(CONST_INTER);
3624 %}
3625 #endif
3626
3627 operand immP13() %{
3628 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3629 match(ConP);
3630 op_cost(0);
3631
3632 format %{ %}
3633 interface(CONST_INTER);
3634 %}
3635
3636 operand immP0() %{
3637 predicate(n->get_ptr() == 0);
3638 match(ConP);
3639 op_cost(0);
3640
3641 format %{ %}
3642 interface(CONST_INTER);
3643 %}
3644
3645 operand immP_poll() %{
3646 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3647 match(ConP);
3648
3649 // formats are generated automatically for constants and base registers
3650 format %{ %}
3651 interface(CONST_INTER);
3652 %}
3653
3654 // Pointer Immediate
3655 operand immN()
3656 %{
3657 match(ConN);
3658
3659 op_cost(10);
3660 format %{ %}
3661 interface(CONST_INTER);
3662 %}
3663
3664 operand immNKlass()
3665 %{
3666 match(ConNKlass);
3667
3668 op_cost(10);
3669 format %{ %}
3670 interface(CONST_INTER);
3671 %}
3672
3673 // NULL Pointer Immediate
3674 operand immN0()
3675 %{
3676 predicate(n->get_narrowcon() == 0);
3677 match(ConN);
3678
3679 op_cost(0);
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3683
3684 operand immL() %{
3685 match(ConL);
3686 op_cost(40);
3687 // formats are generated automatically for constants and base registers
3688 format %{ %}
3689 interface(CONST_INTER);
3690 %}
3691
3692 operand immL0() %{
3693 predicate(n->get_long() == 0L);
3694 match(ConL);
3695 op_cost(0);
3696 // formats are generated automatically for constants and base registers
3697 format %{ %}
3698 interface(CONST_INTER);
3699 %}
3700
3701 // Integer Immediate: 5-bit
3702 operand immL5() %{
3703 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3704 match(ConL);
3705 op_cost(0);
3706 format %{ %}
3707 interface(CONST_INTER);
3708 %}
3709
3710 // Long Immediate: 13-bit
3711 operand immL13() %{
3712 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3713 match(ConL);
3714 op_cost(0);
3715
3716 format %{ %}
3717 interface(CONST_INTER);
3718 %}
3719
3720 // Long Immediate: 13-bit minus 7
3721 operand immL13m7() %{
3722 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3723 match(ConL);
3724 op_cost(0);
3725
3726 format %{ %}
3727 interface(CONST_INTER);
3728 %}
3729
3730 // Long Immediate: low 32-bit mask
3731 operand immL_32bits() %{
3732 predicate(n->get_long() == 0xFFFFFFFFL);
3733 match(ConL);
3734 op_cost(0);
3735
3736 format %{ %}
3737 interface(CONST_INTER);
3738 %}
3739
3740 // Long Immediate: cheap (materialize in <= 3 instructions)
3741 operand immL_cheap() %{
3742 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3743 match(ConL);
3744 op_cost(0);
3745
3746 format %{ %}
3747 interface(CONST_INTER);
3748 %}
3749
3750 // Long Immediate: expensive (materialize in > 3 instructions)
3751 operand immL_expensive() %{
3752 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3753 match(ConL);
3754 op_cost(0);
3755
3756 format %{ %}
3757 interface(CONST_INTER);
3758 %}
3759
3760 // Double Immediate
3761 operand immD() %{
3762 match(ConD);
3763
3764 op_cost(40);
3765 format %{ %}
3766 interface(CONST_INTER);
3767 %}
3768
3769 // Double Immediate: +0.0d
3770 operand immD0() %{
3771 predicate(jlong_cast(n->getd()) == 0);
3772 match(ConD);
3773
3774 op_cost(0);
3775 format %{ %}
3776 interface(CONST_INTER);
3777 %}
3778
3779 // Float Immediate
3780 operand immF() %{
3781 match(ConF);
3782
3783 op_cost(20);
3784 format %{ %}
3785 interface(CONST_INTER);
3786 %}
3787
3788 // Float Immediate: +0.0f
3789 operand immF0() %{
3790 predicate(jint_cast(n->getf()) == 0);
3791 match(ConF);
3792
3793 op_cost(0);
3794 format %{ %}
3795 interface(CONST_INTER);
3796 %}
3797
3798 // Integer Register Operands
3799 // Integer Register
3800 operand iRegI() %{
3801 constraint(ALLOC_IN_RC(int_reg));
3802 match(RegI);
3803
3804 match(notemp_iRegI);
3805 match(g1RegI);
3806 match(o0RegI);
3807 match(iRegIsafe);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand notemp_iRegI() %{
3814 constraint(ALLOC_IN_RC(notemp_int_reg));
3815 match(RegI);
3816
3817 match(o0RegI);
3818
3819 format %{ %}
3820 interface(REG_INTER);
3821 %}
3822
3823 operand o0RegI() %{
3824 constraint(ALLOC_IN_RC(o0_regI));
3825 match(iRegI);
3826
3827 format %{ %}
3828 interface(REG_INTER);
3829 %}
3830
3831 // Pointer Register
3832 operand iRegP() %{
3833 constraint(ALLOC_IN_RC(ptr_reg));
3834 match(RegP);
3835
3836 match(lock_ptr_RegP);
3837 match(g1RegP);
3838 match(g2RegP);
3839 match(g3RegP);
3840 match(g4RegP);
3841 match(i0RegP);
3842 match(o0RegP);
3843 match(o1RegP);
3844 match(l7RegP);
3845
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 operand sp_ptr_RegP() %{
3851 constraint(ALLOC_IN_RC(sp_ptr_reg));
3852 match(RegP);
3853 match(iRegP);
3854
3855 format %{ %}
3856 interface(REG_INTER);
3857 %}
3858
3859 operand lock_ptr_RegP() %{
3860 constraint(ALLOC_IN_RC(lock_ptr_reg));
3861 match(RegP);
3862 match(i0RegP);
3863 match(o0RegP);
3864 match(o1RegP);
3865 match(l7RegP);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand g1RegP() %{
3872 constraint(ALLOC_IN_RC(g1_regP));
3873 match(iRegP);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand g2RegP() %{
3880 constraint(ALLOC_IN_RC(g2_regP));
3881 match(iRegP);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand g3RegP() %{
3888 constraint(ALLOC_IN_RC(g3_regP));
3889 match(iRegP);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895 operand g1RegI() %{
3896 constraint(ALLOC_IN_RC(g1_regI));
3897 match(iRegI);
3898
3899 format %{ %}
3900 interface(REG_INTER);
3901 %}
3902
3903 operand g3RegI() %{
3904 constraint(ALLOC_IN_RC(g3_regI));
3905 match(iRegI);
3906
3907 format %{ %}
3908 interface(REG_INTER);
3909 %}
3910
3911 operand g4RegI() %{
3912 constraint(ALLOC_IN_RC(g4_regI));
3913 match(iRegI);
3914
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3918
3919 operand g4RegP() %{
3920 constraint(ALLOC_IN_RC(g4_regP));
3921 match(iRegP);
3922
3923 format %{ %}
3924 interface(REG_INTER);
3925 %}
3926
3927 operand i0RegP() %{
3928 constraint(ALLOC_IN_RC(i0_regP));
3929 match(iRegP);
3930
3931 format %{ %}
3932 interface(REG_INTER);
3933 %}
3934
3935 operand o0RegP() %{
3936 constraint(ALLOC_IN_RC(o0_regP));
3937 match(iRegP);
3938
3939 format %{ %}
3940 interface(REG_INTER);
3941 %}
3942
3943 operand o1RegP() %{
3944 constraint(ALLOC_IN_RC(o1_regP));
3945 match(iRegP);
3946
3947 format %{ %}
3948 interface(REG_INTER);
3949 %}
3950
3951 operand o2RegP() %{
3952 constraint(ALLOC_IN_RC(o2_regP));
3953 match(iRegP);
3954
3955 format %{ %}
3956 interface(REG_INTER);
3957 %}
3958
3959 operand o7RegP() %{
3960 constraint(ALLOC_IN_RC(o7_regP));
3961 match(iRegP);
3962
3963 format %{ %}
3964 interface(REG_INTER);
3965 %}
3966
3967 operand l7RegP() %{
3968 constraint(ALLOC_IN_RC(l7_regP));
3969 match(iRegP);
3970
3971 format %{ %}
3972 interface(REG_INTER);
3973 %}
3974
3975 operand o7RegI() %{
3976 constraint(ALLOC_IN_RC(o7_regI));
3977 match(iRegI);
3978
3979 format %{ %}
3980 interface(REG_INTER);
3981 %}
3982
3983 operand iRegN() %{
3984 constraint(ALLOC_IN_RC(int_reg));
3985 match(RegN);
3986
3987 format %{ %}
3988 interface(REG_INTER);
3989 %}
3990
3991 // Long Register
3992 operand iRegL() %{
3993 constraint(ALLOC_IN_RC(long_reg));
3994 match(RegL);
3995
3996 format %{ %}
3997 interface(REG_INTER);
3998 %}
3999
4000 operand o2RegL() %{
4001 constraint(ALLOC_IN_RC(o2_regL));
4002 match(iRegL);
4003
4004 format %{ %}
4005 interface(REG_INTER);
4006 %}
4007
4008 operand o7RegL() %{
4009 constraint(ALLOC_IN_RC(o7_regL));
4010 match(iRegL);
4011
4012 format %{ %}
4013 interface(REG_INTER);
4014 %}
4015
4016 operand g1RegL() %{
4017 constraint(ALLOC_IN_RC(g1_regL));
4018 match(iRegL);
4019
4020 format %{ %}
4021 interface(REG_INTER);
4022 %}
4023
4024 operand g3RegL() %{
4025 constraint(ALLOC_IN_RC(g3_regL));
4026 match(iRegL);
4027
4028 format %{ %}
4029 interface(REG_INTER);
4030 %}
4031
4032 // Int Register safe
4033 // This is 64bit safe
4034 operand iRegIsafe() %{
4035 constraint(ALLOC_IN_RC(long_reg));
4036
4037 match(iRegI);
4038
4039 format %{ %}
4040 interface(REG_INTER);
4041 %}
4042
4043 // Condition Code Flag Register
4044 operand flagsReg() %{
4045 constraint(ALLOC_IN_RC(int_flags));
4046 match(RegFlags);
4047
4048 format %{ "ccr" %} // both ICC and XCC
4049 interface(REG_INTER);
4050 %}
4051
4052 // Condition Code Register, unsigned comparisons.
4053 operand flagsRegU() %{
4054 constraint(ALLOC_IN_RC(int_flags));
4055 match(RegFlags);
4056
4057 format %{ "icc_U" %}
4058 interface(REG_INTER);
4059 %}
4060
4061 // Condition Code Register, pointer comparisons.
4062 operand flagsRegP() %{
4063 constraint(ALLOC_IN_RC(int_flags));
4064 match(RegFlags);
4065
4066 #ifdef _LP64
4067 format %{ "xcc_P" %}
4068 #else
4069 format %{ "icc_P" %}
4070 #endif
4071 interface(REG_INTER);
4072 %}
4073
4074 // Condition Code Register, long comparisons.
4075 operand flagsRegL() %{
4076 constraint(ALLOC_IN_RC(int_flags));
4077 match(RegFlags);
4078
4079 format %{ "xcc_L" %}
4080 interface(REG_INTER);
4081 %}
4082
4083 // Condition Code Register, floating comparisons, unordered same as "less".
4084 operand flagsRegF() %{
4085 constraint(ALLOC_IN_RC(float_flags));
4086 match(RegFlags);
4087 match(flagsRegF0);
4088
4089 format %{ %}
4090 interface(REG_INTER);
4091 %}
4092
4093 operand flagsRegF0() %{
4094 constraint(ALLOC_IN_RC(float_flag0));
4095 match(RegFlags);
4096
4097 format %{ %}
4098 interface(REG_INTER);
4099 %}
4100
4101
4102 // Condition Code Flag Register used by long compare
4103 operand flagsReg_long_LTGE() %{
4104 constraint(ALLOC_IN_RC(int_flags));
4105 match(RegFlags);
4106 format %{ "icc_LTGE" %}
4107 interface(REG_INTER);
4108 %}
4109 operand flagsReg_long_EQNE() %{
4110 constraint(ALLOC_IN_RC(int_flags));
4111 match(RegFlags);
4112 format %{ "icc_EQNE" %}
4113 interface(REG_INTER);
4114 %}
4115 operand flagsReg_long_LEGT() %{
4116 constraint(ALLOC_IN_RC(int_flags));
4117 match(RegFlags);
4118 format %{ "icc_LEGT" %}
4119 interface(REG_INTER);
4120 %}
4121
4122
4123 operand regD() %{
4124 constraint(ALLOC_IN_RC(dflt_reg));
4125 match(RegD);
4126
4127 match(regD_low);
4128
4129 format %{ %}
4130 interface(REG_INTER);
4131 %}
4132
4133 operand regF() %{
4134 constraint(ALLOC_IN_RC(sflt_reg));
4135 match(RegF);
4136
4137 format %{ %}
4138 interface(REG_INTER);
4139 %}
4140
4141 operand regD_low() %{
4142 constraint(ALLOC_IN_RC(dflt_low_reg));
4143 match(regD);
4144
4145 format %{ %}
4146 interface(REG_INTER);
4147 %}
4148
4149 // Special Registers
4150
4151 // Method Register
4152 operand inline_cache_regP(iRegP reg) %{
4153 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4154 match(reg);
4155 format %{ %}
4156 interface(REG_INTER);
4157 %}
4158
4159 operand interpreter_method_oop_regP(iRegP reg) %{
4160 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4161 match(reg);
4162 format %{ %}
4163 interface(REG_INTER);
4164 %}
4165
4166
4167 //----------Complex Operands---------------------------------------------------
4168 // Indirect Memory Reference
4169 operand indirect(sp_ptr_RegP reg) %{
4170 constraint(ALLOC_IN_RC(sp_ptr_reg));
4171 match(reg);
4172
4173 op_cost(100);
4174 format %{ "[$reg]" %}
4175 interface(MEMORY_INTER) %{
4176 base($reg);
4177 index(0x0);
4178 scale(0x0);
4179 disp(0x0);
4180 %}
4181 %}
4182
4183 // Indirect with simm13 Offset
4184 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4185 constraint(ALLOC_IN_RC(sp_ptr_reg));
4186 match(AddP reg offset);
4187
4188 op_cost(100);
4189 format %{ "[$reg + $offset]" %}
4190 interface(MEMORY_INTER) %{
4191 base($reg);
4192 index(0x0);
4193 scale(0x0);
4194 disp($offset);
4195 %}
4196 %}
4197
4198 // Indirect with simm13 Offset minus 7
4199 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4200 constraint(ALLOC_IN_RC(sp_ptr_reg));
4201 match(AddP reg offset);
4202
4203 op_cost(100);
4204 format %{ "[$reg + $offset]" %}
4205 interface(MEMORY_INTER) %{
4206 base($reg);
4207 index(0x0);
4208 scale(0x0);
4209 disp($offset);
4210 %}
4211 %}
4212
4213 // Note: Intel has a swapped version also, like this:
4214 //operand indOffsetX(iRegI reg, immP offset) %{
4215 // constraint(ALLOC_IN_RC(int_reg));
4216 // match(AddP offset reg);
4217 //
4218 // op_cost(100);
4219 // format %{ "[$reg + $offset]" %}
4220 // interface(MEMORY_INTER) %{
4221 // base($reg);
4222 // index(0x0);
4223 // scale(0x0);
4224 // disp($offset);
4225 // %}
4226 //%}
4227 //// However, it doesn't make sense for SPARC, since
4228 // we have no particularly good way to embed oops in
4229 // single instructions.
4230
4231 // Indirect with Register Index
4232 operand indIndex(iRegP addr, iRegX index) %{
4233 constraint(ALLOC_IN_RC(ptr_reg));
4234 match(AddP addr index);
4235
4236 op_cost(100);
4237 format %{ "[$addr + $index]" %}
4238 interface(MEMORY_INTER) %{
4239 base($addr);
4240 index($index);
4241 scale(0x0);
4242 disp(0x0);
4243 %}
4244 %}
4245
4246 //----------Special Memory Operands--------------------------------------------
4247 // Stack Slot Operand - This operand is used for loading and storing temporary
4248 // values on the stack where a match requires a value to
4249 // flow through memory.
4250 operand stackSlotI(sRegI reg) %{
4251 constraint(ALLOC_IN_RC(stack_slots));
4252 op_cost(100);
4253 //match(RegI);
4254 format %{ "[$reg]" %}
4255 interface(MEMORY_INTER) %{
4256 base(0xE); // R_SP
4257 index(0x0);
4258 scale(0x0);
4259 disp($reg); // Stack Offset
4260 %}
4261 %}
4262
4263 operand stackSlotP(sRegP reg) %{
4264 constraint(ALLOC_IN_RC(stack_slots));
4265 op_cost(100);
4266 //match(RegP);
4267 format %{ "[$reg]" %}
4268 interface(MEMORY_INTER) %{
4269 base(0xE); // R_SP
4270 index(0x0);
4271 scale(0x0);
4272 disp($reg); // Stack Offset
4273 %}
4274 %}
4275
4276 operand stackSlotF(sRegF reg) %{
4277 constraint(ALLOC_IN_RC(stack_slots));
4278 op_cost(100);
4279 //match(RegF);
4280 format %{ "[$reg]" %}
4281 interface(MEMORY_INTER) %{
4282 base(0xE); // R_SP
4283 index(0x0);
4284 scale(0x0);
4285 disp($reg); // Stack Offset
4286 %}
4287 %}
4288 operand stackSlotD(sRegD reg) %{
4289 constraint(ALLOC_IN_RC(stack_slots));
4290 op_cost(100);
4291 //match(RegD);
4292 format %{ "[$reg]" %}
4293 interface(MEMORY_INTER) %{
4294 base(0xE); // R_SP
4295 index(0x0);
4296 scale(0x0);
4297 disp($reg); // Stack Offset
4298 %}
4299 %}
4300 operand stackSlotL(sRegL reg) %{
4301 constraint(ALLOC_IN_RC(stack_slots));
4302 op_cost(100);
4303 //match(RegL);
4304 format %{ "[$reg]" %}
4305 interface(MEMORY_INTER) %{
4306 base(0xE); // R_SP
4307 index(0x0);
4308 scale(0x0);
4309 disp($reg); // Stack Offset
4310 %}
4311 %}
4312
4313 // Operands for expressing Control Flow
4314 // NOTE: Label is a predefined operand which should not be redefined in
4315 // the AD file. It is generically handled within the ADLC.
4316
4317 //----------Conditional Branch Operands----------------------------------------
4318 // Comparison Op - This is the operation of the comparison, and is limited to
4319 // the following set of codes:
4320 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4321 //
4322 // Other attributes of the comparison, such as unsignedness, are specified
4323 // by the comparison instruction that sets a condition code flags register.
4324 // That result is represented by a flags operand whose subtype is appropriate
4325 // to the unsignedness (etc.) of the comparison.
4326 //
4327 // Later, the instruction which matches both the Comparison Op (a Bool) and
4328 // the flags (produced by the Cmp) specifies the coding of the comparison op
4329 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4330
4331 operand cmpOp() %{
4332 match(Bool);
4333
4334 format %{ "" %}
4335 interface(COND_INTER) %{
4336 equal(0x1);
4337 not_equal(0x9);
4338 less(0x3);
4339 greater_equal(0xB);
4340 less_equal(0x2);
4341 greater(0xA);
4342 overflow(0x7);
4343 no_overflow(0xF);
4344 %}
4345 %}
4346
4347 // Comparison Op, unsigned
4348 operand cmpOpU() %{
4349 match(Bool);
4350 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4351 n->as_Bool()->_test._test != BoolTest::no_overflow);
4352
4353 format %{ "u" %}
4354 interface(COND_INTER) %{
4355 equal(0x1);
4356 not_equal(0x9);
4357 less(0x5);
4358 greater_equal(0xD);
4359 less_equal(0x4);
4360 greater(0xC);
4361 overflow(0x7);
4362 no_overflow(0xF);
4363 %}
4364 %}
4365
4366 // Comparison Op, pointer (same as unsigned)
4367 operand cmpOpP() %{
4368 match(Bool);
4369 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4370 n->as_Bool()->_test._test != BoolTest::no_overflow);
4371
4372 format %{ "p" %}
4373 interface(COND_INTER) %{
4374 equal(0x1);
4375 not_equal(0x9);
4376 less(0x5);
4377 greater_equal(0xD);
4378 less_equal(0x4);
4379 greater(0xC);
4380 overflow(0x7);
4381 no_overflow(0xF);
4382 %}
4383 %}
4384
4385 // Comparison Op, branch-register encoding
4386 operand cmpOp_reg() %{
4387 match(Bool);
4388 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4389 n->as_Bool()->_test._test != BoolTest::no_overflow);
4390
4391 format %{ "" %}
4392 interface(COND_INTER) %{
4393 equal (0x1);
4394 not_equal (0x5);
4395 less (0x3);
4396 greater_equal(0x7);
4397 less_equal (0x2);
4398 greater (0x6);
4399 overflow(0x7); // not supported
4400 no_overflow(0xF); // not supported
4401 %}
4402 %}
4403
4404 // Comparison Code, floating, unordered same as less
4405 operand cmpOpF() %{
4406 match(Bool);
4407 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4408 n->as_Bool()->_test._test != BoolTest::no_overflow);
4409
4410 format %{ "fl" %}
4411 interface(COND_INTER) %{
4412 equal(0x9);
4413 not_equal(0x1);
4414 less(0x3);
4415 greater_equal(0xB);
4416 less_equal(0xE);
4417 greater(0x6);
4418
4419 overflow(0x7); // not supported
4420 no_overflow(0xF); // not supported
4421 %}
4422 %}
4423
4424 // Used by long compare
4425 operand cmpOp_commute() %{
4426 match(Bool);
4427 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4428 n->as_Bool()->_test._test != BoolTest::no_overflow);
4429
4430 format %{ "" %}
4431 interface(COND_INTER) %{
4432 equal(0x1);
4433 not_equal(0x9);
4434 less(0xA);
4435 greater_equal(0x2);
4436 less_equal(0xB);
4437 greater(0x3);
4438 overflow(0x7);
4439 no_overflow(0xF);
4440 %}
4441 %}
4442
4443 //----------OPERAND CLASSES----------------------------------------------------
4444 // Operand Classes are groups of operands that are used to simplify
4445 // instruction definitions by not requiring the AD writer to specify separate
4446 // instructions for every form of operand when the instruction accepts
4447 // multiple operand types with the same basic encoding and format. The classic
4448 // case of this is memory operands.
4449 opclass memory( indirect, indOffset13, indIndex );
4450 opclass indIndexMemory( indIndex );
4451
4452 //----------PIPELINE-----------------------------------------------------------
4453 pipeline %{
4454
4455 //----------ATTRIBUTES---------------------------------------------------------
4456 attributes %{
4457 fixed_size_instructions; // Fixed size instructions
4458 branch_has_delay_slot; // Branch has delay slot following
4459 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4460 instruction_unit_size = 4; // An instruction is 4 bytes long
4461 instruction_fetch_unit_size = 16; // The processor fetches one line
4462 instruction_fetch_units = 1; // of 16 bytes
4463
4464 // List of nop instructions
4465 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4466 %}
4467
4468 //----------RESOURCES----------------------------------------------------------
4469 // Resources are the functional units available to the machine
4470 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4471
4472 //----------PIPELINE DESCRIPTION-----------------------------------------------
4473 // Pipeline Description specifies the stages in the machine's pipeline
4474
4475 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4476
4477 //----------PIPELINE CLASSES---------------------------------------------------
4478 // Pipeline Classes describe the stages in which input and output are
4479 // referenced by the hardware pipeline.
4480
4481 // Integer ALU reg-reg operation
4482 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4483 single_instruction;
4484 dst : E(write);
4485 src1 : R(read);
4486 src2 : R(read);
4487 IALU : R;
4488 %}
4489
4490 // Integer ALU reg-reg long operation
4491 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4492 instruction_count(2);
4493 dst : E(write);
4494 src1 : R(read);
4495 src2 : R(read);
4496 IALU : R;
4497 IALU : R;
4498 %}
4499
4500 // Integer ALU reg-reg long dependent operation
4501 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4502 instruction_count(1); multiple_bundles;
4503 dst : E(write);
4504 src1 : R(read);
4505 src2 : R(read);
4506 cr : E(write);
4507 IALU : R(2);
4508 %}
4509
4510 // Integer ALU reg-imm operaion
4511 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4512 single_instruction;
4513 dst : E(write);
4514 src1 : R(read);
4515 IALU : R;
4516 %}
4517
4518 // Integer ALU reg-reg operation with condition code
4519 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4520 single_instruction;
4521 dst : E(write);
4522 cr : E(write);
4523 src1 : R(read);
4524 src2 : R(read);
4525 IALU : R;
4526 %}
4527
4528 // Integer ALU reg-imm operation with condition code
4529 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4530 single_instruction;
4531 dst : E(write);
4532 cr : E(write);
4533 src1 : R(read);
4534 IALU : R;
4535 %}
4536
4537 // Integer ALU zero-reg operation
4538 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4539 single_instruction;
4540 dst : E(write);
4541 src2 : R(read);
4542 IALU : R;
4543 %}
4544
4545 // Integer ALU zero-reg operation with condition code only
4546 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4547 single_instruction;
4548 cr : E(write);
4549 src : R(read);
4550 IALU : R;
4551 %}
4552
4553 // Integer ALU reg-reg operation with condition code only
4554 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4555 single_instruction;
4556 cr : E(write);
4557 src1 : R(read);
4558 src2 : R(read);
4559 IALU : R;
4560 %}
4561
4562 // Integer ALU reg-imm operation with condition code only
4563 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4564 single_instruction;
4565 cr : E(write);
4566 src1 : R(read);
4567 IALU : R;
4568 %}
4569
4570 // Integer ALU reg-reg-zero operation with condition code only
4571 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4572 single_instruction;
4573 cr : E(write);
4574 src1 : R(read);
4575 src2 : R(read);
4576 IALU : R;
4577 %}
4578
4579 // Integer ALU reg-imm-zero operation with condition code only
4580 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4581 single_instruction;
4582 cr : E(write);
4583 src1 : R(read);
4584 IALU : R;
4585 %}
4586
4587 // Integer ALU reg-reg operation with condition code, src1 modified
4588 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4589 single_instruction;
4590 cr : E(write);
4591 src1 : E(write);
4592 src1 : R(read);
4593 src2 : R(read);
4594 IALU : R;
4595 %}
4596
4597 // Integer ALU reg-imm operation with condition code, src1 modified
4598 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4599 single_instruction;
4600 cr : E(write);
4601 src1 : E(write);
4602 src1 : R(read);
4603 IALU : R;
4604 %}
4605
4606 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4607 multiple_bundles;
4608 dst : E(write)+4;
4609 cr : E(write);
4610 src1 : R(read);
4611 src2 : R(read);
4612 IALU : R(3);
4613 BR : R(2);
4614 %}
4615
4616 // Integer ALU operation
4617 pipe_class ialu_none(iRegI dst) %{
4618 single_instruction;
4619 dst : E(write);
4620 IALU : R;
4621 %}
4622
4623 // Integer ALU reg operation
4624 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4625 single_instruction; may_have_no_code;
4626 dst : E(write);
4627 src : R(read);
4628 IALU : R;
4629 %}
4630
4631 // Integer ALU reg conditional operation
4632 // This instruction has a 1 cycle stall, and cannot execute
4633 // in the same cycle as the instruction setting the condition
4634 // code. We kludge this by pretending to read the condition code
4635 // 1 cycle earlier, and by marking the functional units as busy
4636 // for 2 cycles with the result available 1 cycle later than
4637 // is really the case.
4638 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4639 single_instruction;
4640 op2_out : C(write);
4641 op1 : R(read);
4642 cr : R(read); // This is really E, with a 1 cycle stall
4643 BR : R(2);
4644 MS : R(2);
4645 %}
4646
4647 #ifdef _LP64
4648 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4649 instruction_count(1); multiple_bundles;
4650 dst : C(write)+1;
4651 src : R(read)+1;
4652 IALU : R(1);
4653 BR : E(2);
4654 MS : E(2);
4655 %}
4656 #endif
4657
4658 // Integer ALU reg operation
4659 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4660 single_instruction; may_have_no_code;
4661 dst : E(write);
4662 src : R(read);
4663 IALU : R;
4664 %}
4665 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4666 single_instruction; may_have_no_code;
4667 dst : E(write);
4668 src : R(read);
4669 IALU : R;
4670 %}
4671
4672 // Two integer ALU reg operations
4673 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4674 instruction_count(2);
4675 dst : E(write);
4676 src : R(read);
4677 A0 : R;
4678 A1 : R;
4679 %}
4680
4681 // Two integer ALU reg operations
4682 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4683 instruction_count(2); may_have_no_code;
4684 dst : E(write);
4685 src : R(read);
4686 A0 : R;
4687 A1 : R;
4688 %}
4689
4690 // Integer ALU imm operation
4691 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4692 single_instruction;
4693 dst : E(write);
4694 IALU : R;
4695 %}
4696
4697 // Integer ALU reg-reg with carry operation
4698 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4699 single_instruction;
4700 dst : E(write);
4701 src1 : R(read);
4702 src2 : R(read);
4703 IALU : R;
4704 %}
4705
4706 // Integer ALU cc operation
4707 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4708 single_instruction;
4709 dst : E(write);
4710 cc : R(read);
4711 IALU : R;
4712 %}
4713
4714 // Integer ALU cc / second IALU operation
4715 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4716 instruction_count(1); multiple_bundles;
4717 dst : E(write)+1;
4718 src : R(read);
4719 IALU : R;
4720 %}
4721
4722 // Integer ALU cc / second IALU operation
4723 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4724 instruction_count(1); multiple_bundles;
4725 dst : E(write)+1;
4726 p : R(read);
4727 q : R(read);
4728 IALU : R;
4729 %}
4730
4731 // Integer ALU hi-lo-reg operation
4732 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4733 instruction_count(1); multiple_bundles;
4734 dst : E(write)+1;
4735 IALU : R(2);
4736 %}
4737
4738 // Float ALU hi-lo-reg operation (with temp)
4739 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4740 instruction_count(1); multiple_bundles;
4741 dst : E(write)+1;
4742 IALU : R(2);
4743 %}
4744
4745 // Long Constant
4746 pipe_class loadConL( iRegL dst, immL src ) %{
4747 instruction_count(2); multiple_bundles;
4748 dst : E(write)+1;
4749 IALU : R(2);
4750 IALU : R(2);
4751 %}
4752
4753 // Pointer Constant
4754 pipe_class loadConP( iRegP dst, immP src ) %{
4755 instruction_count(0); multiple_bundles;
4756 fixed_latency(6);
4757 %}
4758
4759 // Polling Address
4760 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4761 #ifdef _LP64
4762 instruction_count(0); multiple_bundles;
4763 fixed_latency(6);
4764 #else
4765 dst : E(write);
4766 IALU : R;
4767 #endif
4768 %}
4769
4770 // Long Constant small
4771 pipe_class loadConLlo( iRegL dst, immL src ) %{
4772 instruction_count(2);
4773 dst : E(write);
4774 IALU : R;
4775 IALU : R;
4776 %}
4777
4778 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4779 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4780 instruction_count(1); multiple_bundles;
4781 src : R(read);
4782 dst : M(write)+1;
4783 IALU : R;
4784 MS : E;
4785 %}
4786
4787 // Integer ALU nop operation
4788 pipe_class ialu_nop() %{
4789 single_instruction;
4790 IALU : R;
4791 %}
4792
4793 // Integer ALU nop operation
4794 pipe_class ialu_nop_A0() %{
4795 single_instruction;
4796 A0 : R;
4797 %}
4798
4799 // Integer ALU nop operation
4800 pipe_class ialu_nop_A1() %{
4801 single_instruction;
4802 A1 : R;
4803 %}
4804
4805 // Integer Multiply reg-reg operation
4806 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4807 single_instruction;
4808 dst : E(write);
4809 src1 : R(read);
4810 src2 : R(read);
4811 MS : R(5);
4812 %}
4813
4814 // Integer Multiply reg-imm operation
4815 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4816 single_instruction;
4817 dst : E(write);
4818 src1 : R(read);
4819 MS : R(5);
4820 %}
4821
4822 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4823 single_instruction;
4824 dst : E(write)+4;
4825 src1 : R(read);
4826 src2 : R(read);
4827 MS : R(6);
4828 %}
4829
4830 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4831 single_instruction;
4832 dst : E(write)+4;
4833 src1 : R(read);
4834 MS : R(6);
4835 %}
4836
4837 // Integer Divide reg-reg
4838 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4839 instruction_count(1); multiple_bundles;
4840 dst : E(write);
4841 temp : E(write);
4842 src1 : R(read);
4843 src2 : R(read);
4844 temp : R(read);
4845 MS : R(38);
4846 %}
4847
4848 // Integer Divide reg-imm
4849 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4850 instruction_count(1); multiple_bundles;
4851 dst : E(write);
4852 temp : E(write);
4853 src1 : R(read);
4854 temp : R(read);
4855 MS : R(38);
4856 %}
4857
4858 // Long Divide
4859 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4860 dst : E(write)+71;
4861 src1 : R(read);
4862 src2 : R(read)+1;
4863 MS : R(70);
4864 %}
4865
4866 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4867 dst : E(write)+71;
4868 src1 : R(read);
4869 MS : R(70);
4870 %}
4871
4872 // Floating Point Add Float
4873 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4874 single_instruction;
4875 dst : X(write);
4876 src1 : E(read);
4877 src2 : E(read);
4878 FA : R;
4879 %}
4880
4881 // Floating Point Add Double
4882 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4883 single_instruction;
4884 dst : X(write);
4885 src1 : E(read);
4886 src2 : E(read);
4887 FA : R;
4888 %}
4889
4890 // Floating Point Conditional Move based on integer flags
4891 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4892 single_instruction;
4893 dst : X(write);
4894 src : E(read);
4895 cr : R(read);
4896 FA : R(2);
4897 BR : R(2);
4898 %}
4899
4900 // Floating Point Conditional Move based on integer flags
4901 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4902 single_instruction;
4903 dst : X(write);
4904 src : E(read);
4905 cr : R(read);
4906 FA : R(2);
4907 BR : R(2);
4908 %}
4909
4910 // Floating Point Multiply Float
4911 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4912 single_instruction;
4913 dst : X(write);
4914 src1 : E(read);
4915 src2 : E(read);
4916 FM : R;
4917 %}
4918
4919 // Floating Point Multiply Double
4920 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4921 single_instruction;
4922 dst : X(write);
4923 src1 : E(read);
4924 src2 : E(read);
4925 FM : R;
4926 %}
4927
4928 // Floating Point Divide Float
4929 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4930 single_instruction;
4931 dst : X(write);
4932 src1 : E(read);
4933 src2 : E(read);
4934 FM : R;
4935 FDIV : C(14);
4936 %}
4937
4938 // Floating Point Divide Double
4939 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4940 single_instruction;
4941 dst : X(write);
4942 src1 : E(read);
4943 src2 : E(read);
4944 FM : R;
4945 FDIV : C(17);
4946 %}
4947
4948 // Floating Point Move/Negate/Abs Float
4949 pipe_class faddF_reg(regF dst, regF src) %{
4950 single_instruction;
4951 dst : W(write);
4952 src : E(read);
4953 FA : R(1);
4954 %}
4955
4956 // Floating Point Move/Negate/Abs Double
4957 pipe_class faddD_reg(regD dst, regD src) %{
4958 single_instruction;
4959 dst : W(write);
4960 src : E(read);
4961 FA : R;
4962 %}
4963
4964 // Floating Point Convert F->D
4965 pipe_class fcvtF2D(regD dst, regF src) %{
4966 single_instruction;
4967 dst : X(write);
4968 src : E(read);
4969 FA : R;
4970 %}
4971
4972 // Floating Point Convert I->D
4973 pipe_class fcvtI2D(regD dst, regF src) %{
4974 single_instruction;
4975 dst : X(write);
4976 src : E(read);
4977 FA : R;
4978 %}
4979
4980 // Floating Point Convert LHi->D
4981 pipe_class fcvtLHi2D(regD dst, regD src) %{
4982 single_instruction;
4983 dst : X(write);
4984 src : E(read);
4985 FA : R;
4986 %}
4987
4988 // Floating Point Convert L->D
4989 pipe_class fcvtL2D(regD dst, regF src) %{
4990 single_instruction;
4991 dst : X(write);
4992 src : E(read);
4993 FA : R;
4994 %}
4995
4996 // Floating Point Convert L->F
4997 pipe_class fcvtL2F(regD dst, regF src) %{
4998 single_instruction;
4999 dst : X(write);
5000 src : E(read);
5001 FA : R;
5002 %}
5003
5004 // Floating Point Convert D->F
5005 pipe_class fcvtD2F(regD dst, regF src) %{
5006 single_instruction;
5007 dst : X(write);
5008 src : E(read);
5009 FA : R;
5010 %}
5011
5012 // Floating Point Convert I->L
5013 pipe_class fcvtI2L(regD dst, regF src) %{
5014 single_instruction;
5015 dst : X(write);
5016 src : E(read);
5017 FA : R;
5018 %}
5019
5020 // Floating Point Convert D->F
5021 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
5022 instruction_count(1); multiple_bundles;
5023 dst : X(write)+6;
5024 src : E(read);
5025 FA : R;
5026 %}
5027
5028 // Floating Point Convert D->L
5029 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
5030 instruction_count(1); multiple_bundles;
5031 dst : X(write)+6;
5032 src : E(read);
5033 FA : R;
5034 %}
5035
5036 // Floating Point Convert F->I
5037 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
5038 instruction_count(1); multiple_bundles;
5039 dst : X(write)+6;
5040 src : E(read);
5041 FA : R;
5042 %}
5043
5044 // Floating Point Convert F->L
5045 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
5046 instruction_count(1); multiple_bundles;
5047 dst : X(write)+6;
5048 src : E(read);
5049 FA : R;
5050 %}
5051
5052 // Floating Point Convert I->F
5053 pipe_class fcvtI2F(regF dst, regF src) %{
5054 single_instruction;
5055 dst : X(write);
5056 src : E(read);
5057 FA : R;
5058 %}
5059
5060 // Floating Point Compare
5061 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5062 single_instruction;
5063 cr : X(write);
5064 src1 : E(read);
5065 src2 : E(read);
5066 FA : R;
5067 %}
5068
5069 // Floating Point Compare
5070 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5071 single_instruction;
5072 cr : X(write);
5073 src1 : E(read);
5074 src2 : E(read);
5075 FA : R;
5076 %}
5077
5078 // Floating Add Nop
5079 pipe_class fadd_nop() %{
5080 single_instruction;
5081 FA : R;
5082 %}
5083
5084 // Integer Store to Memory
5085 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5086 single_instruction;
5087 mem : R(read);
5088 src : C(read);
5089 MS : R;
5090 %}
5091
5092 // Integer Store to Memory
5093 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5094 single_instruction;
5095 mem : R(read);
5096 src : C(read);
5097 MS : R;
5098 %}
5099
5100 // Integer Store Zero to Memory
5101 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5102 single_instruction;
5103 mem : R(read);
5104 MS : R;
5105 %}
5106
5107 // Special Stack Slot Store
5108 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5109 single_instruction;
5110 stkSlot : R(read);
5111 src : C(read);
5112 MS : R;
5113 %}
5114
5115 // Special Stack Slot Store
5116 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5117 instruction_count(2); multiple_bundles;
5118 stkSlot : R(read);
5119 src : C(read);
5120 MS : R(2);
5121 %}
5122
5123 // Float Store
5124 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5125 single_instruction;
5126 mem : R(read);
5127 src : C(read);
5128 MS : R;
5129 %}
5130
5131 // Float Store
5132 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5133 single_instruction;
5134 mem : R(read);
5135 MS : R;
5136 %}
5137
5138 // Double Store
5139 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5140 instruction_count(1);
5141 mem : R(read);
5142 src : C(read);
5143 MS : R;
5144 %}
5145
5146 // Double Store
5147 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5148 single_instruction;
5149 mem : R(read);
5150 MS : R;
5151 %}
5152
5153 // Special Stack Slot Float Store
5154 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5155 single_instruction;
5156 stkSlot : R(read);
5157 src : C(read);
5158 MS : R;
5159 %}
5160
5161 // Special Stack Slot Double Store
5162 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5163 single_instruction;
5164 stkSlot : R(read);
5165 src : C(read);
5166 MS : R;
5167 %}
5168
5169 // Integer Load (when sign bit propagation not needed)
5170 pipe_class iload_mem(iRegI dst, memory mem) %{
5171 single_instruction;
5172 mem : R(read);
5173 dst : C(write);
5174 MS : R;
5175 %}
5176
5177 // Integer Load from stack operand
5178 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5179 single_instruction;
5180 mem : R(read);
5181 dst : C(write);
5182 MS : R;
5183 %}
5184
5185 // Integer Load (when sign bit propagation or masking is needed)
5186 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5187 single_instruction;
5188 mem : R(read);
5189 dst : M(write);
5190 MS : R;
5191 %}
5192
5193 // Float Load
5194 pipe_class floadF_mem(regF dst, memory mem) %{
5195 single_instruction;
5196 mem : R(read);
5197 dst : M(write);
5198 MS : R;
5199 %}
5200
5201 // Float Load
5202 pipe_class floadD_mem(regD dst, memory mem) %{
5203 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5204 mem : R(read);
5205 dst : M(write);
5206 MS : R;
5207 %}
5208
5209 // Float Load
5210 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5211 single_instruction;
5212 stkSlot : R(read);
5213 dst : M(write);
5214 MS : R;
5215 %}
5216
5217 // Float Load
5218 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5219 single_instruction;
5220 stkSlot : R(read);
5221 dst : M(write);
5222 MS : R;
5223 %}
5224
5225 // Memory Nop
5226 pipe_class mem_nop() %{
5227 single_instruction;
5228 MS : R;
5229 %}
5230
5231 pipe_class sethi(iRegP dst, immI src) %{
5232 single_instruction;
5233 dst : E(write);
5234 IALU : R;
5235 %}
5236
5237 pipe_class loadPollP(iRegP poll) %{
5238 single_instruction;
5239 poll : R(read);
5240 MS : R;
5241 %}
5242
5243 pipe_class br(Universe br, label labl) %{
5244 single_instruction_with_delay_slot;
5245 BR : R;
5246 %}
5247
5248 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5249 single_instruction_with_delay_slot;
5250 cr : E(read);
5251 BR : R;
5252 %}
5253
5254 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5255 single_instruction_with_delay_slot;
5256 op1 : E(read);
5257 BR : R;
5258 MS : R;
5259 %}
5260
5261 // Compare and branch
5262 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5263 instruction_count(2); has_delay_slot;
5264 cr : E(write);
5265 src1 : R(read);
5266 src2 : R(read);
5267 IALU : R;
5268 BR : R;
5269 %}
5270
5271 // Compare and branch
5272 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5273 instruction_count(2); has_delay_slot;
5274 cr : E(write);
5275 src1 : R(read);
5276 IALU : R;
5277 BR : R;
5278 %}
5279
5280 // Compare and branch using cbcond
5281 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5282 single_instruction;
5283 src1 : E(read);
5284 src2 : E(read);
5285 IALU : R;
5286 BR : R;
5287 %}
5288
5289 // Compare and branch using cbcond
5290 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5291 single_instruction;
5292 src1 : E(read);
5293 IALU : R;
5294 BR : R;
5295 %}
5296
5297 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5298 single_instruction_with_delay_slot;
5299 cr : E(read);
5300 BR : R;
5301 %}
5302
5303 pipe_class br_nop() %{
5304 single_instruction;
5305 BR : R;
5306 %}
5307
5308 pipe_class simple_call(method meth) %{
5309 instruction_count(2); multiple_bundles; force_serialization;
5310 fixed_latency(100);
5311 BR : R(1);
5312 MS : R(1);
5313 A0 : R(1);
5314 %}
5315
5316 pipe_class compiled_call(method meth) %{
5317 instruction_count(1); multiple_bundles; force_serialization;
5318 fixed_latency(100);
5319 MS : R(1);
5320 %}
5321
5322 pipe_class call(method meth) %{
5323 instruction_count(0); multiple_bundles; force_serialization;
5324 fixed_latency(100);
5325 %}
5326
5327 pipe_class tail_call(Universe ignore, label labl) %{
5328 single_instruction; has_delay_slot;
5329 fixed_latency(100);
5330 BR : R(1);
5331 MS : R(1);
5332 %}
5333
5334 pipe_class ret(Universe ignore) %{
5335 single_instruction; has_delay_slot;
5336 BR : R(1);
5337 MS : R(1);
5338 %}
5339
5340 pipe_class ret_poll(g3RegP poll) %{
5341 instruction_count(3); has_delay_slot;
5342 poll : E(read);
5343 MS : R;
5344 %}
5345
5346 // The real do-nothing guy
5347 pipe_class empty( ) %{
5348 instruction_count(0);
5349 %}
5350
5351 pipe_class long_memory_op() %{
5352 instruction_count(0); multiple_bundles; force_serialization;
5353 fixed_latency(25);
5354 MS : R(1);
5355 %}
5356
5357 // Check-cast
5358 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5359 array : R(read);
5360 match : R(read);
5361 IALU : R(2);
5362 BR : R(2);
5363 MS : R;
5364 %}
5365
5366 // Convert FPU flags into +1,0,-1
5367 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5368 src1 : E(read);
5369 src2 : E(read);
5370 dst : E(write);
5371 FA : R;
5372 MS : R(2);
5373 BR : R(2);
5374 %}
5375
5376 // Compare for p < q, and conditionally add y
5377 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5378 p : E(read);
5379 q : E(read);
5380 y : E(read);
5381 IALU : R(3)
5382 %}
5383
5384 // Perform a compare, then move conditionally in a branch delay slot.
5385 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5386 src2 : E(read);
5387 srcdst : E(read);
5388 IALU : R;
5389 BR : R;
5390 %}
5391
5392 // Define the class for the Nop node
5393 define %{
5394 MachNop = ialu_nop;
5395 %}
5396
5397 %}
5398
5399 //----------INSTRUCTIONS-------------------------------------------------------
5400
5401 //------------Special Stack Slot instructions - no match rules-----------------
5402 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5403 // No match rule to avoid chain rule match.
5404 effect(DEF dst, USE src);
5405 ins_cost(MEMORY_REF_COST);
5406 size(4);
5407 format %{ "LDF $src,$dst\t! stkI to regF" %}
5408 opcode(Assembler::ldf_op3);
5409 ins_encode(simple_form3_mem_reg(src, dst));
5410 ins_pipe(floadF_stk);
5411 %}
5412
5413 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5414 // No match rule to avoid chain rule match.
5415 effect(DEF dst, USE src);
5416 ins_cost(MEMORY_REF_COST);
5417 size(4);
5418 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5419 opcode(Assembler::lddf_op3);
5420 ins_encode(simple_form3_mem_reg(src, dst));
5421 ins_pipe(floadD_stk);
5422 %}
5423
5424 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5425 // No match rule to avoid chain rule match.
5426 effect(DEF dst, USE src);
5427 ins_cost(MEMORY_REF_COST);
5428 size(4);
5429 format %{ "STF $src,$dst\t! regF to stkI" %}
5430 opcode(Assembler::stf_op3);
5431 ins_encode(simple_form3_mem_reg(dst, src));
5432 ins_pipe(fstoreF_stk_reg);
5433 %}
5434
5435 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5436 // No match rule to avoid chain rule match.
5437 effect(DEF dst, USE src);
5438 ins_cost(MEMORY_REF_COST);
5439 size(4);
5440 format %{ "STDF $src,$dst\t! regD to stkL" %}
5441 opcode(Assembler::stdf_op3);
5442 ins_encode(simple_form3_mem_reg(dst, src));
5443 ins_pipe(fstoreD_stk_reg);
5444 %}
5445
5446 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5447 effect(DEF dst, USE src);
5448 ins_cost(MEMORY_REF_COST*2);
5449 size(8);
5450 format %{ "STW $src,$dst.hi\t! long\n\t"
5451 "STW R_G0,$dst.lo" %}
5452 opcode(Assembler::stw_op3);
5453 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5454 ins_pipe(lstoreI_stk_reg);
5455 %}
5456
5457 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5458 // No match rule to avoid chain rule match.
5459 effect(DEF dst, USE src);
5460 ins_cost(MEMORY_REF_COST);
5461 size(4);
5462 format %{ "STX $src,$dst\t! regL to stkD" %}
5463 opcode(Assembler::stx_op3);
5464 ins_encode(simple_form3_mem_reg( dst, src ) );
5465 ins_pipe(istore_stk_reg);
5466 %}
5467
5468 //---------- Chain stack slots between similar types --------
5469
5470 // Load integer from stack slot
5471 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5472 match(Set dst src);
5473 ins_cost(MEMORY_REF_COST);
5474
5475 size(4);
5476 format %{ "LDUW $src,$dst\t!stk" %}
5477 opcode(Assembler::lduw_op3);
5478 ins_encode(simple_form3_mem_reg( src, dst ) );
5479 ins_pipe(iload_mem);
5480 %}
5481
5482 // Store integer to stack slot
5483 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5484 match(Set dst src);
5485 ins_cost(MEMORY_REF_COST);
5486
5487 size(4);
5488 format %{ "STW $src,$dst\t!stk" %}
5489 opcode(Assembler::stw_op3);
5490 ins_encode(simple_form3_mem_reg( dst, src ) );
5491 ins_pipe(istore_mem_reg);
5492 %}
5493
5494 // Load long from stack slot
5495 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5496 match(Set dst src);
5497
5498 ins_cost(MEMORY_REF_COST);
5499 size(4);
5500 format %{ "LDX $src,$dst\t! long" %}
5501 opcode(Assembler::ldx_op3);
5502 ins_encode(simple_form3_mem_reg( src, dst ) );
5503 ins_pipe(iload_mem);
5504 %}
5505
5506 // Store long to stack slot
5507 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5508 match(Set dst src);
5509
5510 ins_cost(MEMORY_REF_COST);
5511 size(4);
5512 format %{ "STX $src,$dst\t! long" %}
5513 opcode(Assembler::stx_op3);
5514 ins_encode(simple_form3_mem_reg( dst, src ) );
5515 ins_pipe(istore_mem_reg);
5516 %}
5517
5518 #ifdef _LP64
5519 // Load pointer from stack slot, 64-bit encoding
5520 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5521 match(Set dst src);
5522 ins_cost(MEMORY_REF_COST);
5523 size(4);
5524 format %{ "LDX $src,$dst\t!ptr" %}
5525 opcode(Assembler::ldx_op3);
5526 ins_encode(simple_form3_mem_reg( src, dst ) );
5527 ins_pipe(iload_mem);
5528 %}
5529
5530 // Store pointer to stack slot
5531 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5532 match(Set dst src);
5533 ins_cost(MEMORY_REF_COST);
5534 size(4);
5535 format %{ "STX $src,$dst\t!ptr" %}
5536 opcode(Assembler::stx_op3);
5537 ins_encode(simple_form3_mem_reg( dst, src ) );
5538 ins_pipe(istore_mem_reg);
5539 %}
5540 #else // _LP64
5541 // Load pointer from stack slot, 32-bit encoding
5542 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5543 match(Set dst src);
5544 ins_cost(MEMORY_REF_COST);
5545 format %{ "LDUW $src,$dst\t!ptr" %}
5546 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5547 ins_encode(simple_form3_mem_reg( src, dst ) );
5548 ins_pipe(iload_mem);
5549 %}
5550
5551 // Store pointer to stack slot
5552 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5553 match(Set dst src);
5554 ins_cost(MEMORY_REF_COST);
5555 format %{ "STW $src,$dst\t!ptr" %}
5556 opcode(Assembler::stw_op3, Assembler::ldst_op);
5557 ins_encode(simple_form3_mem_reg( dst, src ) );
5558 ins_pipe(istore_mem_reg);
5559 %}
5560 #endif // _LP64
5561
5562 //------------Special Nop instructions for bundling - no match rules-----------
5563 // Nop using the A0 functional unit
5564 instruct Nop_A0() %{
5565 ins_cost(0);
5566
5567 format %{ "NOP ! Alu Pipeline" %}
5568 opcode(Assembler::or_op3, Assembler::arith_op);
5569 ins_encode( form2_nop() );
5570 ins_pipe(ialu_nop_A0);
5571 %}
5572
5573 // Nop using the A1 functional unit
5574 instruct Nop_A1( ) %{
5575 ins_cost(0);
5576
5577 format %{ "NOP ! Alu Pipeline" %}
5578 opcode(Assembler::or_op3, Assembler::arith_op);
5579 ins_encode( form2_nop() );
5580 ins_pipe(ialu_nop_A1);
5581 %}
5582
5583 // Nop using the memory functional unit
5584 instruct Nop_MS( ) %{
5585 ins_cost(0);
5586
5587 format %{ "NOP ! Memory Pipeline" %}
5588 ins_encode( emit_mem_nop );
5589 ins_pipe(mem_nop);
5590 %}
5591
5592 // Nop using the floating add functional unit
5593 instruct Nop_FA( ) %{
5594 ins_cost(0);
5595
5596 format %{ "NOP ! Floating Add Pipeline" %}
5597 ins_encode( emit_fadd_nop );
5598 ins_pipe(fadd_nop);
5599 %}
5600
5601 // Nop using the branch functional unit
5602 instruct Nop_BR( ) %{
5603 ins_cost(0);
5604
5605 format %{ "NOP ! Branch Pipeline" %}
5606 ins_encode( emit_br_nop );
5607 ins_pipe(br_nop);
5608 %}
5609
5610 //----------Load/Store/Move Instructions---------------------------------------
5611 //----------Load Instructions--------------------------------------------------
5612 // Load Byte (8bit signed)
5613 instruct loadB(iRegI dst, memory mem) %{
5614 match(Set dst (LoadB mem));
5615 ins_cost(MEMORY_REF_COST);
5616
5617 size(4);
5618 format %{ "LDSB $mem,$dst\t! byte" %}
5619 ins_encode %{
5620 __ ldsb($mem$$Address, $dst$$Register);
5621 %}
5622 ins_pipe(iload_mask_mem);
5623 %}
5624
5625 // Load Byte (8bit signed) into a Long Register
5626 instruct loadB2L(iRegL dst, memory mem) %{
5627 match(Set dst (ConvI2L (LoadB mem)));
5628 ins_cost(MEMORY_REF_COST);
5629
5630 size(4);
5631 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5632 ins_encode %{
5633 __ ldsb($mem$$Address, $dst$$Register);
5634 %}
5635 ins_pipe(iload_mask_mem);
5636 %}
5637
5638 // Load Unsigned Byte (8bit UNsigned) into an int reg
5639 instruct loadUB(iRegI dst, memory mem) %{
5640 match(Set dst (LoadUB mem));
5641 ins_cost(MEMORY_REF_COST);
5642
5643 size(4);
5644 format %{ "LDUB $mem,$dst\t! ubyte" %}
5645 ins_encode %{
5646 __ ldub($mem$$Address, $dst$$Register);
5647 %}
5648 ins_pipe(iload_mem);
5649 %}
5650
5651 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5652 instruct loadUB2L(iRegL dst, memory mem) %{
5653 match(Set dst (ConvI2L (LoadUB mem)));
5654 ins_cost(MEMORY_REF_COST);
5655
5656 size(4);
5657 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5658 ins_encode %{
5659 __ ldub($mem$$Address, $dst$$Register);
5660 %}
5661 ins_pipe(iload_mem);
5662 %}
5663
5664 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5665 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5666 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5667 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5668
5669 size(2*4);
5670 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5671 "AND $dst,right_n_bits($mask, 8),$dst" %}
5672 ins_encode %{
5673 __ ldub($mem$$Address, $dst$$Register);
5674 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5675 %}
5676 ins_pipe(iload_mem);
5677 %}
5678
5679 // Load Short (16bit signed)
5680 instruct loadS(iRegI dst, memory mem) %{
5681 match(Set dst (LoadS mem));
5682 ins_cost(MEMORY_REF_COST);
5683
5684 size(4);
5685 format %{ "LDSH $mem,$dst\t! short" %}
5686 ins_encode %{
5687 __ ldsh($mem$$Address, $dst$$Register);
5688 %}
5689 ins_pipe(iload_mask_mem);
5690 %}
5691
5692 // Load Short (16 bit signed) to Byte (8 bit signed)
5693 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5694 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5695 ins_cost(MEMORY_REF_COST);
5696
5697 size(4);
5698
5699 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5700 ins_encode %{
5701 __ ldsb($mem$$Address, $dst$$Register, 1);
5702 %}
5703 ins_pipe(iload_mask_mem);
5704 %}
5705
5706 // Load Short (16bit signed) into a Long Register
5707 instruct loadS2L(iRegL dst, memory mem) %{
5708 match(Set dst (ConvI2L (LoadS mem)));
5709 ins_cost(MEMORY_REF_COST);
5710
5711 size(4);
5712 format %{ "LDSH $mem,$dst\t! short -> long" %}
5713 ins_encode %{
5714 __ ldsh($mem$$Address, $dst$$Register);
5715 %}
5716 ins_pipe(iload_mask_mem);
5717 %}
5718
5719 // Load Unsigned Short/Char (16bit UNsigned)
5720 instruct loadUS(iRegI dst, memory mem) %{
5721 match(Set dst (LoadUS mem));
5722 ins_cost(MEMORY_REF_COST);
5723
5724 size(4);
5725 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5726 ins_encode %{
5727 __ lduh($mem$$Address, $dst$$Register);
5728 %}
5729 ins_pipe(iload_mem);
5730 %}
5731
5732 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5733 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5734 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5735 ins_cost(MEMORY_REF_COST);
5736
5737 size(4);
5738 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5739 ins_encode %{
5740 __ ldsb($mem$$Address, $dst$$Register, 1);
5741 %}
5742 ins_pipe(iload_mask_mem);
5743 %}
5744
5745 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5746 instruct loadUS2L(iRegL dst, memory mem) %{
5747 match(Set dst (ConvI2L (LoadUS mem)));
5748 ins_cost(MEMORY_REF_COST);
5749
5750 size(4);
5751 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5752 ins_encode %{
5753 __ lduh($mem$$Address, $dst$$Register);
5754 %}
5755 ins_pipe(iload_mem);
5756 %}
5757
5758 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5759 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5760 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5761 ins_cost(MEMORY_REF_COST);
5762
5763 size(4);
5764 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5765 ins_encode %{
5766 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5767 %}
5768 ins_pipe(iload_mem);
5769 %}
5770
5771 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5772 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5773 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5774 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5775
5776 size(2*4);
5777 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5778 "AND $dst,$mask,$dst" %}
5779 ins_encode %{
5780 Register Rdst = $dst$$Register;
5781 __ lduh($mem$$Address, Rdst);
5782 __ and3(Rdst, $mask$$constant, Rdst);
5783 %}
5784 ins_pipe(iload_mem);
5785 %}
5786
5787 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5788 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5789 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5790 effect(TEMP dst, TEMP tmp);
5791 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5792
5793 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5794 "SET right_n_bits($mask, 16),$tmp\n\t"
5795 "AND $dst,$tmp,$dst" %}
5796 ins_encode %{
5797 Register Rdst = $dst$$Register;
5798 Register Rtmp = $tmp$$Register;
5799 __ lduh($mem$$Address, Rdst);
5800 __ set($mask$$constant & right_n_bits(16), Rtmp);
5801 __ and3(Rdst, Rtmp, Rdst);
5802 %}
5803 ins_pipe(iload_mem);
5804 %}
5805
5806 // Load Integer
5807 instruct loadI(iRegI dst, memory mem) %{
5808 match(Set dst (LoadI mem));
5809 ins_cost(MEMORY_REF_COST);
5810
5811 size(4);
5812 format %{ "LDUW $mem,$dst\t! int" %}
5813 ins_encode %{
5814 __ lduw($mem$$Address, $dst$$Register);
5815 %}
5816 ins_pipe(iload_mem);
5817 %}
5818
5819 // Load Integer to Byte (8 bit signed)
5820 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5821 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5822 ins_cost(MEMORY_REF_COST);
5823
5824 size(4);
5825
5826 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5827 ins_encode %{
5828 __ ldsb($mem$$Address, $dst$$Register, 3);
5829 %}
5830 ins_pipe(iload_mask_mem);
5831 %}
5832
5833 // Load Integer to Unsigned Byte (8 bit UNsigned)
5834 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5835 match(Set dst (AndI (LoadI mem) mask));
5836 ins_cost(MEMORY_REF_COST);
5837
5838 size(4);
5839
5840 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5841 ins_encode %{
5842 __ ldub($mem$$Address, $dst$$Register, 3);
5843 %}
5844 ins_pipe(iload_mask_mem);
5845 %}
5846
5847 // Load Integer to Short (16 bit signed)
5848 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5849 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5850 ins_cost(MEMORY_REF_COST);
5851
5852 size(4);
5853
5854 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5855 ins_encode %{
5856 __ ldsh($mem$$Address, $dst$$Register, 2);
5857 %}
5858 ins_pipe(iload_mask_mem);
5859 %}
5860
5861 // Load Integer to Unsigned Short (16 bit UNsigned)
5862 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5863 match(Set dst (AndI (LoadI mem) mask));
5864 ins_cost(MEMORY_REF_COST);
5865
5866 size(4);
5867
5868 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5869 ins_encode %{
5870 __ lduh($mem$$Address, $dst$$Register, 2);
5871 %}
5872 ins_pipe(iload_mask_mem);
5873 %}
5874
5875 // Load Integer into a Long Register
5876 instruct loadI2L(iRegL dst, memory mem) %{
5877 match(Set dst (ConvI2L (LoadI mem)));
5878 ins_cost(MEMORY_REF_COST);
5879
5880 size(4);
5881 format %{ "LDSW $mem,$dst\t! int -> long" %}
5882 ins_encode %{
5883 __ ldsw($mem$$Address, $dst$$Register);
5884 %}
5885 ins_pipe(iload_mask_mem);
5886 %}
5887
5888 // Load Integer with mask 0xFF into a Long Register
5889 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5890 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5891 ins_cost(MEMORY_REF_COST);
5892
5893 size(4);
5894 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5895 ins_encode %{
5896 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5897 %}
5898 ins_pipe(iload_mem);
5899 %}
5900
5901 // Load Integer with mask 0xFFFF into a Long Register
5902 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5903 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5904 ins_cost(MEMORY_REF_COST);
5905
5906 size(4);
5907 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5908 ins_encode %{
5909 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5910 %}
5911 ins_pipe(iload_mem);
5912 %}
5913
5914 // Load Integer with a 12-bit mask into a Long Register
5915 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5916 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5917 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5918
5919 size(2*4);
5920 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5921 "AND $dst,$mask,$dst" %}
5922 ins_encode %{
5923 Register Rdst = $dst$$Register;
5924 __ lduw($mem$$Address, Rdst);
5925 __ and3(Rdst, $mask$$constant, Rdst);
5926 %}
5927 ins_pipe(iload_mem);
5928 %}
5929
5930 // Load Integer with a 31-bit mask into a Long Register
5931 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5932 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5933 effect(TEMP dst, TEMP tmp);
5934 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5935
5936 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5937 "SET $mask,$tmp\n\t"
5938 "AND $dst,$tmp,$dst" %}
5939 ins_encode %{
5940 Register Rdst = $dst$$Register;
5941 Register Rtmp = $tmp$$Register;
5942 __ lduw($mem$$Address, Rdst);
5943 __ set($mask$$constant, Rtmp);
5944 __ and3(Rdst, Rtmp, Rdst);
5945 %}
5946 ins_pipe(iload_mem);
5947 %}
5948
5949 // Load Unsigned Integer into a Long Register
5950 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5951 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5952 ins_cost(MEMORY_REF_COST);
5953
5954 size(4);
5955 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5956 ins_encode %{
5957 __ lduw($mem$$Address, $dst$$Register);
5958 %}
5959 ins_pipe(iload_mem);
5960 %}
5961
5962 // Load Long - aligned
5963 instruct loadL(iRegL dst, memory mem ) %{
5964 match(Set dst (LoadL mem));
5965 ins_cost(MEMORY_REF_COST);
5966
5967 size(4);
5968 format %{ "LDX $mem,$dst\t! long" %}
5969 ins_encode %{
5970 __ ldx($mem$$Address, $dst$$Register);
5971 %}
5972 ins_pipe(iload_mem);
5973 %}
5974
5975 // Load Long - UNaligned
5976 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5977 match(Set dst (LoadL_unaligned mem));
5978 effect(KILL tmp);
5979 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5980 size(16);
5981 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5982 "\tLDUW $mem ,$dst\n"
5983 "\tSLLX #32, $dst, $dst\n"
5984 "\tOR $dst, R_O7, $dst" %}
5985 opcode(Assembler::lduw_op3);
5986 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5987 ins_pipe(iload_mem);
5988 %}
5989
5990 // Load Range
5991 instruct loadRange(iRegI dst, memory mem) %{
5992 match(Set dst (LoadRange mem));
5993 ins_cost(MEMORY_REF_COST);
5994
5995 size(4);
5996 format %{ "LDUW $mem,$dst\t! range" %}
5997 opcode(Assembler::lduw_op3);
5998 ins_encode(simple_form3_mem_reg( mem, dst ) );
5999 ins_pipe(iload_mem);
6000 %}
6001
6002 // Load Integer into %f register (for fitos/fitod)
6003 instruct loadI_freg(regF dst, memory mem) %{
6004 match(Set dst (LoadI mem));
6005 ins_cost(MEMORY_REF_COST);
6006 size(4);
6007
6008 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
6009 opcode(Assembler::ldf_op3);
6010 ins_encode(simple_form3_mem_reg( mem, dst ) );
6011 ins_pipe(floadF_mem);
6012 %}
6013
6014 // Load Pointer
6015 instruct loadP(iRegP dst, memory mem) %{
6016 match(Set dst (LoadP mem));
6017 ins_cost(MEMORY_REF_COST);
6018 size(4);
6019
6020 #ifndef _LP64
6021 format %{ "LDUW $mem,$dst\t! ptr" %}
6022 ins_encode %{
6023 __ lduw($mem$$Address, $dst$$Register);
6024 %}
6025 #else
6026 format %{ "LDX $mem,$dst\t! ptr" %}
6027 ins_encode %{
6028 __ ldx($mem$$Address, $dst$$Register);
6029 %}
6030 #endif
6031 ins_pipe(iload_mem);
6032 %}
6033
6034 // Load Compressed Pointer
6035 instruct loadN(iRegN dst, memory mem) %{
6036 match(Set dst (LoadN mem));
6037 ins_cost(MEMORY_REF_COST);
6038 size(4);
6039
6040 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6041 ins_encode %{
6042 __ lduw($mem$$Address, $dst$$Register);
6043 %}
6044 ins_pipe(iload_mem);
6045 %}
6046
6047 // Load Klass Pointer
6048 instruct loadKlass(iRegP dst, memory mem) %{
6049 match(Set dst (LoadKlass mem));
6050 ins_cost(MEMORY_REF_COST);
6051 size(4);
6052
6053 #ifndef _LP64
6054 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6055 ins_encode %{
6056 __ lduw($mem$$Address, $dst$$Register);
6057 %}
6058 #else
6059 format %{ "LDX $mem,$dst\t! klass ptr" %}
6060 ins_encode %{
6061 __ ldx($mem$$Address, $dst$$Register);
6062 %}
6063 #endif
6064 ins_pipe(iload_mem);
6065 %}
6066
6067 // Load narrow Klass Pointer
6068 instruct loadNKlass(iRegN dst, memory mem) %{
6069 match(Set dst (LoadNKlass mem));
6070 ins_cost(MEMORY_REF_COST);
6071 size(4);
6072
6073 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6074 ins_encode %{
6075 __ lduw($mem$$Address, $dst$$Register);
6076 %}
6077 ins_pipe(iload_mem);
6078 %}
6079
6080 // Load Double
6081 instruct loadD(regD dst, memory mem) %{
6082 match(Set dst (LoadD mem));
6083 ins_cost(MEMORY_REF_COST);
6084
6085 size(4);
6086 format %{ "LDDF $mem,$dst" %}
6087 opcode(Assembler::lddf_op3);
6088 ins_encode(simple_form3_mem_reg( mem, dst ) );
6089 ins_pipe(floadD_mem);
6090 %}
6091
6092 // Load Double - UNaligned
6093 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6094 match(Set dst (LoadD_unaligned mem));
6095 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6096 size(8);
6097 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6098 "\tLDF $mem+4,$dst.lo\t!" %}
6099 opcode(Assembler::ldf_op3);
6100 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6101 ins_pipe(iload_mem);
6102 %}
6103
6104 // Load Float
6105 instruct loadF(regF dst, memory mem) %{
6106 match(Set dst (LoadF mem));
6107 ins_cost(MEMORY_REF_COST);
6108
6109 size(4);
6110 format %{ "LDF $mem,$dst" %}
6111 opcode(Assembler::ldf_op3);
6112 ins_encode(simple_form3_mem_reg( mem, dst ) );
6113 ins_pipe(floadF_mem);
6114 %}
6115
6116 // Load Constant
6117 instruct loadConI( iRegI dst, immI src ) %{
6118 match(Set dst src);
6119 ins_cost(DEFAULT_COST * 3/2);
6120 format %{ "SET $src,$dst" %}
6121 ins_encode( Set32(src, dst) );
6122 ins_pipe(ialu_hi_lo_reg);
6123 %}
6124
6125 instruct loadConI13( iRegI dst, immI13 src ) %{
6126 match(Set dst src);
6127
6128 size(4);
6129 format %{ "MOV $src,$dst" %}
6130 ins_encode( Set13( src, dst ) );
6131 ins_pipe(ialu_imm);
6132 %}
6133
6134 #ifndef _LP64
6135 instruct loadConP(iRegP dst, immP con) %{
6136 match(Set dst con);
6137 ins_cost(DEFAULT_COST * 3/2);
6138 format %{ "SET $con,$dst\t!ptr" %}
6139 ins_encode %{
6140 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6141 intptr_t val = $con$$constant;
6142 if (constant_reloc == relocInfo::oop_type) {
6143 __ set_oop_constant((jobject) val, $dst$$Register);
6144 } else if (constant_reloc == relocInfo::metadata_type) {
6145 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6146 } else { // non-oop pointers, e.g. card mark base, heap top
6147 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6148 __ set(val, $dst$$Register);
6149 }
6150 %}
6151 ins_pipe(loadConP);
6152 %}
6153 #else
6154 instruct loadConP_set(iRegP dst, immP_set con) %{
6155 match(Set dst con);
6156 ins_cost(DEFAULT_COST * 3/2);
6157 format %{ "SET $con,$dst\t! ptr" %}
6158 ins_encode %{
6159 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6160 intptr_t val = $con$$constant;
6161 if (constant_reloc == relocInfo::oop_type) {
6162 __ set_oop_constant((jobject) val, $dst$$Register);
6163 } else if (constant_reloc == relocInfo::metadata_type) {
6164 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6165 } else { // non-oop pointers, e.g. card mark base, heap top
6166 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6167 __ set(val, $dst$$Register);
6168 }
6169 %}
6170 ins_pipe(loadConP);
6171 %}
6172
6173 instruct loadConP_load(iRegP dst, immP_load con) %{
6174 match(Set dst con);
6175 ins_cost(MEMORY_REF_COST);
6176 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6177 ins_encode %{
6178 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6179 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6180 %}
6181 ins_pipe(loadConP);
6182 %}
6183
6184 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6185 match(Set dst con);
6186 ins_cost(DEFAULT_COST * 3/2);
6187 format %{ "SET $con,$dst\t! non-oop ptr" %}
6188 ins_encode %{
6189 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6190 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6191 } else {
6192 __ set($con$$constant, $dst$$Register);
6193 }
6194 %}
6195 ins_pipe(loadConP);
6196 %}
6197 #endif // _LP64
6198
6199 instruct loadConP0(iRegP dst, immP0 src) %{
6200 match(Set dst src);
6201
6202 size(4);
6203 format %{ "CLR $dst\t!ptr" %}
6204 ins_encode %{
6205 __ clr($dst$$Register);
6206 %}
6207 ins_pipe(ialu_imm);
6208 %}
6209
6210 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6211 match(Set dst src);
6212 ins_cost(DEFAULT_COST);
6213 format %{ "SET $src,$dst\t!ptr" %}
6214 ins_encode %{
6215 AddressLiteral polling_page(os::get_polling_page());
6216 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6217 %}
6218 ins_pipe(loadConP_poll);
6219 %}
6220
6221 instruct loadConN0(iRegN dst, immN0 src) %{
6222 match(Set dst src);
6223
6224 size(4);
6225 format %{ "CLR $dst\t! compressed NULL ptr" %}
6226 ins_encode %{
6227 __ clr($dst$$Register);
6228 %}
6229 ins_pipe(ialu_imm);
6230 %}
6231
6232 instruct loadConN(iRegN dst, immN src) %{
6233 match(Set dst src);
6234 ins_cost(DEFAULT_COST * 3/2);
6235 format %{ "SET $src,$dst\t! compressed ptr" %}
6236 ins_encode %{
6237 Register dst = $dst$$Register;
6238 __ set_narrow_oop((jobject)$src$$constant, dst);
6239 %}
6240 ins_pipe(ialu_hi_lo_reg);
6241 %}
6242
6243 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6244 match(Set dst src);
6245 ins_cost(DEFAULT_COST * 3/2);
6246 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6247 ins_encode %{
6248 Register dst = $dst$$Register;
6249 __ set_narrow_klass((Klass*)$src$$constant, dst);
6250 %}
6251 ins_pipe(ialu_hi_lo_reg);
6252 %}
6253
6254 // Materialize long value (predicated by immL_cheap).
6255 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6256 match(Set dst con);
6257 effect(KILL tmp);
6258 ins_cost(DEFAULT_COST * 3);
6259 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6260 ins_encode %{
6261 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6262 %}
6263 ins_pipe(loadConL);
6264 %}
6265
6266 // Load long value from constant table (predicated by immL_expensive).
6267 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6268 match(Set dst con);
6269 ins_cost(MEMORY_REF_COST);
6270 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6271 ins_encode %{
6272 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6273 __ ldx($constanttablebase, con_offset, $dst$$Register);
6274 %}
6275 ins_pipe(loadConL);
6276 %}
6277
6278 instruct loadConL0( iRegL dst, immL0 src ) %{
6279 match(Set dst src);
6280 ins_cost(DEFAULT_COST);
6281 size(4);
6282 format %{ "CLR $dst\t! long" %}
6283 ins_encode( Set13( src, dst ) );
6284 ins_pipe(ialu_imm);
6285 %}
6286
6287 instruct loadConL13( iRegL dst, immL13 src ) %{
6288 match(Set dst src);
6289 ins_cost(DEFAULT_COST * 2);
6290
6291 size(4);
6292 format %{ "MOV $src,$dst\t! long" %}
6293 ins_encode( Set13( src, dst ) );
6294 ins_pipe(ialu_imm);
6295 %}
6296
6297 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6298 match(Set dst con);
6299 effect(KILL tmp);
6300 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6301 ins_encode %{
6302 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6303 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6304 %}
6305 ins_pipe(loadConFD);
6306 %}
6307
6308 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6309 match(Set dst con);
6310 effect(KILL tmp);
6311 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6312 ins_encode %{
6313 // XXX This is a quick fix for 6833573.
6314 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6315 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6316 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6317 %}
6318 ins_pipe(loadConFD);
6319 %}
6320
6321 // Prefetch instructions for allocation.
6322 // Must be safe to execute with invalid address (cannot fault).
6323
6324 instruct prefetchAlloc( memory mem ) %{
6325 predicate(AllocatePrefetchInstr == 0);
6326 match( PrefetchAllocation mem );
6327 ins_cost(MEMORY_REF_COST);
6328 size(4);
6329
6330 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6331 opcode(Assembler::prefetch_op3);
6332 ins_encode( form3_mem_prefetch_write( mem ) );
6333 ins_pipe(iload_mem);
6334 %}
6335
6336 // Use BIS instruction to prefetch for allocation.
6337 // Could fault, need space at the end of TLAB.
6338 instruct prefetchAlloc_bis( iRegP dst ) %{
6339 predicate(AllocatePrefetchInstr == 1);
6340 match( PrefetchAllocation dst );
6341 ins_cost(MEMORY_REF_COST);
6342 size(4);
6343
6344 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6345 ins_encode %{
6346 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6347 %}
6348 ins_pipe(istore_mem_reg);
6349 %}
6350
6351 // Next code is used for finding next cache line address to prefetch.
6352 #ifndef _LP64
6353 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6354 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6355 ins_cost(DEFAULT_COST);
6356 size(4);
6357
6358 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6359 ins_encode %{
6360 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6361 %}
6362 ins_pipe(ialu_reg_imm);
6363 %}
6364 #else
6365 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6366 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6367 ins_cost(DEFAULT_COST);
6368 size(4);
6369
6370 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6371 ins_encode %{
6372 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6373 %}
6374 ins_pipe(ialu_reg_imm);
6375 %}
6376 #endif
6377
6378 //----------Store Instructions-------------------------------------------------
6379 // Store Byte
6380 instruct storeB(memory mem, iRegI src) %{
6381 match(Set mem (StoreB mem src));
6382 ins_cost(MEMORY_REF_COST);
6383
6384 size(4);
6385 format %{ "STB $src,$mem\t! byte" %}
6386 opcode(Assembler::stb_op3);
6387 ins_encode(simple_form3_mem_reg( mem, src ) );
6388 ins_pipe(istore_mem_reg);
6389 %}
6390
6391 instruct storeB0(memory mem, immI0 src) %{
6392 match(Set mem (StoreB mem src));
6393 ins_cost(MEMORY_REF_COST);
6394
6395 size(4);
6396 format %{ "STB $src,$mem\t! byte" %}
6397 opcode(Assembler::stb_op3);
6398 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6399 ins_pipe(istore_mem_zero);
6400 %}
6401
6402 instruct storeCM0(memory mem, immI0 src) %{
6403 match(Set mem (StoreCM mem src));
6404 ins_cost(MEMORY_REF_COST);
6405
6406 size(4);
6407 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6408 opcode(Assembler::stb_op3);
6409 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6410 ins_pipe(istore_mem_zero);
6411 %}
6412
6413 // Store Char/Short
6414 instruct storeC(memory mem, iRegI src) %{
6415 match(Set mem (StoreC mem src));
6416 ins_cost(MEMORY_REF_COST);
6417
6418 size(4);
6419 format %{ "STH $src,$mem\t! short" %}
6420 opcode(Assembler::sth_op3);
6421 ins_encode(simple_form3_mem_reg( mem, src ) );
6422 ins_pipe(istore_mem_reg);
6423 %}
6424
6425 instruct storeC0(memory mem, immI0 src) %{
6426 match(Set mem (StoreC mem src));
6427 ins_cost(MEMORY_REF_COST);
6428
6429 size(4);
6430 format %{ "STH $src,$mem\t! short" %}
6431 opcode(Assembler::sth_op3);
6432 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6433 ins_pipe(istore_mem_zero);
6434 %}
6435
6436 // Store Integer
6437 instruct storeI(memory mem, iRegI src) %{
6438 match(Set mem (StoreI mem src));
6439 ins_cost(MEMORY_REF_COST);
6440
6441 size(4);
6442 format %{ "STW $src,$mem" %}
6443 opcode(Assembler::stw_op3);
6444 ins_encode(simple_form3_mem_reg( mem, src ) );
6445 ins_pipe(istore_mem_reg);
6446 %}
6447
6448 // Store Long
6449 instruct storeL(memory mem, iRegL src) %{
6450 match(Set mem (StoreL mem src));
6451 ins_cost(MEMORY_REF_COST);
6452 size(4);
6453 format %{ "STX $src,$mem\t! long" %}
6454 opcode(Assembler::stx_op3);
6455 ins_encode(simple_form3_mem_reg( mem, src ) );
6456 ins_pipe(istore_mem_reg);
6457 %}
6458
6459 instruct storeI0(memory mem, immI0 src) %{
6460 match(Set mem (StoreI mem src));
6461 ins_cost(MEMORY_REF_COST);
6462
6463 size(4);
6464 format %{ "STW $src,$mem" %}
6465 opcode(Assembler::stw_op3);
6466 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6467 ins_pipe(istore_mem_zero);
6468 %}
6469
6470 instruct storeL0(memory mem, immL0 src) %{
6471 match(Set mem (StoreL mem src));
6472 ins_cost(MEMORY_REF_COST);
6473
6474 size(4);
6475 format %{ "STX $src,$mem" %}
6476 opcode(Assembler::stx_op3);
6477 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6478 ins_pipe(istore_mem_zero);
6479 %}
6480
6481 // Store Integer from float register (used after fstoi)
6482 instruct storeI_Freg(memory mem, regF src) %{
6483 match(Set mem (StoreI mem src));
6484 ins_cost(MEMORY_REF_COST);
6485
6486 size(4);
6487 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6488 opcode(Assembler::stf_op3);
6489 ins_encode(simple_form3_mem_reg( mem, src ) );
6490 ins_pipe(fstoreF_mem_reg);
6491 %}
6492
6493 // Store Pointer
6494 instruct storeP(memory dst, sp_ptr_RegP src) %{
6495 match(Set dst (StoreP dst src));
6496 ins_cost(MEMORY_REF_COST);
6497 size(4);
6498
6499 #ifndef _LP64
6500 format %{ "STW $src,$dst\t! ptr" %}
6501 opcode(Assembler::stw_op3, 0, REGP_OP);
6502 #else
6503 format %{ "STX $src,$dst\t! ptr" %}
6504 opcode(Assembler::stx_op3, 0, REGP_OP);
6505 #endif
6506 ins_encode( form3_mem_reg( dst, src ) );
6507 ins_pipe(istore_mem_spORreg);
6508 %}
6509
6510 instruct storeP0(memory dst, immP0 src) %{
6511 match(Set dst (StoreP dst src));
6512 ins_cost(MEMORY_REF_COST);
6513 size(4);
6514
6515 #ifndef _LP64
6516 format %{ "STW $src,$dst\t! ptr" %}
6517 opcode(Assembler::stw_op3, 0, REGP_OP);
6518 #else
6519 format %{ "STX $src,$dst\t! ptr" %}
6520 opcode(Assembler::stx_op3, 0, REGP_OP);
6521 #endif
6522 ins_encode( form3_mem_reg( dst, R_G0 ) );
6523 ins_pipe(istore_mem_zero);
6524 %}
6525
6526 // Store Compressed Pointer
6527 instruct storeN(memory dst, iRegN src) %{
6528 match(Set dst (StoreN dst src));
6529 ins_cost(MEMORY_REF_COST);
6530 size(4);
6531
6532 format %{ "STW $src,$dst\t! compressed ptr" %}
6533 ins_encode %{
6534 Register base = as_Register($dst$$base);
6535 Register index = as_Register($dst$$index);
6536 Register src = $src$$Register;
6537 if (index != G0) {
6538 __ stw(src, base, index);
6539 } else {
6540 __ stw(src, base, $dst$$disp);
6541 }
6542 %}
6543 ins_pipe(istore_mem_spORreg);
6544 %}
6545
6546 instruct storeNKlass(memory dst, iRegN src) %{
6547 match(Set dst (StoreNKlass dst src));
6548 ins_cost(MEMORY_REF_COST);
6549 size(4);
6550
6551 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6552 ins_encode %{
6553 Register base = as_Register($dst$$base);
6554 Register index = as_Register($dst$$index);
6555 Register src = $src$$Register;
6556 if (index != G0) {
6557 __ stw(src, base, index);
6558 } else {
6559 __ stw(src, base, $dst$$disp);
6560 }
6561 %}
6562 ins_pipe(istore_mem_spORreg);
6563 %}
6564
6565 instruct storeN0(memory dst, immN0 src) %{
6566 match(Set dst (StoreN dst src));
6567 ins_cost(MEMORY_REF_COST);
6568 size(4);
6569
6570 format %{ "STW $src,$dst\t! compressed ptr" %}
6571 ins_encode %{
6572 Register base = as_Register($dst$$base);
6573 Register index = as_Register($dst$$index);
6574 if (index != G0) {
6575 __ stw(0, base, index);
6576 } else {
6577 __ stw(0, base, $dst$$disp);
6578 }
6579 %}
6580 ins_pipe(istore_mem_zero);
6581 %}
6582
6583 // Store Double
6584 instruct storeD( memory mem, regD src) %{
6585 match(Set mem (StoreD mem src));
6586 ins_cost(MEMORY_REF_COST);
6587
6588 size(4);
6589 format %{ "STDF $src,$mem" %}
6590 opcode(Assembler::stdf_op3);
6591 ins_encode(simple_form3_mem_reg( mem, src ) );
6592 ins_pipe(fstoreD_mem_reg);
6593 %}
6594
6595 instruct storeD0( memory mem, immD0 src) %{
6596 match(Set mem (StoreD mem src));
6597 ins_cost(MEMORY_REF_COST);
6598
6599 size(4);
6600 format %{ "STX $src,$mem" %}
6601 opcode(Assembler::stx_op3);
6602 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6603 ins_pipe(fstoreD_mem_zero);
6604 %}
6605
6606 // Store Float
6607 instruct storeF( memory mem, regF src) %{
6608 match(Set mem (StoreF mem src));
6609 ins_cost(MEMORY_REF_COST);
6610
6611 size(4);
6612 format %{ "STF $src,$mem" %}
6613 opcode(Assembler::stf_op3);
6614 ins_encode(simple_form3_mem_reg( mem, src ) );
6615 ins_pipe(fstoreF_mem_reg);
6616 %}
6617
6618 instruct storeF0( memory mem, immF0 src) %{
6619 match(Set mem (StoreF mem src));
6620 ins_cost(MEMORY_REF_COST);
6621
6622 size(4);
6623 format %{ "STW $src,$mem\t! storeF0" %}
6624 opcode(Assembler::stw_op3);
6625 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6626 ins_pipe(fstoreF_mem_zero);
6627 %}
6628
6629 // Convert oop pointer into compressed form
6630 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6631 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6632 match(Set dst (EncodeP src));
6633 format %{ "encode_heap_oop $src, $dst" %}
6634 ins_encode %{
6635 __ encode_heap_oop($src$$Register, $dst$$Register);
6636 %}
6637 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6638 ins_pipe(ialu_reg);
6639 %}
6640
6641 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6642 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6643 match(Set dst (EncodeP src));
6644 format %{ "encode_heap_oop_not_null $src, $dst" %}
6645 ins_encode %{
6646 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6647 %}
6648 ins_pipe(ialu_reg);
6649 %}
6650
6651 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6652 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6653 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6654 match(Set dst (DecodeN src));
6655 format %{ "decode_heap_oop $src, $dst" %}
6656 ins_encode %{
6657 __ decode_heap_oop($src$$Register, $dst$$Register);
6658 %}
6659 ins_pipe(ialu_reg);
6660 %}
6661
6662 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6663 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6664 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6665 match(Set dst (DecodeN src));
6666 format %{ "decode_heap_oop_not_null $src, $dst" %}
6667 ins_encode %{
6668 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6669 %}
6670 ins_pipe(ialu_reg);
6671 %}
6672
6673 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6674 match(Set dst (EncodePKlass src));
6675 format %{ "encode_klass_not_null $src, $dst" %}
6676 ins_encode %{
6677 __ encode_klass_not_null($src$$Register, $dst$$Register);
6678 %}
6679 ins_pipe(ialu_reg);
6680 %}
6681
6682 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6683 match(Set dst (DecodeNKlass src));
6684 format %{ "decode_klass_not_null $src, $dst" %}
6685 ins_encode %{
6686 __ decode_klass_not_null($src$$Register, $dst$$Register);
6687 %}
6688 ins_pipe(ialu_reg);
6689 %}
6690
6691 //----------MemBar Instructions-----------------------------------------------
6692 // Memory barrier flavors
6693
6694 instruct membar_acquire() %{
6695 match(MemBarAcquire);
6696 match(LoadFence);
6697 ins_cost(4*MEMORY_REF_COST);
6698
6699 size(0);
6700 format %{ "MEMBAR-acquire" %}
6701 ins_encode( enc_membar_acquire );
6702 ins_pipe(long_memory_op);
6703 %}
6704
6705 instruct membar_acquire_lock() %{
6706 match(MemBarAcquireLock);
6707 ins_cost(0);
6708
6709 size(0);
6710 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6711 ins_encode( );
6712 ins_pipe(empty);
6713 %}
6714
6715 instruct membar_release() %{
6716 match(MemBarRelease);
6717 match(StoreFence);
6718 ins_cost(4*MEMORY_REF_COST);
6719
6720 size(0);
6721 format %{ "MEMBAR-release" %}
6722 ins_encode( enc_membar_release );
6723 ins_pipe(long_memory_op);
6724 %}
6725
6726 instruct membar_release_lock() %{
6727 match(MemBarReleaseLock);
6728 ins_cost(0);
6729
6730 size(0);
6731 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6732 ins_encode( );
6733 ins_pipe(empty);
6734 %}
6735
6736 instruct membar_volatile() %{
6737 match(MemBarVolatile);
6738 ins_cost(4*MEMORY_REF_COST);
6739
6740 size(4);
6741 format %{ "MEMBAR-volatile" %}
6742 ins_encode( enc_membar_volatile );
6743 ins_pipe(long_memory_op);
6744 %}
6745
6746 instruct unnecessary_membar_volatile() %{
6747 match(MemBarVolatile);
6748 predicate(Matcher::post_store_load_barrier(n));
6749 ins_cost(0);
6750
6751 size(0);
6752 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6753 ins_encode( );
6754 ins_pipe(empty);
6755 %}
6756
6757 instruct membar_storestore() %{
6758 match(MemBarStoreStore);
6759 ins_cost(0);
6760
6761 size(0);
6762 format %{ "!MEMBAR-storestore (empty encoding)" %}
6763 ins_encode( );
6764 ins_pipe(empty);
6765 %}
6766
6767 //----------Register Move Instructions-----------------------------------------
6768 instruct roundDouble_nop(regD dst) %{
6769 match(Set dst (RoundDouble dst));
6770 ins_cost(0);
6771 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6772 ins_encode( );
6773 ins_pipe(empty);
6774 %}
6775
6776
6777 instruct roundFloat_nop(regF dst) %{
6778 match(Set dst (RoundFloat dst));
6779 ins_cost(0);
6780 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6781 ins_encode( );
6782 ins_pipe(empty);
6783 %}
6784
6785
6786 // Cast Index to Pointer for unsafe natives
6787 instruct castX2P(iRegX src, iRegP dst) %{
6788 match(Set dst (CastX2P src));
6789
6790 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6791 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6792 ins_pipe(ialu_reg);
6793 %}
6794
6795 // Cast Pointer to Index for unsafe natives
6796 instruct castP2X(iRegP src, iRegX dst) %{
6797 match(Set dst (CastP2X src));
6798
6799 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6800 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6801 ins_pipe(ialu_reg);
6802 %}
6803
6804 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6805 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6806 match(Set stkSlot src); // chain rule
6807 ins_cost(MEMORY_REF_COST);
6808 format %{ "STDF $src,$stkSlot\t!stk" %}
6809 opcode(Assembler::stdf_op3);
6810 ins_encode(simple_form3_mem_reg(stkSlot, src));
6811 ins_pipe(fstoreD_stk_reg);
6812 %}
6813
6814 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6815 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6816 match(Set dst stkSlot); // chain rule
6817 ins_cost(MEMORY_REF_COST);
6818 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6819 opcode(Assembler::lddf_op3);
6820 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6821 ins_pipe(floadD_stk);
6822 %}
6823
6824 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6825 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6826 match(Set stkSlot src); // chain rule
6827 ins_cost(MEMORY_REF_COST);
6828 format %{ "STF $src,$stkSlot\t!stk" %}
6829 opcode(Assembler::stf_op3);
6830 ins_encode(simple_form3_mem_reg(stkSlot, src));
6831 ins_pipe(fstoreF_stk_reg);
6832 %}
6833
6834 //----------Conditional Move---------------------------------------------------
6835 // Conditional move
6836 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6837 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6838 ins_cost(150);
6839 format %{ "MOV$cmp $pcc,$src,$dst" %}
6840 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6841 ins_pipe(ialu_reg);
6842 %}
6843
6844 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6845 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6846 ins_cost(140);
6847 format %{ "MOV$cmp $pcc,$src,$dst" %}
6848 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6849 ins_pipe(ialu_imm);
6850 %}
6851
6852 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6853 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6854 ins_cost(150);
6855 size(4);
6856 format %{ "MOV$cmp $icc,$src,$dst" %}
6857 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6858 ins_pipe(ialu_reg);
6859 %}
6860
6861 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6862 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6863 ins_cost(140);
6864 size(4);
6865 format %{ "MOV$cmp $icc,$src,$dst" %}
6866 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6867 ins_pipe(ialu_imm);
6868 %}
6869
6870 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6871 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6872 ins_cost(150);
6873 size(4);
6874 format %{ "MOV$cmp $icc,$src,$dst" %}
6875 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6876 ins_pipe(ialu_reg);
6877 %}
6878
6879 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6880 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6881 ins_cost(140);
6882 size(4);
6883 format %{ "MOV$cmp $icc,$src,$dst" %}
6884 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6885 ins_pipe(ialu_imm);
6886 %}
6887
6888 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6889 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6890 ins_cost(150);
6891 size(4);
6892 format %{ "MOV$cmp $fcc,$src,$dst" %}
6893 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6894 ins_pipe(ialu_reg);
6895 %}
6896
6897 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6898 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6899 ins_cost(140);
6900 size(4);
6901 format %{ "MOV$cmp $fcc,$src,$dst" %}
6902 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6903 ins_pipe(ialu_imm);
6904 %}
6905
6906 // Conditional move for RegN. Only cmov(reg,reg).
6907 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6908 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6909 ins_cost(150);
6910 format %{ "MOV$cmp $pcc,$src,$dst" %}
6911 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6912 ins_pipe(ialu_reg);
6913 %}
6914
6915 // This instruction also works with CmpN so we don't need cmovNN_reg.
6916 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6917 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6918 ins_cost(150);
6919 size(4);
6920 format %{ "MOV$cmp $icc,$src,$dst" %}
6921 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6922 ins_pipe(ialu_reg);
6923 %}
6924
6925 // This instruction also works with CmpN so we don't need cmovNN_reg.
6926 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6927 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6928 ins_cost(150);
6929 size(4);
6930 format %{ "MOV$cmp $icc,$src,$dst" %}
6931 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6932 ins_pipe(ialu_reg);
6933 %}
6934
6935 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6936 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6937 ins_cost(150);
6938 size(4);
6939 format %{ "MOV$cmp $fcc,$src,$dst" %}
6940 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6941 ins_pipe(ialu_reg);
6942 %}
6943
6944 // Conditional move
6945 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6946 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6947 ins_cost(150);
6948 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6949 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6950 ins_pipe(ialu_reg);
6951 %}
6952
6953 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6954 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6955 ins_cost(140);
6956 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6957 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6958 ins_pipe(ialu_imm);
6959 %}
6960
6961 // This instruction also works with CmpN so we don't need cmovPN_reg.
6962 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6963 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6964 ins_cost(150);
6965
6966 size(4);
6967 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6968 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6969 ins_pipe(ialu_reg);
6970 %}
6971
6972 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6973 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6974 ins_cost(150);
6975
6976 size(4);
6977 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6978 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6979 ins_pipe(ialu_reg);
6980 %}
6981
6982 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6983 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6984 ins_cost(140);
6985
6986 size(4);
6987 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6988 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6989 ins_pipe(ialu_imm);
6990 %}
6991
6992 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6993 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6994 ins_cost(140);
6995
6996 size(4);
6997 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6998 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6999 ins_pipe(ialu_imm);
7000 %}
7001
7002 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
7003 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7004 ins_cost(150);
7005 size(4);
7006 format %{ "MOV$cmp $fcc,$src,$dst" %}
7007 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7008 ins_pipe(ialu_imm);
7009 %}
7010
7011 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
7012 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7013 ins_cost(140);
7014 size(4);
7015 format %{ "MOV$cmp $fcc,$src,$dst" %}
7016 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
7017 ins_pipe(ialu_imm);
7018 %}
7019
7020 // Conditional move
7021 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
7022 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
7023 ins_cost(150);
7024 opcode(0x101);
7025 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7026 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7027 ins_pipe(int_conditional_float_move);
7028 %}
7029
7030 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7031 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7032 ins_cost(150);
7033
7034 size(4);
7035 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7036 opcode(0x101);
7037 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7038 ins_pipe(int_conditional_float_move);
7039 %}
7040
7041 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7042 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7043 ins_cost(150);
7044
7045 size(4);
7046 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7047 opcode(0x101);
7048 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7049 ins_pipe(int_conditional_float_move);
7050 %}
7051
7052 // Conditional move,
7053 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7054 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7055 ins_cost(150);
7056 size(4);
7057 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7058 opcode(0x1);
7059 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7060 ins_pipe(int_conditional_double_move);
7061 %}
7062
7063 // Conditional move
7064 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7065 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7066 ins_cost(150);
7067 size(4);
7068 opcode(0x102);
7069 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7070 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7071 ins_pipe(int_conditional_double_move);
7072 %}
7073
7074 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7075 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7076 ins_cost(150);
7077
7078 size(4);
7079 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7080 opcode(0x102);
7081 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7082 ins_pipe(int_conditional_double_move);
7083 %}
7084
7085 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7086 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7087 ins_cost(150);
7088
7089 size(4);
7090 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7091 opcode(0x102);
7092 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7093 ins_pipe(int_conditional_double_move);
7094 %}
7095
7096 // Conditional move,
7097 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7098 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7099 ins_cost(150);
7100 size(4);
7101 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7102 opcode(0x2);
7103 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7104 ins_pipe(int_conditional_double_move);
7105 %}
7106
7107 // Conditional move
7108 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7109 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7110 ins_cost(150);
7111 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7112 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7113 ins_pipe(ialu_reg);
7114 %}
7115
7116 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7117 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7118 ins_cost(140);
7119 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7120 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7121 ins_pipe(ialu_imm);
7122 %}
7123
7124 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7125 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7126 ins_cost(150);
7127
7128 size(4);
7129 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7130 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7131 ins_pipe(ialu_reg);
7132 %}
7133
7134
7135 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7136 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7137 ins_cost(150);
7138
7139 size(4);
7140 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7141 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7142 ins_pipe(ialu_reg);
7143 %}
7144
7145
7146 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7147 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7148 ins_cost(150);
7149
7150 size(4);
7151 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7152 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7153 ins_pipe(ialu_reg);
7154 %}
7155
7156
7157
7158 //----------OS and Locking Instructions----------------------------------------
7159
7160 // This name is KNOWN by the ADLC and cannot be changed.
7161 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7162 // for this guy.
7163 instruct tlsLoadP(g2RegP dst) %{
7164 match(Set dst (ThreadLocal));
7165
7166 size(0);
7167 ins_cost(0);
7168 format %{ "# TLS is in G2" %}
7169 ins_encode( /*empty encoding*/ );
7170 ins_pipe(ialu_none);
7171 %}
7172
7173 instruct checkCastPP( iRegP dst ) %{
7174 match(Set dst (CheckCastPP dst));
7175
7176 size(0);
7177 format %{ "# checkcastPP of $dst" %}
7178 ins_encode( /*empty encoding*/ );
7179 ins_pipe(empty);
7180 %}
7181
7182
7183 instruct castPP( iRegP dst ) %{
7184 match(Set dst (CastPP dst));
7185 format %{ "# castPP of $dst" %}
7186 ins_encode( /*empty encoding*/ );
7187 ins_pipe(empty);
7188 %}
7189
7190 instruct castII( iRegI dst ) %{
7191 match(Set dst (CastII dst));
7192 format %{ "# castII of $dst" %}
7193 ins_encode( /*empty encoding*/ );
7194 ins_cost(0);
7195 ins_pipe(empty);
7196 %}
7197
7198 //----------Arithmetic Instructions--------------------------------------------
7199 // Addition Instructions
7200 // Register Addition
7201 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7202 match(Set dst (AddI src1 src2));
7203
7204 size(4);
7205 format %{ "ADD $src1,$src2,$dst" %}
7206 ins_encode %{
7207 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7208 %}
7209 ins_pipe(ialu_reg_reg);
7210 %}
7211
7212 // Immediate Addition
7213 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7214 match(Set dst (AddI src1 src2));
7215
7216 size(4);
7217 format %{ "ADD $src1,$src2,$dst" %}
7218 opcode(Assembler::add_op3, Assembler::arith_op);
7219 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7220 ins_pipe(ialu_reg_imm);
7221 %}
7222
7223 // Pointer Register Addition
7224 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7225 match(Set dst (AddP src1 src2));
7226
7227 size(4);
7228 format %{ "ADD $src1,$src2,$dst" %}
7229 opcode(Assembler::add_op3, Assembler::arith_op);
7230 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7231 ins_pipe(ialu_reg_reg);
7232 %}
7233
7234 // Pointer Immediate Addition
7235 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7236 match(Set dst (AddP src1 src2));
7237
7238 size(4);
7239 format %{ "ADD $src1,$src2,$dst" %}
7240 opcode(Assembler::add_op3, Assembler::arith_op);
7241 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7242 ins_pipe(ialu_reg_imm);
7243 %}
7244
7245 // Long Addition
7246 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7247 match(Set dst (AddL src1 src2));
7248
7249 size(4);
7250 format %{ "ADD $src1,$src2,$dst\t! long" %}
7251 opcode(Assembler::add_op3, Assembler::arith_op);
7252 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7253 ins_pipe(ialu_reg_reg);
7254 %}
7255
7256 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7257 match(Set dst (AddL src1 con));
7258
7259 size(4);
7260 format %{ "ADD $src1,$con,$dst" %}
7261 opcode(Assembler::add_op3, Assembler::arith_op);
7262 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7263 ins_pipe(ialu_reg_imm);
7264 %}
7265
7266 //----------Conditional_store--------------------------------------------------
7267 // Conditional-store of the updated heap-top.
7268 // Used during allocation of the shared heap.
7269 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7270
7271 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7272 instruct loadPLocked(iRegP dst, memory mem) %{
7273 match(Set dst (LoadPLocked mem));
7274 ins_cost(MEMORY_REF_COST);
7275
7276 #ifndef _LP64
7277 size(4);
7278 format %{ "LDUW $mem,$dst\t! ptr" %}
7279 opcode(Assembler::lduw_op3, 0, REGP_OP);
7280 #else
7281 format %{ "LDX $mem,$dst\t! ptr" %}
7282 opcode(Assembler::ldx_op3, 0, REGP_OP);
7283 #endif
7284 ins_encode( form3_mem_reg( mem, dst ) );
7285 ins_pipe(iload_mem);
7286 %}
7287
7288 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7289 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7290 effect( KILL newval );
7291 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7292 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7293 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7294 ins_pipe( long_memory_op );
7295 %}
7296
7297 // Conditional-store of an int value.
7298 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7299 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7300 effect( KILL newval );
7301 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7302 "CMP $oldval,$newval\t\t! See if we made progress" %}
7303 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7304 ins_pipe( long_memory_op );
7305 %}
7306
7307 // Conditional-store of a long value.
7308 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7309 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7310 effect( KILL newval );
7311 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7312 "CMP $oldval,$newval\t\t! See if we made progress" %}
7313 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7314 ins_pipe( long_memory_op );
7315 %}
7316
7317 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7318
7319 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7320 predicate(VM_Version::supports_cx8());
7321 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7322 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7323 format %{
7324 "MOV $newval,O7\n\t"
7325 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7326 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7327 "MOV 1,$res\n\t"
7328 "MOVne xcc,R_G0,$res"
7329 %}
7330 ins_encode( enc_casx(mem_ptr, oldval, newval),
7331 enc_lflags_ne_to_boolean(res) );
7332 ins_pipe( long_memory_op );
7333 %}
7334
7335
7336 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7337 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7338 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7339 format %{
7340 "MOV $newval,O7\n\t"
7341 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7342 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7343 "MOV 1,$res\n\t"
7344 "MOVne icc,R_G0,$res"
7345 %}
7346 ins_encode( enc_casi(mem_ptr, oldval, newval),
7347 enc_iflags_ne_to_boolean(res) );
7348 ins_pipe( long_memory_op );
7349 %}
7350
7351 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7352 #ifdef _LP64
7353 predicate(VM_Version::supports_cx8());
7354 #endif
7355 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7356 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7357 format %{
7358 "MOV $newval,O7\n\t"
7359 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7360 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7361 "MOV 1,$res\n\t"
7362 "MOVne xcc,R_G0,$res"
7363 %}
7364 #ifdef _LP64
7365 ins_encode( enc_casx(mem_ptr, oldval, newval),
7366 enc_lflags_ne_to_boolean(res) );
7367 #else
7368 ins_encode( enc_casi(mem_ptr, oldval, newval),
7369 enc_iflags_ne_to_boolean(res) );
7370 #endif
7371 ins_pipe( long_memory_op );
7372 %}
7373
7374 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7375 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7376 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7377 format %{
7378 "MOV $newval,O7\n\t"
7379 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7380 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7381 "MOV 1,$res\n\t"
7382 "MOVne icc,R_G0,$res"
7383 %}
7384 ins_encode( enc_casi(mem_ptr, oldval, newval),
7385 enc_iflags_ne_to_boolean(res) );
7386 ins_pipe( long_memory_op );
7387 %}
7388
7389 instruct xchgI( memory mem, iRegI newval) %{
7390 match(Set newval (GetAndSetI mem newval));
7391 format %{ "SWAP [$mem],$newval" %}
7392 size(4);
7393 ins_encode %{
7394 __ swap($mem$$Address, $newval$$Register);
7395 %}
7396 ins_pipe( long_memory_op );
7397 %}
7398
7399 #ifndef _LP64
7400 instruct xchgP( memory mem, iRegP newval) %{
7401 match(Set newval (GetAndSetP mem newval));
7402 format %{ "SWAP [$mem],$newval" %}
7403 size(4);
7404 ins_encode %{
7405 __ swap($mem$$Address, $newval$$Register);
7406 %}
7407 ins_pipe( long_memory_op );
7408 %}
7409 #endif
7410
7411 instruct xchgN( memory mem, iRegN newval) %{
7412 match(Set newval (GetAndSetN mem newval));
7413 format %{ "SWAP [$mem],$newval" %}
7414 size(4);
7415 ins_encode %{
7416 __ swap($mem$$Address, $newval$$Register);
7417 %}
7418 ins_pipe( long_memory_op );
7419 %}
7420
7421 //---------------------
7422 // Subtraction Instructions
7423 // Register Subtraction
7424 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7425 match(Set dst (SubI src1 src2));
7426
7427 size(4);
7428 format %{ "SUB $src1,$src2,$dst" %}
7429 opcode(Assembler::sub_op3, Assembler::arith_op);
7430 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7431 ins_pipe(ialu_reg_reg);
7432 %}
7433
7434 // Immediate Subtraction
7435 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7436 match(Set dst (SubI src1 src2));
7437
7438 size(4);
7439 format %{ "SUB $src1,$src2,$dst" %}
7440 opcode(Assembler::sub_op3, Assembler::arith_op);
7441 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7442 ins_pipe(ialu_reg_imm);
7443 %}
7444
7445 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7446 match(Set dst (SubI zero src2));
7447
7448 size(4);
7449 format %{ "NEG $src2,$dst" %}
7450 opcode(Assembler::sub_op3, Assembler::arith_op);
7451 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7452 ins_pipe(ialu_zero_reg);
7453 %}
7454
7455 // Long subtraction
7456 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7457 match(Set dst (SubL src1 src2));
7458
7459 size(4);
7460 format %{ "SUB $src1,$src2,$dst\t! long" %}
7461 opcode(Assembler::sub_op3, Assembler::arith_op);
7462 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7463 ins_pipe(ialu_reg_reg);
7464 %}
7465
7466 // Immediate Subtraction
7467 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7468 match(Set dst (SubL src1 con));
7469
7470 size(4);
7471 format %{ "SUB $src1,$con,$dst\t! long" %}
7472 opcode(Assembler::sub_op3, Assembler::arith_op);
7473 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7474 ins_pipe(ialu_reg_imm);
7475 %}
7476
7477 // Long negation
7478 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7479 match(Set dst (SubL zero src2));
7480
7481 size(4);
7482 format %{ "NEG $src2,$dst\t! long" %}
7483 opcode(Assembler::sub_op3, Assembler::arith_op);
7484 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7485 ins_pipe(ialu_zero_reg);
7486 %}
7487
7488 // Multiplication Instructions
7489 // Integer Multiplication
7490 // Register Multiplication
7491 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7492 match(Set dst (MulI src1 src2));
7493
7494 size(4);
7495 format %{ "MULX $src1,$src2,$dst" %}
7496 opcode(Assembler::mulx_op3, Assembler::arith_op);
7497 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7498 ins_pipe(imul_reg_reg);
7499 %}
7500
7501 // Immediate Multiplication
7502 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7503 match(Set dst (MulI src1 src2));
7504
7505 size(4);
7506 format %{ "MULX $src1,$src2,$dst" %}
7507 opcode(Assembler::mulx_op3, Assembler::arith_op);
7508 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7509 ins_pipe(imul_reg_imm);
7510 %}
7511
7512 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7513 match(Set dst (MulL src1 src2));
7514 ins_cost(DEFAULT_COST * 5);
7515 size(4);
7516 format %{ "MULX $src1,$src2,$dst\t! long" %}
7517 opcode(Assembler::mulx_op3, Assembler::arith_op);
7518 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7519 ins_pipe(mulL_reg_reg);
7520 %}
7521
7522 // Immediate Multiplication
7523 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7524 match(Set dst (MulL src1 src2));
7525 ins_cost(DEFAULT_COST * 5);
7526 size(4);
7527 format %{ "MULX $src1,$src2,$dst" %}
7528 opcode(Assembler::mulx_op3, Assembler::arith_op);
7529 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7530 ins_pipe(mulL_reg_imm);
7531 %}
7532
7533 // Integer Division
7534 // Register Division
7535 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7536 match(Set dst (DivI src1 src2));
7537 ins_cost((2+71)*DEFAULT_COST);
7538
7539 format %{ "SRA $src2,0,$src2\n\t"
7540 "SRA $src1,0,$src1\n\t"
7541 "SDIVX $src1,$src2,$dst" %}
7542 ins_encode( idiv_reg( src1, src2, dst ) );
7543 ins_pipe(sdiv_reg_reg);
7544 %}
7545
7546 // Immediate Division
7547 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7548 match(Set dst (DivI src1 src2));
7549 ins_cost((2+71)*DEFAULT_COST);
7550
7551 format %{ "SRA $src1,0,$src1\n\t"
7552 "SDIVX $src1,$src2,$dst" %}
7553 ins_encode( idiv_imm( src1, src2, dst ) );
7554 ins_pipe(sdiv_reg_imm);
7555 %}
7556
7557 //----------Div-By-10-Expansion------------------------------------------------
7558 // Extract hi bits of a 32x32->64 bit multiply.
7559 // Expand rule only, not matched
7560 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7561 effect( DEF dst, USE src1, USE src2 );
7562 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7563 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7564 ins_encode( enc_mul_hi(dst,src1,src2));
7565 ins_pipe(sdiv_reg_reg);
7566 %}
7567
7568 // Magic constant, reciprocal of 10
7569 instruct loadConI_x66666667(iRegIsafe dst) %{
7570 effect( DEF dst );
7571
7572 size(8);
7573 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7574 ins_encode( Set32(0x66666667, dst) );
7575 ins_pipe(ialu_hi_lo_reg);
7576 %}
7577
7578 // Register Shift Right Arithmetic Long by 32-63
7579 instruct sra_31( iRegI dst, iRegI src ) %{
7580 effect( DEF dst, USE src );
7581 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7582 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7583 ins_pipe(ialu_reg_reg);
7584 %}
7585
7586 // Arithmetic Shift Right by 8-bit immediate
7587 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7588 effect( DEF dst, USE src );
7589 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7590 opcode(Assembler::sra_op3, Assembler::arith_op);
7591 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7592 ins_pipe(ialu_reg_imm);
7593 %}
7594
7595 // Integer DIV with 10
7596 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7597 match(Set dst (DivI src div));
7598 ins_cost((6+6)*DEFAULT_COST);
7599 expand %{
7600 iRegIsafe tmp1; // Killed temps;
7601 iRegIsafe tmp2; // Killed temps;
7602 iRegI tmp3; // Killed temps;
7603 iRegI tmp4; // Killed temps;
7604 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7605 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7606 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7607 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7608 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7609 %}
7610 %}
7611
7612 // Register Long Division
7613 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7614 match(Set dst (DivL src1 src2));
7615 ins_cost(DEFAULT_COST*71);
7616 size(4);
7617 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7618 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7619 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7620 ins_pipe(divL_reg_reg);
7621 %}
7622
7623 // Register Long Division
7624 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7625 match(Set dst (DivL src1 src2));
7626 ins_cost(DEFAULT_COST*71);
7627 size(4);
7628 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7629 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7630 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7631 ins_pipe(divL_reg_imm);
7632 %}
7633
7634 // Integer Remainder
7635 // Register Remainder
7636 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7637 match(Set dst (ModI src1 src2));
7638 effect( KILL ccr, KILL temp);
7639
7640 format %{ "SREM $src1,$src2,$dst" %}
7641 ins_encode( irem_reg(src1, src2, dst, temp) );
7642 ins_pipe(sdiv_reg_reg);
7643 %}
7644
7645 // Immediate Remainder
7646 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7647 match(Set dst (ModI src1 src2));
7648 effect( KILL ccr, KILL temp);
7649
7650 format %{ "SREM $src1,$src2,$dst" %}
7651 ins_encode( irem_imm(src1, src2, dst, temp) );
7652 ins_pipe(sdiv_reg_imm);
7653 %}
7654
7655 // Register Long Remainder
7656 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7657 effect(DEF dst, USE src1, USE src2);
7658 size(4);
7659 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7660 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7661 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7662 ins_pipe(divL_reg_reg);
7663 %}
7664
7665 // Register Long Division
7666 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7667 effect(DEF dst, USE src1, USE src2);
7668 size(4);
7669 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7670 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7671 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7672 ins_pipe(divL_reg_imm);
7673 %}
7674
7675 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7676 effect(DEF dst, USE src1, USE src2);
7677 size(4);
7678 format %{ "MULX $src1,$src2,$dst\t! long" %}
7679 opcode(Assembler::mulx_op3, Assembler::arith_op);
7680 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7681 ins_pipe(mulL_reg_reg);
7682 %}
7683
7684 // Immediate Multiplication
7685 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7686 effect(DEF dst, USE src1, USE src2);
7687 size(4);
7688 format %{ "MULX $src1,$src2,$dst" %}
7689 opcode(Assembler::mulx_op3, Assembler::arith_op);
7690 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7691 ins_pipe(mulL_reg_imm);
7692 %}
7693
7694 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7695 effect(DEF dst, USE src1, USE src2);
7696 size(4);
7697 format %{ "SUB $src1,$src2,$dst\t! long" %}
7698 opcode(Assembler::sub_op3, Assembler::arith_op);
7699 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7700 ins_pipe(ialu_reg_reg);
7701 %}
7702
7703 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7704 effect(DEF dst, USE src1, USE src2);
7705 size(4);
7706 format %{ "SUB $src1,$src2,$dst\t! long" %}
7707 opcode(Assembler::sub_op3, Assembler::arith_op);
7708 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7709 ins_pipe(ialu_reg_reg);
7710 %}
7711
7712 // Register Long Remainder
7713 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7714 match(Set dst (ModL src1 src2));
7715 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7716 expand %{
7717 iRegL tmp1;
7718 iRegL tmp2;
7719 divL_reg_reg_1(tmp1, src1, src2);
7720 mulL_reg_reg_1(tmp2, tmp1, src2);
7721 subL_reg_reg_1(dst, src1, tmp2);
7722 %}
7723 %}
7724
7725 // Register Long Remainder
7726 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7727 match(Set dst (ModL src1 src2));
7728 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7729 expand %{
7730 iRegL tmp1;
7731 iRegL tmp2;
7732 divL_reg_imm13_1(tmp1, src1, src2);
7733 mulL_reg_imm13_1(tmp2, tmp1, src2);
7734 subL_reg_reg_2 (dst, src1, tmp2);
7735 %}
7736 %}
7737
7738 // Integer Shift Instructions
7739 // Register Shift Left
7740 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7741 match(Set dst (LShiftI src1 src2));
7742
7743 size(4);
7744 format %{ "SLL $src1,$src2,$dst" %}
7745 opcode(Assembler::sll_op3, Assembler::arith_op);
7746 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7747 ins_pipe(ialu_reg_reg);
7748 %}
7749
7750 // Register Shift Left Immediate
7751 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7752 match(Set dst (LShiftI src1 src2));
7753
7754 size(4);
7755 format %{ "SLL $src1,$src2,$dst" %}
7756 opcode(Assembler::sll_op3, Assembler::arith_op);
7757 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7758 ins_pipe(ialu_reg_imm);
7759 %}
7760
7761 // Register Shift Left
7762 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7763 match(Set dst (LShiftL src1 src2));
7764
7765 size(4);
7766 format %{ "SLLX $src1,$src2,$dst" %}
7767 opcode(Assembler::sllx_op3, Assembler::arith_op);
7768 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7769 ins_pipe(ialu_reg_reg);
7770 %}
7771
7772 // Register Shift Left Immediate
7773 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7774 match(Set dst (LShiftL src1 src2));
7775
7776 size(4);
7777 format %{ "SLLX $src1,$src2,$dst" %}
7778 opcode(Assembler::sllx_op3, Assembler::arith_op);
7779 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7780 ins_pipe(ialu_reg_imm);
7781 %}
7782
7783 // Register Arithmetic Shift Right
7784 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7785 match(Set dst (RShiftI src1 src2));
7786 size(4);
7787 format %{ "SRA $src1,$src2,$dst" %}
7788 opcode(Assembler::sra_op3, Assembler::arith_op);
7789 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7790 ins_pipe(ialu_reg_reg);
7791 %}
7792
7793 // Register Arithmetic Shift Right Immediate
7794 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7795 match(Set dst (RShiftI src1 src2));
7796
7797 size(4);
7798 format %{ "SRA $src1,$src2,$dst" %}
7799 opcode(Assembler::sra_op3, Assembler::arith_op);
7800 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7801 ins_pipe(ialu_reg_imm);
7802 %}
7803
7804 // Register Shift Right Arithmatic Long
7805 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7806 match(Set dst (RShiftL src1 src2));
7807
7808 size(4);
7809 format %{ "SRAX $src1,$src2,$dst" %}
7810 opcode(Assembler::srax_op3, Assembler::arith_op);
7811 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7812 ins_pipe(ialu_reg_reg);
7813 %}
7814
7815 // Register Shift Left Immediate
7816 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7817 match(Set dst (RShiftL src1 src2));
7818
7819 size(4);
7820 format %{ "SRAX $src1,$src2,$dst" %}
7821 opcode(Assembler::srax_op3, Assembler::arith_op);
7822 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7823 ins_pipe(ialu_reg_imm);
7824 %}
7825
7826 // Register Shift Right
7827 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7828 match(Set dst (URShiftI src1 src2));
7829
7830 size(4);
7831 format %{ "SRL $src1,$src2,$dst" %}
7832 opcode(Assembler::srl_op3, Assembler::arith_op);
7833 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7834 ins_pipe(ialu_reg_reg);
7835 %}
7836
7837 // Register Shift Right Immediate
7838 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7839 match(Set dst (URShiftI src1 src2));
7840
7841 size(4);
7842 format %{ "SRL $src1,$src2,$dst" %}
7843 opcode(Assembler::srl_op3, Assembler::arith_op);
7844 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7845 ins_pipe(ialu_reg_imm);
7846 %}
7847
7848 // Register Shift Right
7849 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7850 match(Set dst (URShiftL src1 src2));
7851
7852 size(4);
7853 format %{ "SRLX $src1,$src2,$dst" %}
7854 opcode(Assembler::srlx_op3, Assembler::arith_op);
7855 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7856 ins_pipe(ialu_reg_reg);
7857 %}
7858
7859 // Register Shift Right Immediate
7860 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7861 match(Set dst (URShiftL src1 src2));
7862
7863 size(4);
7864 format %{ "SRLX $src1,$src2,$dst" %}
7865 opcode(Assembler::srlx_op3, Assembler::arith_op);
7866 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7867 ins_pipe(ialu_reg_imm);
7868 %}
7869
7870 // Register Shift Right Immediate with a CastP2X
7871 #ifdef _LP64
7872 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7873 match(Set dst (URShiftL (CastP2X src1) src2));
7874 size(4);
7875 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7876 opcode(Assembler::srlx_op3, Assembler::arith_op);
7877 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7878 ins_pipe(ialu_reg_imm);
7879 %}
7880 #else
7881 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7882 match(Set dst (URShiftI (CastP2X src1) src2));
7883 size(4);
7884 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7885 opcode(Assembler::srl_op3, Assembler::arith_op);
7886 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7887 ins_pipe(ialu_reg_imm);
7888 %}
7889 #endif
7890
7891
7892 //----------Floating Point Arithmetic Instructions-----------------------------
7893
7894 // Add float single precision
7895 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7896 match(Set dst (AddF src1 src2));
7897
7898 size(4);
7899 format %{ "FADDS $src1,$src2,$dst" %}
7900 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7901 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7902 ins_pipe(faddF_reg_reg);
7903 %}
7904
7905 // Add float double precision
7906 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7907 match(Set dst (AddD src1 src2));
7908
7909 size(4);
7910 format %{ "FADDD $src1,$src2,$dst" %}
7911 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7912 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7913 ins_pipe(faddD_reg_reg);
7914 %}
7915
7916 // Sub float single precision
7917 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7918 match(Set dst (SubF src1 src2));
7919
7920 size(4);
7921 format %{ "FSUBS $src1,$src2,$dst" %}
7922 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7923 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7924 ins_pipe(faddF_reg_reg);
7925 %}
7926
7927 // Sub float double precision
7928 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7929 match(Set dst (SubD src1 src2));
7930
7931 size(4);
7932 format %{ "FSUBD $src1,$src2,$dst" %}
7933 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7934 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7935 ins_pipe(faddD_reg_reg);
7936 %}
7937
7938 // Mul float single precision
7939 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7940 match(Set dst (MulF src1 src2));
7941
7942 size(4);
7943 format %{ "FMULS $src1,$src2,$dst" %}
7944 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7945 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7946 ins_pipe(fmulF_reg_reg);
7947 %}
7948
7949 // Mul float double precision
7950 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7951 match(Set dst (MulD src1 src2));
7952
7953 size(4);
7954 format %{ "FMULD $src1,$src2,$dst" %}
7955 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7956 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7957 ins_pipe(fmulD_reg_reg);
7958 %}
7959
7960 // Div float single precision
7961 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7962 match(Set dst (DivF src1 src2));
7963
7964 size(4);
7965 format %{ "FDIVS $src1,$src2,$dst" %}
7966 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7967 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7968 ins_pipe(fdivF_reg_reg);
7969 %}
7970
7971 // Div float double precision
7972 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7973 match(Set dst (DivD src1 src2));
7974
7975 size(4);
7976 format %{ "FDIVD $src1,$src2,$dst" %}
7977 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7978 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7979 ins_pipe(fdivD_reg_reg);
7980 %}
7981
7982 // Absolute float double precision
7983 instruct absD_reg(regD dst, regD src) %{
7984 match(Set dst (AbsD src));
7985
7986 format %{ "FABSd $src,$dst" %}
7987 ins_encode(fabsd(dst, src));
7988 ins_pipe(faddD_reg);
7989 %}
7990
7991 // Absolute float single precision
7992 instruct absF_reg(regF dst, regF src) %{
7993 match(Set dst (AbsF src));
7994
7995 format %{ "FABSs $src,$dst" %}
7996 ins_encode(fabss(dst, src));
7997 ins_pipe(faddF_reg);
7998 %}
7999
8000 instruct negF_reg(regF dst, regF src) %{
8001 match(Set dst (NegF src));
8002
8003 size(4);
8004 format %{ "FNEGs $src,$dst" %}
8005 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
8006 ins_encode(form3_opf_rs2F_rdF(src, dst));
8007 ins_pipe(faddF_reg);
8008 %}
8009
8010 instruct negD_reg(regD dst, regD src) %{
8011 match(Set dst (NegD src));
8012
8013 format %{ "FNEGd $src,$dst" %}
8014 ins_encode(fnegd(dst, src));
8015 ins_pipe(faddD_reg);
8016 %}
8017
8018 // Sqrt float double precision
8019 instruct sqrtF_reg_reg(regF dst, regF src) %{
8020 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8021
8022 size(4);
8023 format %{ "FSQRTS $src,$dst" %}
8024 ins_encode(fsqrts(dst, src));
8025 ins_pipe(fdivF_reg_reg);
8026 %}
8027
8028 // Sqrt float double precision
8029 instruct sqrtD_reg_reg(regD dst, regD src) %{
8030 match(Set dst (SqrtD src));
8031
8032 size(4);
8033 format %{ "FSQRTD $src,$dst" %}
8034 ins_encode(fsqrtd(dst, src));
8035 ins_pipe(fdivD_reg_reg);
8036 %}
8037
8038 //----------Logical Instructions-----------------------------------------------
8039 // And Instructions
8040 // Register And
8041 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8042 match(Set dst (AndI src1 src2));
8043
8044 size(4);
8045 format %{ "AND $src1,$src2,$dst" %}
8046 opcode(Assembler::and_op3, Assembler::arith_op);
8047 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8048 ins_pipe(ialu_reg_reg);
8049 %}
8050
8051 // Immediate And
8052 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8053 match(Set dst (AndI src1 src2));
8054
8055 size(4);
8056 format %{ "AND $src1,$src2,$dst" %}
8057 opcode(Assembler::and_op3, Assembler::arith_op);
8058 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8059 ins_pipe(ialu_reg_imm);
8060 %}
8061
8062 // Register And Long
8063 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8064 match(Set dst (AndL src1 src2));
8065
8066 ins_cost(DEFAULT_COST);
8067 size(4);
8068 format %{ "AND $src1,$src2,$dst\t! long" %}
8069 opcode(Assembler::and_op3, Assembler::arith_op);
8070 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8071 ins_pipe(ialu_reg_reg);
8072 %}
8073
8074 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8075 match(Set dst (AndL src1 con));
8076
8077 ins_cost(DEFAULT_COST);
8078 size(4);
8079 format %{ "AND $src1,$con,$dst\t! long" %}
8080 opcode(Assembler::and_op3, Assembler::arith_op);
8081 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8082 ins_pipe(ialu_reg_imm);
8083 %}
8084
8085 // Or Instructions
8086 // Register Or
8087 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8088 match(Set dst (OrI src1 src2));
8089
8090 size(4);
8091 format %{ "OR $src1,$src2,$dst" %}
8092 opcode(Assembler::or_op3, Assembler::arith_op);
8093 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8094 ins_pipe(ialu_reg_reg);
8095 %}
8096
8097 // Immediate Or
8098 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8099 match(Set dst (OrI src1 src2));
8100
8101 size(4);
8102 format %{ "OR $src1,$src2,$dst" %}
8103 opcode(Assembler::or_op3, Assembler::arith_op);
8104 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8105 ins_pipe(ialu_reg_imm);
8106 %}
8107
8108 // Register Or Long
8109 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8110 match(Set dst (OrL src1 src2));
8111
8112 ins_cost(DEFAULT_COST);
8113 size(4);
8114 format %{ "OR $src1,$src2,$dst\t! long" %}
8115 opcode(Assembler::or_op3, Assembler::arith_op);
8116 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8117 ins_pipe(ialu_reg_reg);
8118 %}
8119
8120 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8121 match(Set dst (OrL src1 con));
8122 ins_cost(DEFAULT_COST*2);
8123
8124 ins_cost(DEFAULT_COST);
8125 size(4);
8126 format %{ "OR $src1,$con,$dst\t! long" %}
8127 opcode(Assembler::or_op3, Assembler::arith_op);
8128 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8129 ins_pipe(ialu_reg_imm);
8130 %}
8131
8132 #ifndef _LP64
8133
8134 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8135 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8136 match(Set dst (OrI src1 (CastP2X src2)));
8137
8138 size(4);
8139 format %{ "OR $src1,$src2,$dst" %}
8140 opcode(Assembler::or_op3, Assembler::arith_op);
8141 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8142 ins_pipe(ialu_reg_reg);
8143 %}
8144
8145 #else
8146
8147 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8148 match(Set dst (OrL src1 (CastP2X src2)));
8149
8150 ins_cost(DEFAULT_COST);
8151 size(4);
8152 format %{ "OR $src1,$src2,$dst\t! long" %}
8153 opcode(Assembler::or_op3, Assembler::arith_op);
8154 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8155 ins_pipe(ialu_reg_reg);
8156 %}
8157
8158 #endif
8159
8160 // Xor Instructions
8161 // Register Xor
8162 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8163 match(Set dst (XorI src1 src2));
8164
8165 size(4);
8166 format %{ "XOR $src1,$src2,$dst" %}
8167 opcode(Assembler::xor_op3, Assembler::arith_op);
8168 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8169 ins_pipe(ialu_reg_reg);
8170 %}
8171
8172 // Immediate Xor
8173 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8174 match(Set dst (XorI src1 src2));
8175
8176 size(4);
8177 format %{ "XOR $src1,$src2,$dst" %}
8178 opcode(Assembler::xor_op3, Assembler::arith_op);
8179 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8180 ins_pipe(ialu_reg_imm);
8181 %}
8182
8183 // Register Xor Long
8184 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8185 match(Set dst (XorL src1 src2));
8186
8187 ins_cost(DEFAULT_COST);
8188 size(4);
8189 format %{ "XOR $src1,$src2,$dst\t! long" %}
8190 opcode(Assembler::xor_op3, Assembler::arith_op);
8191 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8192 ins_pipe(ialu_reg_reg);
8193 %}
8194
8195 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8196 match(Set dst (XorL src1 con));
8197
8198 ins_cost(DEFAULT_COST);
8199 size(4);
8200 format %{ "XOR $src1,$con,$dst\t! long" %}
8201 opcode(Assembler::xor_op3, Assembler::arith_op);
8202 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8203 ins_pipe(ialu_reg_imm);
8204 %}
8205
8206 //----------Convert to Boolean-------------------------------------------------
8207 // Nice hack for 32-bit tests but doesn't work for
8208 // 64-bit pointers.
8209 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8210 match(Set dst (Conv2B src));
8211 effect( KILL ccr );
8212 ins_cost(DEFAULT_COST*2);
8213 format %{ "CMP R_G0,$src\n\t"
8214 "ADDX R_G0,0,$dst" %}
8215 ins_encode( enc_to_bool( src, dst ) );
8216 ins_pipe(ialu_reg_ialu);
8217 %}
8218
8219 #ifndef _LP64
8220 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8221 match(Set dst (Conv2B src));
8222 effect( KILL ccr );
8223 ins_cost(DEFAULT_COST*2);
8224 format %{ "CMP R_G0,$src\n\t"
8225 "ADDX R_G0,0,$dst" %}
8226 ins_encode( enc_to_bool( src, dst ) );
8227 ins_pipe(ialu_reg_ialu);
8228 %}
8229 #else
8230 instruct convP2B( iRegI dst, iRegP src ) %{
8231 match(Set dst (Conv2B src));
8232 ins_cost(DEFAULT_COST*2);
8233 format %{ "MOV $src,$dst\n\t"
8234 "MOVRNZ $src,1,$dst" %}
8235 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8236 ins_pipe(ialu_clr_and_mover);
8237 %}
8238 #endif
8239
8240 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8241 match(Set dst (CmpLTMask src zero));
8242 effect(KILL ccr);
8243 size(4);
8244 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8245 ins_encode %{
8246 __ sra($src$$Register, 31, $dst$$Register);
8247 %}
8248 ins_pipe(ialu_reg_imm);
8249 %}
8250
8251 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8252 match(Set dst (CmpLTMask p q));
8253 effect( KILL ccr );
8254 ins_cost(DEFAULT_COST*4);
8255 format %{ "CMP $p,$q\n\t"
8256 "MOV #0,$dst\n\t"
8257 "BLT,a .+8\n\t"
8258 "MOV #-1,$dst" %}
8259 ins_encode( enc_ltmask(p,q,dst) );
8260 ins_pipe(ialu_reg_reg_ialu);
8261 %}
8262
8263 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8264 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8265 effect(KILL ccr, TEMP tmp);
8266 ins_cost(DEFAULT_COST*3);
8267
8268 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8269 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8270 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8271 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8272 ins_pipe(cadd_cmpltmask);
8273 %}
8274
8275 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8276 match(Set p (AndI (CmpLTMask p q) y));
8277 effect(KILL ccr);
8278 ins_cost(DEFAULT_COST*3);
8279
8280 format %{ "CMP $p,$q\n\t"
8281 "MOV $y,$p\n\t"
8282 "MOVge G0,$p" %}
8283 ins_encode %{
8284 __ cmp($p$$Register, $q$$Register);
8285 __ mov($y$$Register, $p$$Register);
8286 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8287 %}
8288 ins_pipe(ialu_reg_reg_ialu);
8289 %}
8290
8291 //-----------------------------------------------------------------
8292 // Direct raw moves between float and general registers using VIS3.
8293
8294 // ins_pipe(faddF_reg);
8295 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8296 predicate(UseVIS >= 3);
8297 match(Set dst (MoveF2I src));
8298
8299 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8300 ins_encode %{
8301 __ movstouw($src$$FloatRegister, $dst$$Register);
8302 %}
8303 ins_pipe(ialu_reg_reg);
8304 %}
8305
8306 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8307 predicate(UseVIS >= 3);
8308 match(Set dst (MoveI2F src));
8309
8310 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8311 ins_encode %{
8312 __ movwtos($src$$Register, $dst$$FloatRegister);
8313 %}
8314 ins_pipe(ialu_reg_reg);
8315 %}
8316
8317 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8318 predicate(UseVIS >= 3);
8319 match(Set dst (MoveD2L src));
8320
8321 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8322 ins_encode %{
8323 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8324 %}
8325 ins_pipe(ialu_reg_reg);
8326 %}
8327
8328 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8329 predicate(UseVIS >= 3);
8330 match(Set dst (MoveL2D src));
8331
8332 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8333 ins_encode %{
8334 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8335 %}
8336 ins_pipe(ialu_reg_reg);
8337 %}
8338
8339
8340 // Raw moves between float and general registers using stack.
8341
8342 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8343 match(Set dst (MoveF2I src));
8344 effect(DEF dst, USE src);
8345 ins_cost(MEMORY_REF_COST);
8346
8347 size(4);
8348 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8349 opcode(Assembler::lduw_op3);
8350 ins_encode(simple_form3_mem_reg( src, dst ) );
8351 ins_pipe(iload_mem);
8352 %}
8353
8354 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8355 match(Set dst (MoveI2F src));
8356 effect(DEF dst, USE src);
8357 ins_cost(MEMORY_REF_COST);
8358
8359 size(4);
8360 format %{ "LDF $src,$dst\t! MoveI2F" %}
8361 opcode(Assembler::ldf_op3);
8362 ins_encode(simple_form3_mem_reg(src, dst));
8363 ins_pipe(floadF_stk);
8364 %}
8365
8366 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8367 match(Set dst (MoveD2L src));
8368 effect(DEF dst, USE src);
8369 ins_cost(MEMORY_REF_COST);
8370
8371 size(4);
8372 format %{ "LDX $src,$dst\t! MoveD2L" %}
8373 opcode(Assembler::ldx_op3);
8374 ins_encode(simple_form3_mem_reg( src, dst ) );
8375 ins_pipe(iload_mem);
8376 %}
8377
8378 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8379 match(Set dst (MoveL2D src));
8380 effect(DEF dst, USE src);
8381 ins_cost(MEMORY_REF_COST);
8382
8383 size(4);
8384 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8385 opcode(Assembler::lddf_op3);
8386 ins_encode(simple_form3_mem_reg(src, dst));
8387 ins_pipe(floadD_stk);
8388 %}
8389
8390 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8391 match(Set dst (MoveF2I src));
8392 effect(DEF dst, USE src);
8393 ins_cost(MEMORY_REF_COST);
8394
8395 size(4);
8396 format %{ "STF $src,$dst\t! MoveF2I" %}
8397 opcode(Assembler::stf_op3);
8398 ins_encode(simple_form3_mem_reg(dst, src));
8399 ins_pipe(fstoreF_stk_reg);
8400 %}
8401
8402 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8403 match(Set dst (MoveI2F src));
8404 effect(DEF dst, USE src);
8405 ins_cost(MEMORY_REF_COST);
8406
8407 size(4);
8408 format %{ "STW $src,$dst\t! MoveI2F" %}
8409 opcode(Assembler::stw_op3);
8410 ins_encode(simple_form3_mem_reg( dst, src ) );
8411 ins_pipe(istore_mem_reg);
8412 %}
8413
8414 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8415 match(Set dst (MoveD2L src));
8416 effect(DEF dst, USE src);
8417 ins_cost(MEMORY_REF_COST);
8418
8419 size(4);
8420 format %{ "STDF $src,$dst\t! MoveD2L" %}
8421 opcode(Assembler::stdf_op3);
8422 ins_encode(simple_form3_mem_reg(dst, src));
8423 ins_pipe(fstoreD_stk_reg);
8424 %}
8425
8426 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8427 match(Set dst (MoveL2D src));
8428 effect(DEF dst, USE src);
8429 ins_cost(MEMORY_REF_COST);
8430
8431 size(4);
8432 format %{ "STX $src,$dst\t! MoveL2D" %}
8433 opcode(Assembler::stx_op3);
8434 ins_encode(simple_form3_mem_reg( dst, src ) );
8435 ins_pipe(istore_mem_reg);
8436 %}
8437
8438
8439 //----------Arithmetic Conversion Instructions---------------------------------
8440 // The conversions operations are all Alpha sorted. Please keep it that way!
8441
8442 instruct convD2F_reg(regF dst, regD src) %{
8443 match(Set dst (ConvD2F src));
8444 size(4);
8445 format %{ "FDTOS $src,$dst" %}
8446 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8447 ins_encode(form3_opf_rs2D_rdF(src, dst));
8448 ins_pipe(fcvtD2F);
8449 %}
8450
8451
8452 // Convert a double to an int in a float register.
8453 // If the double is a NAN, stuff a zero in instead.
8454 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8455 effect(DEF dst, USE src, KILL fcc0);
8456 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8457 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8458 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8459 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8460 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8461 "skip:" %}
8462 ins_encode(form_d2i_helper(src,dst));
8463 ins_pipe(fcvtD2I);
8464 %}
8465
8466 instruct convD2I_stk(stackSlotI dst, regD src) %{
8467 match(Set dst (ConvD2I src));
8468 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8469 expand %{
8470 regF tmp;
8471 convD2I_helper(tmp, src);
8472 regF_to_stkI(dst, tmp);
8473 %}
8474 %}
8475
8476 instruct convD2I_reg(iRegI dst, regD src) %{
8477 predicate(UseVIS >= 3);
8478 match(Set dst (ConvD2I src));
8479 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8480 expand %{
8481 regF tmp;
8482 convD2I_helper(tmp, src);
8483 MoveF2I_reg_reg(dst, tmp);
8484 %}
8485 %}
8486
8487
8488 // Convert a double to a long in a double register.
8489 // If the double is a NAN, stuff a zero in instead.
8490 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8491 effect(DEF dst, USE src, KILL fcc0);
8492 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8493 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8494 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8495 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8496 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8497 "skip:" %}
8498 ins_encode(form_d2l_helper(src,dst));
8499 ins_pipe(fcvtD2L);
8500 %}
8501
8502 instruct convD2L_stk(stackSlotL dst, regD src) %{
8503 match(Set dst (ConvD2L src));
8504 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8505 expand %{
8506 regD tmp;
8507 convD2L_helper(tmp, src);
8508 regD_to_stkL(dst, tmp);
8509 %}
8510 %}
8511
8512 instruct convD2L_reg(iRegL dst, regD src) %{
8513 predicate(UseVIS >= 3);
8514 match(Set dst (ConvD2L src));
8515 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8516 expand %{
8517 regD tmp;
8518 convD2L_helper(tmp, src);
8519 MoveD2L_reg_reg(dst, tmp);
8520 %}
8521 %}
8522
8523
8524 instruct convF2D_reg(regD dst, regF src) %{
8525 match(Set dst (ConvF2D src));
8526 format %{ "FSTOD $src,$dst" %}
8527 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8528 ins_encode(form3_opf_rs2F_rdD(src, dst));
8529 ins_pipe(fcvtF2D);
8530 %}
8531
8532
8533 // Convert a float to an int in a float register.
8534 // If the float is a NAN, stuff a zero in instead.
8535 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8536 effect(DEF dst, USE src, KILL fcc0);
8537 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8538 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8539 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8540 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8541 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8542 "skip:" %}
8543 ins_encode(form_f2i_helper(src,dst));
8544 ins_pipe(fcvtF2I);
8545 %}
8546
8547 instruct convF2I_stk(stackSlotI dst, regF src) %{
8548 match(Set dst (ConvF2I src));
8549 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8550 expand %{
8551 regF tmp;
8552 convF2I_helper(tmp, src);
8553 regF_to_stkI(dst, tmp);
8554 %}
8555 %}
8556
8557 instruct convF2I_reg(iRegI dst, regF src) %{
8558 predicate(UseVIS >= 3);
8559 match(Set dst (ConvF2I src));
8560 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8561 expand %{
8562 regF tmp;
8563 convF2I_helper(tmp, src);
8564 MoveF2I_reg_reg(dst, tmp);
8565 %}
8566 %}
8567
8568
8569 // Convert a float to a long in a float register.
8570 // If the float is a NAN, stuff a zero in instead.
8571 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8572 effect(DEF dst, USE src, KILL fcc0);
8573 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8574 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8575 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8576 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8577 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8578 "skip:" %}
8579 ins_encode(form_f2l_helper(src,dst));
8580 ins_pipe(fcvtF2L);
8581 %}
8582
8583 instruct convF2L_stk(stackSlotL dst, regF src) %{
8584 match(Set dst (ConvF2L src));
8585 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8586 expand %{
8587 regD tmp;
8588 convF2L_helper(tmp, src);
8589 regD_to_stkL(dst, tmp);
8590 %}
8591 %}
8592
8593 instruct convF2L_reg(iRegL dst, regF src) %{
8594 predicate(UseVIS >= 3);
8595 match(Set dst (ConvF2L src));
8596 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8597 expand %{
8598 regD tmp;
8599 convF2L_helper(tmp, src);
8600 MoveD2L_reg_reg(dst, tmp);
8601 %}
8602 %}
8603
8604
8605 instruct convI2D_helper(regD dst, regF tmp) %{
8606 effect(USE tmp, DEF dst);
8607 format %{ "FITOD $tmp,$dst" %}
8608 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8609 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8610 ins_pipe(fcvtI2D);
8611 %}
8612
8613 instruct convI2D_stk(stackSlotI src, regD dst) %{
8614 match(Set dst (ConvI2D src));
8615 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8616 expand %{
8617 regF tmp;
8618 stkI_to_regF(tmp, src);
8619 convI2D_helper(dst, tmp);
8620 %}
8621 %}
8622
8623 instruct convI2D_reg(regD_low dst, iRegI src) %{
8624 predicate(UseVIS >= 3);
8625 match(Set dst (ConvI2D src));
8626 expand %{
8627 regF tmp;
8628 MoveI2F_reg_reg(tmp, src);
8629 convI2D_helper(dst, tmp);
8630 %}
8631 %}
8632
8633 instruct convI2D_mem(regD_low dst, memory mem) %{
8634 match(Set dst (ConvI2D (LoadI mem)));
8635 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8636 size(8);
8637 format %{ "LDF $mem,$dst\n\t"
8638 "FITOD $dst,$dst" %}
8639 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8640 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8641 ins_pipe(floadF_mem);
8642 %}
8643
8644
8645 instruct convI2F_helper(regF dst, regF tmp) %{
8646 effect(DEF dst, USE tmp);
8647 format %{ "FITOS $tmp,$dst" %}
8648 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8649 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8650 ins_pipe(fcvtI2F);
8651 %}
8652
8653 instruct convI2F_stk(regF dst, stackSlotI src) %{
8654 match(Set dst (ConvI2F src));
8655 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8656 expand %{
8657 regF tmp;
8658 stkI_to_regF(tmp,src);
8659 convI2F_helper(dst, tmp);
8660 %}
8661 %}
8662
8663 instruct convI2F_reg(regF dst, iRegI src) %{
8664 predicate(UseVIS >= 3);
8665 match(Set dst (ConvI2F src));
8666 ins_cost(DEFAULT_COST);
8667 expand %{
8668 regF tmp;
8669 MoveI2F_reg_reg(tmp, src);
8670 convI2F_helper(dst, tmp);
8671 %}
8672 %}
8673
8674 instruct convI2F_mem( regF dst, memory mem ) %{
8675 match(Set dst (ConvI2F (LoadI mem)));
8676 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8677 size(8);
8678 format %{ "LDF $mem,$dst\n\t"
8679 "FITOS $dst,$dst" %}
8680 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8681 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8682 ins_pipe(floadF_mem);
8683 %}
8684
8685
8686 instruct convI2L_reg(iRegL dst, iRegI src) %{
8687 match(Set dst (ConvI2L src));
8688 size(4);
8689 format %{ "SRA $src,0,$dst\t! int->long" %}
8690 opcode(Assembler::sra_op3, Assembler::arith_op);
8691 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8692 ins_pipe(ialu_reg_reg);
8693 %}
8694
8695 // Zero-extend convert int to long
8696 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8697 match(Set dst (AndL (ConvI2L src) mask) );
8698 size(4);
8699 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8700 opcode(Assembler::srl_op3, Assembler::arith_op);
8701 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8702 ins_pipe(ialu_reg_reg);
8703 %}
8704
8705 // Zero-extend long
8706 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8707 match(Set dst (AndL src mask) );
8708 size(4);
8709 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8710 opcode(Assembler::srl_op3, Assembler::arith_op);
8711 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8712 ins_pipe(ialu_reg_reg);
8713 %}
8714
8715
8716 //-----------
8717 // Long to Double conversion using V8 opcodes.
8718 // Still useful because cheetah traps and becomes
8719 // amazingly slow for some common numbers.
8720
8721 // Magic constant, 0x43300000
8722 instruct loadConI_x43300000(iRegI dst) %{
8723 effect(DEF dst);
8724 size(4);
8725 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8726 ins_encode(SetHi22(0x43300000, dst));
8727 ins_pipe(ialu_none);
8728 %}
8729
8730 // Magic constant, 0x41f00000
8731 instruct loadConI_x41f00000(iRegI dst) %{
8732 effect(DEF dst);
8733 size(4);
8734 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8735 ins_encode(SetHi22(0x41f00000, dst));
8736 ins_pipe(ialu_none);
8737 %}
8738
8739 // Construct a double from two float halves
8740 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8741 effect(DEF dst, USE src1, USE src2);
8742 size(8);
8743 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8744 "FMOVS $src2.lo,$dst.lo" %}
8745 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8746 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8747 ins_pipe(faddD_reg_reg);
8748 %}
8749
8750 // Convert integer in high half of a double register (in the lower half of
8751 // the double register file) to double
8752 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8753 effect(DEF dst, USE src);
8754 size(4);
8755 format %{ "FITOD $src,$dst" %}
8756 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8757 ins_encode(form3_opf_rs2D_rdD(src, dst));
8758 ins_pipe(fcvtLHi2D);
8759 %}
8760
8761 // Add float double precision
8762 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8763 effect(DEF dst, USE src1, USE src2);
8764 size(4);
8765 format %{ "FADDD $src1,$src2,$dst" %}
8766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8767 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8768 ins_pipe(faddD_reg_reg);
8769 %}
8770
8771 // Sub float double precision
8772 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8773 effect(DEF dst, USE src1, USE src2);
8774 size(4);
8775 format %{ "FSUBD $src1,$src2,$dst" %}
8776 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8777 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8778 ins_pipe(faddD_reg_reg);
8779 %}
8780
8781 // Mul float double precision
8782 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8783 effect(DEF dst, USE src1, USE src2);
8784 size(4);
8785 format %{ "FMULD $src1,$src2,$dst" %}
8786 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8787 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8788 ins_pipe(fmulD_reg_reg);
8789 %}
8790
8791 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8792 match(Set dst (ConvL2D src));
8793 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8794
8795 expand %{
8796 regD_low tmpsrc;
8797 iRegI ix43300000;
8798 iRegI ix41f00000;
8799 stackSlotL lx43300000;
8800 stackSlotL lx41f00000;
8801 regD_low dx43300000;
8802 regD dx41f00000;
8803 regD tmp1;
8804 regD_low tmp2;
8805 regD tmp3;
8806 regD tmp4;
8807
8808 stkL_to_regD(tmpsrc, src);
8809
8810 loadConI_x43300000(ix43300000);
8811 loadConI_x41f00000(ix41f00000);
8812 regI_to_stkLHi(lx43300000, ix43300000);
8813 regI_to_stkLHi(lx41f00000, ix41f00000);
8814 stkL_to_regD(dx43300000, lx43300000);
8815 stkL_to_regD(dx41f00000, lx41f00000);
8816
8817 convI2D_regDHi_regD(tmp1, tmpsrc);
8818 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8819 subD_regD_regD(tmp3, tmp2, dx43300000);
8820 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8821 addD_regD_regD(dst, tmp3, tmp4);
8822 %}
8823 %}
8824
8825 // Long to Double conversion using fast fxtof
8826 instruct convL2D_helper(regD dst, regD tmp) %{
8827 effect(DEF dst, USE tmp);
8828 size(4);
8829 format %{ "FXTOD $tmp,$dst" %}
8830 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8831 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8832 ins_pipe(fcvtL2D);
8833 %}
8834
8835 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8836 predicate(VM_Version::has_fast_fxtof());
8837 match(Set dst (ConvL2D src));
8838 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8839 expand %{
8840 regD tmp;
8841 stkL_to_regD(tmp, src);
8842 convL2D_helper(dst, tmp);
8843 %}
8844 %}
8845
8846 instruct convL2D_reg(regD dst, iRegL src) %{
8847 predicate(UseVIS >= 3);
8848 match(Set dst (ConvL2D src));
8849 expand %{
8850 regD tmp;
8851 MoveL2D_reg_reg(tmp, src);
8852 convL2D_helper(dst, tmp);
8853 %}
8854 %}
8855
8856 // Long to Float conversion using fast fxtof
8857 instruct convL2F_helper(regF dst, regD tmp) %{
8858 effect(DEF dst, USE tmp);
8859 size(4);
8860 format %{ "FXTOS $tmp,$dst" %}
8861 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8862 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8863 ins_pipe(fcvtL2F);
8864 %}
8865
8866 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8867 match(Set dst (ConvL2F src));
8868 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8869 expand %{
8870 regD tmp;
8871 stkL_to_regD(tmp, src);
8872 convL2F_helper(dst, tmp);
8873 %}
8874 %}
8875
8876 instruct convL2F_reg(regF dst, iRegL src) %{
8877 predicate(UseVIS >= 3);
8878 match(Set dst (ConvL2F src));
8879 ins_cost(DEFAULT_COST);
8880 expand %{
8881 regD tmp;
8882 MoveL2D_reg_reg(tmp, src);
8883 convL2F_helper(dst, tmp);
8884 %}
8885 %}
8886
8887 //-----------
8888
8889 instruct convL2I_reg(iRegI dst, iRegL src) %{
8890 match(Set dst (ConvL2I src));
8891 #ifndef _LP64
8892 format %{ "MOV $src.lo,$dst\t! long->int" %}
8893 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8894 ins_pipe(ialu_move_reg_I_to_L);
8895 #else
8896 size(4);
8897 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8898 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8899 ins_pipe(ialu_reg);
8900 #endif
8901 %}
8902
8903 // Register Shift Right Immediate
8904 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8905 match(Set dst (ConvL2I (RShiftL src cnt)));
8906
8907 size(4);
8908 format %{ "SRAX $src,$cnt,$dst" %}
8909 opcode(Assembler::srax_op3, Assembler::arith_op);
8910 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8911 ins_pipe(ialu_reg_imm);
8912 %}
8913
8914 //----------Control Flow Instructions------------------------------------------
8915 // Compare Instructions
8916 // Compare Integers
8917 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8918 match(Set icc (CmpI op1 op2));
8919 effect( DEF icc, USE op1, USE op2 );
8920
8921 size(4);
8922 format %{ "CMP $op1,$op2" %}
8923 opcode(Assembler::subcc_op3, Assembler::arith_op);
8924 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8925 ins_pipe(ialu_cconly_reg_reg);
8926 %}
8927
8928 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8929 match(Set icc (CmpU op1 op2));
8930
8931 size(4);
8932 format %{ "CMP $op1,$op2\t! unsigned" %}
8933 opcode(Assembler::subcc_op3, Assembler::arith_op);
8934 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8935 ins_pipe(ialu_cconly_reg_reg);
8936 %}
8937
8938 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8939 match(Set icc (CmpI op1 op2));
8940 effect( DEF icc, USE op1 );
8941
8942 size(4);
8943 format %{ "CMP $op1,$op2" %}
8944 opcode(Assembler::subcc_op3, Assembler::arith_op);
8945 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8946 ins_pipe(ialu_cconly_reg_imm);
8947 %}
8948
8949 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8950 match(Set icc (CmpI (AndI op1 op2) zero));
8951
8952 size(4);
8953 format %{ "BTST $op2,$op1" %}
8954 opcode(Assembler::andcc_op3, Assembler::arith_op);
8955 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8956 ins_pipe(ialu_cconly_reg_reg_zero);
8957 %}
8958
8959 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8960 match(Set icc (CmpI (AndI op1 op2) zero));
8961
8962 size(4);
8963 format %{ "BTST $op2,$op1" %}
8964 opcode(Assembler::andcc_op3, Assembler::arith_op);
8965 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8966 ins_pipe(ialu_cconly_reg_imm_zero);
8967 %}
8968
8969 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8970 match(Set xcc (CmpL op1 op2));
8971 effect( DEF xcc, USE op1, USE op2 );
8972
8973 size(4);
8974 format %{ "CMP $op1,$op2\t\t! long" %}
8975 opcode(Assembler::subcc_op3, Assembler::arith_op);
8976 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8977 ins_pipe(ialu_cconly_reg_reg);
8978 %}
8979
8980 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8981 match(Set xcc (CmpL op1 con));
8982 effect( DEF xcc, USE op1, USE con );
8983
8984 size(4);
8985 format %{ "CMP $op1,$con\t\t! long" %}
8986 opcode(Assembler::subcc_op3, Assembler::arith_op);
8987 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8988 ins_pipe(ialu_cconly_reg_reg);
8989 %}
8990
8991 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8992 match(Set xcc (CmpL (AndL op1 op2) zero));
8993 effect( DEF xcc, USE op1, USE op2 );
8994
8995 size(4);
8996 format %{ "BTST $op1,$op2\t\t! long" %}
8997 opcode(Assembler::andcc_op3, Assembler::arith_op);
8998 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8999 ins_pipe(ialu_cconly_reg_reg);
9000 %}
9001
9002 // useful for checking the alignment of a pointer:
9003 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9004 match(Set xcc (CmpL (AndL op1 con) zero));
9005 effect( DEF xcc, USE op1, USE con );
9006
9007 size(4);
9008 format %{ "BTST $op1,$con\t\t! long" %}
9009 opcode(Assembler::andcc_op3, Assembler::arith_op);
9010 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9011 ins_pipe(ialu_cconly_reg_reg);
9012 %}
9013
9014 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
9015 match(Set icc (CmpU op1 op2));
9016
9017 size(4);
9018 format %{ "CMP $op1,$op2\t! unsigned" %}
9019 opcode(Assembler::subcc_op3, Assembler::arith_op);
9020 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9021 ins_pipe(ialu_cconly_reg_imm);
9022 %}
9023
9024 // Compare Pointers
9025 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9026 match(Set pcc (CmpP op1 op2));
9027
9028 size(4);
9029 format %{ "CMP $op1,$op2\t! ptr" %}
9030 opcode(Assembler::subcc_op3, Assembler::arith_op);
9031 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9032 ins_pipe(ialu_cconly_reg_reg);
9033 %}
9034
9035 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9036 match(Set pcc (CmpP op1 op2));
9037
9038 size(4);
9039 format %{ "CMP $op1,$op2\t! ptr" %}
9040 opcode(Assembler::subcc_op3, Assembler::arith_op);
9041 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9042 ins_pipe(ialu_cconly_reg_imm);
9043 %}
9044
9045 // Compare Narrow oops
9046 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9047 match(Set icc (CmpN op1 op2));
9048
9049 size(4);
9050 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9051 opcode(Assembler::subcc_op3, Assembler::arith_op);
9052 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9053 ins_pipe(ialu_cconly_reg_reg);
9054 %}
9055
9056 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9057 match(Set icc (CmpN op1 op2));
9058
9059 size(4);
9060 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9061 opcode(Assembler::subcc_op3, Assembler::arith_op);
9062 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9063 ins_pipe(ialu_cconly_reg_imm);
9064 %}
9065
9066 //----------Max and Min--------------------------------------------------------
9067 // Min Instructions
9068 // Conditional move for min
9069 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9070 effect( USE_DEF op2, USE op1, USE icc );
9071
9072 size(4);
9073 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9074 opcode(Assembler::less);
9075 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9076 ins_pipe(ialu_reg_flags);
9077 %}
9078
9079 // Min Register with Register.
9080 instruct minI_eReg(iRegI op1, iRegI op2) %{
9081 match(Set op2 (MinI op1 op2));
9082 ins_cost(DEFAULT_COST*2);
9083 expand %{
9084 flagsReg icc;
9085 compI_iReg(icc,op1,op2);
9086 cmovI_reg_lt(op2,op1,icc);
9087 %}
9088 %}
9089
9090 // Max Instructions
9091 // Conditional move for max
9092 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9093 effect( USE_DEF op2, USE op1, USE icc );
9094 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9095 opcode(Assembler::greater);
9096 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9097 ins_pipe(ialu_reg_flags);
9098 %}
9099
9100 // Max Register with Register
9101 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9102 match(Set op2 (MaxI op1 op2));
9103 ins_cost(DEFAULT_COST*2);
9104 expand %{
9105 flagsReg icc;
9106 compI_iReg(icc,op1,op2);
9107 cmovI_reg_gt(op2,op1,icc);
9108 %}
9109 %}
9110
9111
9112 //----------Float Compares----------------------------------------------------
9113 // Compare floating, generate condition code
9114 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9115 match(Set fcc (CmpF src1 src2));
9116
9117 size(4);
9118 format %{ "FCMPs $fcc,$src1,$src2" %}
9119 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9120 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9121 ins_pipe(faddF_fcc_reg_reg_zero);
9122 %}
9123
9124 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9125 match(Set fcc (CmpD src1 src2));
9126
9127 size(4);
9128 format %{ "FCMPd $fcc,$src1,$src2" %}
9129 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9130 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9131 ins_pipe(faddD_fcc_reg_reg_zero);
9132 %}
9133
9134
9135 // Compare floating, generate -1,0,1
9136 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9137 match(Set dst (CmpF3 src1 src2));
9138 effect(KILL fcc0);
9139 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9140 format %{ "fcmpl $dst,$src1,$src2" %}
9141 // Primary = float
9142 opcode( true );
9143 ins_encode( floating_cmp( dst, src1, src2 ) );
9144 ins_pipe( floating_cmp );
9145 %}
9146
9147 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9148 match(Set dst (CmpD3 src1 src2));
9149 effect(KILL fcc0);
9150 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9151 format %{ "dcmpl $dst,$src1,$src2" %}
9152 // Primary = double (not float)
9153 opcode( false );
9154 ins_encode( floating_cmp( dst, src1, src2 ) );
9155 ins_pipe( floating_cmp );
9156 %}
9157
9158 //----------Branches---------------------------------------------------------
9159 // Jump
9160 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9161 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9162 match(Jump switch_val);
9163 effect(TEMP table);
9164
9165 ins_cost(350);
9166
9167 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9168 "LD [O7 + $switch_val], O7\n\t"
9169 "JUMP O7" %}
9170 ins_encode %{
9171 // Calculate table address into a register.
9172 Register table_reg;
9173 Register label_reg = O7;
9174 // If we are calculating the size of this instruction don't trust
9175 // zero offsets because they might change when
9176 // MachConstantBaseNode decides to optimize the constant table
9177 // base.
9178 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9179 table_reg = $constanttablebase;
9180 } else {
9181 table_reg = O7;
9182 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9183 __ add($constanttablebase, con_offset, table_reg);
9184 }
9185
9186 // Jump to base address + switch value
9187 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9188 __ jmp(label_reg, G0);
9189 __ delayed()->nop();
9190 %}
9191 ins_pipe(ialu_reg_reg);
9192 %}
9193
9194 // Direct Branch. Use V8 version with longer range.
9195 instruct branch(label labl) %{
9196 match(Goto);
9197 effect(USE labl);
9198
9199 size(8);
9200 ins_cost(BRANCH_COST);
9201 format %{ "BA $labl" %}
9202 ins_encode %{
9203 Label* L = $labl$$label;
9204 __ ba(*L);
9205 __ delayed()->nop();
9206 %}
9207 ins_avoid_back_to_back(AVOID_BEFORE);
9208 ins_pipe(br);
9209 %}
9210
9211 // Direct Branch, short with no delay slot
9212 instruct branch_short(label labl) %{
9213 match(Goto);
9214 predicate(UseCBCond);
9215 effect(USE labl);
9216
9217 size(4);
9218 ins_cost(BRANCH_COST);
9219 format %{ "BA $labl\t! short branch" %}
9220 ins_encode %{
9221 Label* L = $labl$$label;
9222 assert(__ use_cbcond(*L), "back to back cbcond");
9223 __ ba_short(*L);
9224 %}
9225 ins_short_branch(1);
9226 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9227 ins_pipe(cbcond_reg_imm);
9228 %}
9229
9230 // Conditional Direct Branch
9231 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9232 match(If cmp icc);
9233 effect(USE labl);
9234
9235 size(8);
9236 ins_cost(BRANCH_COST);
9237 format %{ "BP$cmp $icc,$labl" %}
9238 // Prim = bits 24-22, Secnd = bits 31-30
9239 ins_encode( enc_bp( labl, cmp, icc ) );
9240 ins_avoid_back_to_back(AVOID_BEFORE);
9241 ins_pipe(br_cc);
9242 %}
9243
9244 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9245 match(If cmp icc);
9246 effect(USE labl);
9247
9248 ins_cost(BRANCH_COST);
9249 format %{ "BP$cmp $icc,$labl" %}
9250 // Prim = bits 24-22, Secnd = bits 31-30
9251 ins_encode( enc_bp( labl, cmp, icc ) );
9252 ins_avoid_back_to_back(AVOID_BEFORE);
9253 ins_pipe(br_cc);
9254 %}
9255
9256 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9257 match(If cmp pcc);
9258 effect(USE labl);
9259
9260 size(8);
9261 ins_cost(BRANCH_COST);
9262 format %{ "BP$cmp $pcc,$labl" %}
9263 ins_encode %{
9264 Label* L = $labl$$label;
9265 Assembler::Predict predict_taken =
9266 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9267
9268 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9269 __ delayed()->nop();
9270 %}
9271 ins_avoid_back_to_back(AVOID_BEFORE);
9272 ins_pipe(br_cc);
9273 %}
9274
9275 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9276 match(If cmp fcc);
9277 effect(USE labl);
9278
9279 size(8);
9280 ins_cost(BRANCH_COST);
9281 format %{ "FBP$cmp $fcc,$labl" %}
9282 ins_encode %{
9283 Label* L = $labl$$label;
9284 Assembler::Predict predict_taken =
9285 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9286
9287 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9288 __ delayed()->nop();
9289 %}
9290 ins_avoid_back_to_back(AVOID_BEFORE);
9291 ins_pipe(br_fcc);
9292 %}
9293
9294 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9295 match(CountedLoopEnd cmp icc);
9296 effect(USE labl);
9297
9298 size(8);
9299 ins_cost(BRANCH_COST);
9300 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9301 // Prim = bits 24-22, Secnd = bits 31-30
9302 ins_encode( enc_bp( labl, cmp, icc ) );
9303 ins_avoid_back_to_back(AVOID_BEFORE);
9304 ins_pipe(br_cc);
9305 %}
9306
9307 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9308 match(CountedLoopEnd cmp icc);
9309 effect(USE labl);
9310
9311 size(8);
9312 ins_cost(BRANCH_COST);
9313 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9314 // Prim = bits 24-22, Secnd = bits 31-30
9315 ins_encode( enc_bp( labl, cmp, icc ) );
9316 ins_avoid_back_to_back(AVOID_BEFORE);
9317 ins_pipe(br_cc);
9318 %}
9319
9320 // Compare and branch instructions
9321 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9322 match(If cmp (CmpI op1 op2));
9323 effect(USE labl, KILL icc);
9324
9325 size(12);
9326 ins_cost(BRANCH_COST);
9327 format %{ "CMP $op1,$op2\t! int\n\t"
9328 "BP$cmp $labl" %}
9329 ins_encode %{
9330 Label* L = $labl$$label;
9331 Assembler::Predict predict_taken =
9332 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9333 __ cmp($op1$$Register, $op2$$Register);
9334 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9335 __ delayed()->nop();
9336 %}
9337 ins_pipe(cmp_br_reg_reg);
9338 %}
9339
9340 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9341 match(If cmp (CmpI op1 op2));
9342 effect(USE labl, KILL icc);
9343
9344 size(12);
9345 ins_cost(BRANCH_COST);
9346 format %{ "CMP $op1,$op2\t! int\n\t"
9347 "BP$cmp $labl" %}
9348 ins_encode %{
9349 Label* L = $labl$$label;
9350 Assembler::Predict predict_taken =
9351 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9352 __ cmp($op1$$Register, $op2$$constant);
9353 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9354 __ delayed()->nop();
9355 %}
9356 ins_pipe(cmp_br_reg_imm);
9357 %}
9358
9359 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9360 match(If cmp (CmpU op1 op2));
9361 effect(USE labl, KILL icc);
9362
9363 size(12);
9364 ins_cost(BRANCH_COST);
9365 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9366 "BP$cmp $labl" %}
9367 ins_encode %{
9368 Label* L = $labl$$label;
9369 Assembler::Predict predict_taken =
9370 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9371 __ cmp($op1$$Register, $op2$$Register);
9372 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9373 __ delayed()->nop();
9374 %}
9375 ins_pipe(cmp_br_reg_reg);
9376 %}
9377
9378 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9379 match(If cmp (CmpU op1 op2));
9380 effect(USE labl, KILL icc);
9381
9382 size(12);
9383 ins_cost(BRANCH_COST);
9384 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9385 "BP$cmp $labl" %}
9386 ins_encode %{
9387 Label* L = $labl$$label;
9388 Assembler::Predict predict_taken =
9389 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9390 __ cmp($op1$$Register, $op2$$constant);
9391 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9392 __ delayed()->nop();
9393 %}
9394 ins_pipe(cmp_br_reg_imm);
9395 %}
9396
9397 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9398 match(If cmp (CmpL op1 op2));
9399 effect(USE labl, KILL xcc);
9400
9401 size(12);
9402 ins_cost(BRANCH_COST);
9403 format %{ "CMP $op1,$op2\t! long\n\t"
9404 "BP$cmp $labl" %}
9405 ins_encode %{
9406 Label* L = $labl$$label;
9407 Assembler::Predict predict_taken =
9408 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9409 __ cmp($op1$$Register, $op2$$Register);
9410 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9411 __ delayed()->nop();
9412 %}
9413 ins_pipe(cmp_br_reg_reg);
9414 %}
9415
9416 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9417 match(If cmp (CmpL op1 op2));
9418 effect(USE labl, KILL xcc);
9419
9420 size(12);
9421 ins_cost(BRANCH_COST);
9422 format %{ "CMP $op1,$op2\t! long\n\t"
9423 "BP$cmp $labl" %}
9424 ins_encode %{
9425 Label* L = $labl$$label;
9426 Assembler::Predict predict_taken =
9427 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9428 __ cmp($op1$$Register, $op2$$constant);
9429 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9430 __ delayed()->nop();
9431 %}
9432 ins_pipe(cmp_br_reg_imm);
9433 %}
9434
9435 // Compare Pointers and branch
9436 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9437 match(If cmp (CmpP op1 op2));
9438 effect(USE labl, KILL pcc);
9439
9440 size(12);
9441 ins_cost(BRANCH_COST);
9442 format %{ "CMP $op1,$op2\t! ptr\n\t"
9443 "B$cmp $labl" %}
9444 ins_encode %{
9445 Label* L = $labl$$label;
9446 Assembler::Predict predict_taken =
9447 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9448 __ cmp($op1$$Register, $op2$$Register);
9449 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9450 __ delayed()->nop();
9451 %}
9452 ins_pipe(cmp_br_reg_reg);
9453 %}
9454
9455 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9456 match(If cmp (CmpP op1 null));
9457 effect(USE labl, KILL pcc);
9458
9459 size(12);
9460 ins_cost(BRANCH_COST);
9461 format %{ "CMP $op1,0\t! ptr\n\t"
9462 "B$cmp $labl" %}
9463 ins_encode %{
9464 Label* L = $labl$$label;
9465 Assembler::Predict predict_taken =
9466 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9467 __ cmp($op1$$Register, G0);
9468 // bpr() is not used here since it has shorter distance.
9469 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9470 __ delayed()->nop();
9471 %}
9472 ins_pipe(cmp_br_reg_reg);
9473 %}
9474
9475 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9476 match(If cmp (CmpN op1 op2));
9477 effect(USE labl, KILL icc);
9478
9479 size(12);
9480 ins_cost(BRANCH_COST);
9481 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9482 "BP$cmp $labl" %}
9483 ins_encode %{
9484 Label* L = $labl$$label;
9485 Assembler::Predict predict_taken =
9486 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9487 __ cmp($op1$$Register, $op2$$Register);
9488 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9489 __ delayed()->nop();
9490 %}
9491 ins_pipe(cmp_br_reg_reg);
9492 %}
9493
9494 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9495 match(If cmp (CmpN op1 null));
9496 effect(USE labl, KILL icc);
9497
9498 size(12);
9499 ins_cost(BRANCH_COST);
9500 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9501 "BP$cmp $labl" %}
9502 ins_encode %{
9503 Label* L = $labl$$label;
9504 Assembler::Predict predict_taken =
9505 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9506 __ cmp($op1$$Register, G0);
9507 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9508 __ delayed()->nop();
9509 %}
9510 ins_pipe(cmp_br_reg_reg);
9511 %}
9512
9513 // Loop back branch
9514 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9515 match(CountedLoopEnd cmp (CmpI op1 op2));
9516 effect(USE labl, KILL icc);
9517
9518 size(12);
9519 ins_cost(BRANCH_COST);
9520 format %{ "CMP $op1,$op2\t! int\n\t"
9521 "BP$cmp $labl\t! Loop end" %}
9522 ins_encode %{
9523 Label* L = $labl$$label;
9524 Assembler::Predict predict_taken =
9525 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9526 __ cmp($op1$$Register, $op2$$Register);
9527 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9528 __ delayed()->nop();
9529 %}
9530 ins_pipe(cmp_br_reg_reg);
9531 %}
9532
9533 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9534 match(CountedLoopEnd cmp (CmpI op1 op2));
9535 effect(USE labl, KILL icc);
9536
9537 size(12);
9538 ins_cost(BRANCH_COST);
9539 format %{ "CMP $op1,$op2\t! int\n\t"
9540 "BP$cmp $labl\t! Loop end" %}
9541 ins_encode %{
9542 Label* L = $labl$$label;
9543 Assembler::Predict predict_taken =
9544 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9545 __ cmp($op1$$Register, $op2$$constant);
9546 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9547 __ delayed()->nop();
9548 %}
9549 ins_pipe(cmp_br_reg_imm);
9550 %}
9551
9552 // Short compare and branch instructions
9553 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9554 match(If cmp (CmpI op1 op2));
9555 predicate(UseCBCond);
9556 effect(USE labl, KILL icc);
9557
9558 size(4);
9559 ins_cost(BRANCH_COST);
9560 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9561 ins_encode %{
9562 Label* L = $labl$$label;
9563 assert(__ use_cbcond(*L), "back to back cbcond");
9564 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9565 %}
9566 ins_short_branch(1);
9567 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9568 ins_pipe(cbcond_reg_reg);
9569 %}
9570
9571 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9572 match(If cmp (CmpI op1 op2));
9573 predicate(UseCBCond);
9574 effect(USE labl, KILL icc);
9575
9576 size(4);
9577 ins_cost(BRANCH_COST);
9578 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9579 ins_encode %{
9580 Label* L = $labl$$label;
9581 assert(__ use_cbcond(*L), "back to back cbcond");
9582 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9583 %}
9584 ins_short_branch(1);
9585 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9586 ins_pipe(cbcond_reg_imm);
9587 %}
9588
9589 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9590 match(If cmp (CmpU op1 op2));
9591 predicate(UseCBCond);
9592 effect(USE labl, KILL icc);
9593
9594 size(4);
9595 ins_cost(BRANCH_COST);
9596 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9597 ins_encode %{
9598 Label* L = $labl$$label;
9599 assert(__ use_cbcond(*L), "back to back cbcond");
9600 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9601 %}
9602 ins_short_branch(1);
9603 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9604 ins_pipe(cbcond_reg_reg);
9605 %}
9606
9607 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9608 match(If cmp (CmpU op1 op2));
9609 predicate(UseCBCond);
9610 effect(USE labl, KILL icc);
9611
9612 size(4);
9613 ins_cost(BRANCH_COST);
9614 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9615 ins_encode %{
9616 Label* L = $labl$$label;
9617 assert(__ use_cbcond(*L), "back to back cbcond");
9618 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9619 %}
9620 ins_short_branch(1);
9621 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9622 ins_pipe(cbcond_reg_imm);
9623 %}
9624
9625 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9626 match(If cmp (CmpL op1 op2));
9627 predicate(UseCBCond);
9628 effect(USE labl, KILL xcc);
9629
9630 size(4);
9631 ins_cost(BRANCH_COST);
9632 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9633 ins_encode %{
9634 Label* L = $labl$$label;
9635 assert(__ use_cbcond(*L), "back to back cbcond");
9636 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9637 %}
9638 ins_short_branch(1);
9639 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9640 ins_pipe(cbcond_reg_reg);
9641 %}
9642
9643 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9644 match(If cmp (CmpL op1 op2));
9645 predicate(UseCBCond);
9646 effect(USE labl, KILL xcc);
9647
9648 size(4);
9649 ins_cost(BRANCH_COST);
9650 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9651 ins_encode %{
9652 Label* L = $labl$$label;
9653 assert(__ use_cbcond(*L), "back to back cbcond");
9654 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9655 %}
9656 ins_short_branch(1);
9657 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9658 ins_pipe(cbcond_reg_imm);
9659 %}
9660
9661 // Compare Pointers and branch
9662 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9663 match(If cmp (CmpP op1 op2));
9664 predicate(UseCBCond);
9665 effect(USE labl, KILL pcc);
9666
9667 size(4);
9668 ins_cost(BRANCH_COST);
9669 #ifdef _LP64
9670 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9671 #else
9672 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9673 #endif
9674 ins_encode %{
9675 Label* L = $labl$$label;
9676 assert(__ use_cbcond(*L), "back to back cbcond");
9677 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9678 %}
9679 ins_short_branch(1);
9680 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9681 ins_pipe(cbcond_reg_reg);
9682 %}
9683
9684 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9685 match(If cmp (CmpP op1 null));
9686 predicate(UseCBCond);
9687 effect(USE labl, KILL pcc);
9688
9689 size(4);
9690 ins_cost(BRANCH_COST);
9691 #ifdef _LP64
9692 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9693 #else
9694 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9695 #endif
9696 ins_encode %{
9697 Label* L = $labl$$label;
9698 assert(__ use_cbcond(*L), "back to back cbcond");
9699 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9700 %}
9701 ins_short_branch(1);
9702 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9703 ins_pipe(cbcond_reg_reg);
9704 %}
9705
9706 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9707 match(If cmp (CmpN op1 op2));
9708 predicate(UseCBCond);
9709 effect(USE labl, KILL icc);
9710
9711 size(4);
9712 ins_cost(BRANCH_COST);
9713 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9714 ins_encode %{
9715 Label* L = $labl$$label;
9716 assert(__ use_cbcond(*L), "back to back cbcond");
9717 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9718 %}
9719 ins_short_branch(1);
9720 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9721 ins_pipe(cbcond_reg_reg);
9722 %}
9723
9724 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9725 match(If cmp (CmpN op1 null));
9726 predicate(UseCBCond);
9727 effect(USE labl, KILL icc);
9728
9729 size(4);
9730 ins_cost(BRANCH_COST);
9731 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9732 ins_encode %{
9733 Label* L = $labl$$label;
9734 assert(__ use_cbcond(*L), "back to back cbcond");
9735 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9736 %}
9737 ins_short_branch(1);
9738 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9739 ins_pipe(cbcond_reg_reg);
9740 %}
9741
9742 // Loop back branch
9743 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9744 match(CountedLoopEnd cmp (CmpI op1 op2));
9745 predicate(UseCBCond);
9746 effect(USE labl, KILL icc);
9747
9748 size(4);
9749 ins_cost(BRANCH_COST);
9750 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9751 ins_encode %{
9752 Label* L = $labl$$label;
9753 assert(__ use_cbcond(*L), "back to back cbcond");
9754 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9755 %}
9756 ins_short_branch(1);
9757 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9758 ins_pipe(cbcond_reg_reg);
9759 %}
9760
9761 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9762 match(CountedLoopEnd cmp (CmpI op1 op2));
9763 predicate(UseCBCond);
9764 effect(USE labl, KILL icc);
9765
9766 size(4);
9767 ins_cost(BRANCH_COST);
9768 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9769 ins_encode %{
9770 Label* L = $labl$$label;
9771 assert(__ use_cbcond(*L), "back to back cbcond");
9772 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9773 %}
9774 ins_short_branch(1);
9775 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9776 ins_pipe(cbcond_reg_imm);
9777 %}
9778
9779 // Branch-on-register tests all 64 bits. We assume that values
9780 // in 64-bit registers always remains zero or sign extended
9781 // unless our code munges the high bits. Interrupts can chop
9782 // the high order bits to zero or sign at any time.
9783 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9784 match(If cmp (CmpI op1 zero));
9785 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9786 effect(USE labl);
9787
9788 size(8);
9789 ins_cost(BRANCH_COST);
9790 format %{ "BR$cmp $op1,$labl" %}
9791 ins_encode( enc_bpr( labl, cmp, op1 ) );
9792 ins_avoid_back_to_back(AVOID_BEFORE);
9793 ins_pipe(br_reg);
9794 %}
9795
9796 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9797 match(If cmp (CmpP op1 null));
9798 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9799 effect(USE labl);
9800
9801 size(8);
9802 ins_cost(BRANCH_COST);
9803 format %{ "BR$cmp $op1,$labl" %}
9804 ins_encode( enc_bpr( labl, cmp, op1 ) );
9805 ins_avoid_back_to_back(AVOID_BEFORE);
9806 ins_pipe(br_reg);
9807 %}
9808
9809 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9810 match(If cmp (CmpL op1 zero));
9811 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9812 effect(USE labl);
9813
9814 size(8);
9815 ins_cost(BRANCH_COST);
9816 format %{ "BR$cmp $op1,$labl" %}
9817 ins_encode( enc_bpr( labl, cmp, op1 ) );
9818 ins_avoid_back_to_back(AVOID_BEFORE);
9819 ins_pipe(br_reg);
9820 %}
9821
9822
9823 // ============================================================================
9824 // Long Compare
9825 //
9826 // Currently we hold longs in 2 registers. Comparing such values efficiently
9827 // is tricky. The flavor of compare used depends on whether we are testing
9828 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9829 // The GE test is the negated LT test. The LE test can be had by commuting
9830 // the operands (yielding a GE test) and then negating; negate again for the
9831 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9832 // NE test is negated from that.
9833
9834 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9835 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9836 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9837 // are collapsed internally in the ADLC's dfa-gen code. The match for
9838 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9839 // foo match ends up with the wrong leaf. One fix is to not match both
9840 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9841 // both forms beat the trinary form of long-compare and both are very useful
9842 // on Intel which has so few registers.
9843
9844 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9845 match(If cmp xcc);
9846 effect(USE labl);
9847
9848 size(8);
9849 ins_cost(BRANCH_COST);
9850 format %{ "BP$cmp $xcc,$labl" %}
9851 ins_encode %{
9852 Label* L = $labl$$label;
9853 Assembler::Predict predict_taken =
9854 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9855
9856 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9857 __ delayed()->nop();
9858 %}
9859 ins_avoid_back_to_back(AVOID_BEFORE);
9860 ins_pipe(br_cc);
9861 %}
9862
9863 // Manifest a CmpL3 result in an integer register. Very painful.
9864 // This is the test to avoid.
9865 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9866 match(Set dst (CmpL3 src1 src2) );
9867 effect( KILL ccr );
9868 ins_cost(6*DEFAULT_COST);
9869 size(24);
9870 format %{ "CMP $src1,$src2\t\t! long\n"
9871 "\tBLT,a,pn done\n"
9872 "\tMOV -1,$dst\t! delay slot\n"
9873 "\tBGT,a,pn done\n"
9874 "\tMOV 1,$dst\t! delay slot\n"
9875 "\tCLR $dst\n"
9876 "done:" %}
9877 ins_encode( cmpl_flag(src1,src2,dst) );
9878 ins_pipe(cmpL_reg);
9879 %}
9880
9881 // Conditional move
9882 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9883 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9884 ins_cost(150);
9885 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9886 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9887 ins_pipe(ialu_reg);
9888 %}
9889
9890 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9891 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9892 ins_cost(140);
9893 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9894 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9895 ins_pipe(ialu_imm);
9896 %}
9897
9898 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9899 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9900 ins_cost(150);
9901 format %{ "MOV$cmp $xcc,$src,$dst" %}
9902 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9903 ins_pipe(ialu_reg);
9904 %}
9905
9906 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9907 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9908 ins_cost(140);
9909 format %{ "MOV$cmp $xcc,$src,$dst" %}
9910 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9911 ins_pipe(ialu_imm);
9912 %}
9913
9914 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9915 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9916 ins_cost(150);
9917 format %{ "MOV$cmp $xcc,$src,$dst" %}
9918 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9919 ins_pipe(ialu_reg);
9920 %}
9921
9922 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9923 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9924 ins_cost(150);
9925 format %{ "MOV$cmp $xcc,$src,$dst" %}
9926 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9927 ins_pipe(ialu_reg);
9928 %}
9929
9930 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9931 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9932 ins_cost(140);
9933 format %{ "MOV$cmp $xcc,$src,$dst" %}
9934 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9935 ins_pipe(ialu_imm);
9936 %}
9937
9938 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9939 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9940 ins_cost(150);
9941 opcode(0x101);
9942 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9943 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9944 ins_pipe(int_conditional_float_move);
9945 %}
9946
9947 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9948 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9949 ins_cost(150);
9950 opcode(0x102);
9951 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9952 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9953 ins_pipe(int_conditional_float_move);
9954 %}
9955
9956 // ============================================================================
9957 // Safepoint Instruction
9958 instruct safePoint_poll(iRegP poll) %{
9959 match(SafePoint poll);
9960 effect(USE poll);
9961
9962 size(4);
9963 #ifdef _LP64
9964 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9965 #else
9966 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9967 #endif
9968 ins_encode %{
9969 __ relocate(relocInfo::poll_type);
9970 __ ld_ptr($poll$$Register, 0, G0);
9971 %}
9972 ins_pipe(loadPollP);
9973 %}
9974
9975 // ============================================================================
9976 // Call Instructions
9977 // Call Java Static Instruction
9978 instruct CallStaticJavaDirect( method meth ) %{
9979 match(CallStaticJava);
9980 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9981 effect(USE meth);
9982
9983 size(8);
9984 ins_cost(CALL_COST);
9985 format %{ "CALL,static ; NOP ==> " %}
9986 ins_encode( Java_Static_Call( meth ), call_epilog );
9987 ins_avoid_back_to_back(AVOID_BEFORE);
9988 ins_pipe(simple_call);
9989 %}
9990
9991 // Call Java Static Instruction (method handle version)
9992 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9993 match(CallStaticJava);
9994 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9995 effect(USE meth, KILL l7_mh_SP_save);
9996
9997 size(16);
9998 ins_cost(CALL_COST);
9999 format %{ "CALL,static/MethodHandle" %}
10000 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
10001 ins_pipe(simple_call);
10002 %}
10003
10004 // Call Java Dynamic Instruction
10005 instruct CallDynamicJavaDirect( method meth ) %{
10006 match(CallDynamicJava);
10007 effect(USE meth);
10008
10009 ins_cost(CALL_COST);
10010 format %{ "SET (empty),R_G5\n\t"
10011 "CALL,dynamic ; NOP ==> " %}
10012 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10013 ins_pipe(call);
10014 %}
10015
10016 // Call Runtime Instruction
10017 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10018 match(CallRuntime);
10019 effect(USE meth, KILL l7);
10020 ins_cost(CALL_COST);
10021 format %{ "CALL,runtime" %}
10022 ins_encode( Java_To_Runtime( meth ),
10023 call_epilog, adjust_long_from_native_call );
10024 ins_avoid_back_to_back(AVOID_BEFORE);
10025 ins_pipe(simple_call);
10026 %}
10027
10028 // Call runtime without safepoint - same as CallRuntime
10029 instruct CallLeafDirect(method meth, l7RegP l7) %{
10030 match(CallLeaf);
10031 effect(USE meth, KILL l7);
10032 ins_cost(CALL_COST);
10033 format %{ "CALL,runtime leaf" %}
10034 ins_encode( Java_To_Runtime( meth ),
10035 call_epilog,
10036 adjust_long_from_native_call );
10037 ins_avoid_back_to_back(AVOID_BEFORE);
10038 ins_pipe(simple_call);
10039 %}
10040
10041 // Call runtime without safepoint - same as CallLeaf
10042 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10043 match(CallLeafNoFP);
10044 effect(USE meth, KILL l7);
10045 ins_cost(CALL_COST);
10046 format %{ "CALL,runtime leaf nofp" %}
10047 ins_encode( Java_To_Runtime( meth ),
10048 call_epilog,
10049 adjust_long_from_native_call );
10050 ins_avoid_back_to_back(AVOID_BEFORE);
10051 ins_pipe(simple_call);
10052 %}
10053
10054 // Tail Call; Jump from runtime stub to Java code.
10055 // Also known as an 'interprocedural jump'.
10056 // Target of jump will eventually return to caller.
10057 // TailJump below removes the return address.
10058 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10059 match(TailCall jump_target method_oop );
10060
10061 ins_cost(CALL_COST);
10062 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10063 ins_encode(form_jmpl(jump_target));
10064 ins_avoid_back_to_back(AVOID_BEFORE);
10065 ins_pipe(tail_call);
10066 %}
10067
10068
10069 // Return Instruction
10070 instruct Ret() %{
10071 match(Return);
10072
10073 // The epilogue node did the ret already.
10074 size(0);
10075 format %{ "! return" %}
10076 ins_encode();
10077 ins_pipe(empty);
10078 %}
10079
10080
10081 // Tail Jump; remove the return address; jump to target.
10082 // TailCall above leaves the return address around.
10083 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10084 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10085 // "restore" before this instruction (in Epilogue), we need to materialize it
10086 // in %i0.
10087 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10088 match( TailJump jump_target ex_oop );
10089 ins_cost(CALL_COST);
10090 format %{ "! discard R_O7\n\t"
10091 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10092 ins_encode(form_jmpl_set_exception_pc(jump_target));
10093 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10094 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10095 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10096 ins_avoid_back_to_back(AVOID_BEFORE);
10097 ins_pipe(tail_call);
10098 %}
10099
10100 // Create exception oop: created by stack-crawling runtime code.
10101 // Created exception is now available to this handler, and is setup
10102 // just prior to jumping to this handler. No code emitted.
10103 instruct CreateException( o0RegP ex_oop )
10104 %{
10105 match(Set ex_oop (CreateEx));
10106 ins_cost(0);
10107
10108 size(0);
10109 // use the following format syntax
10110 format %{ "! exception oop is in R_O0; no code emitted" %}
10111 ins_encode();
10112 ins_pipe(empty);
10113 %}
10114
10115
10116 // Rethrow exception:
10117 // The exception oop will come in the first argument position.
10118 // Then JUMP (not call) to the rethrow stub code.
10119 instruct RethrowException()
10120 %{
10121 match(Rethrow);
10122 ins_cost(CALL_COST);
10123
10124 // use the following format syntax
10125 format %{ "Jmp rethrow_stub" %}
10126 ins_encode(enc_rethrow);
10127 ins_avoid_back_to_back(AVOID_BEFORE);
10128 ins_pipe(tail_call);
10129 %}
10130
10131
10132 // Die now
10133 instruct ShouldNotReachHere( )
10134 %{
10135 match(Halt);
10136 ins_cost(CALL_COST);
10137
10138 size(4);
10139 // Use the following format syntax
10140 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10141 ins_encode( form2_illtrap() );
10142 ins_pipe(tail_call);
10143 %}
10144
10145 // ============================================================================
10146 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10147 // array for an instance of the superklass. Set a hidden internal cache on a
10148 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10149 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10150 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10151 match(Set index (PartialSubtypeCheck sub super));
10152 effect( KILL pcc, KILL o7 );
10153 ins_cost(DEFAULT_COST*10);
10154 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10155 ins_encode( enc_PartialSubtypeCheck() );
10156 ins_avoid_back_to_back(AVOID_BEFORE);
10157 ins_pipe(partial_subtype_check_pipe);
10158 %}
10159
10160 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10161 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10162 effect( KILL idx, KILL o7 );
10163 ins_cost(DEFAULT_COST*10);
10164 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10165 ins_encode( enc_PartialSubtypeCheck() );
10166 ins_avoid_back_to_back(AVOID_BEFORE);
10167 ins_pipe(partial_subtype_check_pipe);
10168 %}
10169
10170
10171 // ============================================================================
10172 // inlined locking and unlocking
10173
10174 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10175 match(Set pcc (FastLock object box));
10176
10177 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10178 ins_cost(100);
10179
10180 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10181 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10182 ins_pipe(long_memory_op);
10183 %}
10184
10185
10186 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10187 match(Set pcc (FastUnlock object box));
10188 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10189 ins_cost(100);
10190
10191 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10192 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10193 ins_pipe(long_memory_op);
10194 %}
10195
10196 // The encodings are generic.
10197 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10198 predicate(!use_block_zeroing(n->in(2)) );
10199 match(Set dummy (ClearArray cnt base));
10200 effect(TEMP temp, KILL ccr);
10201 ins_cost(300);
10202 format %{ "MOV $cnt,$temp\n"
10203 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10204 " BRge loop\t\t! Clearing loop\n"
10205 " STX G0,[$base+$temp]\t! delay slot" %}
10206
10207 ins_encode %{
10208 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10209 Register nof_bytes_arg = $cnt$$Register;
10210 Register nof_bytes_tmp = $temp$$Register;
10211 Register base_pointer_arg = $base$$Register;
10212
10213 Label loop;
10214 __ mov(nof_bytes_arg, nof_bytes_tmp);
10215
10216 // Loop and clear, walking backwards through the array.
10217 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10218 __ bind(loop);
10219 __ deccc(nof_bytes_tmp, 8);
10220 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10221 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10222 // %%%% this mini-loop must not cross a cache boundary!
10223 %}
10224 ins_pipe(long_memory_op);
10225 %}
10226
10227 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10228 predicate(use_block_zeroing(n->in(2)));
10229 match(Set dummy (ClearArray cnt base));
10230 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10231 ins_cost(300);
10232 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10233
10234 ins_encode %{
10235
10236 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10237 Register to = $base$$Register;
10238 Register count = $cnt$$Register;
10239
10240 Label Ldone;
10241 __ nop(); // Separate short branches
10242 // Use BIS for zeroing (temp is not used).
10243 __ bis_zeroing(to, count, G0, Ldone);
10244 __ bind(Ldone);
10245
10246 %}
10247 ins_pipe(long_memory_op);
10248 %}
10249
10250 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10251 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10252 match(Set dummy (ClearArray cnt base));
10253 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10254 ins_cost(300);
10255 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10256
10257 ins_encode %{
10258
10259 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10260 Register to = $base$$Register;
10261 Register count = $cnt$$Register;
10262 Register temp = $tmp$$Register;
10263
10264 Label Ldone;
10265 __ nop(); // Separate short branches
10266 // Use BIS for zeroing
10267 __ bis_zeroing(to, count, temp, Ldone);
10268 __ bind(Ldone);
10269
10270 %}
10271 ins_pipe(long_memory_op);
10272 %}
10273
10274 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10275 o7RegI tmp, flagsReg ccr) %{
10276 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10277 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10278 ins_cost(300);
10279 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10280 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10281 ins_pipe(long_memory_op);
10282 %}
10283
10284 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10285 o7RegI tmp, flagsReg ccr) %{
10286 match(Set result (StrEquals (Binary str1 str2) cnt));
10287 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10288 ins_cost(300);
10289 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10290 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10291 ins_pipe(long_memory_op);
10292 %}
10293
10294 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10295 o7RegI tmp2, flagsReg ccr) %{
10296 match(Set result (AryEq ary1 ary2));
10297 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10298 ins_cost(300);
10299 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10300 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10301 ins_pipe(long_memory_op);
10302 %}
10303
10304
10305 //---------- Zeros Count Instructions ------------------------------------------
10306
10307 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10308 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10309 match(Set dst (CountLeadingZerosI src));
10310 effect(TEMP dst, TEMP tmp, KILL cr);
10311
10312 // x |= (x >> 1);
10313 // x |= (x >> 2);
10314 // x |= (x >> 4);
10315 // x |= (x >> 8);
10316 // x |= (x >> 16);
10317 // return (WORDBITS - popc(x));
10318 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10319 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10320 "OR $dst,$tmp,$dst\n\t"
10321 "SRL $dst,2,$tmp\n\t"
10322 "OR $dst,$tmp,$dst\n\t"
10323 "SRL $dst,4,$tmp\n\t"
10324 "OR $dst,$tmp,$dst\n\t"
10325 "SRL $dst,8,$tmp\n\t"
10326 "OR $dst,$tmp,$dst\n\t"
10327 "SRL $dst,16,$tmp\n\t"
10328 "OR $dst,$tmp,$dst\n\t"
10329 "POPC $dst,$dst\n\t"
10330 "MOV 32,$tmp\n\t"
10331 "SUB $tmp,$dst,$dst" %}
10332 ins_encode %{
10333 Register Rdst = $dst$$Register;
10334 Register Rsrc = $src$$Register;
10335 Register Rtmp = $tmp$$Register;
10336 __ srl(Rsrc, 1, Rtmp);
10337 __ srl(Rsrc, 0, Rdst);
10338 __ or3(Rdst, Rtmp, Rdst);
10339 __ srl(Rdst, 2, Rtmp);
10340 __ or3(Rdst, Rtmp, Rdst);
10341 __ srl(Rdst, 4, Rtmp);
10342 __ or3(Rdst, Rtmp, Rdst);
10343 __ srl(Rdst, 8, Rtmp);
10344 __ or3(Rdst, Rtmp, Rdst);
10345 __ srl(Rdst, 16, Rtmp);
10346 __ or3(Rdst, Rtmp, Rdst);
10347 __ popc(Rdst, Rdst);
10348 __ mov(BitsPerInt, Rtmp);
10349 __ sub(Rtmp, Rdst, Rdst);
10350 %}
10351 ins_pipe(ialu_reg);
10352 %}
10353
10354 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10355 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10356 match(Set dst (CountLeadingZerosL src));
10357 effect(TEMP dst, TEMP tmp, KILL cr);
10358
10359 // x |= (x >> 1);
10360 // x |= (x >> 2);
10361 // x |= (x >> 4);
10362 // x |= (x >> 8);
10363 // x |= (x >> 16);
10364 // x |= (x >> 32);
10365 // return (WORDBITS - popc(x));
10366 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10367 "OR $src,$tmp,$dst\n\t"
10368 "SRLX $dst,2,$tmp\n\t"
10369 "OR $dst,$tmp,$dst\n\t"
10370 "SRLX $dst,4,$tmp\n\t"
10371 "OR $dst,$tmp,$dst\n\t"
10372 "SRLX $dst,8,$tmp\n\t"
10373 "OR $dst,$tmp,$dst\n\t"
10374 "SRLX $dst,16,$tmp\n\t"
10375 "OR $dst,$tmp,$dst\n\t"
10376 "SRLX $dst,32,$tmp\n\t"
10377 "OR $dst,$tmp,$dst\n\t"
10378 "POPC $dst,$dst\n\t"
10379 "MOV 64,$tmp\n\t"
10380 "SUB $tmp,$dst,$dst" %}
10381 ins_encode %{
10382 Register Rdst = $dst$$Register;
10383 Register Rsrc = $src$$Register;
10384 Register Rtmp = $tmp$$Register;
10385 __ srlx(Rsrc, 1, Rtmp);
10386 __ or3( Rsrc, Rtmp, Rdst);
10387 __ srlx(Rdst, 2, Rtmp);
10388 __ or3( Rdst, Rtmp, Rdst);
10389 __ srlx(Rdst, 4, Rtmp);
10390 __ or3( Rdst, Rtmp, Rdst);
10391 __ srlx(Rdst, 8, Rtmp);
10392 __ or3( Rdst, Rtmp, Rdst);
10393 __ srlx(Rdst, 16, Rtmp);
10394 __ or3( Rdst, Rtmp, Rdst);
10395 __ srlx(Rdst, 32, Rtmp);
10396 __ or3( Rdst, Rtmp, Rdst);
10397 __ popc(Rdst, Rdst);
10398 __ mov(BitsPerLong, Rtmp);
10399 __ sub(Rtmp, Rdst, Rdst);
10400 %}
10401 ins_pipe(ialu_reg);
10402 %}
10403
10404 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10405 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10406 match(Set dst (CountTrailingZerosI src));
10407 effect(TEMP dst, KILL cr);
10408
10409 // return popc(~x & (x - 1));
10410 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10411 "ANDN $dst,$src,$dst\n\t"
10412 "SRL $dst,R_G0,$dst\n\t"
10413 "POPC $dst,$dst" %}
10414 ins_encode %{
10415 Register Rdst = $dst$$Register;
10416 Register Rsrc = $src$$Register;
10417 __ sub(Rsrc, 1, Rdst);
10418 __ andn(Rdst, Rsrc, Rdst);
10419 __ srl(Rdst, G0, Rdst);
10420 __ popc(Rdst, Rdst);
10421 %}
10422 ins_pipe(ialu_reg);
10423 %}
10424
10425 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10426 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10427 match(Set dst (CountTrailingZerosL src));
10428 effect(TEMP dst, KILL cr);
10429
10430 // return popc(~x & (x - 1));
10431 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10432 "ANDN $dst,$src,$dst\n\t"
10433 "POPC $dst,$dst" %}
10434 ins_encode %{
10435 Register Rdst = $dst$$Register;
10436 Register Rsrc = $src$$Register;
10437 __ sub(Rsrc, 1, Rdst);
10438 __ andn(Rdst, Rsrc, Rdst);
10439 __ popc(Rdst, Rdst);
10440 %}
10441 ins_pipe(ialu_reg);
10442 %}
10443
10444
10445 //---------- Population Count Instructions -------------------------------------
10446
10447 instruct popCountI(iRegIsafe dst, iRegI src) %{
10448 predicate(UsePopCountInstruction);
10449 match(Set dst (PopCountI src));
10450
10451 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10452 "POPC $dst, $dst" %}
10453 ins_encode %{
10454 __ srl($src$$Register, G0, $dst$$Register);
10455 __ popc($dst$$Register, $dst$$Register);
10456 %}
10457 ins_pipe(ialu_reg);
10458 %}
10459
10460 // Note: Long.bitCount(long) returns an int.
10461 instruct popCountL(iRegIsafe dst, iRegL src) %{
10462 predicate(UsePopCountInstruction);
10463 match(Set dst (PopCountL src));
10464
10465 format %{ "POPC $src, $dst" %}
10466 ins_encode %{
10467 __ popc($src$$Register, $dst$$Register);
10468 %}
10469 ins_pipe(ialu_reg);
10470 %}
10471
10472
10473 // ============================================================================
10474 //------------Bytes reverse--------------------------------------------------
10475
10476 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10477 match(Set dst (ReverseBytesI src));
10478
10479 // Op cost is artificially doubled to make sure that load or store
10480 // instructions are preferred over this one which requires a spill
10481 // onto a stack slot.
10482 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10483 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10484
10485 ins_encode %{
10486 __ set($src$$disp + STACK_BIAS, O7);
10487 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10488 %}
10489 ins_pipe( iload_mem );
10490 %}
10491
10492 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10493 match(Set dst (ReverseBytesL src));
10494
10495 // Op cost is artificially doubled to make sure that load or store
10496 // instructions are preferred over this one which requires a spill
10497 // onto a stack slot.
10498 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10499 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10500
10501 ins_encode %{
10502 __ set($src$$disp + STACK_BIAS, O7);
10503 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10504 %}
10505 ins_pipe( iload_mem );
10506 %}
10507
10508 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10509 match(Set dst (ReverseBytesUS src));
10510
10511 // Op cost is artificially doubled to make sure that load or store
10512 // instructions are preferred over this one which requires a spill
10513 // onto a stack slot.
10514 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10515 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10516
10517 ins_encode %{
10518 // the value was spilled as an int so bias the load
10519 __ set($src$$disp + STACK_BIAS + 2, O7);
10520 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10521 %}
10522 ins_pipe( iload_mem );
10523 %}
10524
10525 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10526 match(Set dst (ReverseBytesS src));
10527
10528 // Op cost is artificially doubled to make sure that load or store
10529 // instructions are preferred over this one which requires a spill
10530 // onto a stack slot.
10531 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10532 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10533
10534 ins_encode %{
10535 // the value was spilled as an int so bias the load
10536 __ set($src$$disp + STACK_BIAS + 2, O7);
10537 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10538 %}
10539 ins_pipe( iload_mem );
10540 %}
10541
10542 // Load Integer reversed byte order
10543 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10544 match(Set dst (ReverseBytesI (LoadI src)));
10545
10546 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10547 size(4);
10548 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10549
10550 ins_encode %{
10551 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10552 %}
10553 ins_pipe(iload_mem);
10554 %}
10555
10556 // Load Long - aligned and reversed
10557 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10558 match(Set dst (ReverseBytesL (LoadL src)));
10559
10560 ins_cost(MEMORY_REF_COST);
10561 size(4);
10562 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10563
10564 ins_encode %{
10565 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10566 %}
10567 ins_pipe(iload_mem);
10568 %}
10569
10570 // Load unsigned short / char reversed byte order
10571 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10572 match(Set dst (ReverseBytesUS (LoadUS src)));
10573
10574 ins_cost(MEMORY_REF_COST);
10575 size(4);
10576 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10577
10578 ins_encode %{
10579 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10580 %}
10581 ins_pipe(iload_mem);
10582 %}
10583
10584 // Load short reversed byte order
10585 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10586 match(Set dst (ReverseBytesS (LoadS src)));
10587
10588 ins_cost(MEMORY_REF_COST);
10589 size(4);
10590 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10591
10592 ins_encode %{
10593 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10594 %}
10595 ins_pipe(iload_mem);
10596 %}
10597
10598 // Store Integer reversed byte order
10599 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10600 match(Set dst (StoreI dst (ReverseBytesI src)));
10601
10602 ins_cost(MEMORY_REF_COST);
10603 size(4);
10604 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10605
10606 ins_encode %{
10607 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10608 %}
10609 ins_pipe(istore_mem_reg);
10610 %}
10611
10612 // Store Long reversed byte order
10613 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10614 match(Set dst (StoreL dst (ReverseBytesL src)));
10615
10616 ins_cost(MEMORY_REF_COST);
10617 size(4);
10618 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10619
10620 ins_encode %{
10621 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10622 %}
10623 ins_pipe(istore_mem_reg);
10624 %}
10625
10626 // Store unsighed short/char reversed byte order
10627 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10628 match(Set dst (StoreC dst (ReverseBytesUS src)));
10629
10630 ins_cost(MEMORY_REF_COST);
10631 size(4);
10632 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10633
10634 ins_encode %{
10635 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10636 %}
10637 ins_pipe(istore_mem_reg);
10638 %}
10639
10640 // Store short reversed byte order
10641 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10642 match(Set dst (StoreC dst (ReverseBytesS src)));
10643
10644 ins_cost(MEMORY_REF_COST);
10645 size(4);
10646 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10647
10648 ins_encode %{
10649 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10650 %}
10651 ins_pipe(istore_mem_reg);
10652 %}
10653
10654 // ====================VECTOR INSTRUCTIONS=====================================
10655
10656 // Load Aligned Packed values into a Double Register
10657 instruct loadV8(regD dst, memory mem) %{
10658 predicate(n->as_LoadVector()->memory_size() == 8);
10659 match(Set dst (LoadVector mem));
10660 ins_cost(MEMORY_REF_COST);
10661 size(4);
10662 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10663 ins_encode %{
10664 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10665 %}
10666 ins_pipe(floadD_mem);
10667 %}
10668
10669 // Store Vector in Double register to memory
10670 instruct storeV8(memory mem, regD src) %{
10671 predicate(n->as_StoreVector()->memory_size() == 8);
10672 match(Set mem (StoreVector mem src));
10673 ins_cost(MEMORY_REF_COST);
10674 size(4);
10675 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10676 ins_encode %{
10677 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10678 %}
10679 ins_pipe(fstoreD_mem_reg);
10680 %}
10681
10682 // Store Zero into vector in memory
10683 instruct storeV8B_zero(memory mem, immI0 zero) %{
10684 predicate(n->as_StoreVector()->memory_size() == 8);
10685 match(Set mem (StoreVector mem (ReplicateB zero)));
10686 ins_cost(MEMORY_REF_COST);
10687 size(4);
10688 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10689 ins_encode %{
10690 __ stx(G0, $mem$$Address);
10691 %}
10692 ins_pipe(fstoreD_mem_zero);
10693 %}
10694
10695 instruct storeV4S_zero(memory mem, immI0 zero) %{
10696 predicate(n->as_StoreVector()->memory_size() == 8);
10697 match(Set mem (StoreVector mem (ReplicateS zero)));
10698 ins_cost(MEMORY_REF_COST);
10699 size(4);
10700 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10701 ins_encode %{
10702 __ stx(G0, $mem$$Address);
10703 %}
10704 ins_pipe(fstoreD_mem_zero);
10705 %}
10706
10707 instruct storeV2I_zero(memory mem, immI0 zero) %{
10708 predicate(n->as_StoreVector()->memory_size() == 8);
10709 match(Set mem (StoreVector mem (ReplicateI zero)));
10710 ins_cost(MEMORY_REF_COST);
10711 size(4);
10712 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10713 ins_encode %{
10714 __ stx(G0, $mem$$Address);
10715 %}
10716 ins_pipe(fstoreD_mem_zero);
10717 %}
10718
10719 instruct storeV2F_zero(memory mem, immF0 zero) %{
10720 predicate(n->as_StoreVector()->memory_size() == 8);
10721 match(Set mem (StoreVector mem (ReplicateF zero)));
10722 ins_cost(MEMORY_REF_COST);
10723 size(4);
10724 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10725 ins_encode %{
10726 __ stx(G0, $mem$$Address);
10727 %}
10728 ins_pipe(fstoreD_mem_zero);
10729 %}
10730
10731 // Replicate scalar to packed byte values into Double register
10732 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10733 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10734 match(Set dst (ReplicateB src));
10735 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10736 format %{ "SLLX $src,56,$tmp\n\t"
10737 "SRLX $tmp, 8,$tmp2\n\t"
10738 "OR $tmp,$tmp2,$tmp\n\t"
10739 "SRLX $tmp,16,$tmp2\n\t"
10740 "OR $tmp,$tmp2,$tmp\n\t"
10741 "SRLX $tmp,32,$tmp2\n\t"
10742 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10743 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10744 ins_encode %{
10745 Register Rsrc = $src$$Register;
10746 Register Rtmp = $tmp$$Register;
10747 Register Rtmp2 = $tmp2$$Register;
10748 __ sllx(Rsrc, 56, Rtmp);
10749 __ srlx(Rtmp, 8, Rtmp2);
10750 __ or3 (Rtmp, Rtmp2, Rtmp);
10751 __ srlx(Rtmp, 16, Rtmp2);
10752 __ or3 (Rtmp, Rtmp2, Rtmp);
10753 __ srlx(Rtmp, 32, Rtmp2);
10754 __ or3 (Rtmp, Rtmp2, Rtmp);
10755 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10756 %}
10757 ins_pipe(ialu_reg);
10758 %}
10759
10760 // Replicate scalar to packed byte values into Double stack
10761 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10762 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10763 match(Set dst (ReplicateB src));
10764 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10765 format %{ "SLLX $src,56,$tmp\n\t"
10766 "SRLX $tmp, 8,$tmp2\n\t"
10767 "OR $tmp,$tmp2,$tmp\n\t"
10768 "SRLX $tmp,16,$tmp2\n\t"
10769 "OR $tmp,$tmp2,$tmp\n\t"
10770 "SRLX $tmp,32,$tmp2\n\t"
10771 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10772 "STX $tmp,$dst\t! regL to stkD" %}
10773 ins_encode %{
10774 Register Rsrc = $src$$Register;
10775 Register Rtmp = $tmp$$Register;
10776 Register Rtmp2 = $tmp2$$Register;
10777 __ sllx(Rsrc, 56, Rtmp);
10778 __ srlx(Rtmp, 8, Rtmp2);
10779 __ or3 (Rtmp, Rtmp2, Rtmp);
10780 __ srlx(Rtmp, 16, Rtmp2);
10781 __ or3 (Rtmp, Rtmp2, Rtmp);
10782 __ srlx(Rtmp, 32, Rtmp2);
10783 __ or3 (Rtmp, Rtmp2, Rtmp);
10784 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10785 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10786 %}
10787 ins_pipe(ialu_reg);
10788 %}
10789
10790 // Replicate scalar constant to packed byte values in Double register
10791 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10792 predicate(n->as_Vector()->length() == 8);
10793 match(Set dst (ReplicateB con));
10794 effect(KILL tmp);
10795 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10796 ins_encode %{
10797 // XXX This is a quick fix for 6833573.
10798 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10799 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10800 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10801 %}
10802 ins_pipe(loadConFD);
10803 %}
10804
10805 // Replicate scalar to packed char/short values into Double register
10806 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10807 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10808 match(Set dst (ReplicateS src));
10809 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10810 format %{ "SLLX $src,48,$tmp\n\t"
10811 "SRLX $tmp,16,$tmp2\n\t"
10812 "OR $tmp,$tmp2,$tmp\n\t"
10813 "SRLX $tmp,32,$tmp2\n\t"
10814 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10815 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10816 ins_encode %{
10817 Register Rsrc = $src$$Register;
10818 Register Rtmp = $tmp$$Register;
10819 Register Rtmp2 = $tmp2$$Register;
10820 __ sllx(Rsrc, 48, Rtmp);
10821 __ srlx(Rtmp, 16, Rtmp2);
10822 __ or3 (Rtmp, Rtmp2, Rtmp);
10823 __ srlx(Rtmp, 32, Rtmp2);
10824 __ or3 (Rtmp, Rtmp2, Rtmp);
10825 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10826 %}
10827 ins_pipe(ialu_reg);
10828 %}
10829
10830 // Replicate scalar to packed char/short values into Double stack
10831 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10832 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10833 match(Set dst (ReplicateS src));
10834 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10835 format %{ "SLLX $src,48,$tmp\n\t"
10836 "SRLX $tmp,16,$tmp2\n\t"
10837 "OR $tmp,$tmp2,$tmp\n\t"
10838 "SRLX $tmp,32,$tmp2\n\t"
10839 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10840 "STX $tmp,$dst\t! regL to stkD" %}
10841 ins_encode %{
10842 Register Rsrc = $src$$Register;
10843 Register Rtmp = $tmp$$Register;
10844 Register Rtmp2 = $tmp2$$Register;
10845 __ sllx(Rsrc, 48, Rtmp);
10846 __ srlx(Rtmp, 16, Rtmp2);
10847 __ or3 (Rtmp, Rtmp2, Rtmp);
10848 __ srlx(Rtmp, 32, Rtmp2);
10849 __ or3 (Rtmp, Rtmp2, Rtmp);
10850 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10851 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10852 %}
10853 ins_pipe(ialu_reg);
10854 %}
10855
10856 // Replicate scalar constant to packed char/short values in Double register
10857 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10858 predicate(n->as_Vector()->length() == 4);
10859 match(Set dst (ReplicateS con));
10860 effect(KILL tmp);
10861 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10862 ins_encode %{
10863 // XXX This is a quick fix for 6833573.
10864 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10865 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10866 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10867 %}
10868 ins_pipe(loadConFD);
10869 %}
10870
10871 // Replicate scalar to packed int values into Double register
10872 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10873 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10874 match(Set dst (ReplicateI src));
10875 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10876 format %{ "SLLX $src,32,$tmp\n\t"
10877 "SRLX $tmp,32,$tmp2\n\t"
10878 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10879 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10880 ins_encode %{
10881 Register Rsrc = $src$$Register;
10882 Register Rtmp = $tmp$$Register;
10883 Register Rtmp2 = $tmp2$$Register;
10884 __ sllx(Rsrc, 32, Rtmp);
10885 __ srlx(Rtmp, 32, Rtmp2);
10886 __ or3 (Rtmp, Rtmp2, Rtmp);
10887 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10888 %}
10889 ins_pipe(ialu_reg);
10890 %}
10891
10892 // Replicate scalar to packed int values into Double stack
10893 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10894 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10895 match(Set dst (ReplicateI src));
10896 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10897 format %{ "SLLX $src,32,$tmp\n\t"
10898 "SRLX $tmp,32,$tmp2\n\t"
10899 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10900 "STX $tmp,$dst\t! regL to stkD" %}
10901 ins_encode %{
10902 Register Rsrc = $src$$Register;
10903 Register Rtmp = $tmp$$Register;
10904 Register Rtmp2 = $tmp2$$Register;
10905 __ sllx(Rsrc, 32, Rtmp);
10906 __ srlx(Rtmp, 32, Rtmp2);
10907 __ or3 (Rtmp, Rtmp2, Rtmp);
10908 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10909 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10910 %}
10911 ins_pipe(ialu_reg);
10912 %}
10913
10914 // Replicate scalar zero constant to packed int values in Double register
10915 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10916 predicate(n->as_Vector()->length() == 2);
10917 match(Set dst (ReplicateI con));
10918 effect(KILL tmp);
10919 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10920 ins_encode %{
10921 // XXX This is a quick fix for 6833573.
10922 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10923 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10924 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10925 %}
10926 ins_pipe(loadConFD);
10927 %}
10928
10929 // Replicate scalar to packed float values into Double stack
10930 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10931 predicate(n->as_Vector()->length() == 2);
10932 match(Set dst (ReplicateF src));
10933 ins_cost(MEMORY_REF_COST*2);
10934 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10935 "STF $src,$dst.lo" %}
10936 opcode(Assembler::stf_op3);
10937 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10938 ins_pipe(fstoreF_stk_reg);
10939 %}
10940
10941 // Replicate scalar zero constant to packed float values in Double register
10942 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10943 predicate(n->as_Vector()->length() == 2);
10944 match(Set dst (ReplicateF con));
10945 effect(KILL tmp);
10946 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10947 ins_encode %{
10948 // XXX This is a quick fix for 6833573.
10949 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10950 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10951 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10952 %}
10953 ins_pipe(loadConFD);
10954 %}
10955
10956 //----------PEEPHOLE RULES-----------------------------------------------------
10957 // These must follow all instruction definitions as they use the names
10958 // defined in the instructions definitions.
10959 //
10960 // peepmatch ( root_instr_name [preceding_instruction]* );
10961 //
10962 // peepconstraint %{
10963 // (instruction_number.operand_name relational_op instruction_number.operand_name
10964 // [, ...] );
10965 // // instruction numbers are zero-based using left to right order in peepmatch
10966 //
10967 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10968 // // provide an instruction_number.operand_name for each operand that appears
10969 // // in the replacement instruction's match rule
10970 //
10971 // ---------VM FLAGS---------------------------------------------------------
10972 //
10973 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10974 //
10975 // Each peephole rule is given an identifying number starting with zero and
10976 // increasing by one in the order seen by the parser. An individual peephole
10977 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10978 // on the command-line.
10979 //
10980 // ---------CURRENT LIMITATIONS----------------------------------------------
10981 //
10982 // Only match adjacent instructions in same basic block
10983 // Only equality constraints
10984 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10985 // Only one replacement instruction
10986 //
10987 // ---------EXAMPLE----------------------------------------------------------
10988 //
10989 // // pertinent parts of existing instructions in architecture description
10990 // instruct movI(eRegI dst, eRegI src) %{
10991 // match(Set dst (CopyI src));
10992 // %}
10993 //
10994 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10995 // match(Set dst (AddI dst src));
10996 // effect(KILL cr);
10997 // %}
10998 //
10999 // // Change (inc mov) to lea
11000 // peephole %{
11001 // // increment preceeded by register-register move
11002 // peepmatch ( incI_eReg movI );
11003 // // require that the destination register of the increment
11004 // // match the destination register of the move
11005 // peepconstraint ( 0.dst == 1.dst );
11006 // // construct a replacement instruction that sets
11007 // // the destination to ( move's source register + one )
11008 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
11009 // %}
11010 //
11011
11012 // // Change load of spilled value to only a spill
11013 // instruct storeI(memory mem, eRegI src) %{
11014 // match(Set mem (StoreI mem src));
11015 // %}
11016 //
11017 // instruct loadI(eRegI dst, memory mem) %{
11018 // match(Set dst (LoadI mem));
11019 // %}
11020 //
11021 // peephole %{
11022 // peepmatch ( loadI storeI );
11023 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11024 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11025 // %}
11026
11027 //----------SMARTSPILL RULES---------------------------------------------------
11028 // These must follow all instruction definitions as they use the names
11029 // defined in the instructions definitions.
11030 //
11031 // SPARC will probably not have any of these rules due to RISC instruction set.
11032
11033 //----------PIPELINE-----------------------------------------------------------
11034 // Rules which define the behavior of the target architectures pipeline.