1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 
  31 // MacroAssembler extends Assembler by frequently used macros.
  32 //
  33 // Instructions for which a 'better' code sequence exists depending
  34 // on arguments should also go in here.
  35 
  36 class MacroAssembler: public Assembler {
  37   friend class LIR_Assembler;
  38 
  39  public:
  40   using Assembler::mov;
  41   using Assembler::movi;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50   virtual void call_VM_leaf_base(
  51     address entry_point,               // the entry point
  52     int     number_of_arguments,        // the number of arguments to pop after the call
  53     Label *retaddr = NULL
  54   );
  55 
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label &retaddr) {
  60     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  61   }
  62 
  63   // This is the base routine called by the different versions of call_VM. The interpreter
  64   // may customize this version by overriding it for its purposes (e.g., to save/restore
  65   // additional registers when doing a VM call).
  66   //
  67   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  68   // returns the register which contains the thread upon return. If a thread register has been
  69   // specified, the return value will correspond to that register. If no last_java_sp is specified
  70   // (noreg) than rsp will be used instead.
  71   virtual void call_VM_base(           // returns the register containing the thread upon return
  72     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  73     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  74     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  75     address  entry_point,              // the entry point
  76     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  77     bool     check_exceptions          // whether to check for pending exceptions after return
  78   );
  79 
  80   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  81 
  82   // Maximum size of class area in Metaspace when compressed
  83   uint64_t use_XOR_for_compressed_class_base;
  84 
  85  public:
  86   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  87     use_XOR_for_compressed_class_base
  88       = (operand_valid_for_logical_immediate(false /*is32*/,
  89                                              (uint64_t)Universe::narrow_klass_base())
  90          && ((uint64_t)Universe::narrow_klass_base()
  91              > (1u << log2_intptr(CompressedClassSpaceSize))));
  92   }
  93 
  94  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  95  // The implementation is only non-empty for the InterpreterMacroAssembler,
  96  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  97  virtual void check_and_handle_popframe(Register java_thread);
  98  virtual void check_and_handle_earlyret(Register java_thread);
  99 
 100   // Biased locking support
 101   // lock_reg and obj_reg must be loaded up with the appropriate values.
 102   // swap_reg is killed.
 103   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 104   // Optional slow case is for implementations (interpreter and C1) which branch to
 105   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 106   // Returns offset of first potentially-faulting instruction for null
 107   // check info (currently consumed only by C1). If
 108   // swap_reg_contains_mark is true then returns -1 as it is assumed
 109   // the calling code has already passed any potential faults.
 110   int biased_locking_enter(Register lock_reg, Register obj_reg,
 111                            Register swap_reg, Register tmp_reg,
 112                            bool swap_reg_contains_mark,
 113                            Label& done, Label* slow_case = NULL,
 114                            BiasedLockingCounters* counters = NULL);
 115   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 116 
 117 
 118   // Helper functions for statistics gathering.
 119   // Unconditional atomic increment.
 120   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 121   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 122     lea(tmp1, counter_addr);
 123     atomic_incw(tmp1, tmp2, tmp3);
 124   }
 125   // Load Effective Address
 126   void lea(Register r, const Address &a) {
 127     InstructionMark im(this);
 128     code_section()->relocate(inst_mark(), a.rspec());
 129     a.lea(this, r);
 130   }
 131 
 132   void addmw(Address a, Register incr, Register scratch) {
 133     ldrw(scratch, a);
 134     addw(scratch, scratch, incr);
 135     strw(scratch, a);
 136   }
 137 
 138   // Add constant to memory word
 139   void addmw(Address a, int imm, Register scratch) {
 140     ldrw(scratch, a);
 141     if (imm > 0)
 142       addw(scratch, scratch, (unsigned)imm);
 143     else
 144       subw(scratch, scratch, (unsigned)-imm);
 145     strw(scratch, a);
 146   }
 147 
 148   void bind(Label& L) {
 149     Assembler::bind(L);
 150     code()->clear_last_membar();
 151   }
 152 
 153   void membar(Membar_mask_bits order_constraint);
 154 
 155   // Frame creation and destruction shared between JITs.
 156   void build_frame(int framesize);
 157   void remove_frame(int framesize);
 158 
 159   virtual void _call_Unimplemented(address call_site) {
 160     mov(rscratch2, call_site);
 161     haltsim();
 162   }
 163 
 164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 165 
 166   virtual void notify(int type);
 167 
 168   // aliases defined in AARCH64 spec
 169 
 170   template<class T>
 171   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 172   // imm is limited to 12 bits.
 173   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 174 
 175   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 176   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 177 
 178   void cset(Register Rd, Assembler::Condition cond) {
 179     csinc(Rd, zr, zr, ~cond);
 180   }
 181   void csetw(Register Rd, Assembler::Condition cond) {
 182     csincw(Rd, zr, zr, ~cond);
 183   }
 184 
 185   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 186     csneg(Rd, Rn, Rn, ~cond);
 187   }
 188   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 189     csnegw(Rd, Rn, Rn, ~cond);
 190   }
 191 
 192   inline void movw(Register Rd, Register Rn) {
 193     if (Rd == sp || Rn == sp) {
 194       addw(Rd, Rn, 0U);
 195     } else {
 196       orrw(Rd, zr, Rn);
 197     }
 198   }
 199   inline void mov(Register Rd, Register Rn) {
 200     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 201     if (Rd == Rn) {
 202     } else if (Rd == sp || Rn == sp) {
 203       add(Rd, Rn, 0U);
 204     } else {
 205       orr(Rd, zr, Rn);
 206     }
 207   }
 208 
 209   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 210   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 211 
 212   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 213   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 214 
 215   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 216   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 217 
 218   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 219     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 220   }
 221   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 222     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 223   }
 224 
 225   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 226     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 227   }
 228   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 229     bfm(Rd, Rn, lsb , (lsb + width - 1));
 230   }
 231 
 232   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 233     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 234   }
 235   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 236     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 237   }
 238 
 239   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 241   }
 242   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 243     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 244   }
 245 
 246   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 248   }
 249   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 251   }
 252 
 253   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 255   }
 256   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 258   }
 259 
 260   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 261     sbfmw(Rd, Rn, imm, 31);
 262   }
 263 
 264   inline void asr(Register Rd, Register Rn, unsigned imm) {
 265     sbfm(Rd, Rn, imm, 63);
 266   }
 267 
 268   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 269     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 270   }
 271 
 272   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 273     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 274   }
 275 
 276   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 277     ubfmw(Rd, Rn, imm, 31);
 278   }
 279 
 280   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 281     ubfm(Rd, Rn, imm, 63);
 282   }
 283 
 284   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 285     extrw(Rd, Rn, Rn, imm);
 286   }
 287 
 288   inline void ror(Register Rd, Register Rn, unsigned imm) {
 289     extr(Rd, Rn, Rn, imm);
 290   }
 291 
 292   inline void sxtbw(Register Rd, Register Rn) {
 293     sbfmw(Rd, Rn, 0, 7);
 294   }
 295   inline void sxthw(Register Rd, Register Rn) {
 296     sbfmw(Rd, Rn, 0, 15);
 297   }
 298   inline void sxtb(Register Rd, Register Rn) {
 299     sbfm(Rd, Rn, 0, 7);
 300   }
 301   inline void sxth(Register Rd, Register Rn) {
 302     sbfm(Rd, Rn, 0, 15);
 303   }
 304   inline void sxtw(Register Rd, Register Rn) {
 305     sbfm(Rd, Rn, 0, 31);
 306   }
 307 
 308   inline void uxtbw(Register Rd, Register Rn) {
 309     ubfmw(Rd, Rn, 0, 7);
 310   }
 311   inline void uxthw(Register Rd, Register Rn) {
 312     ubfmw(Rd, Rn, 0, 15);
 313   }
 314   inline void uxtb(Register Rd, Register Rn) {
 315     ubfm(Rd, Rn, 0, 7);
 316   }
 317   inline void uxth(Register Rd, Register Rn) {
 318     ubfm(Rd, Rn, 0, 15);
 319   }
 320   inline void uxtw(Register Rd, Register Rn) {
 321     ubfm(Rd, Rn, 0, 31);
 322   }
 323 
 324   inline void cmnw(Register Rn, Register Rm) {
 325     addsw(zr, Rn, Rm);
 326   }
 327   inline void cmn(Register Rn, Register Rm) {
 328     adds(zr, Rn, Rm);
 329   }
 330 
 331   inline void cmpw(Register Rn, Register Rm) {
 332     subsw(zr, Rn, Rm);
 333   }
 334   inline void cmp(Register Rn, Register Rm) {
 335     subs(zr, Rn, Rm);
 336   }
 337 
 338   inline void negw(Register Rd, Register Rn) {
 339     subw(Rd, zr, Rn);
 340   }
 341 
 342   inline void neg(Register Rd, Register Rn) {
 343     sub(Rd, zr, Rn);
 344   }
 345 
 346   inline void negsw(Register Rd, Register Rn) {
 347     subsw(Rd, zr, Rn);
 348   }
 349 
 350   inline void negs(Register Rd, Register Rn) {
 351     subs(Rd, zr, Rn);
 352   }
 353 
 354   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 355     addsw(zr, Rn, Rm, kind, shift);
 356   }
 357   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 358     adds(zr, Rn, Rm, kind, shift);
 359   }
 360 
 361   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 362     subsw(zr, Rn, Rm, kind, shift);
 363   }
 364   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 365     subs(zr, Rn, Rm, kind, shift);
 366   }
 367 
 368   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 369     subw(Rd, zr, Rn, kind, shift);
 370   }
 371 
 372   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 373     sub(Rd, zr, Rn, kind, shift);
 374   }
 375 
 376   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 377     subsw(Rd, zr, Rn, kind, shift);
 378   }
 379 
 380   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 381     subs(Rd, zr, Rn, kind, shift);
 382   }
 383 
 384   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 385     msubw(Rd, Rn, Rm, zr);
 386   }
 387   inline void mneg(Register Rd, Register Rn, Register Rm) {
 388     msub(Rd, Rn, Rm, zr);
 389   }
 390 
 391   inline void mulw(Register Rd, Register Rn, Register Rm) {
 392     maddw(Rd, Rn, Rm, zr);
 393   }
 394   inline void mul(Register Rd, Register Rn, Register Rm) {
 395     madd(Rd, Rn, Rm, zr);
 396   }
 397 
 398   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 399     smsubl(Rd, Rn, Rm, zr);
 400   }
 401   inline void smull(Register Rd, Register Rn, Register Rm) {
 402     smaddl(Rd, Rn, Rm, zr);
 403   }
 404 
 405   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 406     umsubl(Rd, Rn, Rm, zr);
 407   }
 408   inline void umull(Register Rd, Register Rn, Register Rm) {
 409     umaddl(Rd, Rn, Rm, zr);
 410   }
 411 
 412 #define WRAP(INSN)                                                            \
 413   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 414     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 415       nop();                                                                  \
 416     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 417   }
 418 
 419   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 420   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 421 #undef WRAP
 422 
 423 
 424   // macro assembly operations needed for aarch64
 425 
 426   // first two private routines for loading 32 bit or 64 bit constants
 427 private:
 428 
 429   void mov_immediate64(Register dst, u_int64_t imm64);
 430   void mov_immediate32(Register dst, u_int32_t imm32);
 431 
 432   int push(unsigned int bitset, Register stack);
 433   int pop(unsigned int bitset, Register stack);
 434 
 435   void mov(Register dst, Address a);
 436 
 437 public:
 438   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 439   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 440 
 441   // Push and pop everything that might be clobbered by a native
 442   // runtime call except rscratch1 and rscratch2.  (They are always
 443   // scratch, so we don't have to protect them.)  Only save the lower
 444   // 64 bits of each vector register.
 445   void push_call_clobbered_registers();
 446   void pop_call_clobbered_registers();
 447 
 448   // now mov instructions for loading absolute addresses and 32 or
 449   // 64 bit integers
 450 
 451   inline void mov(Register dst, address addr)
 452   {
 453     mov_immediate64(dst, (u_int64_t)addr);
 454   }
 455 
 456   inline void mov(Register dst, u_int64_t imm64)
 457   {
 458     mov_immediate64(dst, imm64);
 459   }
 460 
 461   inline void movw(Register dst, u_int32_t imm32)
 462   {
 463     mov_immediate32(dst, imm32);
 464   }
 465 
 466   inline void mov(Register dst, long l)
 467   {
 468     mov(dst, (u_int64_t)l);
 469   }
 470 
 471   inline void mov(Register dst, int i)
 472   {
 473     mov(dst, (long)i);
 474   }
 475 
 476   void mov(Register dst, RegisterOrConstant src) {
 477     if (src.is_register())
 478       mov(dst, src.as_register());
 479     else
 480       mov(dst, src.as_constant());
 481   }
 482 
 483   void movptr(Register r, uintptr_t imm64);
 484 
 485   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 486 
 487   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 488     orr(Vd, T, Vn, Vn);
 489   }
 490 
 491 public:
 492 
 493   // Generalized Test Bit And Branch, including a "far" variety which
 494   // spans more than 32KiB.
 495   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 496     assert(cond == EQ || cond == NE, "must be");
 497 
 498     if (far)
 499       cond = ~cond;
 500 
 501     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 502     if (cond == Assembler::EQ)
 503       branch = &Assembler::tbz;
 504     else
 505       branch = &Assembler::tbnz;
 506 
 507     if (far) {
 508       Label L;
 509       (this->*branch)(Rt, bitpos, L);
 510       b(dest);
 511       bind(L);
 512     } else {
 513       (this->*branch)(Rt, bitpos, dest);
 514     }
 515   }
 516 
 517   // macro instructions for accessing and updating floating point
 518   // status register
 519   //
 520   // FPSR : op1 == 011
 521   //        CRn == 0100
 522   //        CRm == 0100
 523   //        op2 == 001
 524 
 525   inline void get_fpsr(Register reg)
 526   {
 527     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 528   }
 529 
 530   inline void set_fpsr(Register reg)
 531   {
 532     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 533   }
 534 
 535   inline void clear_fpsr()
 536   {
 537     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 538   }
 539 
 540   // DCZID_EL0: op1 == 011
 541   //            CRn == 0000
 542   //            CRm == 0000
 543   //            op2 == 111
 544   inline void get_dczid_el0(Register reg)
 545   {
 546     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 547   }
 548 
 549   // CTR_EL0:   op1 == 011
 550   //            CRn == 0000
 551   //            CRm == 0000
 552   //            op2 == 001
 553   inline void get_ctr_el0(Register reg)
 554   {
 555     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 556   }
 557 
 558   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 559   int corrected_idivl(Register result, Register ra, Register rb,
 560                       bool want_remainder, Register tmp = rscratch1);
 561   int corrected_idivq(Register result, Register ra, Register rb,
 562                       bool want_remainder, Register tmp = rscratch1);
 563 
 564   // Support for NULL-checks
 565   //
 566   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 567   // If the accessed location is M[reg + offset] and the offset is known, provide the
 568   // offset. No explicit code generation is needed if the offset is within a certain
 569   // range (0 <= offset <= page_size).
 570 
 571   virtual void null_check(Register reg, int offset = -1);
 572   static bool needs_explicit_null_check(intptr_t offset);
 573 
 574   static address target_addr_for_insn(address insn_addr, unsigned insn);
 575   static address target_addr_for_insn(address insn_addr) {
 576     unsigned insn = *(unsigned*)insn_addr;
 577     return target_addr_for_insn(insn_addr, insn);
 578   }
 579 
 580   // Required platform-specific helpers for Label::patch_instructions.
 581   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 582   static int pd_patch_instruction_size(address branch, address target);
 583   static void pd_patch_instruction(address branch, address target) {
 584     pd_patch_instruction_size(branch, target);
 585   }
 586   static address pd_call_destination(address branch) {
 587     return target_addr_for_insn(branch);
 588   }
 589 #ifndef PRODUCT
 590   static void pd_print_patched_instruction(address branch);
 591 #endif
 592 
 593   static int patch_oop(address insn_addr, address o);
 594   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 595 
 596   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 597 
 598   // The following 4 methods return the offset of the appropriate move instruction
 599 
 600   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 601   int load_unsigned_byte(Register dst, Address src);
 602   int load_unsigned_short(Register dst, Address src);
 603 
 604   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 605   int load_signed_byte(Register dst, Address src);
 606   int load_signed_short(Register dst, Address src);
 607 
 608   int load_signed_byte32(Register dst, Address src);
 609   int load_signed_short32(Register dst, Address src);
 610 
 611   // Support for sign-extension (hi:lo = extend_sign(lo))
 612   void extend_sign(Register hi, Register lo);
 613 
 614   // Load and store values by size and signed-ness
 615   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 616   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 617 
 618   // Support for inc/dec with optimal instruction selection depending on value
 619 
 620   // x86_64 aliases an unqualified register/address increment and
 621   // decrement to call incrementq and decrementq but also supports
 622   // explicitly sized calls to incrementq/decrementq or
 623   // incrementl/decrementl
 624 
 625   // for aarch64 the proper convention would be to use
 626   // increment/decrement for 64 bit operatons and
 627   // incrementw/decrementw for 32 bit operations. so when porting
 628   // x86_64 code we can leave calls to increment/decrement as is,
 629   // replace incrementq/decrementq with increment/decrement and
 630   // replace incrementl/decrementl with incrementw/decrementw.
 631 
 632   // n.b. increment/decrement calls with an Address destination will
 633   // need to use a scratch register to load the value to be
 634   // incremented. increment/decrement calls which add or subtract a
 635   // constant value greater than 2^12 will need to use a 2nd scratch
 636   // register to hold the constant. so, a register increment/decrement
 637   // may trash rscratch2 and an address increment/decrement trash
 638   // rscratch and rscratch2
 639 
 640   void decrementw(Address dst, int value = 1);
 641   void decrementw(Register reg, int value = 1);
 642 
 643   void decrement(Register reg, int value = 1);
 644   void decrement(Address dst, int value = 1);
 645 
 646   void incrementw(Address dst, int value = 1);
 647   void incrementw(Register reg, int value = 1);
 648 
 649   void increment(Register reg, int value = 1);
 650   void increment(Address dst, int value = 1);
 651 
 652 
 653   // Alignment
 654   void align(int modulus);
 655 
 656   // Stack frame creation/removal
 657   void enter()
 658   {
 659     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 660     mov(rfp, sp);
 661   }
 662   void leave()
 663   {
 664     mov(sp, rfp);
 665     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 666   }
 667 
 668   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 669   // The pointer will be loaded into the thread register.
 670   void get_thread(Register thread);
 671 
 672 
 673   // Support for VM calls
 674   //
 675   // It is imperative that all calls into the VM are handled via the call_VM macros.
 676   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 677   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 678 
 679 
 680   void call_VM(Register oop_result,
 681                address entry_point,
 682                bool check_exceptions = true);
 683   void call_VM(Register oop_result,
 684                address entry_point,
 685                Register arg_1,
 686                bool check_exceptions = true);
 687   void call_VM(Register oop_result,
 688                address entry_point,
 689                Register arg_1, Register arg_2,
 690                bool check_exceptions = true);
 691   void call_VM(Register oop_result,
 692                address entry_point,
 693                Register arg_1, Register arg_2, Register arg_3,
 694                bool check_exceptions = true);
 695 
 696   // Overloadings with last_Java_sp
 697   void call_VM(Register oop_result,
 698                Register last_java_sp,
 699                address entry_point,
 700                int number_of_arguments = 0,
 701                bool check_exceptions = true);
 702   void call_VM(Register oop_result,
 703                Register last_java_sp,
 704                address entry_point,
 705                Register arg_1, bool
 706                check_exceptions = true);
 707   void call_VM(Register oop_result,
 708                Register last_java_sp,
 709                address entry_point,
 710                Register arg_1, Register arg_2,
 711                bool check_exceptions = true);
 712   void call_VM(Register oop_result,
 713                Register last_java_sp,
 714                address entry_point,
 715                Register arg_1, Register arg_2, Register arg_3,
 716                bool check_exceptions = true);
 717 
 718   void get_vm_result  (Register oop_result, Register thread);
 719   void get_vm_result_2(Register metadata_result, Register thread);
 720 
 721   // These always tightly bind to MacroAssembler::call_VM_base
 722   // bypassing the virtual implementation
 723   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 724   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 725   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 726   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 727   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 728 
 729   void call_VM_leaf(address entry_point,
 730                     int number_of_arguments = 0);
 731   void call_VM_leaf(address entry_point,
 732                     Register arg_1);
 733   void call_VM_leaf(address entry_point,
 734                     Register arg_1, Register arg_2);
 735   void call_VM_leaf(address entry_point,
 736                     Register arg_1, Register arg_2, Register arg_3);
 737 
 738   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 739   // bypassing the virtual implementation
 740   void super_call_VM_leaf(address entry_point);
 741   void super_call_VM_leaf(address entry_point, Register arg_1);
 742   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 743   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 744   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 745 
 746   // last Java Frame (fills frame anchor)
 747   void set_last_Java_frame(Register last_java_sp,
 748                            Register last_java_fp,
 749                            address last_java_pc,
 750                            Register scratch);
 751 
 752   void set_last_Java_frame(Register last_java_sp,
 753                            Register last_java_fp,
 754                            Label &last_java_pc,
 755                            Register scratch);
 756 
 757   void set_last_Java_frame(Register last_java_sp,
 758                            Register last_java_fp,
 759                            Register last_java_pc,
 760                            Register scratch);
 761 
 762   void reset_last_Java_frame(Register thread);
 763 
 764   // thread in the default location (rthread)
 765   void reset_last_Java_frame(bool clear_fp);
 766 
 767   // Stores
 768   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 769   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 770 
 771 #if INCLUDE_ALL_GCS
 772 
 773   void g1_write_barrier_pre(Register obj,
 774                             Register pre_val,
 775                             Register thread,
 776                             Register tmp,
 777                             bool tosca_live,
 778                             bool expand_call);
 779 
 780   void g1_write_barrier_post(Register store_addr,
 781                              Register new_val,
 782                              Register thread,
 783                              Register tmp,
 784                              Register tmp2);
 785 
 786 #endif // INCLUDE_ALL_GCS
 787 
 788   // oop manipulations
 789   void load_klass(Register dst, Register src);
 790   void store_klass(Register dst, Register src);
 791   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 792 
 793   void resolve_oop_handle(Register result);
 794   void load_mirror(Register dst, Register method);
 795 
 796   void load_heap_oop(Register dst, Address src);
 797 
 798   void load_heap_oop_not_null(Register dst, Address src);
 799   void store_heap_oop(Address dst, Register src);
 800 
 801   // currently unimplemented
 802   // Used for storing NULL. All other oop constants should be
 803   // stored using routines that take a jobject.
 804   void store_heap_oop_null(Address dst);
 805 
 806   void load_prototype_header(Register dst, Register src);
 807 
 808   void store_klass_gap(Register dst, Register src);
 809 
 810   // This dummy is to prevent a call to store_heap_oop from
 811   // converting a zero (like NULL) into a Register by giving
 812   // the compiler two choices it can't resolve
 813 
 814   void store_heap_oop(Address dst, void* dummy);
 815 
 816   void encode_heap_oop(Register d, Register s);
 817   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 818   void decode_heap_oop(Register d, Register s);
 819   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 820   void encode_heap_oop_not_null(Register r);
 821   void decode_heap_oop_not_null(Register r);
 822   void encode_heap_oop_not_null(Register dst, Register src);
 823   void decode_heap_oop_not_null(Register dst, Register src);
 824 
 825   void set_narrow_oop(Register dst, jobject obj);
 826 
 827   void encode_klass_not_null(Register r);
 828   void decode_klass_not_null(Register r);
 829   void encode_klass_not_null(Register dst, Register src);
 830   void decode_klass_not_null(Register dst, Register src);
 831 
 832   void set_narrow_klass(Register dst, Klass* k);
 833 
 834   // if heap base register is used - reinit it with the correct value
 835   void reinit_heapbase();
 836 
 837   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 838 
 839   void push_CPU_state(bool save_vectors = false);
 840   void pop_CPU_state(bool restore_vectors = false) ;
 841 
 842   // Round up to a power of two
 843   void round_to(Register reg, int modulus);
 844 
 845   // allocation
 846   void eden_allocate(
 847     Register obj,                      // result: pointer to object after successful allocation
 848     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 849     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 850     Register t1,                       // temp register
 851     Label&   slow_case                 // continuation point if fast allocation fails
 852   );
 853   void tlab_allocate(
 854     Register obj,                      // result: pointer to object after successful allocation
 855     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 856     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 857     Register t1,                       // temp register
 858     Register t2,                       // temp register
 859     Label&   slow_case                 // continuation point if fast allocation fails
 860   );
 861   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 862   void zero_memory(Register addr, Register len, Register t1);
 863   void verify_tlab();
 864 
 865   void incr_allocated_bytes(Register thread,
 866                             Register var_size_in_bytes, int con_size_in_bytes,
 867                             Register t1 = noreg);
 868 
 869   // interface method calling
 870   void lookup_interface_method(Register recv_klass,
 871                                Register intf_klass,
 872                                RegisterOrConstant itable_index,
 873                                Register method_result,
 874                                Register scan_temp,
 875                                Label& no_such_interface);
 876 
 877   // virtual method calling
 878   // n.b. x86 allows RegisterOrConstant for vtable_index
 879   void lookup_virtual_method(Register recv_klass,
 880                              RegisterOrConstant vtable_index,
 881                              Register method_result);
 882 
 883   // Test sub_klass against super_klass, with fast and slow paths.
 884 
 885   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 886   // One of the three labels can be NULL, meaning take the fall-through.
 887   // If super_check_offset is -1, the value is loaded up from super_klass.
 888   // No registers are killed, except temp_reg.
 889   void check_klass_subtype_fast_path(Register sub_klass,
 890                                      Register super_klass,
 891                                      Register temp_reg,
 892                                      Label* L_success,
 893                                      Label* L_failure,
 894                                      Label* L_slow_path,
 895                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 896 
 897   // The rest of the type check; must be wired to a corresponding fast path.
 898   // It does not repeat the fast path logic, so don't use it standalone.
 899   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 900   // Updates the sub's secondary super cache as necessary.
 901   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 902   void check_klass_subtype_slow_path(Register sub_klass,
 903                                      Register super_klass,
 904                                      Register temp_reg,
 905                                      Register temp2_reg,
 906                                      Label* L_success,
 907                                      Label* L_failure,
 908                                      bool set_cond_codes = false);
 909 
 910   // Simplified, combined version, good for typical uses.
 911   // Falls through on failure.
 912   void check_klass_subtype(Register sub_klass,
 913                            Register super_klass,
 914                            Register temp_reg,
 915                            Label& L_success);
 916 
 917   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 918 
 919 
 920   // Debugging
 921 
 922   // only if +VerifyOops
 923   void verify_oop(Register reg, const char* s = "broken oop");
 924   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 925 
 926 // TODO: verify method and klass metadata (compare against vptr?)
 927   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 928   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 929 
 930 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 931 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 932 
 933   // only if +VerifyFPU
 934   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 935 
 936   // prints msg, dumps registers and stops execution
 937   void stop(const char* msg);
 938 
 939   // prints msg and continues
 940   void warn(const char* msg);
 941 
 942   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 943 
 944   void untested()                                { stop("untested"); }
 945 
 946   void unimplemented(const char* what = "");
 947 
 948   void should_not_reach_here()                   { stop("should not reach here"); }
 949 
 950   // Stack overflow checking
 951   void bang_stack_with_offset(int offset) {
 952     // stack grows down, caller passes positive offset
 953     assert(offset > 0, "must bang with negative offset");
 954     sub(rscratch2, sp, offset);
 955     str(zr, Address(rscratch2));
 956   }
 957 
 958   // Writes to stack successive pages until offset reached to check for
 959   // stack overflow + shadow pages.  Also, clobbers tmp
 960   void bang_stack_size(Register size, Register tmp);
 961 
 962   // Check for reserved stack access in method being exited (for JIT)
 963   void reserved_stack_check();
 964 
 965   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 966                                                 Register tmp,
 967                                                 int offset);
 968 
 969   // Support for serializing memory accesses between threads
 970   void serialize_memory(Register thread, Register tmp);
 971 
 972   // Arithmetics
 973 
 974   void addptr(const Address &dst, int32_t src);
 975   void cmpptr(Register src1, Address src2);
 976 
 977   // Various forms of CAS
 978 
 979   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
 980                           Label &suceed, Label *fail);
 981   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 982                   Label &suceed, Label *fail);
 983 
 984   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 985                   Label &suceed, Label *fail);
 986 
 987   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 988   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 989   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
 990   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
 991 
 992   void atomic_xchg(Register prev, Register newv, Register addr);
 993   void atomic_xchgw(Register prev, Register newv, Register addr);
 994   void atomic_xchgal(Register prev, Register newv, Register addr);
 995   void atomic_xchgalw(Register prev, Register newv, Register addr);
 996 
 997   void orptr(Address adr, RegisterOrConstant src) {
 998     ldr(rscratch2, adr);
 999     if (src.is_register())
1000       orr(rscratch2, rscratch2, src.as_register());
1001     else
1002       orr(rscratch2, rscratch2, src.as_constant());
1003     str(rscratch2, adr);
1004   }
1005 
1006   // A generic CAS; success or failure is in the EQ flag.
1007   // Clobbers rscratch1
1008   void cmpxchg(Register addr, Register expected, Register new_val,
1009                enum operand_size size,
1010                bool acquire, bool release, bool weak,
1011                Register result);
1012 
1013   // Calls
1014 
1015   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1016 
1017   static bool far_branches() {
1018     return ReservedCodeCacheSize > branch_range;
1019   }
1020 
1021   // Jumps that can reach anywhere in the code cache.
1022   // Trashes tmp.
1023   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1024   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1025 
1026   static int far_branch_size() {
1027     if (far_branches()) {
1028       return 3 * 4;  // adrp, add, br
1029     } else {
1030       return 4;
1031     }
1032   }
1033 
1034   // Emit the CompiledIC call idiom
1035   address ic_call(address entry, jint method_index = 0);
1036 
1037 public:
1038 
1039   // Data
1040 
1041   void mov_metadata(Register dst, Metadata* obj);
1042   Address allocate_metadata_address(Metadata* obj);
1043   Address constant_oop_address(jobject obj);
1044 
1045   void movoop(Register dst, jobject obj, bool immediate = false);
1046 
1047   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1048   void kernel_crc32(Register crc, Register buf, Register len,
1049         Register table0, Register table1, Register table2, Register table3,
1050         Register tmp, Register tmp2, Register tmp3);
1051   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1052   void kernel_crc32c(Register crc, Register buf, Register len,
1053         Register table0, Register table1, Register table2, Register table3,
1054         Register tmp, Register tmp2, Register tmp3);
1055 
1056   // Stack push and pop individual 64 bit registers
1057   void push(Register src);
1058   void pop(Register dst);
1059 
1060   // push all registers onto the stack
1061   void pusha();
1062   void popa();
1063 
1064   void repne_scan(Register addr, Register value, Register count,
1065                   Register scratch);
1066   void repne_scanw(Register addr, Register value, Register count,
1067                    Register scratch);
1068 
1069   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1070   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1071 
1072   // If a constant does not fit in an immediate field, generate some
1073   // number of MOV instructions and then perform the operation
1074   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1075                              add_sub_imm_insn insn1,
1076                              add_sub_reg_insn insn2);
1077   // Seperate vsn which sets the flags
1078   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1079                              add_sub_imm_insn insn1,
1080                              add_sub_reg_insn insn2);
1081 
1082 #define WRAP(INSN)                                                      \
1083   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1084     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1085   }                                                                     \
1086                                                                         \
1087   void INSN(Register Rd, Register Rn, Register Rm,                      \
1088              enum shift_kind kind, unsigned shift = 0) {                \
1089     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1090   }                                                                     \
1091                                                                         \
1092   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1093     Assembler::INSN(Rd, Rn, Rm);                                        \
1094   }                                                                     \
1095                                                                         \
1096   void INSN(Register Rd, Register Rn, Register Rm,                      \
1097            ext::operation option, int amount = 0) {                     \
1098     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1099   }
1100 
1101   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1102 
1103 #undef WRAP
1104 #define WRAP(INSN)                                                      \
1105   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1106     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1107   }                                                                     \
1108                                                                         \
1109   void INSN(Register Rd, Register Rn, Register Rm,                      \
1110              enum shift_kind kind, unsigned shift = 0) {                \
1111     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1112   }                                                                     \
1113                                                                         \
1114   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1115     Assembler::INSN(Rd, Rn, Rm);                                        \
1116   }                                                                     \
1117                                                                         \
1118   void INSN(Register Rd, Register Rn, Register Rm,                      \
1119            ext::operation option, int amount = 0) {                     \
1120     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1121   }
1122 
1123   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1124 
1125   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1126   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1127   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1128   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1129 
1130   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1131 
1132   void tableswitch(Register index, jint lowbound, jint highbound,
1133                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1134     adr(rscratch1, jumptable);
1135     subsw(rscratch2, index, lowbound);
1136     subsw(zr, rscratch2, highbound - lowbound);
1137     br(Assembler::HS, jumptable_end);
1138     add(rscratch1, rscratch1, rscratch2,
1139         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1140     br(rscratch1);
1141   }
1142 
1143   // Form an address from base + offset in Rd.  Rd may or may not
1144   // actually be used: you must use the Address that is returned.  It
1145   // is up to you to ensure that the shift provided matches the size
1146   // of your data.
1147   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1148 
1149   // Return true iff an address is within the 48-bit AArch64 address
1150   // space.
1151   bool is_valid_AArch64_address(address a) {
1152     return ((uint64_t)a >> 48) == 0;
1153   }
1154 
1155   // Load the base of the cardtable byte map into reg.
1156   void load_byte_map_base(Register reg);
1157 
1158   // Prolog generator routines to support switch between x86 code and
1159   // generated ARM code
1160 
1161   // routine to generate an x86 prolog for a stub function which
1162   // bootstraps into the generated ARM code which directly follows the
1163   // stub
1164   //
1165 
1166   public:
1167   // enum used for aarch64--x86 linkage to define return type of x86 function
1168   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1169 
1170 #ifdef BUILTIN_SIM
1171   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1172 #else
1173   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1174 #endif
1175 
1176   // special version of call_VM_leaf_base needed for aarch64 simulator
1177   // where we need to specify both the gp and fp arg counts and the
1178   // return type so that the linkage routine from aarch64 to x86 and
1179   // back knows which aarch64 registers to copy to x86 registers and
1180   // which x86 result register to copy back to an aarch64 register
1181 
1182   void call_VM_leaf_base1(
1183     address  entry_point,             // the entry point
1184     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1185     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1186     ret_type type,                    // the return type for the call
1187     Label*   retaddr = NULL
1188   );
1189 
1190   void ldr_constant(Register dest, const Address &const_addr) {
1191     if (NearCpool) {
1192       ldr(dest, const_addr);
1193     } else {
1194       unsigned long offset;
1195       adrp(dest, InternalAddress(const_addr.target()), offset);
1196       ldr(dest, Address(dest, offset));
1197     }
1198   }
1199 
1200   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1201   address read_polling_page(Register r, relocInfo::relocType rtype);
1202 
1203   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1204   void update_byte_crc32(Register crc, Register val, Register table);
1205   void update_word_crc32(Register crc, Register v, Register tmp,
1206         Register table0, Register table1, Register table2, Register table3,
1207         bool upper = false);
1208 
1209   void string_compare(Register str1, Register str2,
1210                       Register cnt1, Register cnt2, Register result,
1211                       Register tmp1,
1212                       FloatRegister vtmp, FloatRegister vtmpZ, int ae);
1213 
1214   void has_negatives(Register ary1, Register len, Register result);
1215 
1216   void arrays_equals(Register a1, Register a2,
1217                      Register result, Register cnt1,
1218                      int elem_size, bool is_string);
1219 
1220   void fill_words(Register base, Register cnt, Register value);
1221   void zero_words(Register base, u_int64_t cnt);
1222   void zero_words(Register ptr, Register cnt);
1223   void zero_dcache_blocks(Register base, Register cnt);
1224 
1225   static const int zero_words_block_size;
1226 
1227   void byte_array_inflate(Register src, Register dst, Register len,
1228                           FloatRegister vtmp1, FloatRegister vtmp2,
1229                           FloatRegister vtmp3, Register tmp4);
1230 
1231   void char_array_compress(Register src, Register dst, Register len,
1232                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1233                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1234                            Register result);
1235 
1236   void encode_iso_array(Register src, Register dst,
1237                         Register len, Register result,
1238                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1239                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1240   void string_indexof(Register str1, Register str2,
1241                       Register cnt1, Register cnt2,
1242                       Register tmp1, Register tmp2,
1243                       Register tmp3, Register tmp4,
1244                       int int_cnt1, Register result, int ae);
1245   void string_indexof_char(Register str1, Register cnt1,
1246                            Register ch, Register result,
1247                            Register tmp1, Register tmp2, Register tmp3);
1248 private:
1249   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1250                        Register src1, Register src2);
1251   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1252     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1253   }
1254   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1255                              Register y, Register y_idx, Register z,
1256                              Register carry, Register product,
1257                              Register idx, Register kdx);
1258   void multiply_128_x_128_loop(Register y, Register z,
1259                                Register carry, Register carry2,
1260                                Register idx, Register jdx,
1261                                Register yz_idx1, Register yz_idx2,
1262                                Register tmp, Register tmp3, Register tmp4,
1263                                Register tmp7, Register product_hi);
1264   void kernel_crc32_using_crc32(Register crc, Register buf,
1265         Register len, Register tmp0, Register tmp1, Register tmp2,
1266         Register tmp3);
1267 public:
1268   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1269                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1270                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1271   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1272   // ISB may be needed because of a safepoint
1273   void maybe_isb() { isb(); }
1274 
1275 private:
1276   // Return the effective address r + (r1 << ext) + offset.
1277   // Uses rscratch2.
1278   Address offsetted_address(Register r, Register r1, Address::extend ext,
1279                             int offset, int size);
1280 
1281 private:
1282   // Returns an address on the stack which is reachable with a ldr/str of size
1283   // Uses rscratch2 if the address is not directly reachable
1284   Address spill_address(int size, int offset, Register tmp=rscratch2);
1285 
1286 public:
1287   void spill(Register Rx, bool is64, int offset) {
1288     if (is64) {
1289       str(Rx, spill_address(8, offset));
1290     } else {
1291       strw(Rx, spill_address(4, offset));
1292     }
1293   }
1294   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1295     str(Vx, T, spill_address(1 << (int)T, offset));
1296   }
1297   void unspill(Register Rx, bool is64, int offset) {
1298     if (is64) {
1299       ldr(Rx, spill_address(8, offset));
1300     } else {
1301       ldrw(Rx, spill_address(4, offset));
1302     }
1303   }
1304   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1305     ldr(Vx, T, spill_address(1 << (int)T, offset));
1306   }
1307   void spill_copy128(int src_offset, int dst_offset,
1308                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1309     if (src_offset < 512 && (src_offset & 7) == 0 &&
1310         dst_offset < 512 && (dst_offset & 7) == 0) {
1311       ldp(tmp1, tmp2, Address(sp, src_offset));
1312       stp(tmp1, tmp2, Address(sp, dst_offset));
1313     } else {
1314       unspill(tmp1, true, src_offset);
1315       spill(tmp1, true, dst_offset);
1316       unspill(tmp1, true, src_offset+8);
1317       spill(tmp1, true, dst_offset+8);
1318     }
1319   }
1320 };
1321 
1322 #ifdef ASSERT
1323 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1324 #endif
1325 
1326 /**
1327  * class SkipIfEqual:
1328  *
1329  * Instantiating this class will result in assembly code being output that will
1330  * jump around any code emitted between the creation of the instance and it's
1331  * automatic destruction at the end of a scope block, depending on the value of
1332  * the flag passed to the constructor, which will be checked at run-time.
1333  */
1334 class SkipIfEqual {
1335  private:
1336   MacroAssembler* _masm;
1337   Label _label;
1338 
1339  public:
1340    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1341    ~SkipIfEqual();
1342 };
1343 
1344 struct tableswitch {
1345   Register _reg;
1346   int _insn_index; jint _first_key; jint _last_key;
1347   Label _after;
1348   Label _branches;
1349 };
1350 
1351 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP