1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc_interface/collectedHeap.hpp"
36 #include "memory/barrierSet.hpp"
37 #include "memory/cardTableModRefBS.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (2 * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
349 __ nop();
350 }
351 }
352 int offset = __ offset();
353 __ inline_cache_check(receiver, IC_Klass);
354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
355 if (do_post_padding) {
356 // force alignment after the cache check.
357 // It's been verified to be aligned if !VerifyOops
358 __ align(CodeEntryAlignment);
359 }
360 return offset;
361 }
362
363
364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
365 jobject o = NULL;
366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
367 __ movoop(reg, o);
368 patching_epilog(patch, lir_patch_normal, reg, info);
369 }
370
371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
372 Metadata* o = NULL;
373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
374 __ mov_metadata(reg, o);
375 patching_epilog(patch, lir_patch_normal, reg, info);
376 }
377
378 // This specifies the rsp decrement needed to build the frame
379 int LIR_Assembler::initial_frame_size_in_bytes() const {
380 // if rounding, must let FrameMap know!
381
382 // The frame_map records size in slots (32bit word)
383
384 // subtract two words to account for return address and link
385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
386 }
387
388
389 int LIR_Assembler::emit_exception_handler() {
390 // if the last instruction is a call (typically to do a throw which
391 // is coming at the end after block reordering) the return address
392 // must still point into the code area in order to avoid assertion
393 // failures when searching for the corresponding bci => add a nop
394 // (was bug 5/14/1999 - gri)
395 __ nop();
396
397 // generate code for exception handler
398 address handler_base = __ start_a_stub(exception_handler_size);
399 if (handler_base == NULL) {
400 // not enough space left for the handler
401 bailout("exception handler overflow");
402 return -1;
403 }
404
405 int offset = code_offset();
406
407 // the exception oop and pc are in rax, and rdx
408 // no other registers need to be preserved, so invalidate them
409 __ invalidate_registers(false, true, true, false, true, true);
410
411 // check that there is really an exception
412 __ verify_not_null_oop(rax);
413
414 // search an exception handler (rax: exception oop, rdx: throwing pc)
415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
416 __ should_not_reach_here();
417 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
418 __ end_a_stub();
419
420 return offset;
421 }
422
423
424 // Emit the code to remove the frame from the stack in the exception
425 // unwind path.
426 int LIR_Assembler::emit_unwind_handler() {
427 #ifndef PRODUCT
428 if (CommentedAssembly) {
429 _masm->block_comment("Unwind handler");
430 }
431 #endif
432
433 int offset = code_offset();
434
435 // Fetch the exception from TLS and clear out exception related thread state
436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
437 NOT_LP64(__ get_thread(rsi));
438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
441
442 __ bind(_unwind_handler_entry);
443 __ verify_not_null_oop(rax);
444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
446 }
447
448 // Preform needed unlocking
449 MonitorExitStub* stub = NULL;
450 if (method()->is_synchronized()) {
451 monitor_address(0, FrameMap::rax_opr);
452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
453 __ unlock_object(rdi, rsi, rax, *stub->entry());
454 __ bind(*stub->continuation());
455 }
456
457 if (compilation()->env()->dtrace_method_probes()) {
458 #ifdef _LP64
459 __ mov(rdi, r15_thread);
460 __ mov_metadata(rsi, method()->constant_encoding());
461 #else
462 __ get_thread(rax);
463 __ movptr(Address(rsp, 0), rax);
464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
465 #endif
466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
467 }
468
469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
470 __ mov(rax, rbx); // Restore the exception
471 }
472
473 // remove the activation and dispatch to the unwind handler
474 __ remove_frame(initial_frame_size_in_bytes());
475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
476
477 // Emit the slow path assembly
478 if (stub != NULL) {
479 stub->emit_code(this);
480 }
481
482 return offset;
483 }
484
485
486 int LIR_Assembler::emit_deopt_handler() {
487 // if the last instruction is a call (typically to do a throw which
488 // is coming at the end after block reordering) the return address
489 // must still point into the code area in order to avoid assertion
490 // failures when searching for the corresponding bci => add a nop
491 // (was bug 5/14/1999 - gri)
492 __ nop();
493
494 // generate code for exception handler
495 address handler_base = __ start_a_stub(deopt_handler_size);
496 if (handler_base == NULL) {
497 // not enough space left for the handler
498 bailout("deopt handler overflow");
499 return -1;
500 }
501
502 int offset = code_offset();
503 InternalAddress here(__ pc());
504
505 __ pushptr(here.addr());
506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
507 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
508 __ end_a_stub();
509
510 return offset;
511 }
512
513
514 // This is the fast version of java.lang.String.compare; it has not
515 // OSR-entry and therefore, we generate a slow version for OSR's
516 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
517 __ movptr (rbx, rcx); // receiver is in rcx
518 __ movptr (rax, arg1->as_register());
519
520 // Get addresses of first characters from both Strings
521 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
522 if (java_lang_String::has_offset_field()) {
523 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
524 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
525 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
526 } else {
527 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
528 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
529 }
530
531 // rbx, may be NULL
532 add_debug_info_for_null_check_here(info);
533 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
534 if (java_lang_String::has_offset_field()) {
535 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
536 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
537 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
538 } else {
539 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
540 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
541 }
542
543 // compute minimum length (in rax) and difference of lengths (on top of stack)
544 __ mov (rcx, rbx);
545 __ subptr(rbx, rax); // subtract lengths
546 __ push (rbx); // result
547 __ cmov (Assembler::lessEqual, rax, rcx);
548
549 // is minimum length 0?
550 Label noLoop, haveResult;
551 __ testptr (rax, rax);
552 __ jcc (Assembler::zero, noLoop);
553
554 // compare first characters
555 __ load_unsigned_short(rcx, Address(rdi, 0));
556 __ load_unsigned_short(rbx, Address(rsi, 0));
557 __ subl(rcx, rbx);
558 __ jcc(Assembler::notZero, haveResult);
559 // starting loop
560 __ decrement(rax); // we already tested index: skip one
561 __ jcc(Assembler::zero, noLoop);
562
563 // set rsi.edi to the end of the arrays (arrays have same length)
564 // negate the index
565
566 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
567 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
568 __ negptr(rax);
569
570 // compare the strings in a loop
571
572 Label loop;
573 __ align(wordSize);
574 __ bind(loop);
575 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
576 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
577 __ subl(rcx, rbx);
578 __ jcc(Assembler::notZero, haveResult);
579 __ increment(rax);
580 __ jcc(Assembler::notZero, loop);
581
582 // strings are equal up to min length
583
584 __ bind(noLoop);
585 __ pop(rax);
586 return_op(LIR_OprFact::illegalOpr);
587
588 __ bind(haveResult);
589 // leave instruction is going to discard the TOS value
590 __ mov (rax, rcx); // result of call is in rax,
591 }
592
593
594 void LIR_Assembler::return_op(LIR_Opr result) {
595 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
596 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
597 assert(result->fpu() == 0, "result must already be on TOS");
598 }
599
600 // Pop the stack before the safepoint code
601 __ remove_frame(initial_frame_size_in_bytes());
602
603 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
604
605 // Note: we do not need to round double result; float result has the right precision
606 // the poll sets the condition code, but no data registers
607 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
608
609 if (Assembler::is_polling_page_far()) {
610 __ lea(rscratch1, polling_page);
611 __ relocate(relocInfo::poll_return_type);
612 __ testl(rax, Address(rscratch1, 0));
613 } else {
614 __ testl(rax, polling_page);
615 }
616 __ ret(0);
617 }
618
619
620 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
621 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
622 guarantee(info != NULL, "Shouldn't be NULL");
623 int offset = __ offset();
624 if (Assembler::is_polling_page_far()) {
625 __ lea(rscratch1, polling_page);
626 offset = __ offset();
627 add_debug_info_for_branch(info);
628 __ relocate(relocInfo::poll_type);
629 __ testl(rax, Address(rscratch1, 0));
630 } else {
631 add_debug_info_for_branch(info);
632 __ testl(rax, polling_page);
633 }
634 return offset;
635 }
636
637
638 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
639 if (from_reg != to_reg) __ mov(to_reg, from_reg);
640 }
641
642 void LIR_Assembler::swap_reg(Register a, Register b) {
643 __ xchgptr(a, b);
644 }
645
646
647 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
648 assert(src->is_constant(), "should not call otherwise");
649 assert(dest->is_register(), "should not call otherwise");
650 LIR_Const* c = src->as_constant_ptr();
651
652 switch (c->type()) {
653 case T_INT: {
654 assert(patch_code == lir_patch_none, "no patching handled here");
655 __ movl(dest->as_register(), c->as_jint());
656 break;
657 }
658
659 case T_ADDRESS: {
660 assert(patch_code == lir_patch_none, "no patching handled here");
661 __ movptr(dest->as_register(), c->as_jint());
662 break;
663 }
664
665 case T_LONG: {
666 assert(patch_code == lir_patch_none, "no patching handled here");
667 #ifdef _LP64
668 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
669 #else
670 __ movptr(dest->as_register_lo(), c->as_jint_lo());
671 __ movptr(dest->as_register_hi(), c->as_jint_hi());
672 #endif // _LP64
673 break;
674 }
675
676 case T_OBJECT: {
677 if (patch_code != lir_patch_none) {
678 jobject2reg_with_patching(dest->as_register(), info);
679 } else {
680 __ movoop(dest->as_register(), c->as_jobject());
681 }
682 break;
683 }
684
685 case T_METADATA: {
686 if (patch_code != lir_patch_none) {
687 klass2reg_with_patching(dest->as_register(), info);
688 } else {
689 __ mov_metadata(dest->as_register(), c->as_metadata());
690 }
691 break;
692 }
693
694 case T_FLOAT: {
695 if (dest->is_single_xmm()) {
696 if (c->is_zero_float()) {
697 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
698 } else {
699 __ movflt(dest->as_xmm_float_reg(),
700 InternalAddress(float_constant(c->as_jfloat())));
701 }
702 } else {
703 assert(dest->is_single_fpu(), "must be");
704 assert(dest->fpu_regnr() == 0, "dest must be TOS");
705 if (c->is_zero_float()) {
706 __ fldz();
707 } else if (c->is_one_float()) {
708 __ fld1();
709 } else {
710 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
711 }
712 }
713 break;
714 }
715
716 case T_DOUBLE: {
717 if (dest->is_double_xmm()) {
718 if (c->is_zero_double()) {
719 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
720 } else {
721 __ movdbl(dest->as_xmm_double_reg(),
722 InternalAddress(double_constant(c->as_jdouble())));
723 }
724 } else {
725 assert(dest->is_double_fpu(), "must be");
726 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
727 if (c->is_zero_double()) {
728 __ fldz();
729 } else if (c->is_one_double()) {
730 __ fld1();
731 } else {
732 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
733 }
734 }
735 break;
736 }
737
738 default:
739 ShouldNotReachHere();
740 }
741 }
742
743 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
744 assert(src->is_constant(), "should not call otherwise");
745 assert(dest->is_stack(), "should not call otherwise");
746 LIR_Const* c = src->as_constant_ptr();
747
748 switch (c->type()) {
749 case T_INT: // fall through
750 case T_FLOAT:
751 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
752 break;
753
754 case T_ADDRESS:
755 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
756 break;
757
758 case T_OBJECT:
759 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
760 break;
761
762 case T_LONG: // fall through
763 case T_DOUBLE:
764 #ifdef _LP64
765 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
766 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
767 #else
768 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
769 lo_word_offset_in_bytes), c->as_jint_lo_bits());
770 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
771 hi_word_offset_in_bytes), c->as_jint_hi_bits());
772 #endif // _LP64
773 break;
774
775 default:
776 ShouldNotReachHere();
777 }
778 }
779
780 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
781 assert(src->is_constant(), "should not call otherwise");
782 assert(dest->is_address(), "should not call otherwise");
783 LIR_Const* c = src->as_constant_ptr();
784 LIR_Address* addr = dest->as_address_ptr();
785
786 int null_check_here = code_offset();
787 switch (type) {
788 case T_INT: // fall through
789 case T_FLOAT:
790 __ movl(as_Address(addr), c->as_jint_bits());
791 break;
792
793 case T_ADDRESS:
794 __ movptr(as_Address(addr), c->as_jint_bits());
795 break;
796
797 case T_OBJECT: // fall through
798 case T_ARRAY:
799 if (c->as_jobject() == NULL) {
800 if (UseCompressedOops && !wide) {
801 __ movl(as_Address(addr), (int32_t)NULL_WORD);
802 } else {
803 #ifdef _LP64
804 __ xorptr(rscratch1, rscratch1);
805 null_check_here = code_offset();
806 __ movptr(as_Address(addr), rscratch1);
807 #else
808 __ movptr(as_Address(addr), NULL_WORD);
809 #endif
810 }
811 } else {
812 if (is_literal_address(addr)) {
813 ShouldNotReachHere();
814 __ movoop(as_Address(addr, noreg), c->as_jobject());
815 } else {
816 #ifdef _LP64
817 __ movoop(rscratch1, c->as_jobject());
818 if (UseCompressedOops && !wide) {
819 __ encode_heap_oop(rscratch1);
820 null_check_here = code_offset();
821 __ movl(as_Address_lo(addr), rscratch1);
822 } else {
823 null_check_here = code_offset();
824 __ movptr(as_Address_lo(addr), rscratch1);
825 }
826 #else
827 __ movoop(as_Address(addr), c->as_jobject());
828 #endif
829 }
830 }
831 break;
832
833 case T_LONG: // fall through
834 case T_DOUBLE:
835 #ifdef _LP64
836 if (is_literal_address(addr)) {
837 ShouldNotReachHere();
838 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
839 } else {
840 __ movptr(r10, (intptr_t)c->as_jlong_bits());
841 null_check_here = code_offset();
842 __ movptr(as_Address_lo(addr), r10);
843 }
844 #else
845 // Always reachable in 32bit so this doesn't produce useless move literal
846 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
847 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
848 #endif // _LP64
849 break;
850
851 case T_BOOLEAN: // fall through
852 case T_BYTE:
853 __ movb(as_Address(addr), c->as_jint() & 0xFF);
854 break;
855
856 case T_CHAR: // fall through
857 case T_SHORT:
858 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
859 break;
860
861 default:
862 ShouldNotReachHere();
863 };
864
865 if (info != NULL) {
866 add_debug_info_for_null_check(null_check_here, info);
867 }
868 }
869
870
871 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
872 assert(src->is_register(), "should not call otherwise");
873 assert(dest->is_register(), "should not call otherwise");
874
875 // move between cpu-registers
876 if (dest->is_single_cpu()) {
877 #ifdef _LP64
878 if (src->type() == T_LONG) {
879 // Can do LONG -> OBJECT
880 move_regs(src->as_register_lo(), dest->as_register());
881 return;
882 }
883 #endif
884 assert(src->is_single_cpu(), "must match");
885 if (src->type() == T_OBJECT) {
886 __ verify_oop(src->as_register());
887 }
888 move_regs(src->as_register(), dest->as_register());
889
890 } else if (dest->is_double_cpu()) {
891 #ifdef _LP64
892 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
893 // Surprising to me but we can see move of a long to t_object
894 __ verify_oop(src->as_register());
895 move_regs(src->as_register(), dest->as_register_lo());
896 return;
897 }
898 #endif
899 assert(src->is_double_cpu(), "must match");
900 Register f_lo = src->as_register_lo();
901 Register f_hi = src->as_register_hi();
902 Register t_lo = dest->as_register_lo();
903 Register t_hi = dest->as_register_hi();
904 #ifdef _LP64
905 assert(f_hi == f_lo, "must be same");
906 assert(t_hi == t_lo, "must be same");
907 move_regs(f_lo, t_lo);
908 #else
909 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
910
911
912 if (f_lo == t_hi && f_hi == t_lo) {
913 swap_reg(f_lo, f_hi);
914 } else if (f_hi == t_lo) {
915 assert(f_lo != t_hi, "overwriting register");
916 move_regs(f_hi, t_hi);
917 move_regs(f_lo, t_lo);
918 } else {
919 assert(f_hi != t_lo, "overwriting register");
920 move_regs(f_lo, t_lo);
921 move_regs(f_hi, t_hi);
922 }
923 #endif // LP64
924
925 // special moves from fpu-register to xmm-register
926 // necessary for method results
927 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
928 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
929 __ fld_s(Address(rsp, 0));
930 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
931 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
932 __ fld_d(Address(rsp, 0));
933 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
934 __ fstp_s(Address(rsp, 0));
935 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
936 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
937 __ fstp_d(Address(rsp, 0));
938 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
939
940 // move between xmm-registers
941 } else if (dest->is_single_xmm()) {
942 assert(src->is_single_xmm(), "must match");
943 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
944 } else if (dest->is_double_xmm()) {
945 assert(src->is_double_xmm(), "must match");
946 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
947
948 // move between fpu-registers (no instruction necessary because of fpu-stack)
949 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
950 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
951 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
952 } else {
953 ShouldNotReachHere();
954 }
955 }
956
957 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
958 assert(src->is_register(), "should not call otherwise");
959 assert(dest->is_stack(), "should not call otherwise");
960
961 if (src->is_single_cpu()) {
962 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
963 if (type == T_OBJECT || type == T_ARRAY) {
964 __ verify_oop(src->as_register());
965 __ movptr (dst, src->as_register());
966 } else if (type == T_METADATA) {
967 __ movptr (dst, src->as_register());
968 } else {
969 __ movl (dst, src->as_register());
970 }
971
972 } else if (src->is_double_cpu()) {
973 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
974 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
975 __ movptr (dstLO, src->as_register_lo());
976 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
977
978 } else if (src->is_single_xmm()) {
979 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
980 __ movflt(dst_addr, src->as_xmm_float_reg());
981
982 } else if (src->is_double_xmm()) {
983 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
984 __ movdbl(dst_addr, src->as_xmm_double_reg());
985
986 } else if (src->is_single_fpu()) {
987 assert(src->fpu_regnr() == 0, "argument must be on TOS");
988 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
989 if (pop_fpu_stack) __ fstp_s (dst_addr);
990 else __ fst_s (dst_addr);
991
992 } else if (src->is_double_fpu()) {
993 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
994 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
995 if (pop_fpu_stack) __ fstp_d (dst_addr);
996 else __ fst_d (dst_addr);
997
998 } else {
999 ShouldNotReachHere();
1000 }
1001 }
1002
1003
1004 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
1005 LIR_Address* to_addr = dest->as_address_ptr();
1006 PatchingStub* patch = NULL;
1007 Register compressed_src = rscratch1;
1008
1009 if (type == T_ARRAY || type == T_OBJECT) {
1010 __ verify_oop(src->as_register());
1011 #ifdef _LP64
1012 if (UseCompressedOops && !wide) {
1013 __ movptr(compressed_src, src->as_register());
1014 __ encode_heap_oop(compressed_src);
1015 if (patch_code != lir_patch_none) {
1016 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1017 }
1018 }
1019 #endif
1020 }
1021
1022 if (patch_code != lir_patch_none) {
1023 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1024 Address toa = as_Address(to_addr);
1025 assert(toa.disp() != 0, "must have");
1026 }
1027
1028 int null_check_here = code_offset();
1029 switch (type) {
1030 case T_FLOAT: {
1031 if (src->is_single_xmm()) {
1032 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1033 } else {
1034 assert(src->is_single_fpu(), "must be");
1035 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1036 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1037 else __ fst_s (as_Address(to_addr));
1038 }
1039 break;
1040 }
1041
1042 case T_DOUBLE: {
1043 if (src->is_double_xmm()) {
1044 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1045 } else {
1046 assert(src->is_double_fpu(), "must be");
1047 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1048 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1049 else __ fst_d (as_Address(to_addr));
1050 }
1051 break;
1052 }
1053
1054 case T_ARRAY: // fall through
1055 case T_OBJECT: // fall through
1056 if (UseCompressedOops && !wide) {
1057 __ movl(as_Address(to_addr), compressed_src);
1058 } else {
1059 __ movptr(as_Address(to_addr), src->as_register());
1060 }
1061 break;
1062 case T_METADATA:
1063 // We get here to store a method pointer to the stack to pass to
1064 // a dtrace runtime call. This can't work on 64 bit with
1065 // compressed klass ptrs: T_METADATA can be a compressed klass
1066 // ptr or a 64 bit method pointer.
1067 LP64_ONLY(ShouldNotReachHere());
1068 __ movptr(as_Address(to_addr), src->as_register());
1069 break;
1070 case T_ADDRESS:
1071 __ movptr(as_Address(to_addr), src->as_register());
1072 break;
1073 case T_INT:
1074 __ movl(as_Address(to_addr), src->as_register());
1075 break;
1076
1077 case T_LONG: {
1078 Register from_lo = src->as_register_lo();
1079 Register from_hi = src->as_register_hi();
1080 #ifdef _LP64
1081 __ movptr(as_Address_lo(to_addr), from_lo);
1082 #else
1083 Register base = to_addr->base()->as_register();
1084 Register index = noreg;
1085 if (to_addr->index()->is_register()) {
1086 index = to_addr->index()->as_register();
1087 }
1088 if (base == from_lo || index == from_lo) {
1089 assert(base != from_hi, "can't be");
1090 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1091 __ movl(as_Address_hi(to_addr), from_hi);
1092 if (patch != NULL) {
1093 patching_epilog(patch, lir_patch_high, base, info);
1094 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1095 patch_code = lir_patch_low;
1096 }
1097 __ movl(as_Address_lo(to_addr), from_lo);
1098 } else {
1099 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1100 __ movl(as_Address_lo(to_addr), from_lo);
1101 if (patch != NULL) {
1102 patching_epilog(patch, lir_patch_low, base, info);
1103 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1104 patch_code = lir_patch_high;
1105 }
1106 __ movl(as_Address_hi(to_addr), from_hi);
1107 }
1108 #endif // _LP64
1109 break;
1110 }
1111
1112 case T_BYTE: // fall through
1113 case T_BOOLEAN: {
1114 Register src_reg = src->as_register();
1115 Address dst_addr = as_Address(to_addr);
1116 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1117 __ movb(dst_addr, src_reg);
1118 break;
1119 }
1120
1121 case T_CHAR: // fall through
1122 case T_SHORT:
1123 __ movw(as_Address(to_addr), src->as_register());
1124 break;
1125
1126 default:
1127 ShouldNotReachHere();
1128 }
1129 if (info != NULL) {
1130 add_debug_info_for_null_check(null_check_here, info);
1131 }
1132
1133 if (patch_code != lir_patch_none) {
1134 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1135 }
1136 }
1137
1138
1139 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1140 assert(src->is_stack(), "should not call otherwise");
1141 assert(dest->is_register(), "should not call otherwise");
1142
1143 if (dest->is_single_cpu()) {
1144 if (type == T_ARRAY || type == T_OBJECT) {
1145 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1146 __ verify_oop(dest->as_register());
1147 } else if (type == T_METADATA) {
1148 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1149 } else {
1150 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1151 }
1152
1153 } else if (dest->is_double_cpu()) {
1154 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1155 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1156 __ movptr(dest->as_register_lo(), src_addr_LO);
1157 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1158
1159 } else if (dest->is_single_xmm()) {
1160 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1161 __ movflt(dest->as_xmm_float_reg(), src_addr);
1162
1163 } else if (dest->is_double_xmm()) {
1164 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1165 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1166
1167 } else if (dest->is_single_fpu()) {
1168 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1169 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1170 __ fld_s(src_addr);
1171
1172 } else if (dest->is_double_fpu()) {
1173 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1174 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1175 __ fld_d(src_addr);
1176
1177 } else {
1178 ShouldNotReachHere();
1179 }
1180 }
1181
1182
1183 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1184 if (src->is_single_stack()) {
1185 if (type == T_OBJECT || type == T_ARRAY) {
1186 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1187 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1188 } else {
1189 #ifndef _LP64
1190 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1191 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1192 #else
1193 //no pushl on 64bits
1194 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1195 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1196 #endif
1197 }
1198
1199 } else if (src->is_double_stack()) {
1200 #ifdef _LP64
1201 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1202 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1203 #else
1204 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1205 // push and pop the part at src + wordSize, adding wordSize for the previous push
1206 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1207 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1208 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1209 #endif // _LP64
1210
1211 } else {
1212 ShouldNotReachHere();
1213 }
1214 }
1215
1216
1217 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1218 assert(src->is_address(), "should not call otherwise");
1219 assert(dest->is_register(), "should not call otherwise");
1220
1221 LIR_Address* addr = src->as_address_ptr();
1222 Address from_addr = as_Address(addr);
1223
1224 if (addr->base()->type() == T_OBJECT) {
1225 __ verify_oop(addr->base()->as_pointer_register());
1226 }
1227
1228 switch (type) {
1229 case T_BOOLEAN: // fall through
1230 case T_BYTE: // fall through
1231 case T_CHAR: // fall through
1232 case T_SHORT:
1233 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1234 // on pre P6 processors we may get partial register stalls
1235 // so blow away the value of to_rinfo before loading a
1236 // partial word into it. Do it here so that it precedes
1237 // the potential patch point below.
1238 __ xorptr(dest->as_register(), dest->as_register());
1239 }
1240 break;
1241 }
1242
1243 PatchingStub* patch = NULL;
1244 if (patch_code != lir_patch_none) {
1245 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1246 assert(from_addr.disp() != 0, "must have");
1247 }
1248 if (info != NULL) {
1249 add_debug_info_for_null_check_here(info);
1250 }
1251
1252 switch (type) {
1253 case T_FLOAT: {
1254 if (dest->is_single_xmm()) {
1255 __ movflt(dest->as_xmm_float_reg(), from_addr);
1256 } else {
1257 assert(dest->is_single_fpu(), "must be");
1258 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1259 __ fld_s(from_addr);
1260 }
1261 break;
1262 }
1263
1264 case T_DOUBLE: {
1265 if (dest->is_double_xmm()) {
1266 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1267 } else {
1268 assert(dest->is_double_fpu(), "must be");
1269 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1270 __ fld_d(from_addr);
1271 }
1272 break;
1273 }
1274
1275 case T_OBJECT: // fall through
1276 case T_ARRAY: // fall through
1277 if (UseCompressedOops && !wide) {
1278 __ movl(dest->as_register(), from_addr);
1279 } else {
1280 __ movptr(dest->as_register(), from_addr);
1281 }
1282 break;
1283
1284 case T_ADDRESS:
1285 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1286 __ movl(dest->as_register(), from_addr);
1287 } else {
1288 __ movptr(dest->as_register(), from_addr);
1289 }
1290 break;
1291 case T_INT:
1292 __ movl(dest->as_register(), from_addr);
1293 break;
1294
1295 case T_LONG: {
1296 Register to_lo = dest->as_register_lo();
1297 Register to_hi = dest->as_register_hi();
1298 #ifdef _LP64
1299 __ movptr(to_lo, as_Address_lo(addr));
1300 #else
1301 Register base = addr->base()->as_register();
1302 Register index = noreg;
1303 if (addr->index()->is_register()) {
1304 index = addr->index()->as_register();
1305 }
1306 if ((base == to_lo && index == to_hi) ||
1307 (base == to_hi && index == to_lo)) {
1308 // addresses with 2 registers are only formed as a result of
1309 // array access so this code will never have to deal with
1310 // patches or null checks.
1311 assert(info == NULL && patch == NULL, "must be");
1312 __ lea(to_hi, as_Address(addr));
1313 __ movl(to_lo, Address(to_hi, 0));
1314 __ movl(to_hi, Address(to_hi, BytesPerWord));
1315 } else if (base == to_lo || index == to_lo) {
1316 assert(base != to_hi, "can't be");
1317 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1318 __ movl(to_hi, as_Address_hi(addr));
1319 if (patch != NULL) {
1320 patching_epilog(patch, lir_patch_high, base, info);
1321 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1322 patch_code = lir_patch_low;
1323 }
1324 __ movl(to_lo, as_Address_lo(addr));
1325 } else {
1326 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1327 __ movl(to_lo, as_Address_lo(addr));
1328 if (patch != NULL) {
1329 patching_epilog(patch, lir_patch_low, base, info);
1330 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1331 patch_code = lir_patch_high;
1332 }
1333 __ movl(to_hi, as_Address_hi(addr));
1334 }
1335 #endif // _LP64
1336 break;
1337 }
1338
1339 case T_BOOLEAN: // fall through
1340 case T_BYTE: {
1341 Register dest_reg = dest->as_register();
1342 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1343 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1344 __ movsbl(dest_reg, from_addr);
1345 } else {
1346 __ movb(dest_reg, from_addr);
1347 __ shll(dest_reg, 24);
1348 __ sarl(dest_reg, 24);
1349 }
1350 break;
1351 }
1352
1353 case T_CHAR: {
1354 Register dest_reg = dest->as_register();
1355 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1356 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1357 __ movzwl(dest_reg, from_addr);
1358 } else {
1359 __ movw(dest_reg, from_addr);
1360 }
1361 break;
1362 }
1363
1364 case T_SHORT: {
1365 Register dest_reg = dest->as_register();
1366 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1367 __ movswl(dest_reg, from_addr);
1368 } else {
1369 __ movw(dest_reg, from_addr);
1370 __ shll(dest_reg, 16);
1371 __ sarl(dest_reg, 16);
1372 }
1373 break;
1374 }
1375
1376 default:
1377 ShouldNotReachHere();
1378 }
1379
1380 if (patch != NULL) {
1381 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1382 }
1383
1384 if (type == T_ARRAY || type == T_OBJECT) {
1385 #ifdef _LP64
1386 if (UseCompressedOops && !wide) {
1387 __ decode_heap_oop(dest->as_register());
1388 }
1389 #endif
1390 __ verify_oop(dest->as_register());
1391 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1392 #ifdef _LP64
1393 if (UseCompressedClassPointers) {
1394 __ decode_klass_not_null(dest->as_register());
1395 }
1396 #endif
1397 }
1398 }
1399
1400
1401 void LIR_Assembler::prefetchr(LIR_Opr src) {
1402 LIR_Address* addr = src->as_address_ptr();
1403 Address from_addr = as_Address(addr);
1404
1405 if (VM_Version::supports_sse()) {
1406 switch (ReadPrefetchInstr) {
1407 case 0:
1408 __ prefetchnta(from_addr); break;
1409 case 1:
1410 __ prefetcht0(from_addr); break;
1411 case 2:
1412 __ prefetcht2(from_addr); break;
1413 default:
1414 ShouldNotReachHere(); break;
1415 }
1416 } else if (VM_Version::supports_3dnow_prefetch()) {
1417 __ prefetchr(from_addr);
1418 }
1419 }
1420
1421
1422 void LIR_Assembler::prefetchw(LIR_Opr src) {
1423 LIR_Address* addr = src->as_address_ptr();
1424 Address from_addr = as_Address(addr);
1425
1426 if (VM_Version::supports_sse()) {
1427 switch (AllocatePrefetchInstr) {
1428 case 0:
1429 __ prefetchnta(from_addr); break;
1430 case 1:
1431 __ prefetcht0(from_addr); break;
1432 case 2:
1433 __ prefetcht2(from_addr); break;
1434 case 3:
1435 __ prefetchw(from_addr); break;
1436 default:
1437 ShouldNotReachHere(); break;
1438 }
1439 } else if (VM_Version::supports_3dnow_prefetch()) {
1440 __ prefetchw(from_addr);
1441 }
1442 }
1443
1444
1445 NEEDS_CLEANUP; // This could be static?
1446 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1447 int elem_size = type2aelembytes(type);
1448 switch (elem_size) {
1449 case 1: return Address::times_1;
1450 case 2: return Address::times_2;
1451 case 4: return Address::times_4;
1452 case 8: return Address::times_8;
1453 }
1454 ShouldNotReachHere();
1455 return Address::no_scale;
1456 }
1457
1458
1459 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1460 switch (op->code()) {
1461 case lir_idiv:
1462 case lir_irem:
1463 arithmetic_idiv(op->code(),
1464 op->in_opr1(),
1465 op->in_opr2(),
1466 op->in_opr3(),
1467 op->result_opr(),
1468 op->info());
1469 break;
1470 default: ShouldNotReachHere(); break;
1471 }
1472 }
1473
1474 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1475 #ifdef ASSERT
1476 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1477 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1478 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1479 #endif
1480
1481 if (op->cond() == lir_cond_always) {
1482 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1483 __ jmp (*(op->label()));
1484 } else {
1485 Assembler::Condition acond = Assembler::zero;
1486 if (op->code() == lir_cond_float_branch) {
1487 assert(op->ublock() != NULL, "must have unordered successor");
1488 __ jcc(Assembler::parity, *(op->ublock()->label()));
1489 switch(op->cond()) {
1490 case lir_cond_equal: acond = Assembler::equal; break;
1491 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1492 case lir_cond_less: acond = Assembler::below; break;
1493 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1494 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1495 case lir_cond_greater: acond = Assembler::above; break;
1496 default: ShouldNotReachHere();
1497 }
1498 } else {
1499 switch (op->cond()) {
1500 case lir_cond_equal: acond = Assembler::equal; break;
1501 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1502 case lir_cond_less: acond = Assembler::less; break;
1503 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1504 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1505 case lir_cond_greater: acond = Assembler::greater; break;
1506 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1507 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1508 default: ShouldNotReachHere();
1509 }
1510 }
1511 __ jcc(acond,*(op->label()));
1512 }
1513 }
1514
1515 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1516 LIR_Opr src = op->in_opr();
1517 LIR_Opr dest = op->result_opr();
1518
1519 switch (op->bytecode()) {
1520 case Bytecodes::_i2l:
1521 #ifdef _LP64
1522 __ movl2ptr(dest->as_register_lo(), src->as_register());
1523 #else
1524 move_regs(src->as_register(), dest->as_register_lo());
1525 move_regs(src->as_register(), dest->as_register_hi());
1526 __ sarl(dest->as_register_hi(), 31);
1527 #endif // LP64
1528 break;
1529
1530 case Bytecodes::_l2i:
1531 #ifdef _LP64
1532 __ movl(dest->as_register(), src->as_register_lo());
1533 #else
1534 move_regs(src->as_register_lo(), dest->as_register());
1535 #endif
1536 break;
1537
1538 case Bytecodes::_i2b:
1539 move_regs(src->as_register(), dest->as_register());
1540 __ sign_extend_byte(dest->as_register());
1541 break;
1542
1543 case Bytecodes::_i2c:
1544 move_regs(src->as_register(), dest->as_register());
1545 __ andl(dest->as_register(), 0xFFFF);
1546 break;
1547
1548 case Bytecodes::_i2s:
1549 move_regs(src->as_register(), dest->as_register());
1550 __ sign_extend_short(dest->as_register());
1551 break;
1552
1553
1554 case Bytecodes::_f2d:
1555 case Bytecodes::_d2f:
1556 if (dest->is_single_xmm()) {
1557 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1558 } else if (dest->is_double_xmm()) {
1559 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1560 } else {
1561 assert(src->fpu() == dest->fpu(), "register must be equal");
1562 // do nothing (float result is rounded later through spilling)
1563 }
1564 break;
1565
1566 case Bytecodes::_i2f:
1567 case Bytecodes::_i2d:
1568 if (dest->is_single_xmm()) {
1569 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1570 } else if (dest->is_double_xmm()) {
1571 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1572 } else {
1573 assert(dest->fpu() == 0, "result must be on TOS");
1574 __ movl(Address(rsp, 0), src->as_register());
1575 __ fild_s(Address(rsp, 0));
1576 }
1577 break;
1578
1579 case Bytecodes::_f2i:
1580 case Bytecodes::_d2i:
1581 if (src->is_single_xmm()) {
1582 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1583 } else if (src->is_double_xmm()) {
1584 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1585 } else {
1586 assert(src->fpu() == 0, "input must be on TOS");
1587 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1588 __ fist_s(Address(rsp, 0));
1589 __ movl(dest->as_register(), Address(rsp, 0));
1590 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1591 }
1592
1593 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1594 assert(op->stub() != NULL, "stub required");
1595 __ cmpl(dest->as_register(), 0x80000000);
1596 __ jcc(Assembler::equal, *op->stub()->entry());
1597 __ bind(*op->stub()->continuation());
1598 break;
1599
1600 case Bytecodes::_l2f:
1601 case Bytecodes::_l2d:
1602 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1603 assert(dest->fpu() == 0, "result must be on TOS");
1604
1605 __ movptr(Address(rsp, 0), src->as_register_lo());
1606 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1607 __ fild_d(Address(rsp, 0));
1608 // float result is rounded later through spilling
1609 break;
1610
1611 case Bytecodes::_f2l:
1612 case Bytecodes::_d2l:
1613 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1614 assert(src->fpu() == 0, "input must be on TOS");
1615 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1616
1617 // instruction sequence too long to inline it here
1618 {
1619 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1620 }
1621 break;
1622
1623 default: ShouldNotReachHere();
1624 }
1625 }
1626
1627 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1628 if (op->init_check()) {
1629 __ cmpb(Address(op->klass()->as_register(),
1630 InstanceKlass::init_state_offset()),
1631 InstanceKlass::fully_initialized);
1632 add_debug_info_for_null_check_here(op->stub()->info());
1633 __ jcc(Assembler::notEqual, *op->stub()->entry());
1634 }
1635 __ allocate_object(op->obj()->as_register(),
1636 op->tmp1()->as_register(),
1637 op->tmp2()->as_register(),
1638 op->header_size(),
1639 op->object_size(),
1640 op->klass()->as_register(),
1641 *op->stub()->entry());
1642 __ bind(*op->stub()->continuation());
1643 }
1644
1645 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1646 Register len = op->len()->as_register();
1647 LP64_ONLY( __ movslq(len, len); )
1648
1649 if (UseSlowPath ||
1650 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1651 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1652 __ jmp(*op->stub()->entry());
1653 } else {
1654 Register tmp1 = op->tmp1()->as_register();
1655 Register tmp2 = op->tmp2()->as_register();
1656 Register tmp3 = op->tmp3()->as_register();
1657 if (len == tmp1) {
1658 tmp1 = tmp3;
1659 } else if (len == tmp2) {
1660 tmp2 = tmp3;
1661 } else if (len == tmp3) {
1662 // everything is ok
1663 } else {
1664 __ mov(tmp3, len);
1665 }
1666 __ allocate_array(op->obj()->as_register(),
1667 len,
1668 tmp1,
1669 tmp2,
1670 arrayOopDesc::header_size(op->type()),
1671 array_element_size(op->type()),
1672 op->klass()->as_register(),
1673 *op->stub()->entry());
1674 }
1675 __ bind(*op->stub()->continuation());
1676 }
1677
1678 void LIR_Assembler::type_profile_helper(Register mdo,
1679 ciMethodData *md, ciProfileData *data,
1680 Register recv, Label* update_done) {
1681 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1682 Label next_test;
1683 // See if the receiver is receiver[n].
1684 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1685 __ jccb(Assembler::notEqual, next_test);
1686 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1687 __ addptr(data_addr, DataLayout::counter_increment);
1688 __ jmp(*update_done);
1689 __ bind(next_test);
1690 }
1691
1692 // Didn't find receiver; find next empty slot and fill it in
1693 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1694 Label next_test;
1695 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1696 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1697 __ jccb(Assembler::notEqual, next_test);
1698 __ movptr(recv_addr, recv);
1699 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1700 __ jmp(*update_done);
1701 __ bind(next_test);
1702 }
1703 }
1704
1705 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1706 // we always need a stub for the failure case.
1707 CodeStub* stub = op->stub();
1708 Register obj = op->object()->as_register();
1709 Register k_RInfo = op->tmp1()->as_register();
1710 Register klass_RInfo = op->tmp2()->as_register();
1711 Register dst = op->result_opr()->as_register();
1712 ciKlass* k = op->klass();
1713 Register Rtmp1 = noreg;
1714
1715 // check if it needs to be profiled
1716 ciMethodData* md;
1717 ciProfileData* data;
1718
1719 if (op->should_profile()) {
1720 ciMethod* method = op->profiled_method();
1721 assert(method != NULL, "Should have method");
1722 int bci = op->profiled_bci();
1723 md = method->method_data_or_null();
1724 assert(md != NULL, "Sanity");
1725 data = md->bci_to_data(bci);
1726 assert(data != NULL, "need data for type check");
1727 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1728 }
1729 Label profile_cast_success, profile_cast_failure;
1730 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1731 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1732
1733 if (obj == k_RInfo) {
1734 k_RInfo = dst;
1735 } else if (obj == klass_RInfo) {
1736 klass_RInfo = dst;
1737 }
1738 if (k->is_loaded() && !UseCompressedClassPointers) {
1739 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1740 } else {
1741 Rtmp1 = op->tmp3()->as_register();
1742 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1743 }
1744
1745 assert_different_registers(obj, k_RInfo, klass_RInfo);
1746
1747 __ cmpptr(obj, (int32_t)NULL_WORD);
1748 if (op->should_profile()) {
1749 Label not_null;
1750 __ jccb(Assembler::notEqual, not_null);
1751 // Object is null; update MDO and exit
1752 Register mdo = klass_RInfo;
1753 __ mov_metadata(mdo, md->constant_encoding());
1754 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1755 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1756 __ orl(data_addr, header_bits);
1757 __ jmp(*obj_is_null);
1758 __ bind(not_null);
1759 } else {
1760 __ jcc(Assembler::equal, *obj_is_null);
1761 }
1762
1763 if (!k->is_loaded()) {
1764 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1765 } else {
1766 #ifdef _LP64
1767 __ mov_metadata(k_RInfo, k->constant_encoding());
1768 #endif // _LP64
1769 }
1770 __ verify_oop(obj);
1771
1772 if (op->fast_check()) {
1773 // get object class
1774 // not a safepoint as obj null check happens earlier
1775 #ifdef _LP64
1776 if (UseCompressedClassPointers) {
1777 __ load_klass(Rtmp1, obj);
1778 __ cmpptr(k_RInfo, Rtmp1);
1779 } else {
1780 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1781 }
1782 #else
1783 if (k->is_loaded()) {
1784 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1785 } else {
1786 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1787 }
1788 #endif
1789 __ jcc(Assembler::notEqual, *failure_target);
1790 // successful cast, fall through to profile or jump
1791 } else {
1792 // get object class
1793 // not a safepoint as obj null check happens earlier
1794 __ load_klass(klass_RInfo, obj);
1795 if (k->is_loaded()) {
1796 // See if we get an immediate positive hit
1797 #ifdef _LP64
1798 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1799 #else
1800 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1801 #endif // _LP64
1802 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1803 __ jcc(Assembler::notEqual, *failure_target);
1804 // successful cast, fall through to profile or jump
1805 } else {
1806 // See if we get an immediate positive hit
1807 __ jcc(Assembler::equal, *success_target);
1808 // check for self
1809 #ifdef _LP64
1810 __ cmpptr(klass_RInfo, k_RInfo);
1811 #else
1812 __ cmpklass(klass_RInfo, k->constant_encoding());
1813 #endif // _LP64
1814 __ jcc(Assembler::equal, *success_target);
1815
1816 __ push(klass_RInfo);
1817 #ifdef _LP64
1818 __ push(k_RInfo);
1819 #else
1820 __ pushklass(k->constant_encoding());
1821 #endif // _LP64
1822 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1823 __ pop(klass_RInfo);
1824 __ pop(klass_RInfo);
1825 // result is a boolean
1826 __ cmpl(klass_RInfo, 0);
1827 __ jcc(Assembler::equal, *failure_target);
1828 // successful cast, fall through to profile or jump
1829 }
1830 } else {
1831 // perform the fast part of the checking logic
1832 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1833 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1834 __ push(klass_RInfo);
1835 __ push(k_RInfo);
1836 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1837 __ pop(klass_RInfo);
1838 __ pop(k_RInfo);
1839 // result is a boolean
1840 __ cmpl(k_RInfo, 0);
1841 __ jcc(Assembler::equal, *failure_target);
1842 // successful cast, fall through to profile or jump
1843 }
1844 }
1845 if (op->should_profile()) {
1846 Register mdo = klass_RInfo, recv = k_RInfo;
1847 __ bind(profile_cast_success);
1848 __ mov_metadata(mdo, md->constant_encoding());
1849 __ load_klass(recv, obj);
1850 Label update_done;
1851 type_profile_helper(mdo, md, data, recv, success);
1852 __ jmp(*success);
1853
1854 __ bind(profile_cast_failure);
1855 __ mov_metadata(mdo, md->constant_encoding());
1856 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1857 __ subptr(counter_addr, DataLayout::counter_increment);
1858 __ jmp(*failure);
1859 }
1860 __ jmp(*success);
1861 }
1862
1863
1864 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1865 LIR_Code code = op->code();
1866 if (code == lir_store_check) {
1867 Register value = op->object()->as_register();
1868 Register array = op->array()->as_register();
1869 Register k_RInfo = op->tmp1()->as_register();
1870 Register klass_RInfo = op->tmp2()->as_register();
1871 Register Rtmp1 = op->tmp3()->as_register();
1872
1873 CodeStub* stub = op->stub();
1874
1875 // check if it needs to be profiled
1876 ciMethodData* md;
1877 ciProfileData* data;
1878
1879 if (op->should_profile()) {
1880 ciMethod* method = op->profiled_method();
1881 assert(method != NULL, "Should have method");
1882 int bci = op->profiled_bci();
1883 md = method->method_data_or_null();
1884 assert(md != NULL, "Sanity");
1885 data = md->bci_to_data(bci);
1886 assert(data != NULL, "need data for type check");
1887 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1888 }
1889 Label profile_cast_success, profile_cast_failure, done;
1890 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1891 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1892
1893 __ cmpptr(value, (int32_t)NULL_WORD);
1894 if (op->should_profile()) {
1895 Label not_null;
1896 __ jccb(Assembler::notEqual, not_null);
1897 // Object is null; update MDO and exit
1898 Register mdo = klass_RInfo;
1899 __ mov_metadata(mdo, md->constant_encoding());
1900 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1901 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1902 __ orl(data_addr, header_bits);
1903 __ jmp(done);
1904 __ bind(not_null);
1905 } else {
1906 __ jcc(Assembler::equal, done);
1907 }
1908
1909 add_debug_info_for_null_check_here(op->info_for_exception());
1910 __ load_klass(k_RInfo, array);
1911 __ load_klass(klass_RInfo, value);
1912
1913 // get instance klass (it's already uncompressed)
1914 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1915 // perform the fast part of the checking logic
1916 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1917 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1918 __ push(klass_RInfo);
1919 __ push(k_RInfo);
1920 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1921 __ pop(klass_RInfo);
1922 __ pop(k_RInfo);
1923 // result is a boolean
1924 __ cmpl(k_RInfo, 0);
1925 __ jcc(Assembler::equal, *failure_target);
1926 // fall through to the success case
1927
1928 if (op->should_profile()) {
1929 Register mdo = klass_RInfo, recv = k_RInfo;
1930 __ bind(profile_cast_success);
1931 __ mov_metadata(mdo, md->constant_encoding());
1932 __ load_klass(recv, value);
1933 Label update_done;
1934 type_profile_helper(mdo, md, data, recv, &done);
1935 __ jmpb(done);
1936
1937 __ bind(profile_cast_failure);
1938 __ mov_metadata(mdo, md->constant_encoding());
1939 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1940 __ subptr(counter_addr, DataLayout::counter_increment);
1941 __ jmp(*stub->entry());
1942 }
1943
1944 __ bind(done);
1945 } else
1946 if (code == lir_checkcast) {
1947 Register obj = op->object()->as_register();
1948 Register dst = op->result_opr()->as_register();
1949 Label success;
1950 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1951 __ bind(success);
1952 if (dst != obj) {
1953 __ mov(dst, obj);
1954 }
1955 } else
1956 if (code == lir_instanceof) {
1957 Register obj = op->object()->as_register();
1958 Register dst = op->result_opr()->as_register();
1959 Label success, failure, done;
1960 emit_typecheck_helper(op, &success, &failure, &failure);
1961 __ bind(failure);
1962 __ xorptr(dst, dst);
1963 __ jmpb(done);
1964 __ bind(success);
1965 __ movptr(dst, 1);
1966 __ bind(done);
1967 } else {
1968 ShouldNotReachHere();
1969 }
1970
1971 }
1972
1973
1974 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1975 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1976 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1977 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1978 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1979 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1980 Register addr = op->addr()->as_register();
1981 if (os::is_MP()) {
1982 __ lock();
1983 }
1984 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1985
1986 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1987 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1988 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1989 Register newval = op->new_value()->as_register();
1990 Register cmpval = op->cmp_value()->as_register();
1991 assert(cmpval == rax, "wrong register");
1992 assert(newval != NULL, "new val must be register");
1993 assert(cmpval != newval, "cmp and new values must be in different registers");
1994 assert(cmpval != addr, "cmp and addr must be in different registers");
1995 assert(newval != addr, "new value and addr must be in different registers");
1996
1997 if ( op->code() == lir_cas_obj) {
1998 #ifdef _LP64
1999 if (UseCompressedOops) {
2000 __ encode_heap_oop(cmpval);
2001 __ mov(rscratch1, newval);
2002 __ encode_heap_oop(rscratch1);
2003 if (os::is_MP()) {
2004 __ lock();
2005 }
2006 // cmpval (rax) is implicitly used by this instruction
2007 __ cmpxchgl(rscratch1, Address(addr, 0));
2008 } else
2009 #endif
2010 {
2011 if (os::is_MP()) {
2012 __ lock();
2013 }
2014 __ cmpxchgptr(newval, Address(addr, 0));
2015 }
2016 } else {
2017 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2018 if (os::is_MP()) {
2019 __ lock();
2020 }
2021 __ cmpxchgl(newval, Address(addr, 0));
2022 }
2023 #ifdef _LP64
2024 } else if (op->code() == lir_cas_long) {
2025 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2026 Register newval = op->new_value()->as_register_lo();
2027 Register cmpval = op->cmp_value()->as_register_lo();
2028 assert(cmpval == rax, "wrong register");
2029 assert(newval != NULL, "new val must be register");
2030 assert(cmpval != newval, "cmp and new values must be in different registers");
2031 assert(cmpval != addr, "cmp and addr must be in different registers");
2032 assert(newval != addr, "new value and addr must be in different registers");
2033 if (os::is_MP()) {
2034 __ lock();
2035 }
2036 __ cmpxchgq(newval, Address(addr, 0));
2037 #endif // _LP64
2038 } else {
2039 Unimplemented();
2040 }
2041 }
2042
2043 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2044 Assembler::Condition acond, ncond;
2045 switch (condition) {
2046 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2047 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2048 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2049 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2050 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2051 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2052 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2053 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2054 default: ShouldNotReachHere();
2055 }
2056
2057 if (opr1->is_cpu_register()) {
2058 reg2reg(opr1, result);
2059 } else if (opr1->is_stack()) {
2060 stack2reg(opr1, result, result->type());
2061 } else if (opr1->is_constant()) {
2062 const2reg(opr1, result, lir_patch_none, NULL);
2063 } else {
2064 ShouldNotReachHere();
2065 }
2066
2067 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2068 // optimized version that does not require a branch
2069 if (opr2->is_single_cpu()) {
2070 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2071 __ cmov(ncond, result->as_register(), opr2->as_register());
2072 } else if (opr2->is_double_cpu()) {
2073 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2074 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2075 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2076 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2077 } else if (opr2->is_single_stack()) {
2078 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2079 } else if (opr2->is_double_stack()) {
2080 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2081 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2082 } else {
2083 ShouldNotReachHere();
2084 }
2085
2086 } else {
2087 Label skip;
2088 __ jcc (acond, skip);
2089 if (opr2->is_cpu_register()) {
2090 reg2reg(opr2, result);
2091 } else if (opr2->is_stack()) {
2092 stack2reg(opr2, result, result->type());
2093 } else if (opr2->is_constant()) {
2094 const2reg(opr2, result, lir_patch_none, NULL);
2095 } else {
2096 ShouldNotReachHere();
2097 }
2098 __ bind(skip);
2099 }
2100 }
2101
2102
2103 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2104 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2105
2106 if (left->is_single_cpu()) {
2107 assert(left == dest, "left and dest must be equal");
2108 Register lreg = left->as_register();
2109
2110 if (right->is_single_cpu()) {
2111 // cpu register - cpu register
2112 Register rreg = right->as_register();
2113 switch (code) {
2114 case lir_add: __ addl (lreg, rreg); break;
2115 case lir_sub: __ subl (lreg, rreg); break;
2116 case lir_mul: __ imull(lreg, rreg); break;
2117 default: ShouldNotReachHere();
2118 }
2119
2120 } else if (right->is_stack()) {
2121 // cpu register - stack
2122 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2123 switch (code) {
2124 case lir_add: __ addl(lreg, raddr); break;
2125 case lir_sub: __ subl(lreg, raddr); break;
2126 default: ShouldNotReachHere();
2127 }
2128
2129 } else if (right->is_constant()) {
2130 // cpu register - constant
2131 jint c = right->as_constant_ptr()->as_jint();
2132 switch (code) {
2133 case lir_add: {
2134 __ incrementl(lreg, c);
2135 break;
2136 }
2137 case lir_sub: {
2138 __ decrementl(lreg, c);
2139 break;
2140 }
2141 default: ShouldNotReachHere();
2142 }
2143
2144 } else {
2145 ShouldNotReachHere();
2146 }
2147
2148 } else if (left->is_double_cpu()) {
2149 assert(left == dest, "left and dest must be equal");
2150 Register lreg_lo = left->as_register_lo();
2151 Register lreg_hi = left->as_register_hi();
2152
2153 if (right->is_double_cpu()) {
2154 // cpu register - cpu register
2155 Register rreg_lo = right->as_register_lo();
2156 Register rreg_hi = right->as_register_hi();
2157 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2158 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2159 switch (code) {
2160 case lir_add:
2161 __ addptr(lreg_lo, rreg_lo);
2162 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2163 break;
2164 case lir_sub:
2165 __ subptr(lreg_lo, rreg_lo);
2166 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2167 break;
2168 case lir_mul:
2169 #ifdef _LP64
2170 __ imulq(lreg_lo, rreg_lo);
2171 #else
2172 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2173 __ imull(lreg_hi, rreg_lo);
2174 __ imull(rreg_hi, lreg_lo);
2175 __ addl (rreg_hi, lreg_hi);
2176 __ mull (rreg_lo);
2177 __ addl (lreg_hi, rreg_hi);
2178 #endif // _LP64
2179 break;
2180 default:
2181 ShouldNotReachHere();
2182 }
2183
2184 } else if (right->is_constant()) {
2185 // cpu register - constant
2186 #ifdef _LP64
2187 jlong c = right->as_constant_ptr()->as_jlong_bits();
2188 __ movptr(r10, (intptr_t) c);
2189 switch (code) {
2190 case lir_add:
2191 __ addptr(lreg_lo, r10);
2192 break;
2193 case lir_sub:
2194 __ subptr(lreg_lo, r10);
2195 break;
2196 default:
2197 ShouldNotReachHere();
2198 }
2199 #else
2200 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2201 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2202 switch (code) {
2203 case lir_add:
2204 __ addptr(lreg_lo, c_lo);
2205 __ adcl(lreg_hi, c_hi);
2206 break;
2207 case lir_sub:
2208 __ subptr(lreg_lo, c_lo);
2209 __ sbbl(lreg_hi, c_hi);
2210 break;
2211 default:
2212 ShouldNotReachHere();
2213 }
2214 #endif // _LP64
2215
2216 } else {
2217 ShouldNotReachHere();
2218 }
2219
2220 } else if (left->is_single_xmm()) {
2221 assert(left == dest, "left and dest must be equal");
2222 XMMRegister lreg = left->as_xmm_float_reg();
2223
2224 if (right->is_single_xmm()) {
2225 XMMRegister rreg = right->as_xmm_float_reg();
2226 switch (code) {
2227 case lir_add: __ addss(lreg, rreg); break;
2228 case lir_sub: __ subss(lreg, rreg); break;
2229 case lir_mul_strictfp: // fall through
2230 case lir_mul: __ mulss(lreg, rreg); break;
2231 case lir_div_strictfp: // fall through
2232 case lir_div: __ divss(lreg, rreg); break;
2233 default: ShouldNotReachHere();
2234 }
2235 } else {
2236 Address raddr;
2237 if (right->is_single_stack()) {
2238 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2239 } else if (right->is_constant()) {
2240 // hack for now
2241 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2242 } else {
2243 ShouldNotReachHere();
2244 }
2245 switch (code) {
2246 case lir_add: __ addss(lreg, raddr); break;
2247 case lir_sub: __ subss(lreg, raddr); break;
2248 case lir_mul_strictfp: // fall through
2249 case lir_mul: __ mulss(lreg, raddr); break;
2250 case lir_div_strictfp: // fall through
2251 case lir_div: __ divss(lreg, raddr); break;
2252 default: ShouldNotReachHere();
2253 }
2254 }
2255
2256 } else if (left->is_double_xmm()) {
2257 assert(left == dest, "left and dest must be equal");
2258
2259 XMMRegister lreg = left->as_xmm_double_reg();
2260 if (right->is_double_xmm()) {
2261 XMMRegister rreg = right->as_xmm_double_reg();
2262 switch (code) {
2263 case lir_add: __ addsd(lreg, rreg); break;
2264 case lir_sub: __ subsd(lreg, rreg); break;
2265 case lir_mul_strictfp: // fall through
2266 case lir_mul: __ mulsd(lreg, rreg); break;
2267 case lir_div_strictfp: // fall through
2268 case lir_div: __ divsd(lreg, rreg); break;
2269 default: ShouldNotReachHere();
2270 }
2271 } else {
2272 Address raddr;
2273 if (right->is_double_stack()) {
2274 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2275 } else if (right->is_constant()) {
2276 // hack for now
2277 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2278 } else {
2279 ShouldNotReachHere();
2280 }
2281 switch (code) {
2282 case lir_add: __ addsd(lreg, raddr); break;
2283 case lir_sub: __ subsd(lreg, raddr); break;
2284 case lir_mul_strictfp: // fall through
2285 case lir_mul: __ mulsd(lreg, raddr); break;
2286 case lir_div_strictfp: // fall through
2287 case lir_div: __ divsd(lreg, raddr); break;
2288 default: ShouldNotReachHere();
2289 }
2290 }
2291
2292 } else if (left->is_single_fpu()) {
2293 assert(dest->is_single_fpu(), "fpu stack allocation required");
2294
2295 if (right->is_single_fpu()) {
2296 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2297
2298 } else {
2299 assert(left->fpu_regnr() == 0, "left must be on TOS");
2300 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2301
2302 Address raddr;
2303 if (right->is_single_stack()) {
2304 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2305 } else if (right->is_constant()) {
2306 address const_addr = float_constant(right->as_jfloat());
2307 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2308 // hack for now
2309 raddr = __ as_Address(InternalAddress(const_addr));
2310 } else {
2311 ShouldNotReachHere();
2312 }
2313
2314 switch (code) {
2315 case lir_add: __ fadd_s(raddr); break;
2316 case lir_sub: __ fsub_s(raddr); break;
2317 case lir_mul_strictfp: // fall through
2318 case lir_mul: __ fmul_s(raddr); break;
2319 case lir_div_strictfp: // fall through
2320 case lir_div: __ fdiv_s(raddr); break;
2321 default: ShouldNotReachHere();
2322 }
2323 }
2324
2325 } else if (left->is_double_fpu()) {
2326 assert(dest->is_double_fpu(), "fpu stack allocation required");
2327
2328 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2329 // Double values require special handling for strictfp mul/div on x86
2330 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2331 __ fmulp(left->fpu_regnrLo() + 1);
2332 }
2333
2334 if (right->is_double_fpu()) {
2335 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2336
2337 } else {
2338 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2339 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2340
2341 Address raddr;
2342 if (right->is_double_stack()) {
2343 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2344 } else if (right->is_constant()) {
2345 // hack for now
2346 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2347 } else {
2348 ShouldNotReachHere();
2349 }
2350
2351 switch (code) {
2352 case lir_add: __ fadd_d(raddr); break;
2353 case lir_sub: __ fsub_d(raddr); break;
2354 case lir_mul_strictfp: // fall through
2355 case lir_mul: __ fmul_d(raddr); break;
2356 case lir_div_strictfp: // fall through
2357 case lir_div: __ fdiv_d(raddr); break;
2358 default: ShouldNotReachHere();
2359 }
2360 }
2361
2362 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2363 // Double values require special handling for strictfp mul/div on x86
2364 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2365 __ fmulp(dest->fpu_regnrLo() + 1);
2366 }
2367
2368 } else if (left->is_single_stack() || left->is_address()) {
2369 assert(left == dest, "left and dest must be equal");
2370
2371 Address laddr;
2372 if (left->is_single_stack()) {
2373 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2374 } else if (left->is_address()) {
2375 laddr = as_Address(left->as_address_ptr());
2376 } else {
2377 ShouldNotReachHere();
2378 }
2379
2380 if (right->is_single_cpu()) {
2381 Register rreg = right->as_register();
2382 switch (code) {
2383 case lir_add: __ addl(laddr, rreg); break;
2384 case lir_sub: __ subl(laddr, rreg); break;
2385 default: ShouldNotReachHere();
2386 }
2387 } else if (right->is_constant()) {
2388 jint c = right->as_constant_ptr()->as_jint();
2389 switch (code) {
2390 case lir_add: {
2391 __ incrementl(laddr, c);
2392 break;
2393 }
2394 case lir_sub: {
2395 __ decrementl(laddr, c);
2396 break;
2397 }
2398 default: ShouldNotReachHere();
2399 }
2400 } else {
2401 ShouldNotReachHere();
2402 }
2403
2404 } else {
2405 ShouldNotReachHere();
2406 }
2407 }
2408
2409 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2410 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2411 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2412 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2413
2414 bool left_is_tos = (left_index == 0);
2415 bool dest_is_tos = (dest_index == 0);
2416 int non_tos_index = (left_is_tos ? right_index : left_index);
2417
2418 switch (code) {
2419 case lir_add:
2420 if (pop_fpu_stack) __ faddp(non_tos_index);
2421 else if (dest_is_tos) __ fadd (non_tos_index);
2422 else __ fadda(non_tos_index);
2423 break;
2424
2425 case lir_sub:
2426 if (left_is_tos) {
2427 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2428 else if (dest_is_tos) __ fsub (non_tos_index);
2429 else __ fsubra(non_tos_index);
2430 } else {
2431 if (pop_fpu_stack) __ fsubp (non_tos_index);
2432 else if (dest_is_tos) __ fsubr (non_tos_index);
2433 else __ fsuba (non_tos_index);
2434 }
2435 break;
2436
2437 case lir_mul_strictfp: // fall through
2438 case lir_mul:
2439 if (pop_fpu_stack) __ fmulp(non_tos_index);
2440 else if (dest_is_tos) __ fmul (non_tos_index);
2441 else __ fmula(non_tos_index);
2442 break;
2443
2444 case lir_div_strictfp: // fall through
2445 case lir_div:
2446 if (left_is_tos) {
2447 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2448 else if (dest_is_tos) __ fdiv (non_tos_index);
2449 else __ fdivra(non_tos_index);
2450 } else {
2451 if (pop_fpu_stack) __ fdivp (non_tos_index);
2452 else if (dest_is_tos) __ fdivr (non_tos_index);
2453 else __ fdiva (non_tos_index);
2454 }
2455 break;
2456
2457 case lir_rem:
2458 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2459 __ fremr(noreg);
2460 break;
2461
2462 default:
2463 ShouldNotReachHere();
2464 }
2465 }
2466
2467
2468 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2469 if (value->is_double_xmm()) {
2470 switch(code) {
2471 case lir_abs :
2472 {
2473 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2474 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2475 }
2476 __ andpd(dest->as_xmm_double_reg(),
2477 ExternalAddress((address)double_signmask_pool));
2478 }
2479 break;
2480
2481 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2482 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2483 default : ShouldNotReachHere();
2484 }
2485
2486 } else if (value->is_double_fpu()) {
2487 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2488 switch(code) {
2489 case lir_log : __ flog() ; break;
2490 case lir_log10 : __ flog10() ; break;
2491 case lir_abs : __ fabs() ; break;
2492 case lir_sqrt : __ fsqrt(); break;
2493 case lir_sin :
2494 // Should consider not saving rbx, if not necessary
2495 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2496 break;
2497 case lir_cos :
2498 // Should consider not saving rbx, if not necessary
2499 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2500 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2501 break;
2502 case lir_tan :
2503 // Should consider not saving rbx, if not necessary
2504 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2505 break;
2506 case lir_exp :
2507 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2508 break;
2509 case lir_pow :
2510 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2511 break;
2512 default : ShouldNotReachHere();
2513 }
2514 } else {
2515 Unimplemented();
2516 }
2517 }
2518
2519 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2520 // assert(left->destroys_register(), "check");
2521 if (left->is_single_cpu()) {
2522 Register reg = left->as_register();
2523 if (right->is_constant()) {
2524 int val = right->as_constant_ptr()->as_jint();
2525 switch (code) {
2526 case lir_logic_and: __ andl (reg, val); break;
2527 case lir_logic_or: __ orl (reg, val); break;
2528 case lir_logic_xor: __ xorl (reg, val); break;
2529 default: ShouldNotReachHere();
2530 }
2531 } else if (right->is_stack()) {
2532 // added support for stack operands
2533 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2534 switch (code) {
2535 case lir_logic_and: __ andl (reg, raddr); break;
2536 case lir_logic_or: __ orl (reg, raddr); break;
2537 case lir_logic_xor: __ xorl (reg, raddr); break;
2538 default: ShouldNotReachHere();
2539 }
2540 } else {
2541 Register rright = right->as_register();
2542 switch (code) {
2543 case lir_logic_and: __ andptr (reg, rright); break;
2544 case lir_logic_or : __ orptr (reg, rright); break;
2545 case lir_logic_xor: __ xorptr (reg, rright); break;
2546 default: ShouldNotReachHere();
2547 }
2548 }
2549 move_regs(reg, dst->as_register());
2550 } else {
2551 Register l_lo = left->as_register_lo();
2552 Register l_hi = left->as_register_hi();
2553 if (right->is_constant()) {
2554 #ifdef _LP64
2555 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2556 switch (code) {
2557 case lir_logic_and:
2558 __ andq(l_lo, rscratch1);
2559 break;
2560 case lir_logic_or:
2561 __ orq(l_lo, rscratch1);
2562 break;
2563 case lir_logic_xor:
2564 __ xorq(l_lo, rscratch1);
2565 break;
2566 default: ShouldNotReachHere();
2567 }
2568 #else
2569 int r_lo = right->as_constant_ptr()->as_jint_lo();
2570 int r_hi = right->as_constant_ptr()->as_jint_hi();
2571 switch (code) {
2572 case lir_logic_and:
2573 __ andl(l_lo, r_lo);
2574 __ andl(l_hi, r_hi);
2575 break;
2576 case lir_logic_or:
2577 __ orl(l_lo, r_lo);
2578 __ orl(l_hi, r_hi);
2579 break;
2580 case lir_logic_xor:
2581 __ xorl(l_lo, r_lo);
2582 __ xorl(l_hi, r_hi);
2583 break;
2584 default: ShouldNotReachHere();
2585 }
2586 #endif // _LP64
2587 } else {
2588 #ifdef _LP64
2589 Register r_lo;
2590 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2591 r_lo = right->as_register();
2592 } else {
2593 r_lo = right->as_register_lo();
2594 }
2595 #else
2596 Register r_lo = right->as_register_lo();
2597 Register r_hi = right->as_register_hi();
2598 assert(l_lo != r_hi, "overwriting registers");
2599 #endif
2600 switch (code) {
2601 case lir_logic_and:
2602 __ andptr(l_lo, r_lo);
2603 NOT_LP64(__ andptr(l_hi, r_hi);)
2604 break;
2605 case lir_logic_or:
2606 __ orptr(l_lo, r_lo);
2607 NOT_LP64(__ orptr(l_hi, r_hi);)
2608 break;
2609 case lir_logic_xor:
2610 __ xorptr(l_lo, r_lo);
2611 NOT_LP64(__ xorptr(l_hi, r_hi);)
2612 break;
2613 default: ShouldNotReachHere();
2614 }
2615 }
2616
2617 Register dst_lo = dst->as_register_lo();
2618 Register dst_hi = dst->as_register_hi();
2619
2620 #ifdef _LP64
2621 move_regs(l_lo, dst_lo);
2622 #else
2623 if (dst_lo == l_hi) {
2624 assert(dst_hi != l_lo, "overwriting registers");
2625 move_regs(l_hi, dst_hi);
2626 move_regs(l_lo, dst_lo);
2627 } else {
2628 assert(dst_lo != l_hi, "overwriting registers");
2629 move_regs(l_lo, dst_lo);
2630 move_regs(l_hi, dst_hi);
2631 }
2632 #endif // _LP64
2633 }
2634 }
2635
2636
2637 // we assume that rax, and rdx can be overwritten
2638 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2639
2640 assert(left->is_single_cpu(), "left must be register");
2641 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2642 assert(result->is_single_cpu(), "result must be register");
2643
2644 // assert(left->destroys_register(), "check");
2645 // assert(right->destroys_register(), "check");
2646
2647 Register lreg = left->as_register();
2648 Register dreg = result->as_register();
2649
2650 if (right->is_constant()) {
2651 int divisor = right->as_constant_ptr()->as_jint();
2652 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2653 if (code == lir_idiv) {
2654 assert(lreg == rax, "must be rax,");
2655 assert(temp->as_register() == rdx, "tmp register must be rdx");
2656 __ cdql(); // sign extend into rdx:rax
2657 if (divisor == 2) {
2658 __ subl(lreg, rdx);
2659 } else {
2660 __ andl(rdx, divisor - 1);
2661 __ addl(lreg, rdx);
2662 }
2663 __ sarl(lreg, log2_intptr(divisor));
2664 move_regs(lreg, dreg);
2665 } else if (code == lir_irem) {
2666 Label done;
2667 __ mov(dreg, lreg);
2668 __ andl(dreg, 0x80000000 | (divisor - 1));
2669 __ jcc(Assembler::positive, done);
2670 __ decrement(dreg);
2671 __ orl(dreg, ~(divisor - 1));
2672 __ increment(dreg);
2673 __ bind(done);
2674 } else {
2675 ShouldNotReachHere();
2676 }
2677 } else {
2678 Register rreg = right->as_register();
2679 assert(lreg == rax, "left register must be rax,");
2680 assert(rreg != rdx, "right register must not be rdx");
2681 assert(temp->as_register() == rdx, "tmp register must be rdx");
2682
2683 move_regs(lreg, rax);
2684
2685 int idivl_offset = __ corrected_idivl(rreg);
2686 add_debug_info_for_div0(idivl_offset, info);
2687 if (code == lir_irem) {
2688 move_regs(rdx, dreg); // result is in rdx
2689 } else {
2690 move_regs(rax, dreg);
2691 }
2692 }
2693 }
2694
2695
2696 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2697 if (opr1->is_single_cpu()) {
2698 Register reg1 = opr1->as_register();
2699 if (opr2->is_single_cpu()) {
2700 // cpu register - cpu register
2701 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2702 __ cmpptr(reg1, opr2->as_register());
2703 } else {
2704 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2705 __ cmpl(reg1, opr2->as_register());
2706 }
2707 } else if (opr2->is_stack()) {
2708 // cpu register - stack
2709 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2710 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2711 } else {
2712 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2713 }
2714 } else if (opr2->is_constant()) {
2715 // cpu register - constant
2716 LIR_Const* c = opr2->as_constant_ptr();
2717 if (c->type() == T_INT) {
2718 __ cmpl(reg1, c->as_jint());
2719 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2720 // In 64bit oops are single register
2721 jobject o = c->as_jobject();
2722 if (o == NULL) {
2723 __ cmpptr(reg1, (int32_t)NULL_WORD);
2724 } else {
2725 #ifdef _LP64
2726 __ movoop(rscratch1, o);
2727 __ cmpptr(reg1, rscratch1);
2728 #else
2729 __ cmpoop(reg1, c->as_jobject());
2730 #endif // _LP64
2731 }
2732 } else {
2733 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2734 }
2735 // cpu register - address
2736 } else if (opr2->is_address()) {
2737 if (op->info() != NULL) {
2738 add_debug_info_for_null_check_here(op->info());
2739 }
2740 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2741 } else {
2742 ShouldNotReachHere();
2743 }
2744
2745 } else if(opr1->is_double_cpu()) {
2746 Register xlo = opr1->as_register_lo();
2747 Register xhi = opr1->as_register_hi();
2748 if (opr2->is_double_cpu()) {
2749 #ifdef _LP64
2750 __ cmpptr(xlo, opr2->as_register_lo());
2751 #else
2752 // cpu register - cpu register
2753 Register ylo = opr2->as_register_lo();
2754 Register yhi = opr2->as_register_hi();
2755 __ subl(xlo, ylo);
2756 __ sbbl(xhi, yhi);
2757 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2758 __ orl(xhi, xlo);
2759 }
2760 #endif // _LP64
2761 } else if (opr2->is_constant()) {
2762 // cpu register - constant 0
2763 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2764 #ifdef _LP64
2765 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2766 #else
2767 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2768 __ orl(xhi, xlo);
2769 #endif // _LP64
2770 } else {
2771 ShouldNotReachHere();
2772 }
2773
2774 } else if (opr1->is_single_xmm()) {
2775 XMMRegister reg1 = opr1->as_xmm_float_reg();
2776 if (opr2->is_single_xmm()) {
2777 // xmm register - xmm register
2778 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2779 } else if (opr2->is_stack()) {
2780 // xmm register - stack
2781 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2782 } else if (opr2->is_constant()) {
2783 // xmm register - constant
2784 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2785 } else if (opr2->is_address()) {
2786 // xmm register - address
2787 if (op->info() != NULL) {
2788 add_debug_info_for_null_check_here(op->info());
2789 }
2790 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2791 } else {
2792 ShouldNotReachHere();
2793 }
2794
2795 } else if (opr1->is_double_xmm()) {
2796 XMMRegister reg1 = opr1->as_xmm_double_reg();
2797 if (opr2->is_double_xmm()) {
2798 // xmm register - xmm register
2799 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2800 } else if (opr2->is_stack()) {
2801 // xmm register - stack
2802 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2803 } else if (opr2->is_constant()) {
2804 // xmm register - constant
2805 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2806 } else if (opr2->is_address()) {
2807 // xmm register - address
2808 if (op->info() != NULL) {
2809 add_debug_info_for_null_check_here(op->info());
2810 }
2811 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2812 } else {
2813 ShouldNotReachHere();
2814 }
2815
2816 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2817 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2818 assert(opr2->is_fpu_register(), "both must be registers");
2819 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2820
2821 } else if (opr1->is_address() && opr2->is_constant()) {
2822 LIR_Const* c = opr2->as_constant_ptr();
2823 #ifdef _LP64
2824 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2825 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2826 __ movoop(rscratch1, c->as_jobject());
2827 }
2828 #endif // LP64
2829 if (op->info() != NULL) {
2830 add_debug_info_for_null_check_here(op->info());
2831 }
2832 // special case: address - constant
2833 LIR_Address* addr = opr1->as_address_ptr();
2834 if (c->type() == T_INT) {
2835 __ cmpl(as_Address(addr), c->as_jint());
2836 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2837 #ifdef _LP64
2838 // %%% Make this explode if addr isn't reachable until we figure out a
2839 // better strategy by giving noreg as the temp for as_Address
2840 __ cmpptr(rscratch1, as_Address(addr, noreg));
2841 #else
2842 __ cmpoop(as_Address(addr), c->as_jobject());
2843 #endif // _LP64
2844 } else {
2845 ShouldNotReachHere();
2846 }
2847
2848 } else {
2849 ShouldNotReachHere();
2850 }
2851 }
2852
2853 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2854 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2855 if (left->is_single_xmm()) {
2856 assert(right->is_single_xmm(), "must match");
2857 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2858 } else if (left->is_double_xmm()) {
2859 assert(right->is_double_xmm(), "must match");
2860 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2861
2862 } else {
2863 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2864 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2865
2866 assert(left->fpu() == 0, "left must be on TOS");
2867 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2868 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2869 }
2870 } else {
2871 assert(code == lir_cmp_l2i, "check");
2872 #ifdef _LP64
2873 Label done;
2874 Register dest = dst->as_register();
2875 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2876 __ movl(dest, -1);
2877 __ jccb(Assembler::less, done);
2878 __ set_byte_if_not_zero(dest);
2879 __ movzbl(dest, dest);
2880 __ bind(done);
2881 #else
2882 __ lcmp2int(left->as_register_hi(),
2883 left->as_register_lo(),
2884 right->as_register_hi(),
2885 right->as_register_lo());
2886 move_regs(left->as_register_hi(), dst->as_register());
2887 #endif // _LP64
2888 }
2889 }
2890
2891
2892 void LIR_Assembler::align_call(LIR_Code code) {
2893 if (os::is_MP()) {
2894 // make sure that the displacement word of the call ends up word aligned
2895 int offset = __ offset();
2896 switch (code) {
2897 case lir_static_call:
2898 case lir_optvirtual_call:
2899 case lir_dynamic_call:
2900 offset += NativeCall::displacement_offset;
2901 break;
2902 case lir_icvirtual_call:
2903 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2904 break;
2905 case lir_virtual_call: // currently, sparc-specific for niagara
2906 default: ShouldNotReachHere();
2907 }
2908 while (offset++ % BytesPerWord != 0) {
2909 __ nop();
2910 }
2911 }
2912 }
2913
2914
2915 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2916 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2917 "must be aligned");
2918 __ call(AddressLiteral(op->addr(), rtype));
2919 add_call_info(code_offset(), op->info());
2920 }
2921
2922
2923 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2924 __ ic_call(op->addr());
2925 add_call_info(code_offset(), op->info());
2926 assert(!os::is_MP() ||
2927 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2928 "must be aligned");
2929 }
2930
2931
2932 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2933 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2934 ShouldNotReachHere();
2935 }
2936
2937
2938 void LIR_Assembler::emit_static_call_stub() {
2939 address call_pc = __ pc();
2940 address stub = __ start_a_stub(call_stub_size);
2941 if (stub == NULL) {
2942 bailout("static call stub overflow");
2943 return;
2944 }
2945
2946 int start = __ offset();
2947 if (os::is_MP()) {
2948 // make sure that the displacement word of the call ends up word aligned
2949 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2950 while (offset++ % BytesPerWord != 0) {
2951 __ nop();
2952 }
2953 }
2954 __ relocate(static_stub_Relocation::spec(call_pc));
2955 __ mov_metadata(rbx, (Metadata*)NULL);
2956 // must be set to -1 at code generation time
2957 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2958 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2959 __ jump(RuntimeAddress(__ pc()));
2960
2961 assert(__ offset() - start <= call_stub_size, "stub too big");
2962 __ end_a_stub();
2963 }
2964
2965
2966 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2967 assert(exceptionOop->as_register() == rax, "must match");
2968 assert(exceptionPC->as_register() == rdx, "must match");
2969
2970 // exception object is not added to oop map by LinearScan
2971 // (LinearScan assumes that no oops are in fixed registers)
2972 info->add_register_oop(exceptionOop);
2973 Runtime1::StubID unwind_id;
2974
2975 // get current pc information
2976 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2977 int pc_for_athrow_offset = __ offset();
2978 InternalAddress pc_for_athrow(__ pc());
2979 __ lea(exceptionPC->as_register(), pc_for_athrow);
2980 add_call_info(pc_for_athrow_offset, info); // for exception handler
2981
2982 __ verify_not_null_oop(rax);
2983 // search an exception handler (rax: exception oop, rdx: throwing pc)
2984 if (compilation()->has_fpu_code()) {
2985 unwind_id = Runtime1::handle_exception_id;
2986 } else {
2987 unwind_id = Runtime1::handle_exception_nofpu_id;
2988 }
2989 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2990
2991 // enough room for two byte trap
2992 __ nop();
2993 }
2994
2995
2996 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2997 assert(exceptionOop->as_register() == rax, "must match");
2998
2999 __ jmp(_unwind_handler_entry);
3000 }
3001
3002
3003 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3004
3005 // optimized version for linear scan:
3006 // * count must be already in ECX (guaranteed by LinearScan)
3007 // * left and dest must be equal
3008 // * tmp must be unused
3009 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3010 assert(left == dest, "left and dest must be equal");
3011 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3012
3013 if (left->is_single_cpu()) {
3014 Register value = left->as_register();
3015 assert(value != SHIFT_count, "left cannot be ECX");
3016
3017 switch (code) {
3018 case lir_shl: __ shll(value); break;
3019 case lir_shr: __ sarl(value); break;
3020 case lir_ushr: __ shrl(value); break;
3021 default: ShouldNotReachHere();
3022 }
3023 } else if (left->is_double_cpu()) {
3024 Register lo = left->as_register_lo();
3025 Register hi = left->as_register_hi();
3026 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3027 #ifdef _LP64
3028 switch (code) {
3029 case lir_shl: __ shlptr(lo); break;
3030 case lir_shr: __ sarptr(lo); break;
3031 case lir_ushr: __ shrptr(lo); break;
3032 default: ShouldNotReachHere();
3033 }
3034 #else
3035
3036 switch (code) {
3037 case lir_shl: __ lshl(hi, lo); break;
3038 case lir_shr: __ lshr(hi, lo, true); break;
3039 case lir_ushr: __ lshr(hi, lo, false); break;
3040 default: ShouldNotReachHere();
3041 }
3042 #endif // LP64
3043 } else {
3044 ShouldNotReachHere();
3045 }
3046 }
3047
3048
3049 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3050 if (dest->is_single_cpu()) {
3051 // first move left into dest so that left is not destroyed by the shift
3052 Register value = dest->as_register();
3053 count = count & 0x1F; // Java spec
3054
3055 move_regs(left->as_register(), value);
3056 switch (code) {
3057 case lir_shl: __ shll(value, count); break;
3058 case lir_shr: __ sarl(value, count); break;
3059 case lir_ushr: __ shrl(value, count); break;
3060 default: ShouldNotReachHere();
3061 }
3062 } else if (dest->is_double_cpu()) {
3063 #ifndef _LP64
3064 Unimplemented();
3065 #else
3066 // first move left into dest so that left is not destroyed by the shift
3067 Register value = dest->as_register_lo();
3068 count = count & 0x1F; // Java spec
3069
3070 move_regs(left->as_register_lo(), value);
3071 switch (code) {
3072 case lir_shl: __ shlptr(value, count); break;
3073 case lir_shr: __ sarptr(value, count); break;
3074 case lir_ushr: __ shrptr(value, count); break;
3075 default: ShouldNotReachHere();
3076 }
3077 #endif // _LP64
3078 } else {
3079 ShouldNotReachHere();
3080 }
3081 }
3082
3083
3084 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3085 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3086 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3087 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3088 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3089 }
3090
3091
3092 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3093 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3094 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3095 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3096 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3097 }
3098
3099
3100 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3101 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3102 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3103 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3104 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3105 }
3106
3107
3108 // This code replaces a call to arraycopy; no exception may
3109 // be thrown in this code, they must be thrown in the System.arraycopy
3110 // activation frame; we could save some checks if this would not be the case
3111 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3112 ciArrayKlass* default_type = op->expected_type();
3113 Register src = op->src()->as_register();
3114 Register dst = op->dst()->as_register();
3115 Register src_pos = op->src_pos()->as_register();
3116 Register dst_pos = op->dst_pos()->as_register();
3117 Register length = op->length()->as_register();
3118 Register tmp = op->tmp()->as_register();
3119
3120 CodeStub* stub = op->stub();
3121 int flags = op->flags();
3122 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3123 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3124
3125 // if we don't know anything, just go through the generic arraycopy
3126 if (default_type == NULL) {
3127 Label done;
3128 // save outgoing arguments on stack in case call to System.arraycopy is needed
3129 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3130 // for interpreter calling conventions. Now we have to do it in new style conventions.
3131 // For the moment until C1 gets the new register allocator I just force all the
3132 // args to the right place (except the register args) and then on the back side
3133 // reload the register args properly if we go slow path. Yuck
3134
3135 // These are proper for the calling convention
3136 store_parameter(length, 2);
3137 store_parameter(dst_pos, 1);
3138 store_parameter(dst, 0);
3139
3140 // these are just temporary placements until we need to reload
3141 store_parameter(src_pos, 3);
3142 store_parameter(src, 4);
3143 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3144
3145 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3146
3147 address copyfunc_addr = StubRoutines::generic_arraycopy();
3148
3149 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3150 #ifdef _LP64
3151 // The arguments are in java calling convention so we can trivially shift them to C
3152 // convention
3153 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3154 __ mov(c_rarg0, j_rarg0);
3155 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3156 __ mov(c_rarg1, j_rarg1);
3157 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3158 __ mov(c_rarg2, j_rarg2);
3159 assert_different_registers(c_rarg3, j_rarg4);
3160 __ mov(c_rarg3, j_rarg3);
3161 #ifdef _WIN64
3162 // Allocate abi space for args but be sure to keep stack aligned
3163 __ subptr(rsp, 6*wordSize);
3164 store_parameter(j_rarg4, 4);
3165 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3166 __ call(RuntimeAddress(C_entry));
3167 } else {
3168 #ifndef PRODUCT
3169 if (PrintC1Statistics) {
3170 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3171 }
3172 #endif
3173 __ call(RuntimeAddress(copyfunc_addr));
3174 }
3175 __ addptr(rsp, 6*wordSize);
3176 #else
3177 __ mov(c_rarg4, j_rarg4);
3178 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3179 __ call(RuntimeAddress(C_entry));
3180 } else {
3181 #ifndef PRODUCT
3182 if (PrintC1Statistics) {
3183 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3184 }
3185 #endif
3186 __ call(RuntimeAddress(copyfunc_addr));
3187 }
3188 #endif // _WIN64
3189 #else
3190 __ push(length);
3191 __ push(dst_pos);
3192 __ push(dst);
3193 __ push(src_pos);
3194 __ push(src);
3195
3196 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3197 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3198 } else {
3199 #ifndef PRODUCT
3200 if (PrintC1Statistics) {
3201 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3202 }
3203 #endif
3204 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3205 }
3206
3207 #endif // _LP64
3208
3209 __ cmpl(rax, 0);
3210 __ jcc(Assembler::equal, *stub->continuation());
3211
3212 if (copyfunc_addr != NULL) {
3213 __ mov(tmp, rax);
3214 __ xorl(tmp, -1);
3215 }
3216
3217 // Reload values from the stack so they are where the stub
3218 // expects them.
3219 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3220 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3221 __ movptr (length, Address(rsp, 2*BytesPerWord));
3222 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3223 __ movptr (src, Address(rsp, 4*BytesPerWord));
3224
3225 if (copyfunc_addr != NULL) {
3226 __ subl(length, tmp);
3227 __ addl(src_pos, tmp);
3228 __ addl(dst_pos, tmp);
3229 }
3230 __ jmp(*stub->entry());
3231
3232 __ bind(*stub->continuation());
3233 return;
3234 }
3235
3236 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3237
3238 int elem_size = type2aelembytes(basic_type);
3239 int shift_amount;
3240 Address::ScaleFactor scale;
3241
3242 switch (elem_size) {
3243 case 1 :
3244 shift_amount = 0;
3245 scale = Address::times_1;
3246 break;
3247 case 2 :
3248 shift_amount = 1;
3249 scale = Address::times_2;
3250 break;
3251 case 4 :
3252 shift_amount = 2;
3253 scale = Address::times_4;
3254 break;
3255 case 8 :
3256 shift_amount = 3;
3257 scale = Address::times_8;
3258 break;
3259 default:
3260 ShouldNotReachHere();
3261 }
3262
3263 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3264 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3265 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3266 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3267
3268 // length and pos's are all sign extended at this point on 64bit
3269
3270 // test for NULL
3271 if (flags & LIR_OpArrayCopy::src_null_check) {
3272 __ testptr(src, src);
3273 __ jcc(Assembler::zero, *stub->entry());
3274 }
3275 if (flags & LIR_OpArrayCopy::dst_null_check) {
3276 __ testptr(dst, dst);
3277 __ jcc(Assembler::zero, *stub->entry());
3278 }
3279
3280 // check if negative
3281 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3282 __ testl(src_pos, src_pos);
3283 __ jcc(Assembler::less, *stub->entry());
3284 }
3285 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3286 __ testl(dst_pos, dst_pos);
3287 __ jcc(Assembler::less, *stub->entry());
3288 }
3289
3290 if (flags & LIR_OpArrayCopy::src_range_check) {
3291 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3292 __ cmpl(tmp, src_length_addr);
3293 __ jcc(Assembler::above, *stub->entry());
3294 }
3295 if (flags & LIR_OpArrayCopy::dst_range_check) {
3296 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3297 __ cmpl(tmp, dst_length_addr);
3298 __ jcc(Assembler::above, *stub->entry());
3299 }
3300
3301 if (flags & LIR_OpArrayCopy::length_positive_check) {
3302 __ testl(length, length);
3303 __ jcc(Assembler::less, *stub->entry());
3304 __ jcc(Assembler::zero, *stub->continuation());
3305 }
3306
3307 #ifdef _LP64
3308 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3309 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3310 #endif
3311
3312 if (flags & LIR_OpArrayCopy::type_check) {
3313 // We don't know the array types are compatible
3314 if (basic_type != T_OBJECT) {
3315 // Simple test for basic type arrays
3316 if (UseCompressedClassPointers) {
3317 __ movl(tmp, src_klass_addr);
3318 __ cmpl(tmp, dst_klass_addr);
3319 } else {
3320 __ movptr(tmp, src_klass_addr);
3321 __ cmpptr(tmp, dst_klass_addr);
3322 }
3323 __ jcc(Assembler::notEqual, *stub->entry());
3324 } else {
3325 // For object arrays, if src is a sub class of dst then we can
3326 // safely do the copy.
3327 Label cont, slow;
3328
3329 __ push(src);
3330 __ push(dst);
3331
3332 __ load_klass(src, src);
3333 __ load_klass(dst, dst);
3334
3335 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3336
3337 __ push(src);
3338 __ push(dst);
3339 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3340 __ pop(dst);
3341 __ pop(src);
3342
3343 __ cmpl(src, 0);
3344 __ jcc(Assembler::notEqual, cont);
3345
3346 __ bind(slow);
3347 __ pop(dst);
3348 __ pop(src);
3349
3350 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3351 if (copyfunc_addr != NULL) { // use stub if available
3352 // src is not a sub class of dst so we have to do a
3353 // per-element check.
3354
3355 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3356 if ((flags & mask) != mask) {
3357 // Check that at least both of them object arrays.
3358 assert(flags & mask, "one of the two should be known to be an object array");
3359
3360 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3361 __ load_klass(tmp, src);
3362 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3363 __ load_klass(tmp, dst);
3364 }
3365 int lh_offset = in_bytes(Klass::layout_helper_offset());
3366 Address klass_lh_addr(tmp, lh_offset);
3367 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3368 __ cmpl(klass_lh_addr, objArray_lh);
3369 __ jcc(Assembler::notEqual, *stub->entry());
3370 }
3371
3372 // Spill because stubs can use any register they like and it's
3373 // easier to restore just those that we care about.
3374 store_parameter(dst, 0);
3375 store_parameter(dst_pos, 1);
3376 store_parameter(length, 2);
3377 store_parameter(src_pos, 3);
3378 store_parameter(src, 4);
3379
3380 #ifndef _LP64
3381 __ movptr(tmp, dst_klass_addr);
3382 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3383 __ push(tmp);
3384 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3385 __ push(tmp);
3386 __ push(length);
3387 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3388 __ push(tmp);
3389 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3390 __ push(tmp);
3391
3392 __ call_VM_leaf(copyfunc_addr, 5);
3393 #else
3394 __ movl2ptr(length, length); //higher 32bits must be null
3395
3396 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3397 assert_different_registers(c_rarg0, dst, dst_pos, length);
3398 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3399 assert_different_registers(c_rarg1, dst, length);
3400
3401 __ mov(c_rarg2, length);
3402 assert_different_registers(c_rarg2, dst);
3403
3404 #ifdef _WIN64
3405 // Allocate abi space for args but be sure to keep stack aligned
3406 __ subptr(rsp, 6*wordSize);
3407 __ load_klass(c_rarg3, dst);
3408 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3409 store_parameter(c_rarg3, 4);
3410 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3411 __ call(RuntimeAddress(copyfunc_addr));
3412 __ addptr(rsp, 6*wordSize);
3413 #else
3414 __ load_klass(c_rarg4, dst);
3415 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3416 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3417 __ call(RuntimeAddress(copyfunc_addr));
3418 #endif
3419
3420 #endif
3421
3422 #ifndef PRODUCT
3423 if (PrintC1Statistics) {
3424 Label failed;
3425 __ testl(rax, rax);
3426 __ jcc(Assembler::notZero, failed);
3427 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3428 __ bind(failed);
3429 }
3430 #endif
3431
3432 __ testl(rax, rax);
3433 __ jcc(Assembler::zero, *stub->continuation());
3434
3435 #ifndef PRODUCT
3436 if (PrintC1Statistics) {
3437 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3438 }
3439 #endif
3440
3441 __ mov(tmp, rax);
3442
3443 __ xorl(tmp, -1);
3444
3445 // Restore previously spilled arguments
3446 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3447 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3448 __ movptr (length, Address(rsp, 2*BytesPerWord));
3449 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3450 __ movptr (src, Address(rsp, 4*BytesPerWord));
3451
3452
3453 __ subl(length, tmp);
3454 __ addl(src_pos, tmp);
3455 __ addl(dst_pos, tmp);
3456 }
3457
3458 __ jmp(*stub->entry());
3459
3460 __ bind(cont);
3461 __ pop(dst);
3462 __ pop(src);
3463 }
3464 }
3465
3466 #ifdef ASSERT
3467 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3468 // Sanity check the known type with the incoming class. For the
3469 // primitive case the types must match exactly with src.klass and
3470 // dst.klass each exactly matching the default type. For the
3471 // object array case, if no type check is needed then either the
3472 // dst type is exactly the expected type and the src type is a
3473 // subtype which we can't check or src is the same array as dst
3474 // but not necessarily exactly of type default_type.
3475 Label known_ok, halt;
3476 __ mov_metadata(tmp, default_type->constant_encoding());
3477 #ifdef _LP64
3478 if (UseCompressedClassPointers) {
3479 __ encode_klass_not_null(tmp);
3480 }
3481 #endif
3482
3483 if (basic_type != T_OBJECT) {
3484
3485 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3486 else __ cmpptr(tmp, dst_klass_addr);
3487 __ jcc(Assembler::notEqual, halt);
3488 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3489 else __ cmpptr(tmp, src_klass_addr);
3490 __ jcc(Assembler::equal, known_ok);
3491 } else {
3492 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3493 else __ cmpptr(tmp, dst_klass_addr);
3494 __ jcc(Assembler::equal, known_ok);
3495 __ cmpptr(src, dst);
3496 __ jcc(Assembler::equal, known_ok);
3497 }
3498 __ bind(halt);
3499 __ stop("incorrect type information in arraycopy");
3500 __ bind(known_ok);
3501 }
3502 #endif
3503
3504 #ifndef PRODUCT
3505 if (PrintC1Statistics) {
3506 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3507 }
3508 #endif
3509
3510 #ifdef _LP64
3511 assert_different_registers(c_rarg0, dst, dst_pos, length);
3512 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3513 assert_different_registers(c_rarg1, length);
3514 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3515 __ mov(c_rarg2, length);
3516
3517 #else
3518 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3519 store_parameter(tmp, 0);
3520 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3521 store_parameter(tmp, 1);
3522 store_parameter(length, 2);
3523 #endif // _LP64
3524
3525 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3526 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3527 const char *name;
3528 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3529 __ call_VM_leaf(entry, 0);
3530
3531 __ bind(*stub->continuation());
3532 }
3533
3534 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3535 assert(op->crc()->is_single_cpu(), "crc must be register");
3536 assert(op->val()->is_single_cpu(), "byte value must be register");
3537 assert(op->result_opr()->is_single_cpu(), "result must be register");
3538 Register crc = op->crc()->as_register();
3539 Register val = op->val()->as_register();
3540 Register res = op->result_opr()->as_register();
3541
3542 assert_different_registers(val, crc, res);
3543
3544 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3545 __ notl(crc); // ~crc
3546 __ update_byte_crc32(crc, val, res);
3547 __ notl(crc); // ~crc
3548 __ mov(res, crc);
3549 }
3550
3551 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3552 Register obj = op->obj_opr()->as_register(); // may not be an oop
3553 Register hdr = op->hdr_opr()->as_register();
3554 Register lock = op->lock_opr()->as_register();
3555 if (!UseFastLocking) {
3556 __ jmp(*op->stub()->entry());
3557 } else if (op->code() == lir_lock) {
3558 Register scratch = noreg;
3559 if (UseBiasedLocking) {
3560 scratch = op->scratch_opr()->as_register();
3561 }
3562 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3563 // add debug info for NullPointerException only if one is possible
3564 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3565 if (op->info() != NULL) {
3566 add_debug_info_for_null_check(null_check_offset, op->info());
3567 }
3568 // done
3569 } else if (op->code() == lir_unlock) {
3570 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3571 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3572 } else {
3573 Unimplemented();
3574 }
3575 __ bind(*op->stub()->continuation());
3576 }
3577
3578
3579 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3580 ciMethod* method = op->profiled_method();
3581 int bci = op->profiled_bci();
3582 ciMethod* callee = op->profiled_callee();
3583
3584 // Update counter for all call types
3585 ciMethodData* md = method->method_data_or_null();
3586 assert(md != NULL, "Sanity");
3587 ciProfileData* data = md->bci_to_data(bci);
3588 assert(data->is_CounterData(), "need CounterData for calls");
3589 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3590 Register mdo = op->mdo()->as_register();
3591 __ mov_metadata(mdo, md->constant_encoding());
3592 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3593 Bytecodes::Code bc = method->java_code_at_bci(bci);
3594 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3595 // Perform additional virtual call profiling for invokevirtual and
3596 // invokeinterface bytecodes
3597 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3598 !callee_is_static && // required for optimized MH invokes
3599 C1ProfileVirtualCalls) {
3600 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3601 Register recv = op->recv()->as_register();
3602 assert_different_registers(mdo, recv);
3603 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3604 ciKlass* known_klass = op->known_holder();
3605 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3606 // We know the type that will be seen at this call site; we can
3607 // statically update the MethodData* rather than needing to do
3608 // dynamic tests on the receiver type
3609
3610 // NOTE: we should probably put a lock around this search to
3611 // avoid collisions by concurrent compilations
3612 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3613 uint i;
3614 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3615 ciKlass* receiver = vc_data->receiver(i);
3616 if (known_klass->equals(receiver)) {
3617 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3618 __ addptr(data_addr, DataLayout::counter_increment);
3619 return;
3620 }
3621 }
3622
3623 // Receiver type not found in profile data; select an empty slot
3624
3625 // Note that this is less efficient than it should be because it
3626 // always does a write to the receiver part of the
3627 // VirtualCallData rather than just the first time
3628 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3629 ciKlass* receiver = vc_data->receiver(i);
3630 if (receiver == NULL) {
3631 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3632 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3633 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3634 __ addptr(data_addr, DataLayout::counter_increment);
3635 return;
3636 }
3637 }
3638 } else {
3639 __ load_klass(recv, recv);
3640 Label update_done;
3641 type_profile_helper(mdo, md, data, recv, &update_done);
3642 // Receiver did not match any saved receiver and there is no empty row for it.
3643 // Increment total counter to indicate polymorphic case.
3644 __ addptr(counter_addr, DataLayout::counter_increment);
3645
3646 __ bind(update_done);
3647 }
3648 } else {
3649 // Static call
3650 __ addptr(counter_addr, DataLayout::counter_increment);
3651 }
3652 }
3653
3654 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3655 Register obj = op->obj()->as_register();
3656 Register tmp = op->tmp()->as_pointer_register();
3657 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3658 ciKlass* exact_klass = op->exact_klass();
3659 intptr_t current_klass = op->current_klass();
3660 bool not_null = op->not_null();
3661 bool no_conflict = op->no_conflict();
3662
3663 Label update, next, none;
3664
3665 bool do_null = !not_null;
3666 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3667 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3668
3669 assert(do_null || do_update, "why are we here?");
3670 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3671
3672 __ verify_oop(obj);
3673
3674 if (tmp != obj) {
3675 __ mov(tmp, obj);
3676 }
3677 if (do_null) {
3678 __ testptr(tmp, tmp);
3679 __ jccb(Assembler::notZero, update);
3680 if (!TypeEntries::was_null_seen(current_klass)) {
3681 __ orptr(mdo_addr, TypeEntries::null_seen);
3682 }
3683 if (do_update) {
3684 #ifndef ASSERT
3685 __ jmpb(next);
3686 }
3687 #else
3688 __ jmp(next);
3689 }
3690 } else {
3691 __ testptr(tmp, tmp);
3692 __ jccb(Assembler::notZero, update);
3693 __ stop("unexpect null obj");
3694 #endif
3695 }
3696
3697 __ bind(update);
3698
3699 if (do_update) {
3700 #ifdef ASSERT
3701 if (exact_klass != NULL) {
3702 Label ok;
3703 __ load_klass(tmp, tmp);
3704 __ push(tmp);
3705 __ mov_metadata(tmp, exact_klass->constant_encoding());
3706 __ cmpptr(tmp, Address(rsp, 0));
3707 __ jccb(Assembler::equal, ok);
3708 __ stop("exact klass and actual klass differ");
3709 __ bind(ok);
3710 __ pop(tmp);
3711 }
3712 #endif
3713 if (!no_conflict) {
3714 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3715 if (exact_klass != NULL) {
3716 __ mov_metadata(tmp, exact_klass->constant_encoding());
3717 } else {
3718 __ load_klass(tmp, tmp);
3719 }
3720
3721 __ xorptr(tmp, mdo_addr);
3722 __ testptr(tmp, TypeEntries::type_klass_mask);
3723 // klass seen before, nothing to do. The unknown bit may have been
3724 // set already but no need to check.
3725 __ jccb(Assembler::zero, next);
3726
3727 __ testptr(tmp, TypeEntries::type_unknown);
3728 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3729
3730 if (TypeEntries::is_type_none(current_klass)) {
3731 __ cmpptr(mdo_addr, 0);
3732 __ jccb(Assembler::equal, none);
3733 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3734 __ jccb(Assembler::equal, none);
3735 // There is a chance that the checks above (re-reading profiling
3736 // data from memory) fail if another thread has just set the
3737 // profiling to this obj's klass
3738 __ xorptr(tmp, mdo_addr);
3739 __ testptr(tmp, TypeEntries::type_klass_mask);
3740 __ jccb(Assembler::zero, next);
3741 }
3742 } else {
3743 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3744 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3745
3746 __ movptr(tmp, mdo_addr);
3747 __ testptr(tmp, TypeEntries::type_unknown);
3748 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3749 }
3750
3751 // different than before. Cannot keep accurate profile.
3752 __ orptr(mdo_addr, TypeEntries::type_unknown);
3753
3754 if (TypeEntries::is_type_none(current_klass)) {
3755 __ jmpb(next);
3756
3757 __ bind(none);
3758 // first time here. Set profile type.
3759 __ movptr(mdo_addr, tmp);
3760 }
3761 } else {
3762 // There's a single possible klass at this profile point
3763 assert(exact_klass != NULL, "should be");
3764 if (TypeEntries::is_type_none(current_klass)) {
3765 __ mov_metadata(tmp, exact_klass->constant_encoding());
3766 __ xorptr(tmp, mdo_addr);
3767 __ testptr(tmp, TypeEntries::type_klass_mask);
3768 #ifdef ASSERT
3769 __ jcc(Assembler::zero, next);
3770
3771 {
3772 Label ok;
3773 __ push(tmp);
3774 __ cmpptr(mdo_addr, 0);
3775 __ jcc(Assembler::equal, ok);
3776 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3777 __ jcc(Assembler::equal, ok);
3778 // may have been set by another thread
3779 __ mov_metadata(tmp, exact_klass->constant_encoding());
3780 __ xorptr(tmp, mdo_addr);
3781 __ testptr(tmp, TypeEntries::type_mask);
3782 __ jcc(Assembler::zero, ok);
3783
3784 __ stop("unexpected profiling mismatch");
3785 __ bind(ok);
3786 __ pop(tmp);
3787 }
3788 #else
3789 __ jccb(Assembler::zero, next);
3790 #endif
3791 // first time here. Set profile type.
3792 __ movptr(mdo_addr, tmp);
3793 } else {
3794 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3795 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3796
3797 __ movptr(tmp, mdo_addr);
3798 __ testptr(tmp, TypeEntries::type_unknown);
3799 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3800
3801 __ orptr(mdo_addr, TypeEntries::type_unknown);
3802 }
3803 }
3804
3805 __ bind(next);
3806 }
3807 }
3808
3809 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3810 Unimplemented();
3811 }
3812
3813
3814 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3815 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3816 }
3817
3818
3819 void LIR_Assembler::align_backward_branch_target() {
3820 __ align(BytesPerWord);
3821 }
3822
3823
3824 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3825 if (left->is_single_cpu()) {
3826 __ negl(left->as_register());
3827 move_regs(left->as_register(), dest->as_register());
3828
3829 } else if (left->is_double_cpu()) {
3830 Register lo = left->as_register_lo();
3831 #ifdef _LP64
3832 Register dst = dest->as_register_lo();
3833 __ movptr(dst, lo);
3834 __ negptr(dst);
3835 #else
3836 Register hi = left->as_register_hi();
3837 __ lneg(hi, lo);
3838 if (dest->as_register_lo() == hi) {
3839 assert(dest->as_register_hi() != lo, "destroying register");
3840 move_regs(hi, dest->as_register_hi());
3841 move_regs(lo, dest->as_register_lo());
3842 } else {
3843 move_regs(lo, dest->as_register_lo());
3844 move_regs(hi, dest->as_register_hi());
3845 }
3846 #endif // _LP64
3847
3848 } else if (dest->is_single_xmm()) {
3849 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3850 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3851 }
3852 __ xorps(dest->as_xmm_float_reg(),
3853 ExternalAddress((address)float_signflip_pool));
3854
3855 } else if (dest->is_double_xmm()) {
3856 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3857 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3858 }
3859 __ xorpd(dest->as_xmm_double_reg(),
3860 ExternalAddress((address)double_signflip_pool));
3861
3862 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3863 assert(left->fpu() == 0, "arg must be on TOS");
3864 assert(dest->fpu() == 0, "dest must be TOS");
3865 __ fchs();
3866
3867 } else {
3868 ShouldNotReachHere();
3869 }
3870 }
3871
3872
3873 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3874 assert(addr->is_address() && dest->is_register(), "check");
3875 Register reg;
3876 reg = dest->as_pointer_register();
3877 __ lea(reg, as_Address(addr->as_address_ptr()));
3878 }
3879
3880
3881
3882 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3883 assert(!tmp->is_valid(), "don't need temporary");
3884 __ call(RuntimeAddress(dest));
3885 if (info != NULL) {
3886 add_call_info_here(info);
3887 }
3888 }
3889
3890
3891 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3892 assert(type == T_LONG, "only for volatile long fields");
3893
3894 if (info != NULL) {
3895 add_debug_info_for_null_check_here(info);
3896 }
3897
3898 if (src->is_double_xmm()) {
3899 if (dest->is_double_cpu()) {
3900 #ifdef _LP64
3901 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3902 #else
3903 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3904 __ psrlq(src->as_xmm_double_reg(), 32);
3905 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3906 #endif // _LP64
3907 } else if (dest->is_double_stack()) {
3908 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3909 } else if (dest->is_address()) {
3910 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3911 } else {
3912 ShouldNotReachHere();
3913 }
3914
3915 } else if (dest->is_double_xmm()) {
3916 if (src->is_double_stack()) {
3917 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3918 } else if (src->is_address()) {
3919 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3920 } else {
3921 ShouldNotReachHere();
3922 }
3923
3924 } else if (src->is_double_fpu()) {
3925 assert(src->fpu_regnrLo() == 0, "must be TOS");
3926 if (dest->is_double_stack()) {
3927 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3928 } else if (dest->is_address()) {
3929 __ fistp_d(as_Address(dest->as_address_ptr()));
3930 } else {
3931 ShouldNotReachHere();
3932 }
3933
3934 } else if (dest->is_double_fpu()) {
3935 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3936 if (src->is_double_stack()) {
3937 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3938 } else if (src->is_address()) {
3939 __ fild_d(as_Address(src->as_address_ptr()));
3940 } else {
3941 ShouldNotReachHere();
3942 }
3943 } else {
3944 ShouldNotReachHere();
3945 }
3946 }
3947
3948 #ifdef ASSERT
3949 // emit run-time assertion
3950 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3951 assert(op->code() == lir_assert, "must be");
3952
3953 if (op->in_opr1()->is_valid()) {
3954 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3955 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3956 } else {
3957 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3958 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3959 }
3960
3961 Label ok;
3962 if (op->condition() != lir_cond_always) {
3963 Assembler::Condition acond = Assembler::zero;
3964 switch (op->condition()) {
3965 case lir_cond_equal: acond = Assembler::equal; break;
3966 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3967 case lir_cond_less: acond = Assembler::less; break;
3968 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3969 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3970 case lir_cond_greater: acond = Assembler::greater; break;
3971 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3972 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3973 default: ShouldNotReachHere();
3974 }
3975 __ jcc(acond, ok);
3976 }
3977 if (op->halt()) {
3978 const char* str = __ code_string(op->msg());
3979 __ stop(str);
3980 } else {
3981 breakpoint();
3982 }
3983 __ bind(ok);
3984 }
3985 #endif
3986
3987 void LIR_Assembler::membar() {
3988 // QQQ sparc TSO uses this,
3989 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3990 }
3991
3992 void LIR_Assembler::membar_acquire() {
3993 // No x86 machines currently require load fences
3994 }
3995
3996 void LIR_Assembler::membar_release() {
3997 // No x86 machines currently require store fences
3998 }
3999
4000 void LIR_Assembler::membar_loadload() {
4001 // no-op
4002 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4003 }
4004
4005 void LIR_Assembler::membar_storestore() {
4006 // no-op
4007 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4008 }
4009
4010 void LIR_Assembler::membar_loadstore() {
4011 // no-op
4012 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4013 }
4014
4015 void LIR_Assembler::membar_storeload() {
4016 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4017 }
4018
4019 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4020 assert(result_reg->is_register(), "check");
4021 #ifdef _LP64
4022 // __ get_thread(result_reg->as_register_lo());
4023 __ mov(result_reg->as_register(), r15_thread);
4024 #else
4025 __ get_thread(result_reg->as_register());
4026 #endif // _LP64
4027 }
4028
4029
4030 void LIR_Assembler::peephole(LIR_List*) {
4031 // do nothing for now
4032 }
4033
4034 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4035 assert(data == dest, "xchg/xadd uses only 2 operands");
4036
4037 if (data->type() == T_INT) {
4038 if (code == lir_xadd) {
4039 if (os::is_MP()) {
4040 __ lock();
4041 }
4042 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4043 } else {
4044 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4045 }
4046 } else if (data->is_oop()) {
4047 assert (code == lir_xchg, "xadd for oops");
4048 Register obj = data->as_register();
4049 #ifdef _LP64
4050 if (UseCompressedOops) {
4051 __ encode_heap_oop(obj);
4052 __ xchgl(obj, as_Address(src->as_address_ptr()));
4053 __ decode_heap_oop(obj);
4054 } else {
4055 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4056 }
4057 #else
4058 __ xchgl(obj, as_Address(src->as_address_ptr()));
4059 #endif
4060 } else if (data->type() == T_LONG) {
4061 #ifdef _LP64
4062 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4063 if (code == lir_xadd) {
4064 if (os::is_MP()) {
4065 __ lock();
4066 }
4067 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4068 } else {
4069 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4070 }
4071 #else
4072 ShouldNotReachHere();
4073 #endif
4074 } else {
4075 ShouldNotReachHere();
4076 }
4077 }
4078
4079 #undef __