44 // associated with instructions preceding isync have
45 // been performed.
46 //
47 // Semantic barrier instructions:
48 // (as defined in orderAccess.hpp)
49 //
50 // - release orders Store|Store, (maps to lwsync)
51 // Load|Store
52 // - acquire orders Load|Store, (maps to lwsync)
53 // Load|Load
54 // - fence orders Store|Store, (maps to sync)
55 // Load|Store,
56 // Load|Load,
57 // Store|Load
58 //
59
60 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
61 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
62 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
63 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
64 #define inlasm_release() inlasm_lwsync();
65 #define inlasm_acquire() inlasm_lwsync();
66 // Use twi-isync for load_acquire (faster than lwsync).
67 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
68 // #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
69 #define inlasm_acquire_reg(X) inlasm_lwsync();
70 #define inlasm_fence() inlasm_sync();
71
72 inline void OrderAccess::loadload() { inlasm_lwsync(); }
73 inline void OrderAccess::storestore() { inlasm_lwsync(); }
74 inline void OrderAccess::loadstore() { inlasm_lwsync(); }
75 inline void OrderAccess::storeload() { inlasm_fence(); }
76
77 inline void OrderAccess::acquire() { inlasm_acquire(); }
78 inline void OrderAccess::release() { inlasm_release(); }
79 inline void OrderAccess::fence() { inlasm_fence(); }
80
81 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_acquire_reg(t); return t; }
82 inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_acquire_reg(t); return t; }
83 inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_acquire_reg(t); return t; }
84 inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_acquire_reg(t); return t; }
85 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_acquire_reg(t); return t; }
86 inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_acquire_reg(t); return t; }
87 inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_acquire_reg(t); return t; }
88 inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); }
89 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_acquire(); return t; }
90 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_acquire(); return t; }
91
92 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); }
93 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
94 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
95
96 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; }
97 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_release(); *p = v; }
98 inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_release(); *p = v; }
99 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_release(); *p = v; }
100 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; }
101 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_release(); *p = v; }
102 inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_release(); *p = v; }
103 inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_release(); *p = v; }
104 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; }
105 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; }
106
107 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; }
108 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; }
109
110 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_fence(); }
111 inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_fence(); }
112 inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_fence(); }
113 inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_fence(); }
114 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_fence(); }
115 inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_fence(); }
116 inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_fence(); }
117 inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_fence(); }
118 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_fence(); }
119 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_fence(); }
120
121 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_fence(); }
122 inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_fence(); }
123
124 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; inlasm_fence(); }
125 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_release(); *p = v; inlasm_fence(); }
126 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_release(); *p = v; inlasm_fence(); }
127 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_release(); *p = v; inlasm_fence(); }
128 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; inlasm_fence(); }
129 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_release(); *p = v; inlasm_fence(); }
130 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_release(); *p = v; inlasm_fence(); }
131 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_release(); *p = v; inlasm_fence(); }
132 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; inlasm_fence(); }
133 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; inlasm_fence(); }
134
135 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; inlasm_fence(); }
136 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; inlasm_fence(); }
137
138 #undef inlasm_sync
139 #undef inlasm_lwsync
140 #undef inlasm_eieio
141 #undef inlasm_isync
142 #undef inlasm_release
143 #undef inlasm_acquire
144 #undef inlasm_fence
145
146 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
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44 // associated with instructions preceding isync have
45 // been performed.
46 //
47 // Semantic barrier instructions:
48 // (as defined in orderAccess.hpp)
49 //
50 // - release orders Store|Store, (maps to lwsync)
51 // Load|Store
52 // - acquire orders Load|Store, (maps to lwsync)
53 // Load|Load
54 // - fence orders Store|Store, (maps to sync)
55 // Load|Store,
56 // Load|Load,
57 // Store|Load
58 //
59
60 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
61 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
62 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
63 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
64 // Use twi-isync for load_acquire (faster than lwsync).
65 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
66 // #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
67 #define inlasm_acquire_reg(X) inlasm_lwsync();
68
69 inline void OrderAccess::loadload() { inlasm_lwsync(); }
70 inline void OrderAccess::storestore() { inlasm_lwsync(); }
71 inline void OrderAccess::loadstore() { inlasm_lwsync(); }
72 inline void OrderAccess::storeload() { inlasm_sync(); }
73
74 inline void OrderAccess::acquire() { inlasm_lwsync(); }
75 inline void OrderAccess::release() { inlasm_lwsync(); }
76 inline void OrderAccess::fence() { inlasm_sync(); }
77
78 template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte* p) { register jbyte t = load(p); inlasm_acquire_reg(t); return t; }
79 template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = load(p); inlasm_acquire_reg(t); return t; }
80 template<> inline jint OrderAccess::specialized_load_acquire<jint> (volatile jint* p) { register jint t = load(p); inlasm_acquire_reg(t); return t; }
81 template<> inline jlong OrderAccess::specialized_load_acquire<jlong> (volatile jlong* p) { register jlong t = load(p); inlasm_acquire_reg(t); return t; }
82
83 #undef inlasm_sync
84 #undef inlasm_lwsync
85 #undef inlasm_eieio
86 #undef inlasm_isync
87
88 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1
89
90 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
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