1 /*
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   3  * Copyright (c) 2012, 2014, SAP AG. All rights reserved.
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   7  * under the terms of the GNU General Public License version 2 only, as
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  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
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  25 
  26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
  27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
  28 
  29 #include "runtime/orderAccess.hpp"
  30 
  31 // Implementation of class OrderAccess.
  32 
  33 //
  34 // Machine barrier instructions:
  35 //
  36 // - sync            Two-way memory barrier, aka fence.
  37 // - lwsync          orders  Store|Store,
  38 //                            Load|Store,
  39 //                            Load|Load,
  40 //                   but not Store|Load
  41 // - eieio           orders  Store|Store
  42 // - isync           Invalidates speculatively executed instructions,
  43 //                   but isync may complete before storage accesses
  44 //                   associated with instructions preceding isync have
  45 //                   been performed.
  46 //
  47 // Semantic barrier instructions:
  48 // (as defined in orderAccess.hpp)
  49 //
  50 // - release         orders Store|Store,       (maps to lwsync)
  51 //                           Load|Store
  52 // - acquire         orders  Load|Store,       (maps to lwsync)
  53 //                           Load|Load
  54 // - fence           orders Store|Store,       (maps to sync)
  55 //                           Load|Store,
  56 //                           Load|Load,
  57 //                          Store|Load
  58 //
  59 
  60 #define inlasm_sync()     __asm__ __volatile__ ("sync"   : : : "memory");
  61 #define inlasm_lwsync()   __asm__ __volatile__ ("lwsync" : : : "memory");
  62 #define inlasm_eieio()    __asm__ __volatile__ ("eieio"  : : : "memory");
  63 #define inlasm_isync()    __asm__ __volatile__ ("isync"  : : : "memory");
  64 // Use twi-isync for load_acquire (faster than lwsync).
  65 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
  66 // #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
  67 #define inlasm_acquire_reg(X) inlasm_lwsync();
  68 
  69 inline void OrderAccess::loadload()   { inlasm_lwsync(); }
  70 inline void OrderAccess::storestore() { inlasm_lwsync(); }
  71 inline void OrderAccess::loadstore()  { inlasm_lwsync(); }
  72 inline void OrderAccess::storeload()  { inlasm_sync();   }
  73 
  74 inline void OrderAccess::acquire()    { inlasm_lwsync(); }
  75 inline void OrderAccess::release()    { inlasm_lwsync(); }
  76 inline void OrderAccess::fence()      { inlasm_sync();   }
  77 
  78 template<> inline jbyte  OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte*  p) { register jbyte t = load(p);  inlasm_acquire_reg(t); return t; }
  79 template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = load(p); inlasm_acquire_reg(t); return t; }
  80 template<> inline jint   OrderAccess::specialized_load_acquire<jint>  (volatile jint*   p) { register jint t = load(p);   inlasm_acquire_reg(t); return t; }
  81 template<> inline jlong  OrderAccess::specialized_load_acquire<jlong> (volatile jlong*  p) { register jlong t = load(p);  inlasm_acquire_reg(t); return t; }
  82 
  83 #undef inlasm_sync
  84 #undef inlasm_lwsync
  85 #undef inlasm_eieio
  86 #undef inlasm_isync
  87 
  88 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1
  89 
  90 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP