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  24 
  25 #ifndef SHARE_VM_RUNTIME_ORDERACCESS_HPP
  26 #define SHARE_VM_RUNTIME_ORDERACCESS_HPP
  27 
  28 #include "memory/allocation.hpp"
  29 
  30 //                Memory Access Ordering Model
  31 //
  32 // This interface is based on the JSR-133 Cookbook for Compiler Writers.
  33 //
  34 // In the following, the terms 'previous', 'subsequent', 'before',
  35 // 'after', 'preceding' and 'succeeding' refer to program order.  The
  36 // terms 'down' and 'below' refer to forward load or store motion
  37 // relative to program order, while 'up' and 'above' refer to backward
  38 // motion.
  39 //
  40 //
  41 // We define four primitive memory barrier operations.
  42 //
  43 // LoadLoad:   Load1(s); LoadLoad; Load2
  44 //
  45 // Ensures that Load1 completes (obtains the value it loads from memory)
  46 // before Load2 and any subsequent load operations.  Loads before Load1
  47 // may *not* float below Load2 and any subsequent load operations.
  48 //
  49 // StoreStore: Store1(s); StoreStore; Store2
  50 //
  51 // Ensures that Store1 completes (the effect on memory of Store1 is made
  52 // visible to other processors) before Store2 and any subsequent store
  53 // operations.  Stores before Store1 may *not* float below Store2 and any
  54 // subsequent store operations.
  55 //
  56 // LoadStore:  Load1(s); LoadStore; Store2
  57 //
  58 // Ensures that Load1 completes before Store2 and any subsequent store
  59 // operations.  Loads before Load1 may *not* float below Store2 and any
  60 // subsequent store operations.
  61 //
  62 // StoreLoad:  Store1(s); StoreLoad; Load2
  63 //
  64 // Ensures that Store1 completes before Load2 and any subsequent load
  65 // operations.  Stores before Store1 may *not* float below Load2 and any
  66 // subsequent load operations.
  67 //
  68 // We define two further barriers: acquire and release.
  69 //
  70 // Conceptually, acquire/release semantics form unidirectional and
  71 // asynchronous barriers w.r.t. a synchronizing load(X) and store(X) pair.
  72 // They should always be used in pairs to publish (release store) and
  73 // access (load acquire) some implicitly understood shared data between
  74 // threads in a relatively cheap fashion not requiring storeload. If not
  75 // used in such a pair, it is adviced to use a membar instead:
  76 // acquire/release only make sense as pairs.
  77 //
  78 // T1: access_shared_data
  79 // T1: ]release
  80 // T1: (...)
  81 // T1: store(X)
  82 //
  83 // T2: load(X)
  84 // T2: (...)
  85 // T2: acquire[
  86 // T2: access_shared_data
  87 //
  88 // It is guaranteed that if T2: load(X) synchronizes with (observes the
  89 // value written by) T1: store(X), then the memory accesses before the T1:
  90 // ]release happen before the memory accesses after the T2: acquire[.
  91 //
  92 // Total Store Order (TSO) machines can be seen as machines issuing a
  93 // release store for each store and a load acquire for each load. Therefore
  94 // there is an inherent resemblence between TSO and acquire/release
  95 // semantics. TSO can be seen as an abstract machine where loads are
  96 // executed immediately when encountered (hence loadload reordering not
  97 // happening) but enqueues stores in a FIFO queue
  98 // for asynchronous serialization (neither storestore or loadstore
  99 // reordering happening). The only reordering happening is storeload due to
 100 // the queue asynchronously serializing stores (yet in order).
 101 //
 102 // Acquire/release semantics essentially exploits this asynchronicity: when
 103 // the load(X) acquire[ observes the store of ]release store(X), the
 104 // accesses before the release must have happened before the accesses after
 105 // acquire.
 106 //
 107 // The API offers both stand-alone acquire() and release() as well as joined
 108 // load_acquire() and release_store(). It is guaranteed that these are
 109 // semantically equivalent w.r.t. the defined model. However, since
 110 // stand-alone acquire()/release() does not know which previous
 111 // load/subsequent store is considered the synchronizing load/store, they
 112 // may be more conservative in implementations. We advice using the joined
 113 // variants whenever possible.
 114 //
 115 // Finally, we define a "fence" operation, as a bidirectional barrier.
 116 // It guarantees that any memory access preceding the fence is not
 117 // reordered w.r.t. any memory accesses subsequent to the fence in program
 118 // order. This may be used to prevent sequences of loads from floating up
 119 // above sequences of stores.
 120 //
 121 // The following table shows the implementations on some architectures:
 122 //
 123 //                       Constraint     x86          sparc              ppc
 124 // ---------------------------------------------------------------------------
 125 // fence                 LoadStore  |   lock         membar #StoreLoad  sync
 126 //                       StoreStore |   addl 0,(sp)
 127 //                       LoadLoad   |
 128 //                       StoreLoad
 129 //
 130 // release               LoadStore  |                                   lwsync
 131 //                       StoreStore
 132 //
 133 // acquire               LoadLoad   |                                   lwsync
 134 //                       LoadStore
 135 //
 136 // release_store                        <store>      <store>            lwsync
 137 //                                                                      <store>
 138 //
 139 // release_store_fence                  xchg         <store>            lwsync
 140 //                                                   membar #StoreLoad  <store>
 141 //                                                                      sync
 142 //
 143 //
 144 // load_acquire                         <load>       <load>             <load>
 145 //                                                                      lwsync
 146 //
 147 // Ordering a load relative to preceding stores requires a StoreLoad,
 148 // which implies a membar #StoreLoad between the store and load under
 149 // sparc-TSO. On x86, we use explicitly locked add.
 150 //
 151 // Conventional usage is to issue a load_acquire for ordered loads.  Use
 152 // release_store for ordered stores when you care only that prior stores
 153 // are visible before the release_store, but don't care exactly when the
 154 // store associated with the release_store becomes visible.  Use
 155 // release_store_fence to update values like the thread state, where we
 156 // don't want the current thread to continue until all our prior memory
 157 // accesses (including the new thread state) are visible to other threads.
 158 // This is equivalent to the volatile semantics of the Java Memory Model.
 159 //
 160 //
 161 //                os::is_MP Considered Redundant
 162 //
 163 // Callers of this interface do not need to test os::is_MP() before
 164 // issuing an operation. The test is taken care of by the implementation
 165 // of the interface (depending on the vm version and platform, the test
 166 // may or may not be actually done by the implementation).
 167 //
 168 //
 169 //                A Note on Memory Ordering and Cache Coherency
 170 //
 171 // Cache coherency and memory ordering are orthogonal concepts, though they
 172 // interact.  E.g., all existing itanium machines are cache-coherent, but
 173 // the hardware can freely reorder loads wrt other loads unless it sees a
 174 // load-acquire instruction.  All existing sparc machines are cache-coherent
 175 // and, unlike itanium, TSO guarantees that the hardware orders loads wrt
 176 // loads and stores, and stores wrt to each other.
 177 //
 178 // Consider the implementation of loadload.  *If* your platform *isn't*
 179 // cache-coherent, then loadload must not only prevent hardware load
 180 // instruction reordering, but it must *also* ensure that subsequent
 181 // loads from addresses that could be written by other processors (i.e.,
 182 // that are broadcast by other processors) go all the way to the first
 183 // level of memory shared by those processors and the one issuing
 184 // the loadload.
 185 //
 186 // So if we have a MP that has, say, a per-processor D$ that doesn't see
 187 // writes by other processors, and has a shared E$ that does, the loadload
 188 // barrier would have to make sure that either
 189 //
 190 // 1. cache lines in the issuing processor's D$ that contained data from
 191 // addresses that could be written by other processors are invalidated, so
 192 // subsequent loads from those addresses go to the E$, (it could do this
 193 // by tagging such cache lines as 'shared', though how to tell the hardware
 194 // to do the tagging is an interesting problem), or
 195 //
 196 // 2. there never are such cache lines in the issuing processor's D$, which
 197 // means all references to shared data (however identified: see above)
 198 // bypass the D$ (i.e., are satisfied from the E$).
 199 //
 200 // If your machine doesn't have an E$, substitute 'main memory' for 'E$'.
 201 //
 202 // Either of these alternatives is a pain, so no current machine we know of
 203 // has incoherent caches.
 204 //
 205 // If loadload didn't have these properties, the store-release sequence for
 206 // publishing a shared data structure wouldn't work, because a processor
 207 // trying to read data newly published by another processor might go to
 208 // its own incoherent caches to satisfy the read instead of to the newly
 209 // written shared memory.
 210 //
 211 //
 212 //                NOTE WELL!!
 213 //
 214 //                A Note on MutexLocker and Friends
 215 //
 216 // See mutexLocker.hpp.  We assume throughout the VM that MutexLocker's
 217 // and friends' constructors do a fence, a lock and an acquire *in that
 218 // order*.  And that their destructors do a release and unlock, in *that*
 219 // order.  If their implementations change such that these assumptions
 220 // are violated, a whole lot of code will break.
 221 
 222 enum ScopedFenceType {
 223     X_ACQUIRE
 224   , RELEASE_X
 225   , RELEASE_X_FENCE
 226 };
 227 
 228 template <ScopedFenceType T>
 229 class ScopedFenceGeneral: public StackObj {
 230  public:
 231   void prefix() {}
 232   void postfix() {}
 233 };
 234 
 235 template <ScopedFenceType T>
 236 class ScopedFence : public ScopedFenceGeneral<T> {
 237   void *const _field;
 238  public:
 239   ScopedFence(void *const field) : _field(field) { prefix(); }
 240   ~ScopedFence() { postfix(); }
 241   void prefix() { ScopedFenceGeneral<T>::prefix(); }
 242   void postfix() { ScopedFenceGeneral<T>::postfix(); }
 243 };
 244 
 245 // This class implements some fences for different platforms and specializes
 246 // the methods of its superclass using template specialization for improved performance.
 247 class OrderAccess : AllStatic {
 248  public:
 249   // barriers
 250   static void     loadload();
 251   static void     storestore();
 252   static void     loadstore();
 253   static void     storeload();
 254 
 255   static void     acquire();
 256   static void     release();
 257   static void     fence();
 258 
 259   static jbyte    load_acquire(volatile jbyte*   p);
 260   static jshort   load_acquire(volatile jshort*  p);
 261   static jint     load_acquire(volatile jint*    p);
 262   static jlong    load_acquire(volatile jlong*   p);
 263   static jubyte   load_acquire(volatile jubyte*  p);
 264   static jushort  load_acquire(volatile jushort* p);
 265   static juint    load_acquire(volatile juint*   p);
 266   static julong   load_acquire(volatile julong*  p);
 267   static jfloat   load_acquire(volatile jfloat*  p);
 268   static jdouble  load_acquire(volatile jdouble* p);
 269 
 270   static intptr_t load_ptr_acquire(volatile intptr_t*   p);
 271   static void*    load_ptr_acquire(volatile void*       p);
 272   static void*    load_ptr_acquire(const volatile void* p);
 273 
 274   static void     release_store(volatile jbyte*   p, jbyte   v);
 275   static void     release_store(volatile jshort*  p, jshort  v);
 276   static void     release_store(volatile jint*    p, jint    v);
 277   static void     release_store(volatile jlong*   p, jlong   v);
 278   static void     release_store(volatile jubyte*  p, jubyte  v);
 279   static void     release_store(volatile jushort* p, jushort v);
 280   static void     release_store(volatile juint*   p, juint   v);
 281   static void     release_store(volatile julong*  p, julong  v);
 282   static void     release_store(volatile jfloat*  p, jfloat  v);
 283   static void     release_store(volatile jdouble* p, jdouble v);
 284 
 285   static void     release_store_ptr(volatile intptr_t* p, intptr_t v);
 286   static void     release_store_ptr(volatile void*     p, void*    v);
 287 
 288   static void     release_store_fence(volatile jbyte*   p, jbyte   v);
 289   static void     release_store_fence(volatile jshort*  p, jshort  v);
 290   static void     release_store_fence(volatile jint*    p, jint    v);
 291   static void     release_store_fence(volatile jlong*   p, jlong   v);
 292   static void     release_store_fence(volatile jubyte*  p, jubyte  v);
 293   static void     release_store_fence(volatile jushort* p, jushort v);
 294   static void     release_store_fence(volatile juint*   p, juint   v);
 295   static void     release_store_fence(volatile julong*  p, julong  v);
 296   static void     release_store_fence(volatile jfloat*  p, jfloat  v);
 297   static void     release_store_fence(volatile jdouble* p, jdouble v);
 298 
 299   static void     release_store_ptr_fence(volatile intptr_t* p, intptr_t v);
 300   static void     release_store_ptr_fence(volatile void*     p, void*    v);
 301 
 302  private:
 303   // This is a helper that invokes the StubRoutines::fence_entry()
 304   // routine if it exists, It should only be used by platforms that
 305   // don't have another way to do the inline assembly.
 306   static void StubRoutines_fence();
 307 
 308   // Give platforms a varation point to specialize.
 309   template<typename T> static T    specialized_load_acquire       (volatile T* p     );
 310   template<typename T> static void specialized_release_store      (volatile T* p, T v);
 311   template<typename T> static void specialized_release_store_fence(volatile T* p, T v);
 312 
 313   template<typename FieldType, ScopedFenceType FenceType>
 314   static void ordered_store(volatile FieldType* p, FieldType v);
 315 
 316   template<typename FieldType, ScopedFenceType FenceType>
 317   static FieldType ordered_load(volatile FieldType* p);
 318 
 319   static void    store(volatile jbyte*   p, jbyte   v);
 320   static void    store(volatile jshort*  p, jshort  v);
 321   static void    store(volatile jint*    p, jint    v);
 322   static void    store(volatile jlong*   p, jlong   v);
 323   static void    store(volatile jdouble* p, jdouble v);
 324   static void    store(volatile jfloat*  p, jfloat  v);
 325 
 326   static jbyte   load (volatile jbyte*   p);
 327   static jshort  load (volatile jshort*  p);
 328   static jint    load (volatile jint*    p);
 329   static jlong   load (volatile jlong*   p);
 330   static jdouble load (volatile jdouble* p);
 331   static jfloat  load (volatile jfloat*  p);
 332 
 333   // The following store_fence methods are deprecated and will be removed
 334   // when all repos conform to the new generalized OrderAccess.
 335   static void    store_fence(jbyte*   p, jbyte   v);
 336   static void    store_fence(jshort*  p, jshort  v);
 337   static void    store_fence(jint*    p, jint    v);
 338   static void    store_fence(jlong*   p, jlong   v);
 339   static void    store_fence(jubyte*  p, jubyte  v);
 340   static void    store_fence(jushort* p, jushort v);
 341   static void    store_fence(juint*   p, juint   v);
 342   static void    store_fence(julong*  p, julong  v);
 343   static void    store_fence(jfloat*  p, jfloat  v);
 344   static void    store_fence(jdouble* p, jdouble v);
 345 
 346   static void    store_ptr_fence(intptr_t* p, intptr_t v);
 347   static void    store_ptr_fence(void**    p, void*    v);
 348 };
 349 
 350 #endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP