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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp

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   1 /*
   2  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


3974     }
3975     __ jcc(acond, ok);
3976   }
3977   if (op->halt()) {
3978     const char* str = __ code_string(op->msg());
3979     __ stop(str);
3980   } else {
3981     breakpoint();
3982   }
3983   __ bind(ok);
3984 }
3985 #endif
3986 
3987 void LIR_Assembler::membar() {
3988   // QQQ sparc TSO uses this,
3989   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3990 }
3991 
3992 void LIR_Assembler::membar_acquire() {
3993   // No x86 machines currently require load fences
3994   // __ load_fence();
3995 }
3996 
3997 void LIR_Assembler::membar_release() {
3998   // No x86 machines currently require store fences
3999   // __ store_fence();
4000 }
4001 
4002 void LIR_Assembler::membar_loadload() {
4003   // no-op
4004   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4005 }
4006 
4007 void LIR_Assembler::membar_storestore() {
4008   // no-op
4009   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4010 }
4011 
4012 void LIR_Assembler::membar_loadstore() {
4013   // no-op
4014   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4015 }
4016 
4017 void LIR_Assembler::membar_storeload() {
4018   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4019 }


   1 /*
   2  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


3974     }
3975     __ jcc(acond, ok);
3976   }
3977   if (op->halt()) {
3978     const char* str = __ code_string(op->msg());
3979     __ stop(str);
3980   } else {
3981     breakpoint();
3982   }
3983   __ bind(ok);
3984 }
3985 #endif
3986 
3987 void LIR_Assembler::membar() {
3988   // QQQ sparc TSO uses this,
3989   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3990 }
3991 
3992 void LIR_Assembler::membar_acquire() {
3993   // No x86 machines currently require load fences

3994 }
3995 
3996 void LIR_Assembler::membar_release() {
3997   // No x86 machines currently require store fences

3998 }
3999 
4000 void LIR_Assembler::membar_loadload() {
4001   // no-op
4002   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4003 }
4004 
4005 void LIR_Assembler::membar_storestore() {
4006   // no-op
4007   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4008 }
4009 
4010 void LIR_Assembler::membar_loadstore() {
4011   // no-op
4012   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4013 }
4014 
4015 void LIR_Assembler::membar_storeload() {
4016   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4017 }


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