1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2014, SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_INLINE_HPP 27 #define OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_INLINE_HPP 28 29 #include "runtime/orderAccess.hpp" 30 31 #ifndef PPC64 32 #error "OrderAccess currently only implemented for PPC64" 33 #endif 34 35 // Implementation of class OrderAccess. 36 37 // 38 // Machine barrier instructions: 39 // 40 // - sync Two-way memory barrier, aka fence. 41 // - lwsync orders Store|Store, 42 // Load|Store, 43 // Load|Load, 44 // but not Store|Load 45 // - eieio orders Store|Store 46 // - isync Invalidates speculatively executed instructions, 47 // but isync may complete before storage accesses 48 // associated with instructions preceding isync have 49 // been performed. 50 // 51 // Semantic barrier instructions: 52 // (as defined in orderAccess.hpp) 53 // 54 // - release orders Store|Store, (maps to lwsync) 55 // Load|Store 56 // - acquire orders Load|Store, (maps to lwsync) 57 // Load|Load 58 // - fence orders Store|Store, (maps to sync) 59 // Load|Store, 60 // Load|Load, 61 // Store|Load 62 // 63 64 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory"); 65 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory"); 66 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory"); 67 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory"); 68 // Use twi-isync for load_acquire (faster than lwsync). 69 #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory"); 70 71 inline void OrderAccess::loadload() { inlasm_lwsync(); } 72 inline void OrderAccess::storestore() { inlasm_lwsync(); } 73 inline void OrderAccess::loadstore() { inlasm_lwsync(); } 74 inline void OrderAccess::storeload() { inlasm_sync(); } 75 76 inline void OrderAccess::acquire() { inlasm_lwsync(); } 77 inline void OrderAccess::release() { inlasm_lwsync(); } 78 inline void OrderAccess::fence() { inlasm_sync(); } 79 80 template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte* p) { register jbyte t = load(p); inlasm_acquire_reg(t); return t; } 81 template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = load(p); inlasm_acquire_reg(t); return t; } 82 template<> inline jint OrderAccess::specialized_load_acquire<jint> (volatile jint* p) { register jint t = load(p); inlasm_acquire_reg(t); return t; } 83 template<> inline jlong OrderAccess::specialized_load_acquire<jlong> (volatile jlong* p) { register jlong t = load(p); inlasm_acquire_reg(t); return t; } 84 85 #undef inlasm_sync 86 #undef inlasm_lwsync 87 #undef inlasm_eieio 88 #undef inlasm_isync 89 #undef inlasm_acquire_reg 90 91 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1 92 93 #endif // OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_INLINE_HPP