1 /* 2 * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2007, 2008, 2009 Red Hat, Inc. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP 27 #define OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP 28 29 #include "runtime/orderAccess.hpp" 30 31 #ifdef ARM 32 33 /* 34 * ARM Kernel helper for memory barrier. 35 * Using __asm __volatile ("":::"memory") does not work reliable on ARM 36 * and gcc __sync_synchronize(); implementation does not use the kernel 37 * helper for all gcc versions so it is unreliable to use as well. 38 */ 39 typedef void (__kernel_dmb_t) (void); 40 #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) 41 42 #define FULL_MEM_BARRIER __kernel_dmb() 43 #define READ_MEM_BARRIER __kernel_dmb() 44 #define WRITE_MEM_BARRIER __kernel_dmb() 45 46 #else // ARM 47 48 #define FULL_MEM_BARRIER __sync_synchronize() 49 50 #ifdef PPC 51 52 #define READ_MEM_BARRIER __asm __volatile ("isync":::"memory") 53 #ifdef __NO_LWSYNC__ 54 #define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory") 55 #else 56 #define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory") 57 #endif 58 59 #else // PPC 60 61 #define READ_MEM_BARRIER __asm __volatile ("":::"memory") 62 #define WRITE_MEM_BARRIER __asm __volatile ("":::"memory") 63 64 #endif // PPC 65 66 #endif // ARM 67 68 69 inline void OrderAccess::loadload() { acquire(); } 70 inline void OrderAccess::storestore() { release(); } 71 inline void OrderAccess::loadstore() { acquire(); } 72 inline void OrderAccess::storeload() { fence(); } 73 74 inline void OrderAccess::acquire() { 75 READ_MEM_BARRIER; 76 } 77 78 inline void OrderAccess::release() { 79 WRITE_MEM_BARRIER; 80 } 81 82 inline void OrderAccess::fence() { 83 FULL_MEM_BARRIER; 84 } 85 86 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; } 87 inline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort data = *p; acquire(); return data; } 88 inline jint OrderAccess::load_acquire(volatile jint* p) { jint data = *p; acquire(); return data; } 89 inline jlong OrderAccess::load_acquire(volatile jlong* p) { 90 jlong tmp; 91 os::atomic_copy64(p, &tmp); 92 acquire(); 93 return tmp; 94 } 95 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte data = *p; acquire(); return data; } 96 inline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort data = *p; acquire(); return data; } 97 inline juint OrderAccess::load_acquire(volatile juint* p) { juint data = *p; acquire(); return data; } 98 inline julong OrderAccess::load_acquire(volatile julong* p) { 99 julong tmp; 100 os::atomic_copy64(p, &tmp); 101 acquire(); 102 return tmp; 103 } 104 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat data = *p; acquire(); return data; } 105 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { 106 jdouble tmp; 107 os::atomic_copy64(p, &tmp); 108 acquire(); 109 return tmp; 110 } 111 112 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { 113 intptr_t data = *p; 114 acquire(); 115 return data; 116 } 117 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { 118 void *data = *(void* volatile *)p; 119 acquire(); 120 return data; 121 } 122 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { 123 void *data = *(void* const volatile *)p; 124 acquire(); 125 return data; 126 } 127 128 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { release(); *p = v; } 129 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { release(); *p = v; } 130 inline void OrderAccess::release_store(volatile jint* p, jint v) { release(); *p = v; } 131 inline void OrderAccess::release_store(volatile jlong* p, jlong v) 132 { release(); os::atomic_copy64(&v, p); } 133 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { release(); *p = v; } 134 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { release(); *p = v; } 135 inline void OrderAccess::release_store(volatile juint* p, juint v) { release(); *p = v; } 136 inline void OrderAccess::release_store(volatile julong* p, julong v) 137 { release(); os::atomic_copy64(&v, p); } 138 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { release(); *p = v; } 139 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) 140 { release(); os::atomic_copy64(&v, p); } 141 142 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { release(); *p = v; } 143 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) 144 { release(); *(void* volatile *)p = v; } 145 146 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); } 147 inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); } 148 inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); } 149 inline void OrderAccess::store_fence(jlong* p, jlong v) { os::atomic_copy64(&v, p); fence(); } 150 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); } 151 inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); } 152 inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); } 153 inline void OrderAccess::store_fence(julong* p, julong v) { os::atomic_copy64(&v, p); fence(); } 154 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); } 155 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { os::atomic_copy64(&v, p); fence(); } 156 157 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); } 158 inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); } 159 160 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { release_store(p, v); fence(); } 161 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { release_store(p, v); fence(); } 162 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { release_store(p, v); fence(); } 163 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); } 164 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store(p, v); fence(); } 165 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store(p, v); fence(); } 166 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store(p, v); fence(); } 167 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); } 168 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { release_store(p, v); fence(); } 169 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store(p, v); fence(); } 170 171 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { release_store_ptr(p, v); fence(); } 172 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { release_store_ptr(p, v); fence(); } 173 174 #endif // OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP | 1 /* 2 * Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2007, 2008, 2009 Red Hat, Inc. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP 27 #define OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP 28 29 #include "runtime/orderAccess.hpp" 30 31 #ifdef ARM 32 33 /* 34 * ARM Kernel helper for memory barrier. 35 * Using __asm __volatile ("":::"memory") does not work reliable on ARM 36 * and gcc __sync_synchronize(); implementation does not use the kernel 37 * helper for all gcc versions so it is unreliable to use as well. 38 */ 39 typedef void (__kernel_dmb_t) (void); 40 #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) 41 42 #define FULL_MEM_BARRIER __kernel_dmb() 43 #define LIGHT_MEM_BARRIER __kernel_dmb() 44 45 #else // ARM 46 47 #define FULL_MEM_BARRIER __sync_synchronize() 48 49 #ifdef PPC 50 51 #ifdef __NO_LWSYNC__ 52 #define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory") 53 #else 54 #define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory") 55 #endif 56 57 #else // PPC 58 59 #define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory") 60 61 #endif // PPC 62 63 #endif // ARM 64 65 // Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient 66 // to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore. 67 68 inline void OrderAccess::loadload() { LIGHT_MEM_BARRIER; } 69 inline void OrderAccess::storestore() { LIGHT_MEM_BARRIER; } 70 inline void OrderAccess::loadstore() { LIGHT_MEM_BARRIER; } 71 inline void OrderAccess::storeload() { FULL_MEM_BARRIER; } 72 73 inline void OrderAccess::acquire() { LIGHT_MEM_BARRIER; } 74 inline void OrderAccess::release() { LIGHT_MEM_BARRIER; } 75 76 inline void OrderAccess::fence() { FULL_MEM_BARRIER; } 77 78 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1 79 80 #endif // OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP |