1 /* 2 * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP 26 #define OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP 27 28 #include "runtime/atomic.inline.hpp" 29 #include "runtime/orderAccess.hpp" 30 #include "runtime/os.hpp" 31 32 // Implementation of class OrderAccess. 33 34 inline void OrderAccess::loadload() { acquire(); } 35 inline void OrderAccess::storestore() { release(); } 36 inline void OrderAccess::loadstore() { acquire(); } 37 inline void OrderAccess::storeload() { fence(); } 38 39 inline void OrderAccess::acquire() { 40 #ifndef AMD64 41 __asm { 42 mov eax, dword ptr [esp]; 43 } 44 #endif // !AMD64 45 } 46 47 inline void OrderAccess::release() { 48 // A volatile store has release semantics. 49 volatile jint local_dummy = 0; 50 } 51 52 inline void OrderAccess::fence() { 53 #ifdef AMD64 54 StubRoutines_fence(); 55 #else 56 if (os::is_MP()) { 57 __asm { 58 lock add dword ptr [esp], 0; 59 } 60 } 61 #endif // AMD64 62 } 63 64 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; } 65 inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; } 66 inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; } 67 inline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); } 68 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; } 69 inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; } 70 inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; } 71 inline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); } 72 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; } 73 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return jdouble_cast(Atomic::load((volatile jlong*)p)); } 74 75 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; } 76 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; } 77 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; } 78 79 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; } 80 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; } 81 inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; } 82 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); } 83 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; } 84 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; } 85 inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; } 86 inline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); } 87 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; } 88 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { release_store((volatile jlong*)p, jlong_cast(v)); } 89 90 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; } 91 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; } 92 93 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { 94 #ifdef AMD64 95 *p = v; fence(); 96 #else 97 __asm { 98 mov edx, p; 99 mov al, v; 100 xchg al, byte ptr [edx]; 101 } 102 #endif // AMD64 103 } 104 105 inline void OrderAccess::store_fence(jshort* p, jshort v) { 106 #ifdef AMD64 107 *p = v; fence(); 108 #else 109 __asm { 110 mov edx, p; 111 mov ax, v; 112 xchg ax, word ptr [edx]; 113 } 114 #endif // AMD64 115 } 116 117 inline void OrderAccess::store_fence(jint* p, jint v) { 118 #ifdef AMD64 119 *p = v; fence(); 120 #else 121 __asm { 122 mov edx, p; 123 mov eax, v; 124 xchg eax, dword ptr [edx]; 125 } 126 #endif // AMD64 127 } 128 129 inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); } 130 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); } 131 inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); } 132 inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); } 133 inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); } 134 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); } 135 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); } 136 137 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { 138 #ifdef AMD64 139 *p = v; fence(); 140 #else 141 store_fence((jint*)p, (jint)v); 142 #endif // AMD64 143 } 144 145 inline void OrderAccess::store_ptr_fence(void** p, void* v) { 146 #ifdef AMD64 147 *p = v; fence(); 148 #else 149 store_fence((jint*)p, (jint)v); 150 #endif // AMD64 151 } 152 153 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile. 154 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { 155 #ifdef AMD64 156 *p = v; fence(); 157 #else 158 __asm { 159 mov edx, p; 160 mov al, v; 161 xchg al, byte ptr [edx]; 162 } 163 #endif // AMD64 164 } 165 166 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { 167 #ifdef AMD64 168 *p = v; fence(); 169 #else 170 __asm { 171 mov edx, p; 172 mov ax, v; 173 xchg ax, word ptr [edx]; 174 } 175 #endif // AMD64 176 } 177 178 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { 179 #ifdef AMD64 180 *p = v; fence(); 181 #else 182 __asm { 183 mov edx, p; 184 mov eax, v; 185 xchg eax, dword ptr [edx]; 186 } 187 #endif // AMD64 188 } 189 190 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); } 191 192 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); } 193 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); } 194 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); } 195 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); } 196 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); } 197 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store_fence((volatile jlong*)p, jlong_cast(v)); } 198 199 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { 200 #ifdef AMD64 201 *p = v; fence(); 202 #else 203 release_store_fence((volatile jint*)p, (jint)v); 204 #endif // AMD64 205 } 206 207 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { 208 #ifdef AMD64 209 *(void* volatile *)p = v; fence(); 210 #else 211 release_store_fence((volatile jint*)p, (jint)v); 212 #endif // AMD64 213 } 214 215 #endif // OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP