1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 51 #ifdef PRODUCT 52 #define BLOCK_COMMENT(str) /* nothing */ 53 #define STOP(error) stop(error) 54 #else 55 #define BLOCK_COMMENT(str) block_comment(str) 56 #define STOP(error) block_comment(error); stop(error) 57 #endif 58 59 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 60 61 #ifdef ASSERT 62 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 63 #endif 64 65 static Assembler::Condition reverse[] = { 66 Assembler::noOverflow /* overflow = 0x0 */ , 67 Assembler::overflow /* noOverflow = 0x1 */ , 68 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 69 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 70 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 71 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 72 Assembler::above /* belowEqual = 0x6 */ , 73 Assembler::belowEqual /* above = 0x7 */ , 74 Assembler::positive /* negative = 0x8 */ , 75 Assembler::negative /* positive = 0x9 */ , 76 Assembler::noParity /* parity = 0xa */ , 77 Assembler::parity /* noParity = 0xb */ , 78 Assembler::greaterEqual /* less = 0xc */ , 79 Assembler::less /* greaterEqual = 0xd */ , 80 Assembler::greater /* lessEqual = 0xe */ , 81 Assembler::lessEqual /* greater = 0xf, */ 82 83 }; 84 85 86 // Implementation of MacroAssembler 87 88 // First all the versions that have distinct versions depending on 32/64 bit 89 // Unless the difference is trivial (1 line or so). 90 91 #ifndef _LP64 92 93 // 32bit versions 94 95 Address MacroAssembler::as_Address(AddressLiteral adr) { 96 return Address(adr.target(), adr.rspec()); 97 } 98 99 Address MacroAssembler::as_Address(ArrayAddress adr) { 100 return Address::make_array(adr); 101 } 102 103 void MacroAssembler::call_VM_leaf_base(address entry_point, 104 int number_of_arguments) { 105 call(RuntimeAddress(entry_point)); 106 increment(rsp, number_of_arguments * wordSize); 107 } 108 109 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 110 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 111 } 112 113 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 115 } 116 117 void MacroAssembler::cmpoop(Address src1, jobject obj) { 118 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 119 } 120 121 void MacroAssembler::cmpoop(Register src1, jobject obj) { 122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 123 } 124 125 void MacroAssembler::extend_sign(Register hi, Register lo) { 126 // According to Intel Doc. AP-526, "Integer Divide", p.18. 127 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 128 cdql(); 129 } else { 130 movl(hi, lo); 131 sarl(hi, 31); 132 } 133 } 134 135 void MacroAssembler::jC2(Register tmp, Label& L) { 136 // set parity bit if FPU flag C2 is set (via rax) 137 save_rax(tmp); 138 fwait(); fnstsw_ax(); 139 sahf(); 140 restore_rax(tmp); 141 // branch 142 jcc(Assembler::parity, L); 143 } 144 145 void MacroAssembler::jnC2(Register tmp, Label& L) { 146 // set parity bit if FPU flag C2 is set (via rax) 147 save_rax(tmp); 148 fwait(); fnstsw_ax(); 149 sahf(); 150 restore_rax(tmp); 151 // branch 152 jcc(Assembler::noParity, L); 153 } 154 155 // 32bit can do a case table jump in one instruction but we no longer allow the base 156 // to be installed in the Address class 157 void MacroAssembler::jump(ArrayAddress entry) { 158 jmp(as_Address(entry)); 159 } 160 161 // Note: y_lo will be destroyed 162 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 163 // Long compare for Java (semantics as described in JVM spec.) 164 Label high, low, done; 165 166 cmpl(x_hi, y_hi); 167 jcc(Assembler::less, low); 168 jcc(Assembler::greater, high); 169 // x_hi is the return register 170 xorl(x_hi, x_hi); 171 cmpl(x_lo, y_lo); 172 jcc(Assembler::below, low); 173 jcc(Assembler::equal, done); 174 175 bind(high); 176 xorl(x_hi, x_hi); 177 increment(x_hi); 178 jmp(done); 179 180 bind(low); 181 xorl(x_hi, x_hi); 182 decrementl(x_hi); 183 184 bind(done); 185 } 186 187 void MacroAssembler::lea(Register dst, AddressLiteral src) { 188 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 189 } 190 191 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 192 // leal(dst, as_Address(adr)); 193 // see note in movl as to why we must use a move 194 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 195 } 196 197 void MacroAssembler::leave() { 198 mov(rsp, rbp); 199 pop(rbp); 200 } 201 202 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 203 // Multiplication of two Java long values stored on the stack 204 // as illustrated below. Result is in rdx:rax. 205 // 206 // rsp ---> [ ?? ] \ \ 207 // .... | y_rsp_offset | 208 // [ y_lo ] / (in bytes) | x_rsp_offset 209 // [ y_hi ] | (in bytes) 210 // .... | 211 // [ x_lo ] / 212 // [ x_hi ] 213 // .... 214 // 215 // Basic idea: lo(result) = lo(x_lo * y_lo) 216 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 217 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 218 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 219 Label quick; 220 // load x_hi, y_hi and check if quick 221 // multiplication is possible 222 movl(rbx, x_hi); 223 movl(rcx, y_hi); 224 movl(rax, rbx); 225 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 226 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 227 // do full multiplication 228 // 1st step 229 mull(y_lo); // x_hi * y_lo 230 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 231 // 2nd step 232 movl(rax, x_lo); 233 mull(rcx); // x_lo * y_hi 234 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 235 // 3rd step 236 bind(quick); // note: rbx, = 0 if quick multiply! 237 movl(rax, x_lo); 238 mull(y_lo); // x_lo * y_lo 239 addl(rdx, rbx); // correct hi(x_lo * y_lo) 240 } 241 242 void MacroAssembler::lneg(Register hi, Register lo) { 243 negl(lo); 244 adcl(hi, 0); 245 negl(hi); 246 } 247 248 void MacroAssembler::lshl(Register hi, Register lo) { 249 // Java shift left long support (semantics as described in JVM spec., p.305) 250 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 251 // shift value is in rcx ! 252 assert(hi != rcx, "must not use rcx"); 253 assert(lo != rcx, "must not use rcx"); 254 const Register s = rcx; // shift count 255 const int n = BitsPerWord; 256 Label L; 257 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 258 cmpl(s, n); // if (s < n) 259 jcc(Assembler::less, L); // else (s >= n) 260 movl(hi, lo); // x := x << n 261 xorl(lo, lo); 262 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 263 bind(L); // s (mod n) < n 264 shldl(hi, lo); // x := x << s 265 shll(lo); 266 } 267 268 269 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 270 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 271 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 272 assert(hi != rcx, "must not use rcx"); 273 assert(lo != rcx, "must not use rcx"); 274 const Register s = rcx; // shift count 275 const int n = BitsPerWord; 276 Label L; 277 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 278 cmpl(s, n); // if (s < n) 279 jcc(Assembler::less, L); // else (s >= n) 280 movl(lo, hi); // x := x >> n 281 if (sign_extension) sarl(hi, 31); 282 else xorl(hi, hi); 283 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 284 bind(L); // s (mod n) < n 285 shrdl(lo, hi); // x := x >> s 286 if (sign_extension) sarl(hi); 287 else shrl(hi); 288 } 289 290 void MacroAssembler::movoop(Register dst, jobject obj) { 291 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 292 } 293 294 void MacroAssembler::movoop(Address dst, jobject obj) { 295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 296 } 297 298 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 299 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 300 } 301 302 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 304 } 305 306 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 307 // scratch register is not used, 308 // it is defined to match parameters of 64-bit version of this method. 309 if (src.is_lval()) { 310 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 311 } else { 312 movl(dst, as_Address(src)); 313 } 314 } 315 316 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 317 movl(as_Address(dst), src); 318 } 319 320 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 321 movl(dst, as_Address(src)); 322 } 323 324 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 325 void MacroAssembler::movptr(Address dst, intptr_t src) { 326 movl(dst, src); 327 } 328 329 330 void MacroAssembler::pop_callee_saved_registers() { 331 pop(rcx); 332 pop(rdx); 333 pop(rdi); 334 pop(rsi); 335 } 336 337 void MacroAssembler::pop_fTOS() { 338 fld_d(Address(rsp, 0)); 339 addl(rsp, 2 * wordSize); 340 } 341 342 void MacroAssembler::push_callee_saved_registers() { 343 push(rsi); 344 push(rdi); 345 push(rdx); 346 push(rcx); 347 } 348 349 void MacroAssembler::push_fTOS() { 350 subl(rsp, 2 * wordSize); 351 fstp_d(Address(rsp, 0)); 352 } 353 354 355 void MacroAssembler::pushoop(jobject obj) { 356 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 357 } 358 359 void MacroAssembler::pushklass(Metadata* obj) { 360 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 361 } 362 363 void MacroAssembler::pushptr(AddressLiteral src) { 364 if (src.is_lval()) { 365 push_literal32((int32_t)src.target(), src.rspec()); 366 } else { 367 pushl(as_Address(src)); 368 } 369 } 370 371 void MacroAssembler::set_word_if_not_zero(Register dst) { 372 xorl(dst, dst); 373 set_byte_if_not_zero(dst); 374 } 375 376 static void pass_arg0(MacroAssembler* masm, Register arg) { 377 masm->push(arg); 378 } 379 380 static void pass_arg1(MacroAssembler* masm, Register arg) { 381 masm->push(arg); 382 } 383 384 static void pass_arg2(MacroAssembler* masm, Register arg) { 385 masm->push(arg); 386 } 387 388 static void pass_arg3(MacroAssembler* masm, Register arg) { 389 masm->push(arg); 390 } 391 392 #ifndef PRODUCT 393 extern "C" void findpc(intptr_t x); 394 #endif 395 396 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 397 // In order to get locks to work, we need to fake a in_VM state 398 JavaThread* thread = JavaThread::current(); 399 JavaThreadState saved_state = thread->thread_state(); 400 thread->set_thread_state(_thread_in_vm); 401 if (ShowMessageBoxOnError) { 402 JavaThread* thread = JavaThread::current(); 403 JavaThreadState saved_state = thread->thread_state(); 404 thread->set_thread_state(_thread_in_vm); 405 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 406 ttyLocker ttyl; 407 BytecodeCounter::print(); 408 } 409 // To see where a verify_oop failed, get $ebx+40/X for this frame. 410 // This is the value of eip which points to where verify_oop will return. 411 if (os::message_box(msg, "Execution stopped, print registers?")) { 412 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 413 BREAKPOINT; 414 } 415 } else { 416 ttyLocker ttyl; 417 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 418 } 419 // Don't assert holding the ttyLock 420 assert(false, "DEBUG MESSAGE: %s", msg); 421 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 422 } 423 424 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 425 ttyLocker ttyl; 426 FlagSetting fs(Debugging, true); 427 tty->print_cr("eip = 0x%08x", eip); 428 #ifndef PRODUCT 429 if ((WizardMode || Verbose) && PrintMiscellaneous) { 430 tty->cr(); 431 findpc(eip); 432 tty->cr(); 433 } 434 #endif 435 #define PRINT_REG(rax) \ 436 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 437 PRINT_REG(rax); 438 PRINT_REG(rbx); 439 PRINT_REG(rcx); 440 PRINT_REG(rdx); 441 PRINT_REG(rdi); 442 PRINT_REG(rsi); 443 PRINT_REG(rbp); 444 PRINT_REG(rsp); 445 #undef PRINT_REG 446 // Print some words near top of staack. 447 int* dump_sp = (int*) rsp; 448 for (int col1 = 0; col1 < 8; col1++) { 449 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 450 os::print_location(tty, *dump_sp++); 451 } 452 for (int row = 0; row < 16; row++) { 453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 454 for (int col = 0; col < 8; col++) { 455 tty->print(" 0x%08x", *dump_sp++); 456 } 457 tty->cr(); 458 } 459 // Print some instructions around pc: 460 Disassembler::decode((address)eip-64, (address)eip); 461 tty->print_cr("--------"); 462 Disassembler::decode((address)eip, (address)eip+32); 463 } 464 465 void MacroAssembler::stop(const char* msg) { 466 ExternalAddress message((address)msg); 467 // push address of message 468 pushptr(message.addr()); 469 { Label L; call(L, relocInfo::none); bind(L); } // push eip 470 pusha(); // push registers 471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 472 hlt(); 473 } 474 475 void MacroAssembler::warn(const char* msg) { 476 push_CPU_state(); 477 478 ExternalAddress message((address) msg); 479 // push address of message 480 pushptr(message.addr()); 481 482 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 483 addl(rsp, wordSize); // discard argument 484 pop_CPU_state(); 485 } 486 487 void MacroAssembler::print_state() { 488 { Label L; call(L, relocInfo::none); bind(L); } // push eip 489 pusha(); // push registers 490 491 push_CPU_state(); 492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 493 pop_CPU_state(); 494 495 popa(); 496 addl(rsp, wordSize); 497 } 498 499 #else // _LP64 500 501 // 64 bit versions 502 503 Address MacroAssembler::as_Address(AddressLiteral adr) { 504 // amd64 always does this as a pc-rel 505 // we can be absolute or disp based on the instruction type 506 // jmp/call are displacements others are absolute 507 assert(!adr.is_lval(), "must be rval"); 508 assert(reachable(adr), "must be"); 509 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 510 511 } 512 513 Address MacroAssembler::as_Address(ArrayAddress adr) { 514 AddressLiteral base = adr.base(); 515 lea(rscratch1, base); 516 Address index = adr.index(); 517 assert(index._disp == 0, "must not have disp"); // maybe it can? 518 Address array(rscratch1, index._index, index._scale, index._disp); 519 return array; 520 } 521 522 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 523 Label L, E; 524 525 #ifdef _WIN64 526 // Windows always allocates space for it's register args 527 assert(num_args <= 4, "only register arguments supported"); 528 subq(rsp, frame::arg_reg_save_area_bytes); 529 #endif 530 531 // Align stack if necessary 532 testl(rsp, 15); 533 jcc(Assembler::zero, L); 534 535 subq(rsp, 8); 536 { 537 call(RuntimeAddress(entry_point)); 538 } 539 addq(rsp, 8); 540 jmp(E); 541 542 bind(L); 543 { 544 call(RuntimeAddress(entry_point)); 545 } 546 547 bind(E); 548 549 #ifdef _WIN64 550 // restore stack pointer 551 addq(rsp, frame::arg_reg_save_area_bytes); 552 #endif 553 554 } 555 556 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 557 assert(!src2.is_lval(), "should use cmpptr"); 558 559 if (reachable(src2)) { 560 cmpq(src1, as_Address(src2)); 561 } else { 562 lea(rscratch1, src2); 563 Assembler::cmpq(src1, Address(rscratch1, 0)); 564 } 565 } 566 567 int MacroAssembler::corrected_idivq(Register reg) { 568 // Full implementation of Java ldiv and lrem; checks for special 569 // case as described in JVM spec., p.243 & p.271. The function 570 // returns the (pc) offset of the idivl instruction - may be needed 571 // for implicit exceptions. 572 // 573 // normal case special case 574 // 575 // input : rax: dividend min_long 576 // reg: divisor (may not be eax/edx) -1 577 // 578 // output: rax: quotient (= rax idiv reg) min_long 579 // rdx: remainder (= rax irem reg) 0 580 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 581 static const int64_t min_long = 0x8000000000000000; 582 Label normal_case, special_case; 583 584 // check for special case 585 cmp64(rax, ExternalAddress((address) &min_long)); 586 jcc(Assembler::notEqual, normal_case); 587 xorl(rdx, rdx); // prepare rdx for possible special case (where 588 // remainder = 0) 589 cmpq(reg, -1); 590 jcc(Assembler::equal, special_case); 591 592 // handle normal case 593 bind(normal_case); 594 cdqq(); 595 int idivq_offset = offset(); 596 idivq(reg); 597 598 // normal and special case exit 599 bind(special_case); 600 601 return idivq_offset; 602 } 603 604 void MacroAssembler::decrementq(Register reg, int value) { 605 if (value == min_jint) { subq(reg, value); return; } 606 if (value < 0) { incrementq(reg, -value); return; } 607 if (value == 0) { ; return; } 608 if (value == 1 && UseIncDec) { decq(reg) ; return; } 609 /* else */ { subq(reg, value) ; return; } 610 } 611 612 void MacroAssembler::decrementq(Address dst, int value) { 613 if (value == min_jint) { subq(dst, value); return; } 614 if (value < 0) { incrementq(dst, -value); return; } 615 if (value == 0) { ; return; } 616 if (value == 1 && UseIncDec) { decq(dst) ; return; } 617 /* else */ { subq(dst, value) ; return; } 618 } 619 620 void MacroAssembler::incrementq(AddressLiteral dst) { 621 if (reachable(dst)) { 622 incrementq(as_Address(dst)); 623 } else { 624 lea(rscratch1, dst); 625 incrementq(Address(rscratch1, 0)); 626 } 627 } 628 629 void MacroAssembler::incrementq(Register reg, int value) { 630 if (value == min_jint) { addq(reg, value); return; } 631 if (value < 0) { decrementq(reg, -value); return; } 632 if (value == 0) { ; return; } 633 if (value == 1 && UseIncDec) { incq(reg) ; return; } 634 /* else */ { addq(reg, value) ; return; } 635 } 636 637 void MacroAssembler::incrementq(Address dst, int value) { 638 if (value == min_jint) { addq(dst, value); return; } 639 if (value < 0) { decrementq(dst, -value); return; } 640 if (value == 0) { ; return; } 641 if (value == 1 && UseIncDec) { incq(dst) ; return; } 642 /* else */ { addq(dst, value) ; return; } 643 } 644 645 // 32bit can do a case table jump in one instruction but we no longer allow the base 646 // to be installed in the Address class 647 void MacroAssembler::jump(ArrayAddress entry) { 648 lea(rscratch1, entry.base()); 649 Address dispatch = entry.index(); 650 assert(dispatch._base == noreg, "must be"); 651 dispatch._base = rscratch1; 652 jmp(dispatch); 653 } 654 655 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 656 ShouldNotReachHere(); // 64bit doesn't use two regs 657 cmpq(x_lo, y_lo); 658 } 659 660 void MacroAssembler::lea(Register dst, AddressLiteral src) { 661 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 662 } 663 664 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 665 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 666 movptr(dst, rscratch1); 667 } 668 669 void MacroAssembler::leave() { 670 // %%% is this really better? Why not on 32bit too? 671 emit_int8((unsigned char)0xC9); // LEAVE 672 } 673 674 void MacroAssembler::lneg(Register hi, Register lo) { 675 ShouldNotReachHere(); // 64bit doesn't use two regs 676 negq(lo); 677 } 678 679 void MacroAssembler::movoop(Register dst, jobject obj) { 680 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 681 } 682 683 void MacroAssembler::movoop(Address dst, jobject obj) { 684 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 685 movq(dst, rscratch1); 686 } 687 688 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 689 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 690 } 691 692 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 693 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 694 movq(dst, rscratch1); 695 } 696 697 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 698 if (src.is_lval()) { 699 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 700 } else { 701 if (reachable(src)) { 702 movq(dst, as_Address(src)); 703 } else { 704 lea(scratch, src); 705 movq(dst, Address(scratch, 0)); 706 } 707 } 708 } 709 710 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 711 movq(as_Address(dst), src); 712 } 713 714 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 715 movq(dst, as_Address(src)); 716 } 717 718 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 719 void MacroAssembler::movptr(Address dst, intptr_t src) { 720 mov64(rscratch1, src); 721 movq(dst, rscratch1); 722 } 723 724 // These are mostly for initializing NULL 725 void MacroAssembler::movptr(Address dst, int32_t src) { 726 movslq(dst, src); 727 } 728 729 void MacroAssembler::movptr(Register dst, int32_t src) { 730 mov64(dst, (intptr_t)src); 731 } 732 733 void MacroAssembler::pushoop(jobject obj) { 734 movoop(rscratch1, obj); 735 push(rscratch1); 736 } 737 738 void MacroAssembler::pushklass(Metadata* obj) { 739 mov_metadata(rscratch1, obj); 740 push(rscratch1); 741 } 742 743 void MacroAssembler::pushptr(AddressLiteral src) { 744 lea(rscratch1, src); 745 if (src.is_lval()) { 746 push(rscratch1); 747 } else { 748 pushq(Address(rscratch1, 0)); 749 } 750 } 751 752 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 753 bool clear_pc) { 754 // we must set sp to zero to clear frame 755 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 756 // must clear fp, so that compiled frames are not confused; it is 757 // possible that we need it only for debugging 758 if (clear_fp) { 759 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 760 } 761 762 if (clear_pc) { 763 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 764 } 765 } 766 767 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 768 Register last_java_fp, 769 address last_java_pc) { 770 // determine last_java_sp register 771 if (!last_java_sp->is_valid()) { 772 last_java_sp = rsp; 773 } 774 775 // last_java_fp is optional 776 if (last_java_fp->is_valid()) { 777 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 778 last_java_fp); 779 } 780 781 // last_java_pc is optional 782 if (last_java_pc != NULL) { 783 Address java_pc(r15_thread, 784 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 785 lea(rscratch1, InternalAddress(last_java_pc)); 786 movptr(java_pc, rscratch1); 787 } 788 789 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 790 } 791 792 static void pass_arg0(MacroAssembler* masm, Register arg) { 793 if (c_rarg0 != arg ) { 794 masm->mov(c_rarg0, arg); 795 } 796 } 797 798 static void pass_arg1(MacroAssembler* masm, Register arg) { 799 if (c_rarg1 != arg ) { 800 masm->mov(c_rarg1, arg); 801 } 802 } 803 804 static void pass_arg2(MacroAssembler* masm, Register arg) { 805 if (c_rarg2 != arg ) { 806 masm->mov(c_rarg2, arg); 807 } 808 } 809 810 static void pass_arg3(MacroAssembler* masm, Register arg) { 811 if (c_rarg3 != arg ) { 812 masm->mov(c_rarg3, arg); 813 } 814 } 815 816 void MacroAssembler::stop(const char* msg) { 817 address rip = pc(); 818 pusha(); // get regs on stack 819 lea(c_rarg0, ExternalAddress((address) msg)); 820 lea(c_rarg1, InternalAddress(rip)); 821 movq(c_rarg2, rsp); // pass pointer to regs array 822 andq(rsp, -16); // align stack as required by ABI 823 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 824 hlt(); 825 } 826 827 void MacroAssembler::warn(const char* msg) { 828 push(rbp); 829 movq(rbp, rsp); 830 andq(rsp, -16); // align stack as required by push_CPU_state and call 831 push_CPU_state(); // keeps alignment at 16 bytes 832 lea(c_rarg0, ExternalAddress((address) msg)); 833 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 834 pop_CPU_state(); 835 mov(rsp, rbp); 836 pop(rbp); 837 } 838 839 void MacroAssembler::print_state() { 840 address rip = pc(); 841 pusha(); // get regs on stack 842 push(rbp); 843 movq(rbp, rsp); 844 andq(rsp, -16); // align stack as required by push_CPU_state and call 845 push_CPU_state(); // keeps alignment at 16 bytes 846 847 lea(c_rarg0, InternalAddress(rip)); 848 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 849 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 850 851 pop_CPU_state(); 852 mov(rsp, rbp); 853 pop(rbp); 854 popa(); 855 } 856 857 #ifndef PRODUCT 858 extern "C" void findpc(intptr_t x); 859 #endif 860 861 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 862 // In order to get locks to work, we need to fake a in_VM state 863 if (ShowMessageBoxOnError) { 864 JavaThread* thread = JavaThread::current(); 865 JavaThreadState saved_state = thread->thread_state(); 866 thread->set_thread_state(_thread_in_vm); 867 #ifndef PRODUCT 868 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 869 ttyLocker ttyl; 870 BytecodeCounter::print(); 871 } 872 #endif 873 // To see where a verify_oop failed, get $ebx+40/X for this frame. 874 // XXX correct this offset for amd64 875 // This is the value of eip which points to where verify_oop will return. 876 if (os::message_box(msg, "Execution stopped, print registers?")) { 877 print_state64(pc, regs); 878 BREAKPOINT; 879 assert(false, "start up GDB"); 880 } 881 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 882 } else { 883 ttyLocker ttyl; 884 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 885 msg); 886 assert(false, "DEBUG MESSAGE: %s", msg); 887 } 888 } 889 890 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 891 ttyLocker ttyl; 892 FlagSetting fs(Debugging, true); 893 tty->print_cr("rip = 0x%016lx", pc); 894 #ifndef PRODUCT 895 tty->cr(); 896 findpc(pc); 897 tty->cr(); 898 #endif 899 #define PRINT_REG(rax, value) \ 900 { tty->print("%s = ", #rax); os::print_location(tty, value); } 901 PRINT_REG(rax, regs[15]); 902 PRINT_REG(rbx, regs[12]); 903 PRINT_REG(rcx, regs[14]); 904 PRINT_REG(rdx, regs[13]); 905 PRINT_REG(rdi, regs[8]); 906 PRINT_REG(rsi, regs[9]); 907 PRINT_REG(rbp, regs[10]); 908 PRINT_REG(rsp, regs[11]); 909 PRINT_REG(r8 , regs[7]); 910 PRINT_REG(r9 , regs[6]); 911 PRINT_REG(r10, regs[5]); 912 PRINT_REG(r11, regs[4]); 913 PRINT_REG(r12, regs[3]); 914 PRINT_REG(r13, regs[2]); 915 PRINT_REG(r14, regs[1]); 916 PRINT_REG(r15, regs[0]); 917 #undef PRINT_REG 918 // Print some words near top of staack. 919 int64_t* rsp = (int64_t*) regs[11]; 920 int64_t* dump_sp = rsp; 921 for (int col1 = 0; col1 < 8; col1++) { 922 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 923 os::print_location(tty, *dump_sp++); 924 } 925 for (int row = 0; row < 25; row++) { 926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 927 for (int col = 0; col < 4; col++) { 928 tty->print(" 0x%016lx", *dump_sp++); 929 } 930 tty->cr(); 931 } 932 // Print some instructions around pc: 933 Disassembler::decode((address)pc-64, (address)pc); 934 tty->print_cr("--------"); 935 Disassembler::decode((address)pc, (address)pc+32); 936 } 937 938 #endif // _LP64 939 940 // Now versions that are common to 32/64 bit 941 942 void MacroAssembler::addptr(Register dst, int32_t imm32) { 943 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 944 } 945 946 void MacroAssembler::addptr(Register dst, Register src) { 947 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 948 } 949 950 void MacroAssembler::addptr(Address dst, Register src) { 951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 952 } 953 954 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 955 if (reachable(src)) { 956 Assembler::addsd(dst, as_Address(src)); 957 } else { 958 lea(rscratch1, src); 959 Assembler::addsd(dst, Address(rscratch1, 0)); 960 } 961 } 962 963 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 964 if (reachable(src)) { 965 addss(dst, as_Address(src)); 966 } else { 967 lea(rscratch1, src); 968 addss(dst, Address(rscratch1, 0)); 969 } 970 } 971 972 void MacroAssembler::align(int modulus) { 973 align(modulus, offset()); 974 } 975 976 void MacroAssembler::align(int modulus, int target) { 977 if (target % modulus != 0) { 978 nop(modulus - (target % modulus)); 979 } 980 } 981 982 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 983 // Used in sign-masking with aligned address. 984 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 985 if (reachable(src)) { 986 Assembler::andpd(dst, as_Address(src)); 987 } else { 988 lea(rscratch1, src); 989 Assembler::andpd(dst, Address(rscratch1, 0)); 990 } 991 } 992 993 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 994 // Used in sign-masking with aligned address. 995 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 996 if (reachable(src)) { 997 Assembler::andps(dst, as_Address(src)); 998 } else { 999 lea(rscratch1, src); 1000 Assembler::andps(dst, Address(rscratch1, 0)); 1001 } 1002 } 1003 1004 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1005 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1006 } 1007 1008 void MacroAssembler::atomic_incl(Address counter_addr) { 1009 if (os::is_MP()) 1010 lock(); 1011 incrementl(counter_addr); 1012 } 1013 1014 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1015 if (reachable(counter_addr)) { 1016 atomic_incl(as_Address(counter_addr)); 1017 } else { 1018 lea(scr, counter_addr); 1019 atomic_incl(Address(scr, 0)); 1020 } 1021 } 1022 1023 #ifdef _LP64 1024 void MacroAssembler::atomic_incq(Address counter_addr) { 1025 if (os::is_MP()) 1026 lock(); 1027 incrementq(counter_addr); 1028 } 1029 1030 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1031 if (reachable(counter_addr)) { 1032 atomic_incq(as_Address(counter_addr)); 1033 } else { 1034 lea(scr, counter_addr); 1035 atomic_incq(Address(scr, 0)); 1036 } 1037 } 1038 #endif 1039 1040 // Writes to stack successive pages until offset reached to check for 1041 // stack overflow + shadow pages. This clobbers tmp. 1042 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1043 movptr(tmp, rsp); 1044 // Bang stack for total size given plus shadow page size. 1045 // Bang one page at a time because large size can bang beyond yellow and 1046 // red zones. 1047 Label loop; 1048 bind(loop); 1049 movl(Address(tmp, (-os::vm_page_size())), size ); 1050 subptr(tmp, os::vm_page_size()); 1051 subl(size, os::vm_page_size()); 1052 jcc(Assembler::greater, loop); 1053 1054 // Bang down shadow pages too. 1055 // At this point, (tmp-0) is the last address touched, so don't 1056 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1057 // was post-decremented.) Skip this address by starting at i=1, and 1058 // touch a few more pages below. N.B. It is important to touch all 1059 // the way down to and including i=StackShadowPages. 1060 for (int i = 1; i < StackShadowPages; i++) { 1061 // this could be any sized move but this is can be a debugging crumb 1062 // so the bigger the better. 1063 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1064 } 1065 } 1066 1067 int MacroAssembler::biased_locking_enter(Register lock_reg, 1068 Register obj_reg, 1069 Register swap_reg, 1070 Register tmp_reg, 1071 bool swap_reg_contains_mark, 1072 Label& done, 1073 Label* slow_case, 1074 BiasedLockingCounters* counters) { 1075 assert(UseBiasedLocking, "why call this otherwise?"); 1076 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1077 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1078 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1079 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1080 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1081 Address saved_mark_addr(lock_reg, 0); 1082 1083 if (PrintBiasedLockingStatistics && counters == NULL) { 1084 counters = BiasedLocking::counters(); 1085 } 1086 // Biased locking 1087 // See whether the lock is currently biased toward our thread and 1088 // whether the epoch is still valid 1089 // Note that the runtime guarantees sufficient alignment of JavaThread 1090 // pointers to allow age to be placed into low bits 1091 // First check to see whether biasing is even enabled for this object 1092 Label cas_label; 1093 int null_check_offset = -1; 1094 if (!swap_reg_contains_mark) { 1095 null_check_offset = offset(); 1096 movptr(swap_reg, mark_addr); 1097 } 1098 movptr(tmp_reg, swap_reg); 1099 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1100 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1101 jcc(Assembler::notEqual, cas_label); 1102 // The bias pattern is present in the object's header. Need to check 1103 // whether the bias owner and the epoch are both still current. 1104 #ifndef _LP64 1105 // Note that because there is no current thread register on x86_32 we 1106 // need to store off the mark word we read out of the object to 1107 // avoid reloading it and needing to recheck invariants below. This 1108 // store is unfortunate but it makes the overall code shorter and 1109 // simpler. 1110 movptr(saved_mark_addr, swap_reg); 1111 #endif 1112 if (swap_reg_contains_mark) { 1113 null_check_offset = offset(); 1114 } 1115 load_prototype_header(tmp_reg, obj_reg); 1116 #ifdef _LP64 1117 orptr(tmp_reg, r15_thread); 1118 xorptr(tmp_reg, swap_reg); 1119 Register header_reg = tmp_reg; 1120 #else 1121 xorptr(tmp_reg, swap_reg); 1122 get_thread(swap_reg); 1123 xorptr(swap_reg, tmp_reg); 1124 Register header_reg = swap_reg; 1125 #endif 1126 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1127 if (counters != NULL) { 1128 cond_inc32(Assembler::zero, 1129 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1130 } 1131 jcc(Assembler::equal, done); 1132 1133 Label try_revoke_bias; 1134 Label try_rebias; 1135 1136 // At this point we know that the header has the bias pattern and 1137 // that we are not the bias owner in the current epoch. We need to 1138 // figure out more details about the state of the header in order to 1139 // know what operations can be legally performed on the object's 1140 // header. 1141 1142 // If the low three bits in the xor result aren't clear, that means 1143 // the prototype header is no longer biased and we have to revoke 1144 // the bias on this object. 1145 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1146 jccb(Assembler::notZero, try_revoke_bias); 1147 1148 // Biasing is still enabled for this data type. See whether the 1149 // epoch of the current bias is still valid, meaning that the epoch 1150 // bits of the mark word are equal to the epoch bits of the 1151 // prototype header. (Note that the prototype header's epoch bits 1152 // only change at a safepoint.) If not, attempt to rebias the object 1153 // toward the current thread. Note that we must be absolutely sure 1154 // that the current epoch is invalid in order to do this because 1155 // otherwise the manipulations it performs on the mark word are 1156 // illegal. 1157 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1158 jccb(Assembler::notZero, try_rebias); 1159 1160 // The epoch of the current bias is still valid but we know nothing 1161 // about the owner; it might be set or it might be clear. Try to 1162 // acquire the bias of the object using an atomic operation. If this 1163 // fails we will go in to the runtime to revoke the object's bias. 1164 // Note that we first construct the presumed unbiased header so we 1165 // don't accidentally blow away another thread's valid bias. 1166 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1167 andptr(swap_reg, 1168 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1169 #ifdef _LP64 1170 movptr(tmp_reg, swap_reg); 1171 orptr(tmp_reg, r15_thread); 1172 #else 1173 get_thread(tmp_reg); 1174 orptr(tmp_reg, swap_reg); 1175 #endif 1176 if (os::is_MP()) { 1177 lock(); 1178 } 1179 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1180 // If the biasing toward our thread failed, this means that 1181 // another thread succeeded in biasing it toward itself and we 1182 // need to revoke that bias. The revocation will occur in the 1183 // interpreter runtime in the slow case. 1184 if (counters != NULL) { 1185 cond_inc32(Assembler::zero, 1186 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1187 } 1188 if (slow_case != NULL) { 1189 jcc(Assembler::notZero, *slow_case); 1190 } 1191 jmp(done); 1192 1193 bind(try_rebias); 1194 // At this point we know the epoch has expired, meaning that the 1195 // current "bias owner", if any, is actually invalid. Under these 1196 // circumstances _only_, we are allowed to use the current header's 1197 // value as the comparison value when doing the cas to acquire the 1198 // bias in the current epoch. In other words, we allow transfer of 1199 // the bias from one thread to another directly in this situation. 1200 // 1201 // FIXME: due to a lack of registers we currently blow away the age 1202 // bits in this situation. Should attempt to preserve them. 1203 load_prototype_header(tmp_reg, obj_reg); 1204 #ifdef _LP64 1205 orptr(tmp_reg, r15_thread); 1206 #else 1207 get_thread(swap_reg); 1208 orptr(tmp_reg, swap_reg); 1209 movptr(swap_reg, saved_mark_addr); 1210 #endif 1211 if (os::is_MP()) { 1212 lock(); 1213 } 1214 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1215 // If the biasing toward our thread failed, then another thread 1216 // succeeded in biasing it toward itself and we need to revoke that 1217 // bias. The revocation will occur in the runtime in the slow case. 1218 if (counters != NULL) { 1219 cond_inc32(Assembler::zero, 1220 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1221 } 1222 if (slow_case != NULL) { 1223 jcc(Assembler::notZero, *slow_case); 1224 } 1225 jmp(done); 1226 1227 bind(try_revoke_bias); 1228 // The prototype mark in the klass doesn't have the bias bit set any 1229 // more, indicating that objects of this data type are not supposed 1230 // to be biased any more. We are going to try to reset the mark of 1231 // this object to the prototype value and fall through to the 1232 // CAS-based locking scheme. Note that if our CAS fails, it means 1233 // that another thread raced us for the privilege of revoking the 1234 // bias of this particular object, so it's okay to continue in the 1235 // normal locking code. 1236 // 1237 // FIXME: due to a lack of registers we currently blow away the age 1238 // bits in this situation. Should attempt to preserve them. 1239 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1240 load_prototype_header(tmp_reg, obj_reg); 1241 if (os::is_MP()) { 1242 lock(); 1243 } 1244 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1245 // Fall through to the normal CAS-based lock, because no matter what 1246 // the result of the above CAS, some thread must have succeeded in 1247 // removing the bias bit from the object's header. 1248 if (counters != NULL) { 1249 cond_inc32(Assembler::zero, 1250 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1251 } 1252 1253 bind(cas_label); 1254 1255 return null_check_offset; 1256 } 1257 1258 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1259 assert(UseBiasedLocking, "why call this otherwise?"); 1260 1261 // Check for biased locking unlock case, which is a no-op 1262 // Note: we do not have to check the thread ID for two reasons. 1263 // First, the interpreter checks for IllegalMonitorStateException at 1264 // a higher level. Second, if the bias was revoked while we held the 1265 // lock, the object could not be rebiased toward another thread, so 1266 // the bias bit would be clear. 1267 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1268 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1269 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1270 jcc(Assembler::equal, done); 1271 } 1272 1273 #ifdef COMPILER2 1274 1275 #if INCLUDE_RTM_OPT 1276 1277 // Update rtm_counters based on abort status 1278 // input: abort_status 1279 // rtm_counters (RTMLockingCounters*) 1280 // flags are killed 1281 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1282 1283 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1284 if (PrintPreciseRTMLockingStatistics) { 1285 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1286 Label check_abort; 1287 testl(abort_status, (1<<i)); 1288 jccb(Assembler::equal, check_abort); 1289 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1290 bind(check_abort); 1291 } 1292 } 1293 } 1294 1295 // Branch if (random & (count-1) != 0), count is 2^n 1296 // tmp, scr and flags are killed 1297 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1298 assert(tmp == rax, ""); 1299 assert(scr == rdx, ""); 1300 rdtsc(); // modifies EDX:EAX 1301 andptr(tmp, count-1); 1302 jccb(Assembler::notZero, brLabel); 1303 } 1304 1305 // Perform abort ratio calculation, set no_rtm bit if high ratio 1306 // input: rtm_counters_Reg (RTMLockingCounters* address) 1307 // tmpReg, rtm_counters_Reg and flags are killed 1308 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1309 Register rtm_counters_Reg, 1310 RTMLockingCounters* rtm_counters, 1311 Metadata* method_data) { 1312 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1313 1314 if (RTMLockingCalculationDelay > 0) { 1315 // Delay calculation 1316 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1317 testptr(tmpReg, tmpReg); 1318 jccb(Assembler::equal, L_done); 1319 } 1320 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1321 // Aborted transactions = abort_count * 100 1322 // All transactions = total_count * RTMTotalCountIncrRate 1323 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1324 1325 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1326 cmpptr(tmpReg, RTMAbortThreshold); 1327 jccb(Assembler::below, L_check_always_rtm2); 1328 imulptr(tmpReg, tmpReg, 100); 1329 1330 Register scrReg = rtm_counters_Reg; 1331 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1332 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1333 imulptr(scrReg, scrReg, RTMAbortRatio); 1334 cmpptr(tmpReg, scrReg); 1335 jccb(Assembler::below, L_check_always_rtm1); 1336 if (method_data != NULL) { 1337 // set rtm_state to "no rtm" in MDO 1338 mov_metadata(tmpReg, method_data); 1339 if (os::is_MP()) { 1340 lock(); 1341 } 1342 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1343 } 1344 jmpb(L_done); 1345 bind(L_check_always_rtm1); 1346 // Reload RTMLockingCounters* address 1347 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1348 bind(L_check_always_rtm2); 1349 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1350 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1351 jccb(Assembler::below, L_done); 1352 if (method_data != NULL) { 1353 // set rtm_state to "always rtm" in MDO 1354 mov_metadata(tmpReg, method_data); 1355 if (os::is_MP()) { 1356 lock(); 1357 } 1358 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1359 } 1360 bind(L_done); 1361 } 1362 1363 // Update counters and perform abort ratio calculation 1364 // input: abort_status_Reg 1365 // rtm_counters_Reg, flags are killed 1366 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1367 Register rtm_counters_Reg, 1368 RTMLockingCounters* rtm_counters, 1369 Metadata* method_data, 1370 bool profile_rtm) { 1371 1372 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1373 // update rtm counters based on rax value at abort 1374 // reads abort_status_Reg, updates flags 1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1376 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1377 if (profile_rtm) { 1378 // Save abort status because abort_status_Reg is used by following code. 1379 if (RTMRetryCount > 0) { 1380 push(abort_status_Reg); 1381 } 1382 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1383 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1384 // restore abort status 1385 if (RTMRetryCount > 0) { 1386 pop(abort_status_Reg); 1387 } 1388 } 1389 } 1390 1391 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1392 // inputs: retry_count_Reg 1393 // : abort_status_Reg 1394 // output: retry_count_Reg decremented by 1 1395 // flags are killed 1396 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1397 Label doneRetry; 1398 assert(abort_status_Reg == rax, ""); 1399 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1400 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1401 // if reason is in 0x6 and retry count != 0 then retry 1402 andptr(abort_status_Reg, 0x6); 1403 jccb(Assembler::zero, doneRetry); 1404 testl(retry_count_Reg, retry_count_Reg); 1405 jccb(Assembler::zero, doneRetry); 1406 pause(); 1407 decrementl(retry_count_Reg); 1408 jmp(retryLabel); 1409 bind(doneRetry); 1410 } 1411 1412 // Spin and retry if lock is busy, 1413 // inputs: box_Reg (monitor address) 1414 // : retry_count_Reg 1415 // output: retry_count_Reg decremented by 1 1416 // : clear z flag if retry count exceeded 1417 // tmp_Reg, scr_Reg, flags are killed 1418 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1419 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1420 Label SpinLoop, SpinExit, doneRetry; 1421 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1422 1423 testl(retry_count_Reg, retry_count_Reg); 1424 jccb(Assembler::zero, doneRetry); 1425 decrementl(retry_count_Reg); 1426 movptr(scr_Reg, RTMSpinLoopCount); 1427 1428 bind(SpinLoop); 1429 pause(); 1430 decrementl(scr_Reg); 1431 jccb(Assembler::lessEqual, SpinExit); 1432 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1433 testptr(tmp_Reg, tmp_Reg); 1434 jccb(Assembler::notZero, SpinLoop); 1435 1436 bind(SpinExit); 1437 jmp(retryLabel); 1438 bind(doneRetry); 1439 incrementl(retry_count_Reg); // clear z flag 1440 } 1441 1442 // Use RTM for normal stack locks 1443 // Input: objReg (object to lock) 1444 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1445 Register retry_on_abort_count_Reg, 1446 RTMLockingCounters* stack_rtm_counters, 1447 Metadata* method_data, bool profile_rtm, 1448 Label& DONE_LABEL, Label& IsInflated) { 1449 assert(UseRTMForStackLocks, "why call this otherwise?"); 1450 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1451 assert(tmpReg == rax, ""); 1452 assert(scrReg == rdx, ""); 1453 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1454 1455 if (RTMRetryCount > 0) { 1456 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1457 bind(L_rtm_retry); 1458 } 1459 movptr(tmpReg, Address(objReg, 0)); 1460 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1461 jcc(Assembler::notZero, IsInflated); 1462 1463 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1464 Label L_noincrement; 1465 if (RTMTotalCountIncrRate > 1) { 1466 // tmpReg, scrReg and flags are killed 1467 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1468 } 1469 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1470 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1471 bind(L_noincrement); 1472 } 1473 xbegin(L_on_abort); 1474 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1475 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1476 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1477 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1478 1479 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1480 if (UseRTMXendForLockBusy) { 1481 xend(); 1482 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1483 jmp(L_decrement_retry); 1484 } 1485 else { 1486 xabort(0); 1487 } 1488 bind(L_on_abort); 1489 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1490 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1491 } 1492 bind(L_decrement_retry); 1493 if (RTMRetryCount > 0) { 1494 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1495 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1496 } 1497 } 1498 1499 // Use RTM for inflating locks 1500 // inputs: objReg (object to lock) 1501 // boxReg (on-stack box address (displaced header location) - KILLED) 1502 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1503 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1504 Register scrReg, Register retry_on_busy_count_Reg, 1505 Register retry_on_abort_count_Reg, 1506 RTMLockingCounters* rtm_counters, 1507 Metadata* method_data, bool profile_rtm, 1508 Label& DONE_LABEL) { 1509 assert(UseRTMLocking, "why call this otherwise?"); 1510 assert(tmpReg == rax, ""); 1511 assert(scrReg == rdx, ""); 1512 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1513 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1514 1515 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1516 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1517 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1518 1519 if (RTMRetryCount > 0) { 1520 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1521 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1522 bind(L_rtm_retry); 1523 } 1524 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1525 Label L_noincrement; 1526 if (RTMTotalCountIncrRate > 1) { 1527 // tmpReg, scrReg and flags are killed 1528 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1529 } 1530 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1531 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1532 bind(L_noincrement); 1533 } 1534 xbegin(L_on_abort); 1535 movptr(tmpReg, Address(objReg, 0)); 1536 movptr(tmpReg, Address(tmpReg, owner_offset)); 1537 testptr(tmpReg, tmpReg); 1538 jcc(Assembler::zero, DONE_LABEL); 1539 if (UseRTMXendForLockBusy) { 1540 xend(); 1541 jmp(L_decrement_retry); 1542 } 1543 else { 1544 xabort(0); 1545 } 1546 bind(L_on_abort); 1547 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1548 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1549 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1550 } 1551 if (RTMRetryCount > 0) { 1552 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1553 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1554 } 1555 1556 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1557 testptr(tmpReg, tmpReg) ; 1558 jccb(Assembler::notZero, L_decrement_retry) ; 1559 1560 // Appears unlocked - try to swing _owner from null to non-null. 1561 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1562 #ifdef _LP64 1563 Register threadReg = r15_thread; 1564 #else 1565 get_thread(scrReg); 1566 Register threadReg = scrReg; 1567 #endif 1568 if (os::is_MP()) { 1569 lock(); 1570 } 1571 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1572 1573 if (RTMRetryCount > 0) { 1574 // success done else retry 1575 jccb(Assembler::equal, DONE_LABEL) ; 1576 bind(L_decrement_retry); 1577 // Spin and retry if lock is busy. 1578 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1579 } 1580 else { 1581 bind(L_decrement_retry); 1582 } 1583 } 1584 1585 #endif // INCLUDE_RTM_OPT 1586 1587 // Fast_Lock and Fast_Unlock used by C2 1588 1589 // Because the transitions from emitted code to the runtime 1590 // monitorenter/exit helper stubs are so slow it's critical that 1591 // we inline both the stack-locking fast-path and the inflated fast path. 1592 // 1593 // See also: cmpFastLock and cmpFastUnlock. 1594 // 1595 // What follows is a specialized inline transliteration of the code 1596 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1597 // another option would be to emit TrySlowEnter and TrySlowExit methods 1598 // at startup-time. These methods would accept arguments as 1599 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1600 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1601 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1602 // In practice, however, the # of lock sites is bounded and is usually small. 1603 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1604 // if the processor uses simple bimodal branch predictors keyed by EIP 1605 // Since the helper routines would be called from multiple synchronization 1606 // sites. 1607 // 1608 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1609 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1610 // to those specialized methods. That'd give us a mostly platform-independent 1611 // implementation that the JITs could optimize and inline at their pleasure. 1612 // Done correctly, the only time we'd need to cross to native could would be 1613 // to park() or unpark() threads. We'd also need a few more unsafe operators 1614 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1615 // (b) explicit barriers or fence operations. 1616 // 1617 // TODO: 1618 // 1619 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1620 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1621 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1622 // the lock operators would typically be faster than reifying Self. 1623 // 1624 // * Ideally I'd define the primitives as: 1625 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1626 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1627 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1628 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1629 // Furthermore the register assignments are overconstrained, possibly resulting in 1630 // sub-optimal code near the synchronization site. 1631 // 1632 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1633 // Alternately, use a better sp-proximity test. 1634 // 1635 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1636 // Either one is sufficient to uniquely identify a thread. 1637 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1638 // 1639 // * Intrinsify notify() and notifyAll() for the common cases where the 1640 // object is locked by the calling thread but the waitlist is empty. 1641 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1642 // 1643 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1644 // But beware of excessive branch density on AMD Opterons. 1645 // 1646 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1647 // or failure of the fast-path. If the fast-path fails then we pass 1648 // control to the slow-path, typically in C. In Fast_Lock and 1649 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1650 // will emit a conditional branch immediately after the node. 1651 // So we have branches to branches and lots of ICC.ZF games. 1652 // Instead, it might be better to have C2 pass a "FailureLabel" 1653 // into Fast_Lock and Fast_Unlock. In the case of success, control 1654 // will drop through the node. ICC.ZF is undefined at exit. 1655 // In the case of failure, the node will branch directly to the 1656 // FailureLabel 1657 1658 1659 // obj: object to lock 1660 // box: on-stack box address (displaced header location) - KILLED 1661 // rax,: tmp -- KILLED 1662 // scr: tmp -- KILLED 1663 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1664 Register scrReg, Register cx1Reg, Register cx2Reg, 1665 BiasedLockingCounters* counters, 1666 RTMLockingCounters* rtm_counters, 1667 RTMLockingCounters* stack_rtm_counters, 1668 Metadata* method_data, 1669 bool use_rtm, bool profile_rtm) { 1670 // Ensure the register assignents are disjoint 1671 assert(tmpReg == rax, ""); 1672 1673 if (use_rtm) { 1674 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1675 } else { 1676 assert(cx1Reg == noreg, ""); 1677 assert(cx2Reg == noreg, ""); 1678 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1679 } 1680 1681 if (counters != NULL) { 1682 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1683 } 1684 if (EmitSync & 1) { 1685 // set box->dhw = markOopDesc::unused_mark() 1686 // Force all sync thru slow-path: slow_enter() and slow_exit() 1687 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1688 cmpptr (rsp, (int32_t)NULL_WORD); 1689 } else { 1690 // Possible cases that we'll encounter in fast_lock 1691 // ------------------------------------------------ 1692 // * Inflated 1693 // -- unlocked 1694 // -- Locked 1695 // = by self 1696 // = by other 1697 // * biased 1698 // -- by Self 1699 // -- by other 1700 // * neutral 1701 // * stack-locked 1702 // -- by self 1703 // = sp-proximity test hits 1704 // = sp-proximity test generates false-negative 1705 // -- by other 1706 // 1707 1708 Label IsInflated, DONE_LABEL; 1709 1710 // it's stack-locked, biased or neutral 1711 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1712 // order to reduce the number of conditional branches in the most common cases. 1713 // Beware -- there's a subtle invariant that fetch of the markword 1714 // at [FETCH], below, will never observe a biased encoding (*101b). 1715 // If this invariant is not held we risk exclusion (safety) failure. 1716 if (UseBiasedLocking && !UseOptoBiasInlining) { 1717 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1718 } 1719 1720 #if INCLUDE_RTM_OPT 1721 if (UseRTMForStackLocks && use_rtm) { 1722 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1723 stack_rtm_counters, method_data, profile_rtm, 1724 DONE_LABEL, IsInflated); 1725 } 1726 #endif // INCLUDE_RTM_OPT 1727 1728 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1729 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1730 jccb(Assembler::notZero, IsInflated); 1731 1732 // Attempt stack-locking ... 1733 orptr (tmpReg, markOopDesc::unlocked_value); 1734 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1735 if (os::is_MP()) { 1736 lock(); 1737 } 1738 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1739 if (counters != NULL) { 1740 cond_inc32(Assembler::equal, 1741 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1742 } 1743 jcc(Assembler::equal, DONE_LABEL); // Success 1744 1745 // Recursive locking. 1746 // The object is stack-locked: markword contains stack pointer to BasicLock. 1747 // Locked by current thread if difference with current SP is less than one page. 1748 subptr(tmpReg, rsp); 1749 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1750 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1751 movptr(Address(boxReg, 0), tmpReg); 1752 if (counters != NULL) { 1753 cond_inc32(Assembler::equal, 1754 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1755 } 1756 jmp(DONE_LABEL); 1757 1758 bind(IsInflated); 1759 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1760 1761 #if INCLUDE_RTM_OPT 1762 // Use the same RTM locking code in 32- and 64-bit VM. 1763 if (use_rtm) { 1764 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1765 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1766 } else { 1767 #endif // INCLUDE_RTM_OPT 1768 1769 #ifndef _LP64 1770 // The object is inflated. 1771 1772 // boxReg refers to the on-stack BasicLock in the current frame. 1773 // We'd like to write: 1774 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1775 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1776 // additional latency as we have another ST in the store buffer that must drain. 1777 1778 if (EmitSync & 8192) { 1779 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1780 get_thread (scrReg); 1781 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1782 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1783 if (os::is_MP()) { 1784 lock(); 1785 } 1786 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1787 } else 1788 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1789 // register juggle because we need tmpReg for cmpxchgptr below 1790 movptr(scrReg, boxReg); 1791 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1792 1793 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1794 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1795 // prefetchw [eax + Offset(_owner)-2] 1796 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1797 } 1798 1799 if ((EmitSync & 64) == 0) { 1800 // Optimistic form: consider XORL tmpReg,tmpReg 1801 movptr(tmpReg, NULL_WORD); 1802 } else { 1803 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1804 // Test-And-CAS instead of CAS 1805 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1806 testptr(tmpReg, tmpReg); // Locked ? 1807 jccb (Assembler::notZero, DONE_LABEL); 1808 } 1809 1810 // Appears unlocked - try to swing _owner from null to non-null. 1811 // Ideally, I'd manifest "Self" with get_thread and then attempt 1812 // to CAS the register containing Self into m->Owner. 1813 // But we don't have enough registers, so instead we can either try to CAS 1814 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1815 // we later store "Self" into m->Owner. Transiently storing a stack address 1816 // (rsp or the address of the box) into m->owner is harmless. 1817 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1818 if (os::is_MP()) { 1819 lock(); 1820 } 1821 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1822 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1823 // If we weren't able to swing _owner from NULL to the BasicLock 1824 // then take the slow path. 1825 jccb (Assembler::notZero, DONE_LABEL); 1826 // update _owner from BasicLock to thread 1827 get_thread (scrReg); // beware: clobbers ICCs 1828 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1829 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1830 1831 // If the CAS fails we can either retry or pass control to the slow-path. 1832 // We use the latter tactic. 1833 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1834 // If the CAS was successful ... 1835 // Self has acquired the lock 1836 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1837 // Intentional fall-through into DONE_LABEL ... 1838 } else { 1839 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1840 movptr(boxReg, tmpReg); 1841 1842 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1843 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1844 // prefetchw [eax + Offset(_owner)-2] 1845 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1846 } 1847 1848 if ((EmitSync & 64) == 0) { 1849 // Optimistic form 1850 xorptr (tmpReg, tmpReg); 1851 } else { 1852 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1853 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1854 testptr(tmpReg, tmpReg); // Locked ? 1855 jccb (Assembler::notZero, DONE_LABEL); 1856 } 1857 1858 // Appears unlocked - try to swing _owner from null to non-null. 1859 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1860 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1861 get_thread (scrReg); 1862 if (os::is_MP()) { 1863 lock(); 1864 } 1865 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1866 1867 // If the CAS fails we can either retry or pass control to the slow-path. 1868 // We use the latter tactic. 1869 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1870 // If the CAS was successful ... 1871 // Self has acquired the lock 1872 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1873 // Intentional fall-through into DONE_LABEL ... 1874 } 1875 #else // _LP64 1876 // It's inflated 1877 movq(scrReg, tmpReg); 1878 xorq(tmpReg, tmpReg); 1879 1880 if (os::is_MP()) { 1881 lock(); 1882 } 1883 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1884 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1885 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1886 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1887 // Intentional fall-through into DONE_LABEL ... 1888 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1889 #endif // _LP64 1890 #if INCLUDE_RTM_OPT 1891 } // use_rtm() 1892 #endif 1893 // DONE_LABEL is a hot target - we'd really like to place it at the 1894 // start of cache line by padding with NOPs. 1895 // See the AMD and Intel software optimization manuals for the 1896 // most efficient "long" NOP encodings. 1897 // Unfortunately none of our alignment mechanisms suffice. 1898 bind(DONE_LABEL); 1899 1900 // At DONE_LABEL the icc ZFlag is set as follows ... 1901 // Fast_Unlock uses the same protocol. 1902 // ZFlag == 1 -> Success 1903 // ZFlag == 0 -> Failure - force control through the slow-path 1904 } 1905 } 1906 1907 // obj: object to unlock 1908 // box: box address (displaced header location), killed. Must be EAX. 1909 // tmp: killed, cannot be obj nor box. 1910 // 1911 // Some commentary on balanced locking: 1912 // 1913 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1914 // Methods that don't have provably balanced locking are forced to run in the 1915 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1916 // The interpreter provides two properties: 1917 // I1: At return-time the interpreter automatically and quietly unlocks any 1918 // objects acquired the current activation (frame). Recall that the 1919 // interpreter maintains an on-stack list of locks currently held by 1920 // a frame. 1921 // I2: If a method attempts to unlock an object that is not held by the 1922 // the frame the interpreter throws IMSX. 1923 // 1924 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1925 // B() doesn't have provably balanced locking so it runs in the interpreter. 1926 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1927 // is still locked by A(). 1928 // 1929 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1930 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1931 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1932 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1933 // Arguably given that the spec legislates the JNI case as undefined our implementation 1934 // could reasonably *avoid* checking owner in Fast_Unlock(). 1935 // In the interest of performance we elide m->Owner==Self check in unlock. 1936 // A perfectly viable alternative is to elide the owner check except when 1937 // Xcheck:jni is enabled. 1938 1939 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1940 assert(boxReg == rax, ""); 1941 assert_different_registers(objReg, boxReg, tmpReg); 1942 1943 if (EmitSync & 4) { 1944 // Disable - inhibit all inlining. Force control through the slow-path 1945 cmpptr (rsp, 0); 1946 } else { 1947 Label DONE_LABEL, Stacked, CheckSucc; 1948 1949 // Critically, the biased locking test must have precedence over 1950 // and appear before the (box->dhw == 0) recursive stack-lock test. 1951 if (UseBiasedLocking && !UseOptoBiasInlining) { 1952 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1953 } 1954 1955 #if INCLUDE_RTM_OPT 1956 if (UseRTMForStackLocks && use_rtm) { 1957 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1958 Label L_regular_unlock; 1959 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1960 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1961 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1962 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1963 xend(); // otherwise end... 1964 jmp(DONE_LABEL); // ... and we're done 1965 bind(L_regular_unlock); 1966 } 1967 #endif 1968 1969 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1970 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1971 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 1972 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 1973 jccb (Assembler::zero, Stacked); 1974 1975 // It's inflated. 1976 #if INCLUDE_RTM_OPT 1977 if (use_rtm) { 1978 Label L_regular_inflated_unlock; 1979 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1980 movptr(boxReg, Address(tmpReg, owner_offset)); 1981 testptr(boxReg, boxReg); 1982 jccb(Assembler::notZero, L_regular_inflated_unlock); 1983 xend(); 1984 jmpb(DONE_LABEL); 1985 bind(L_regular_inflated_unlock); 1986 } 1987 #endif 1988 1989 // Despite our balanced locking property we still check that m->_owner == Self 1990 // as java routines or native JNI code called by this thread might 1991 // have released the lock. 1992 // Refer to the comments in synchronizer.cpp for how we might encode extra 1993 // state in _succ so we can avoid fetching EntryList|cxq. 1994 // 1995 // I'd like to add more cases in fast_lock() and fast_unlock() -- 1996 // such as recursive enter and exit -- but we have to be wary of 1997 // I$ bloat, T$ effects and BP$ effects. 1998 // 1999 // If there's no contention try a 1-0 exit. That is, exit without 2000 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2001 // we detect and recover from the race that the 1-0 exit admits. 2002 // 2003 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2004 // before it STs null into _owner, releasing the lock. Updates 2005 // to data protected by the critical section must be visible before 2006 // we drop the lock (and thus before any other thread could acquire 2007 // the lock and observe the fields protected by the lock). 2008 // IA32's memory-model is SPO, so STs are ordered with respect to 2009 // each other and there's no need for an explicit barrier (fence). 2010 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2011 #ifndef _LP64 2012 get_thread (boxReg); 2013 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2014 // prefetchw [ebx + Offset(_owner)-2] 2015 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2016 } 2017 2018 // Note that we could employ various encoding schemes to reduce 2019 // the number of loads below (currently 4) to just 2 or 3. 2020 // Refer to the comments in synchronizer.cpp. 2021 // In practice the chain of fetches doesn't seem to impact performance, however. 2022 xorptr(boxReg, boxReg); 2023 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2024 // Attempt to reduce branch density - AMD's branch predictor. 2025 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2026 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2027 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2028 jccb (Assembler::notZero, DONE_LABEL); 2029 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2030 jmpb (DONE_LABEL); 2031 } else { 2032 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2033 jccb (Assembler::notZero, DONE_LABEL); 2034 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2035 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2036 jccb (Assembler::notZero, CheckSucc); 2037 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2038 jmpb (DONE_LABEL); 2039 } 2040 2041 // The Following code fragment (EmitSync & 65536) improves the performance of 2042 // contended applications and contended synchronization microbenchmarks. 2043 // Unfortunately the emission of the code - even though not executed - causes regressions 2044 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2045 // with an equal number of never-executed NOPs results in the same regression. 2046 // We leave it off by default. 2047 2048 if ((EmitSync & 65536) != 0) { 2049 Label LSuccess, LGoSlowPath ; 2050 2051 bind (CheckSucc); 2052 2053 // Optional pre-test ... it's safe to elide this 2054 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2055 jccb(Assembler::zero, LGoSlowPath); 2056 2057 // We have a classic Dekker-style idiom: 2058 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2059 // There are a number of ways to implement the barrier: 2060 // (1) lock:andl &m->_owner, 0 2061 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2062 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2063 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2064 // (2) If supported, an explicit MFENCE is appealing. 2065 // In older IA32 processors MFENCE is slower than lock:add or xchg 2066 // particularly if the write-buffer is full as might be the case if 2067 // if stores closely precede the fence or fence-equivalent instruction. 2068 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2069 // as the situation has changed with Nehalem and Shanghai. 2070 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2071 // The $lines underlying the top-of-stack should be in M-state. 2072 // The locked add instruction is serializing, of course. 2073 // (4) Use xchg, which is serializing 2074 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2075 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2076 // The integer condition codes will tell us if succ was 0. 2077 // Since _succ and _owner should reside in the same $line and 2078 // we just stored into _owner, it's likely that the $line 2079 // remains in M-state for the lock:orl. 2080 // 2081 // We currently use (3), although it's likely that switching to (2) 2082 // is correct for the future. 2083 2084 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2085 if (os::is_MP()) { 2086 lock(); addptr(Address(rsp, 0), 0); 2087 } 2088 // Ratify _succ remains non-null 2089 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2090 jccb (Assembler::notZero, LSuccess); 2091 2092 xorptr(boxReg, boxReg); // box is really EAX 2093 if (os::is_MP()) { lock(); } 2094 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2095 // There's no successor so we tried to regrab the lock with the 2096 // placeholder value. If that didn't work, then another thread 2097 // grabbed the lock so we're done (and exit was a success). 2098 jccb (Assembler::notEqual, LSuccess); 2099 // Since we're low on registers we installed rsp as a placeholding in _owner. 2100 // Now install Self over rsp. This is safe as we're transitioning from 2101 // non-null to non=null 2102 get_thread (boxReg); 2103 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2104 // Intentional fall-through into LGoSlowPath ... 2105 2106 bind (LGoSlowPath); 2107 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2108 jmpb (DONE_LABEL); 2109 2110 bind (LSuccess); 2111 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2112 jmpb (DONE_LABEL); 2113 } 2114 2115 bind (Stacked); 2116 // It's not inflated and it's not recursively stack-locked and it's not biased. 2117 // It must be stack-locked. 2118 // Try to reset the header to displaced header. 2119 // The "box" value on the stack is stable, so we can reload 2120 // and be assured we observe the same value as above. 2121 movptr(tmpReg, Address(boxReg, 0)); 2122 if (os::is_MP()) { 2123 lock(); 2124 } 2125 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2126 // Intention fall-thru into DONE_LABEL 2127 2128 // DONE_LABEL is a hot target - we'd really like to place it at the 2129 // start of cache line by padding with NOPs. 2130 // See the AMD and Intel software optimization manuals for the 2131 // most efficient "long" NOP encodings. 2132 // Unfortunately none of our alignment mechanisms suffice. 2133 if ((EmitSync & 65536) == 0) { 2134 bind (CheckSucc); 2135 } 2136 #else // _LP64 2137 // It's inflated 2138 if (EmitSync & 1024) { 2139 // Emit code to check that _owner == Self 2140 // We could fold the _owner test into subsequent code more efficiently 2141 // than using a stand-alone check, but since _owner checking is off by 2142 // default we don't bother. We also might consider predicating the 2143 // _owner==Self check on Xcheck:jni or running on a debug build. 2144 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2145 xorptr(boxReg, r15_thread); 2146 } else { 2147 xorptr(boxReg, boxReg); 2148 } 2149 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2150 jccb (Assembler::notZero, DONE_LABEL); 2151 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2152 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2153 jccb (Assembler::notZero, CheckSucc); 2154 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2155 jmpb (DONE_LABEL); 2156 2157 if ((EmitSync & 65536) == 0) { 2158 // Try to avoid passing control into the slow_path ... 2159 Label LSuccess, LGoSlowPath ; 2160 bind (CheckSucc); 2161 2162 // The following optional optimization can be elided if necessary 2163 // Effectively: if (succ == null) goto SlowPath 2164 // The code reduces the window for a race, however, 2165 // and thus benefits performance. 2166 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2167 jccb (Assembler::zero, LGoSlowPath); 2168 2169 if ((EmitSync & 16) && os::is_MP()) { 2170 orptr(boxReg, boxReg); 2171 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2172 } else { 2173 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2174 if (os::is_MP()) { 2175 // Memory barrier/fence 2176 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2177 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2178 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2179 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2180 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2181 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2182 lock(); addl(Address(rsp, 0), 0); 2183 } 2184 } 2185 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2186 jccb (Assembler::notZero, LSuccess); 2187 2188 // Rare inopportune interleaving - race. 2189 // The successor vanished in the small window above. 2190 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2191 // We need to ensure progress and succession. 2192 // Try to reacquire the lock. 2193 // If that fails then the new owner is responsible for succession and this 2194 // thread needs to take no further action and can exit via the fast path (success). 2195 // If the re-acquire succeeds then pass control into the slow path. 2196 // As implemented, this latter mode is horrible because we generated more 2197 // coherence traffic on the lock *and* artifically extended the critical section 2198 // length while by virtue of passing control into the slow path. 2199 2200 // box is really RAX -- the following CMPXCHG depends on that binding 2201 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2202 movptr(boxReg, (int32_t)NULL_WORD); 2203 if (os::is_MP()) { lock(); } 2204 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2205 // There's no successor so we tried to regrab the lock. 2206 // If that didn't work, then another thread grabbed the 2207 // lock so we're done (and exit was a success). 2208 jccb (Assembler::notEqual, LSuccess); 2209 // Intentional fall-through into slow-path 2210 2211 bind (LGoSlowPath); 2212 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2213 jmpb (DONE_LABEL); 2214 2215 bind (LSuccess); 2216 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2217 jmpb (DONE_LABEL); 2218 } 2219 2220 bind (Stacked); 2221 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2222 if (os::is_MP()) { lock(); } 2223 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2224 2225 if (EmitSync & 65536) { 2226 bind (CheckSucc); 2227 } 2228 #endif 2229 bind(DONE_LABEL); 2230 } 2231 } 2232 #endif // COMPILER2 2233 2234 void MacroAssembler::c2bool(Register x) { 2235 // implements x == 0 ? 0 : 1 2236 // note: must only look at least-significant byte of x 2237 // since C-style booleans are stored in one byte 2238 // only! (was bug) 2239 andl(x, 0xFF); 2240 setb(Assembler::notZero, x); 2241 } 2242 2243 // Wouldn't need if AddressLiteral version had new name 2244 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2245 Assembler::call(L, rtype); 2246 } 2247 2248 void MacroAssembler::call(Register entry) { 2249 Assembler::call(entry); 2250 } 2251 2252 void MacroAssembler::call(AddressLiteral entry) { 2253 if (reachable(entry)) { 2254 Assembler::call_literal(entry.target(), entry.rspec()); 2255 } else { 2256 lea(rscratch1, entry); 2257 Assembler::call(rscratch1); 2258 } 2259 } 2260 2261 void MacroAssembler::ic_call(address entry) { 2262 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2263 movptr(rax, (intptr_t)Universe::non_oop_word()); 2264 call(AddressLiteral(entry, rh)); 2265 } 2266 2267 // Implementation of call_VM versions 2268 2269 void MacroAssembler::call_VM(Register oop_result, 2270 address entry_point, 2271 bool check_exceptions) { 2272 Label C, E; 2273 call(C, relocInfo::none); 2274 jmp(E); 2275 2276 bind(C); 2277 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2278 ret(0); 2279 2280 bind(E); 2281 } 2282 2283 void MacroAssembler::call_VM(Register oop_result, 2284 address entry_point, 2285 Register arg_1, 2286 bool check_exceptions) { 2287 Label C, E; 2288 call(C, relocInfo::none); 2289 jmp(E); 2290 2291 bind(C); 2292 pass_arg1(this, arg_1); 2293 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2294 ret(0); 2295 2296 bind(E); 2297 } 2298 2299 void MacroAssembler::call_VM(Register oop_result, 2300 address entry_point, 2301 Register arg_1, 2302 Register arg_2, 2303 bool check_exceptions) { 2304 Label C, E; 2305 call(C, relocInfo::none); 2306 jmp(E); 2307 2308 bind(C); 2309 2310 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2311 2312 pass_arg2(this, arg_2); 2313 pass_arg1(this, arg_1); 2314 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2315 ret(0); 2316 2317 bind(E); 2318 } 2319 2320 void MacroAssembler::call_VM(Register oop_result, 2321 address entry_point, 2322 Register arg_1, 2323 Register arg_2, 2324 Register arg_3, 2325 bool check_exceptions) { 2326 Label C, E; 2327 call(C, relocInfo::none); 2328 jmp(E); 2329 2330 bind(C); 2331 2332 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2333 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2334 pass_arg3(this, arg_3); 2335 2336 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2337 pass_arg2(this, arg_2); 2338 2339 pass_arg1(this, arg_1); 2340 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2341 ret(0); 2342 2343 bind(E); 2344 } 2345 2346 void MacroAssembler::call_VM(Register oop_result, 2347 Register last_java_sp, 2348 address entry_point, 2349 int number_of_arguments, 2350 bool check_exceptions) { 2351 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2352 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2353 } 2354 2355 void MacroAssembler::call_VM(Register oop_result, 2356 Register last_java_sp, 2357 address entry_point, 2358 Register arg_1, 2359 bool check_exceptions) { 2360 pass_arg1(this, arg_1); 2361 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2362 } 2363 2364 void MacroAssembler::call_VM(Register oop_result, 2365 Register last_java_sp, 2366 address entry_point, 2367 Register arg_1, 2368 Register arg_2, 2369 bool check_exceptions) { 2370 2371 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2372 pass_arg2(this, arg_2); 2373 pass_arg1(this, arg_1); 2374 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2375 } 2376 2377 void MacroAssembler::call_VM(Register oop_result, 2378 Register last_java_sp, 2379 address entry_point, 2380 Register arg_1, 2381 Register arg_2, 2382 Register arg_3, 2383 bool check_exceptions) { 2384 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2385 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2386 pass_arg3(this, arg_3); 2387 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2388 pass_arg2(this, arg_2); 2389 pass_arg1(this, arg_1); 2390 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2391 } 2392 2393 void MacroAssembler::super_call_VM(Register oop_result, 2394 Register last_java_sp, 2395 address entry_point, 2396 int number_of_arguments, 2397 bool check_exceptions) { 2398 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2399 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2400 } 2401 2402 void MacroAssembler::super_call_VM(Register oop_result, 2403 Register last_java_sp, 2404 address entry_point, 2405 Register arg_1, 2406 bool check_exceptions) { 2407 pass_arg1(this, arg_1); 2408 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2409 } 2410 2411 void MacroAssembler::super_call_VM(Register oop_result, 2412 Register last_java_sp, 2413 address entry_point, 2414 Register arg_1, 2415 Register arg_2, 2416 bool check_exceptions) { 2417 2418 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2419 pass_arg2(this, arg_2); 2420 pass_arg1(this, arg_1); 2421 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2422 } 2423 2424 void MacroAssembler::super_call_VM(Register oop_result, 2425 Register last_java_sp, 2426 address entry_point, 2427 Register arg_1, 2428 Register arg_2, 2429 Register arg_3, 2430 bool check_exceptions) { 2431 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2432 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2433 pass_arg3(this, arg_3); 2434 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2435 pass_arg2(this, arg_2); 2436 pass_arg1(this, arg_1); 2437 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2438 } 2439 2440 void MacroAssembler::call_VM_base(Register oop_result, 2441 Register java_thread, 2442 Register last_java_sp, 2443 address entry_point, 2444 int number_of_arguments, 2445 bool check_exceptions) { 2446 // determine java_thread register 2447 if (!java_thread->is_valid()) { 2448 #ifdef _LP64 2449 java_thread = r15_thread; 2450 #else 2451 java_thread = rdi; 2452 get_thread(java_thread); 2453 #endif // LP64 2454 } 2455 // determine last_java_sp register 2456 if (!last_java_sp->is_valid()) { 2457 last_java_sp = rsp; 2458 } 2459 // debugging support 2460 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2461 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2462 #ifdef ASSERT 2463 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2464 // r12 is the heapbase. 2465 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2466 #endif // ASSERT 2467 2468 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2469 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2470 2471 // push java thread (becomes first argument of C function) 2472 2473 NOT_LP64(push(java_thread); number_of_arguments++); 2474 LP64_ONLY(mov(c_rarg0, r15_thread)); 2475 2476 // set last Java frame before call 2477 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2478 2479 // Only interpreter should have to set fp 2480 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2481 2482 // do the call, remove parameters 2483 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2484 2485 // restore the thread (cannot use the pushed argument since arguments 2486 // may be overwritten by C code generated by an optimizing compiler); 2487 // however can use the register value directly if it is callee saved. 2488 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2489 // rdi & rsi (also r15) are callee saved -> nothing to do 2490 #ifdef ASSERT 2491 guarantee(java_thread != rax, "change this code"); 2492 push(rax); 2493 { Label L; 2494 get_thread(rax); 2495 cmpptr(java_thread, rax); 2496 jcc(Assembler::equal, L); 2497 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2498 bind(L); 2499 } 2500 pop(rax); 2501 #endif 2502 } else { 2503 get_thread(java_thread); 2504 } 2505 // reset last Java frame 2506 // Only interpreter should have to clear fp 2507 reset_last_Java_frame(java_thread, true, false); 2508 2509 #ifndef CC_INTERP 2510 // C++ interp handles this in the interpreter 2511 check_and_handle_popframe(java_thread); 2512 check_and_handle_earlyret(java_thread); 2513 #endif /* CC_INTERP */ 2514 2515 if (check_exceptions) { 2516 // check for pending exceptions (java_thread is set upon return) 2517 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2518 #ifndef _LP64 2519 jump_cc(Assembler::notEqual, 2520 RuntimeAddress(StubRoutines::forward_exception_entry())); 2521 #else 2522 // This used to conditionally jump to forward_exception however it is 2523 // possible if we relocate that the branch will not reach. So we must jump 2524 // around so we can always reach 2525 2526 Label ok; 2527 jcc(Assembler::equal, ok); 2528 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2529 bind(ok); 2530 #endif // LP64 2531 } 2532 2533 // get oop result if there is one and reset the value in the thread 2534 if (oop_result->is_valid()) { 2535 get_vm_result(oop_result, java_thread); 2536 } 2537 } 2538 2539 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2540 2541 // Calculate the value for last_Java_sp 2542 // somewhat subtle. call_VM does an intermediate call 2543 // which places a return address on the stack just under the 2544 // stack pointer as the user finsihed with it. This allows 2545 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2546 // On 32bit we then have to push additional args on the stack to accomplish 2547 // the actual requested call. On 64bit call_VM only can use register args 2548 // so the only extra space is the return address that call_VM created. 2549 // This hopefully explains the calculations here. 2550 2551 #ifdef _LP64 2552 // We've pushed one address, correct last_Java_sp 2553 lea(rax, Address(rsp, wordSize)); 2554 #else 2555 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2556 #endif // LP64 2557 2558 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2559 2560 } 2561 2562 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2563 call_VM_leaf_base(entry_point, number_of_arguments); 2564 } 2565 2566 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2567 pass_arg0(this, arg_0); 2568 call_VM_leaf(entry_point, 1); 2569 } 2570 2571 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2572 2573 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2574 pass_arg1(this, arg_1); 2575 pass_arg0(this, arg_0); 2576 call_VM_leaf(entry_point, 2); 2577 } 2578 2579 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2580 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2581 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2582 pass_arg2(this, arg_2); 2583 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2584 pass_arg1(this, arg_1); 2585 pass_arg0(this, arg_0); 2586 call_VM_leaf(entry_point, 3); 2587 } 2588 2589 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2590 pass_arg0(this, arg_0); 2591 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2592 } 2593 2594 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2595 2596 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2597 pass_arg1(this, arg_1); 2598 pass_arg0(this, arg_0); 2599 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2600 } 2601 2602 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2603 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2604 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2605 pass_arg2(this, arg_2); 2606 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2607 pass_arg1(this, arg_1); 2608 pass_arg0(this, arg_0); 2609 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2610 } 2611 2612 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2613 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2614 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2615 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2616 pass_arg3(this, arg_3); 2617 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2618 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2619 pass_arg2(this, arg_2); 2620 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2621 pass_arg1(this, arg_1); 2622 pass_arg0(this, arg_0); 2623 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2624 } 2625 2626 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2627 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2628 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2629 verify_oop(oop_result, "broken oop in call_VM_base"); 2630 } 2631 2632 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2633 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2634 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2635 } 2636 2637 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2638 } 2639 2640 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2641 } 2642 2643 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2644 if (reachable(src1)) { 2645 cmpl(as_Address(src1), imm); 2646 } else { 2647 lea(rscratch1, src1); 2648 cmpl(Address(rscratch1, 0), imm); 2649 } 2650 } 2651 2652 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2653 assert(!src2.is_lval(), "use cmpptr"); 2654 if (reachable(src2)) { 2655 cmpl(src1, as_Address(src2)); 2656 } else { 2657 lea(rscratch1, src2); 2658 cmpl(src1, Address(rscratch1, 0)); 2659 } 2660 } 2661 2662 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2663 Assembler::cmpl(src1, imm); 2664 } 2665 2666 void MacroAssembler::cmp32(Register src1, Address src2) { 2667 Assembler::cmpl(src1, src2); 2668 } 2669 2670 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2671 ucomisd(opr1, opr2); 2672 2673 Label L; 2674 if (unordered_is_less) { 2675 movl(dst, -1); 2676 jcc(Assembler::parity, L); 2677 jcc(Assembler::below , L); 2678 movl(dst, 0); 2679 jcc(Assembler::equal , L); 2680 increment(dst); 2681 } else { // unordered is greater 2682 movl(dst, 1); 2683 jcc(Assembler::parity, L); 2684 jcc(Assembler::above , L); 2685 movl(dst, 0); 2686 jcc(Assembler::equal , L); 2687 decrementl(dst); 2688 } 2689 bind(L); 2690 } 2691 2692 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2693 ucomiss(opr1, opr2); 2694 2695 Label L; 2696 if (unordered_is_less) { 2697 movl(dst, -1); 2698 jcc(Assembler::parity, L); 2699 jcc(Assembler::below , L); 2700 movl(dst, 0); 2701 jcc(Assembler::equal , L); 2702 increment(dst); 2703 } else { // unordered is greater 2704 movl(dst, 1); 2705 jcc(Assembler::parity, L); 2706 jcc(Assembler::above , L); 2707 movl(dst, 0); 2708 jcc(Assembler::equal , L); 2709 decrementl(dst); 2710 } 2711 bind(L); 2712 } 2713 2714 2715 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2716 if (reachable(src1)) { 2717 cmpb(as_Address(src1), imm); 2718 } else { 2719 lea(rscratch1, src1); 2720 cmpb(Address(rscratch1, 0), imm); 2721 } 2722 } 2723 2724 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2725 #ifdef _LP64 2726 if (src2.is_lval()) { 2727 movptr(rscratch1, src2); 2728 Assembler::cmpq(src1, rscratch1); 2729 } else if (reachable(src2)) { 2730 cmpq(src1, as_Address(src2)); 2731 } else { 2732 lea(rscratch1, src2); 2733 Assembler::cmpq(src1, Address(rscratch1, 0)); 2734 } 2735 #else 2736 if (src2.is_lval()) { 2737 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2738 } else { 2739 cmpl(src1, as_Address(src2)); 2740 } 2741 #endif // _LP64 2742 } 2743 2744 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2745 assert(src2.is_lval(), "not a mem-mem compare"); 2746 #ifdef _LP64 2747 // moves src2's literal address 2748 movptr(rscratch1, src2); 2749 Assembler::cmpq(src1, rscratch1); 2750 #else 2751 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2752 #endif // _LP64 2753 } 2754 2755 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2756 if (reachable(adr)) { 2757 if (os::is_MP()) 2758 lock(); 2759 cmpxchgptr(reg, as_Address(adr)); 2760 } else { 2761 lea(rscratch1, adr); 2762 if (os::is_MP()) 2763 lock(); 2764 cmpxchgptr(reg, Address(rscratch1, 0)); 2765 } 2766 } 2767 2768 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2769 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2770 } 2771 2772 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2773 if (reachable(src)) { 2774 Assembler::comisd(dst, as_Address(src)); 2775 } else { 2776 lea(rscratch1, src); 2777 Assembler::comisd(dst, Address(rscratch1, 0)); 2778 } 2779 } 2780 2781 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2782 if (reachable(src)) { 2783 Assembler::comiss(dst, as_Address(src)); 2784 } else { 2785 lea(rscratch1, src); 2786 Assembler::comiss(dst, Address(rscratch1, 0)); 2787 } 2788 } 2789 2790 2791 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2792 Condition negated_cond = negate_condition(cond); 2793 Label L; 2794 jcc(negated_cond, L); 2795 pushf(); // Preserve flags 2796 atomic_incl(counter_addr); 2797 popf(); 2798 bind(L); 2799 } 2800 2801 int MacroAssembler::corrected_idivl(Register reg) { 2802 // Full implementation of Java idiv and irem; checks for 2803 // special case as described in JVM spec., p.243 & p.271. 2804 // The function returns the (pc) offset of the idivl 2805 // instruction - may be needed for implicit exceptions. 2806 // 2807 // normal case special case 2808 // 2809 // input : rax,: dividend min_int 2810 // reg: divisor (may not be rax,/rdx) -1 2811 // 2812 // output: rax,: quotient (= rax, idiv reg) min_int 2813 // rdx: remainder (= rax, irem reg) 0 2814 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2815 const int min_int = 0x80000000; 2816 Label normal_case, special_case; 2817 2818 // check for special case 2819 cmpl(rax, min_int); 2820 jcc(Assembler::notEqual, normal_case); 2821 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2822 cmpl(reg, -1); 2823 jcc(Assembler::equal, special_case); 2824 2825 // handle normal case 2826 bind(normal_case); 2827 cdql(); 2828 int idivl_offset = offset(); 2829 idivl(reg); 2830 2831 // normal and special case exit 2832 bind(special_case); 2833 2834 return idivl_offset; 2835 } 2836 2837 2838 2839 void MacroAssembler::decrementl(Register reg, int value) { 2840 if (value == min_jint) {subl(reg, value) ; return; } 2841 if (value < 0) { incrementl(reg, -value); return; } 2842 if (value == 0) { ; return; } 2843 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2844 /* else */ { subl(reg, value) ; return; } 2845 } 2846 2847 void MacroAssembler::decrementl(Address dst, int value) { 2848 if (value == min_jint) {subl(dst, value) ; return; } 2849 if (value < 0) { incrementl(dst, -value); return; } 2850 if (value == 0) { ; return; } 2851 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2852 /* else */ { subl(dst, value) ; return; } 2853 } 2854 2855 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2856 assert (shift_value > 0, "illegal shift value"); 2857 Label _is_positive; 2858 testl (reg, reg); 2859 jcc (Assembler::positive, _is_positive); 2860 int offset = (1 << shift_value) - 1 ; 2861 2862 if (offset == 1) { 2863 incrementl(reg); 2864 } else { 2865 addl(reg, offset); 2866 } 2867 2868 bind (_is_positive); 2869 sarl(reg, shift_value); 2870 } 2871 2872 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2873 if (reachable(src)) { 2874 Assembler::divsd(dst, as_Address(src)); 2875 } else { 2876 lea(rscratch1, src); 2877 Assembler::divsd(dst, Address(rscratch1, 0)); 2878 } 2879 } 2880 2881 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2882 if (reachable(src)) { 2883 Assembler::divss(dst, as_Address(src)); 2884 } else { 2885 lea(rscratch1, src); 2886 Assembler::divss(dst, Address(rscratch1, 0)); 2887 } 2888 } 2889 2890 // !defined(COMPILER2) is because of stupid core builds 2891 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2892 void MacroAssembler::empty_FPU_stack() { 2893 if (VM_Version::supports_mmx()) { 2894 emms(); 2895 } else { 2896 for (int i = 8; i-- > 0; ) ffree(i); 2897 } 2898 } 2899 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2900 2901 2902 // Defines obj, preserves var_size_in_bytes 2903 void MacroAssembler::eden_allocate(Register obj, 2904 Register var_size_in_bytes, 2905 int con_size_in_bytes, 2906 Register t1, 2907 Label& slow_case) { 2908 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2909 assert_different_registers(obj, var_size_in_bytes, t1); 2910 if (!Universe::heap()->supports_inline_contig_alloc()) { 2911 jmp(slow_case); 2912 } else { 2913 Register end = t1; 2914 Label retry; 2915 bind(retry); 2916 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2917 movptr(obj, heap_top); 2918 if (var_size_in_bytes == noreg) { 2919 lea(end, Address(obj, con_size_in_bytes)); 2920 } else { 2921 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2922 } 2923 // if end < obj then we wrapped around => object too long => slow case 2924 cmpptr(end, obj); 2925 jcc(Assembler::below, slow_case); 2926 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2927 jcc(Assembler::above, slow_case); 2928 // Compare obj with the top addr, and if still equal, store the new top addr in 2929 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2930 // it otherwise. Use lock prefix for atomicity on MPs. 2931 locked_cmpxchgptr(end, heap_top); 2932 jcc(Assembler::notEqual, retry); 2933 } 2934 } 2935 2936 void MacroAssembler::enter() { 2937 push(rbp); 2938 mov(rbp, rsp); 2939 } 2940 2941 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2942 void MacroAssembler::fat_nop() { 2943 if (UseAddressNop) { 2944 addr_nop_5(); 2945 } else { 2946 emit_int8(0x26); // es: 2947 emit_int8(0x2e); // cs: 2948 emit_int8(0x64); // fs: 2949 emit_int8(0x65); // gs: 2950 emit_int8((unsigned char)0x90); 2951 } 2952 } 2953 2954 void MacroAssembler::fcmp(Register tmp) { 2955 fcmp(tmp, 1, true, true); 2956 } 2957 2958 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2959 assert(!pop_right || pop_left, "usage error"); 2960 if (VM_Version::supports_cmov()) { 2961 assert(tmp == noreg, "unneeded temp"); 2962 if (pop_left) { 2963 fucomip(index); 2964 } else { 2965 fucomi(index); 2966 } 2967 if (pop_right) { 2968 fpop(); 2969 } 2970 } else { 2971 assert(tmp != noreg, "need temp"); 2972 if (pop_left) { 2973 if (pop_right) { 2974 fcompp(); 2975 } else { 2976 fcomp(index); 2977 } 2978 } else { 2979 fcom(index); 2980 } 2981 // convert FPU condition into eflags condition via rax, 2982 save_rax(tmp); 2983 fwait(); fnstsw_ax(); 2984 sahf(); 2985 restore_rax(tmp); 2986 } 2987 // condition codes set as follows: 2988 // 2989 // CF (corresponds to C0) if x < y 2990 // PF (corresponds to C2) if unordered 2991 // ZF (corresponds to C3) if x = y 2992 } 2993 2994 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 2995 fcmp2int(dst, unordered_is_less, 1, true, true); 2996 } 2997 2998 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 2999 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3000 Label L; 3001 if (unordered_is_less) { 3002 movl(dst, -1); 3003 jcc(Assembler::parity, L); 3004 jcc(Assembler::below , L); 3005 movl(dst, 0); 3006 jcc(Assembler::equal , L); 3007 increment(dst); 3008 } else { // unordered is greater 3009 movl(dst, 1); 3010 jcc(Assembler::parity, L); 3011 jcc(Assembler::above , L); 3012 movl(dst, 0); 3013 jcc(Assembler::equal , L); 3014 decrementl(dst); 3015 } 3016 bind(L); 3017 } 3018 3019 void MacroAssembler::fld_d(AddressLiteral src) { 3020 fld_d(as_Address(src)); 3021 } 3022 3023 void MacroAssembler::fld_s(AddressLiteral src) { 3024 fld_s(as_Address(src)); 3025 } 3026 3027 void MacroAssembler::fld_x(AddressLiteral src) { 3028 Assembler::fld_x(as_Address(src)); 3029 } 3030 3031 void MacroAssembler::fldcw(AddressLiteral src) { 3032 Assembler::fldcw(as_Address(src)); 3033 } 3034 3035 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3036 if (reachable(src)) { 3037 Assembler::mulpd(dst, as_Address(src)); 3038 } else { 3039 lea(rscratch1, src); 3040 Assembler::mulpd(dst, Address(rscratch1, 0)); 3041 } 3042 } 3043 3044 void MacroAssembler::pow_exp_core_encoding() { 3045 // kills rax, rcx, rdx 3046 subptr(rsp,sizeof(jdouble)); 3047 // computes 2^X. Stack: X ... 3048 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and 3049 // keep it on the thread's stack to compute 2^int(X) later 3050 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) 3051 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) 3052 fld_s(0); // Stack: X X ... 3053 frndint(); // Stack: int(X) X ... 3054 fsuba(1); // Stack: int(X) X-int(X) ... 3055 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... 3056 f2xm1(); // Stack: 2^(X-int(X))-1 ... 3057 fld1(); // Stack: 1 2^(X-int(X))-1 ... 3058 faddp(1); // Stack: 2^(X-int(X)) 3059 // computes 2^(int(X)): add exponent bias (1023) to int(X), then 3060 // shift int(X)+1023 to exponent position. 3061 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 3062 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent 3063 // values so detect them and set result to NaN. 3064 movl(rax,Address(rsp,0)); 3065 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding 3066 addl(rax, 1023); 3067 movl(rdx,rax); 3068 shll(rax,20); 3069 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. 3070 addl(rdx,1); 3071 // Check that 1 < int(X)+1023+1 < 2048 3072 // in 3 steps: 3073 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 3074 // 2- (int(X)+1023+1)&-2048 != 0 3075 // 3- (int(X)+1023+1)&-2048 != 1 3076 // Do 2- first because addl just updated the flags. 3077 cmov32(Assembler::equal,rax,rcx); 3078 cmpl(rdx,1); 3079 cmov32(Assembler::equal,rax,rcx); 3080 testl(rdx,rcx); 3081 cmov32(Assembler::notEqual,rax,rcx); 3082 movl(Address(rsp,4),rax); 3083 movl(Address(rsp,0),0); 3084 fmul_d(Address(rsp,0)); // Stack: 2^X ... 3085 addptr(rsp,sizeof(jdouble)); 3086 } 3087 3088 void MacroAssembler::increase_precision() { 3089 subptr(rsp, BytesPerWord); 3090 fnstcw(Address(rsp, 0)); 3091 movl(rax, Address(rsp, 0)); 3092 orl(rax, 0x300); 3093 push(rax); 3094 fldcw(Address(rsp, 0)); 3095 pop(rax); 3096 } 3097 3098 void MacroAssembler::restore_precision() { 3099 fldcw(Address(rsp, 0)); 3100 addptr(rsp, BytesPerWord); 3101 } 3102 3103 void MacroAssembler::fast_pow() { 3104 // computes X^Y = 2^(Y * log2(X)) 3105 // if fast computation is not possible, result is NaN. Requires 3106 // fallback from user of this macro. 3107 // increase precision for intermediate steps of the computation 3108 BLOCK_COMMENT("fast_pow {"); 3109 increase_precision(); 3110 fyl2x(); // Stack: (Y*log2(X)) ... 3111 pow_exp_core_encoding(); // Stack: exp(X) ... 3112 restore_precision(); 3113 BLOCK_COMMENT("} fast_pow"); 3114 } 3115 3116 void MacroAssembler::pow_or_exp(int num_fpu_regs_in_use) { 3117 // kills rax, rcx, rdx 3118 // pow and exp needs 2 extra registers on the fpu stack. 3119 Label slow_case, done; 3120 Register tmp = noreg; 3121 if (!VM_Version::supports_cmov()) { 3122 // fcmp needs a temporary so preserve rdx, 3123 tmp = rdx; 3124 } 3125 Register tmp2 = rax; 3126 Register tmp3 = rcx; 3127 3128 // Stack: X Y 3129 Label x_negative, y_not_2; 3130 3131 static double two = 2.0; 3132 ExternalAddress two_addr((address)&two); 3133 3134 // constant maybe too far on 64 bit 3135 lea(tmp2, two_addr); 3136 fld_d(Address(tmp2, 0)); // Stack: 2 X Y 3137 fcmp(tmp, 2, true, false); // Stack: X Y 3138 jcc(Assembler::parity, y_not_2); 3139 jcc(Assembler::notEqual, y_not_2); 3140 3141 fxch(); fpop(); // Stack: X 3142 fmul(0); // Stack: X*X 3143 3144 jmp(done); 3145 3146 bind(y_not_2); 3147 3148 fldz(); // Stack: 0 X Y 3149 fcmp(tmp, 1, true, false); // Stack: X Y 3150 jcc(Assembler::above, x_negative); 3151 3152 // X >= 0 3153 3154 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y 3155 fld_s(1); // Stack: X Y X Y 3156 fast_pow(); // Stack: X^Y X Y 3157 fcmp(tmp, 0, false, false); // Stack: X^Y X Y 3158 // X^Y not equal to itself: X^Y is NaN go to slow case. 3159 jcc(Assembler::parity, slow_case); 3160 // get rid of duplicate arguments. Stack: X^Y 3161 if (num_fpu_regs_in_use > 0) { 3162 fxch(); fpop(); 3163 fxch(); fpop(); 3164 } else { 3165 ffree(2); 3166 ffree(1); 3167 } 3168 jmp(done); 3169 3170 // X <= 0 3171 bind(x_negative); 3172 3173 fld_s(1); // Stack: Y X Y 3174 frndint(); // Stack: int(Y) X Y 3175 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y 3176 jcc(Assembler::notEqual, slow_case); 3177 3178 subptr(rsp, 8); 3179 3180 // For X^Y, when X < 0, Y has to be an integer and the final 3181 // result depends on whether it's odd or even. We just checked 3182 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit 3183 // integer to test its parity. If int(Y) is huge and doesn't fit 3184 // in the 64 bit integer range, the integer indefinite value will 3185 // end up in the gp registers. Huge numbers are all even, the 3186 // integer indefinite number is even so it's fine. 3187 3188 #ifdef ASSERT 3189 // Let's check we don't end up with an integer indefinite number 3190 // when not expected. First test for huge numbers: check whether 3191 // int(Y)+1 == int(Y) which is true for very large numbers and 3192 // those are all even. A 64 bit integer is guaranteed to not 3193 // overflow for numbers where y+1 != y (when precision is set to 3194 // double precision). 3195 Label y_not_huge; 3196 3197 fld1(); // Stack: 1 int(Y) X Y 3198 fadd(1); // Stack: 1+int(Y) int(Y) X Y 3199 3200 #ifdef _LP64 3201 // trip to memory to force the precision down from double extended 3202 // precision 3203 fstp_d(Address(rsp, 0)); 3204 fld_d(Address(rsp, 0)); 3205 #endif 3206 3207 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y 3208 #endif 3209 3210 // move int(Y) as 64 bit integer to thread's stack 3211 fistp_d(Address(rsp,0)); // Stack: X Y 3212 3213 #ifdef ASSERT 3214 jcc(Assembler::notEqual, y_not_huge); 3215 3216 // Y is huge so we know it's even. It may not fit in a 64 bit 3217 // integer and we don't want the debug code below to see the 3218 // integer indefinite value so overwrite int(Y) on the thread's 3219 // stack with 0. 3220 movl(Address(rsp, 0), 0); 3221 movl(Address(rsp, 4), 0); 3222 3223 bind(y_not_huge); 3224 #endif 3225 3226 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y 3227 fld_s(1); // Stack: X Y X Y 3228 fabs(); // Stack: abs(X) Y X Y 3229 fast_pow(); // Stack: abs(X)^Y X Y 3230 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y 3231 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. 3232 3233 pop(tmp2); 3234 NOT_LP64(pop(tmp3)); 3235 jcc(Assembler::parity, slow_case); 3236 3237 #ifdef ASSERT 3238 // Check that int(Y) is not integer indefinite value (int 3239 // overflow). Shouldn't happen because for values that would 3240 // overflow, 1+int(Y)==Y which was tested earlier. 3241 #ifndef _LP64 3242 { 3243 Label integer; 3244 testl(tmp2, tmp2); 3245 jcc(Assembler::notZero, integer); 3246 cmpl(tmp3, 0x80000000); 3247 jcc(Assembler::notZero, integer); 3248 STOP("integer indefinite value shouldn't be seen here"); 3249 bind(integer); 3250 } 3251 #else 3252 { 3253 Label integer; 3254 mov(tmp3, tmp2); // preserve tmp2 for parity check below 3255 shlq(tmp3, 1); 3256 jcc(Assembler::carryClear, integer); 3257 jcc(Assembler::notZero, integer); 3258 STOP("integer indefinite value shouldn't be seen here"); 3259 bind(integer); 3260 } 3261 #endif 3262 #endif 3263 3264 // get rid of duplicate arguments. Stack: X^Y 3265 if (num_fpu_regs_in_use > 0) { 3266 fxch(); fpop(); 3267 fxch(); fpop(); 3268 } else { 3269 ffree(2); 3270 ffree(1); 3271 } 3272 3273 testl(tmp2, 1); 3274 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y 3275 // X <= 0, Y even: X^Y = -abs(X)^Y 3276 3277 fchs(); // Stack: -abs(X)^Y Y 3278 jmp(done); 3279 3280 // slow case: runtime call 3281 bind(slow_case); 3282 3283 fpop(); // pop incorrect result or int(Y) 3284 3285 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), 2, num_fpu_regs_in_use); 3286 3287 // Come here with result in F-TOS 3288 bind(done); 3289 } 3290 3291 void MacroAssembler::fpop() { 3292 ffree(); 3293 fincstp(); 3294 } 3295 3296 void MacroAssembler::load_float(Address src) { 3297 if (UseSSE >= 1) { 3298 movflt(xmm0, src); 3299 } else { 3300 LP64_ONLY(ShouldNotReachHere()); 3301 NOT_LP64(fld_s(src)); 3302 } 3303 } 3304 3305 void MacroAssembler::store_float(Address dst) { 3306 if (UseSSE >= 1) { 3307 movflt(dst, xmm0); 3308 } else { 3309 LP64_ONLY(ShouldNotReachHere()); 3310 NOT_LP64(fstp_s(dst)); 3311 } 3312 } 3313 3314 void MacroAssembler::load_double(Address src) { 3315 if (UseSSE >= 2) { 3316 movdbl(xmm0, src); 3317 } else { 3318 LP64_ONLY(ShouldNotReachHere()); 3319 NOT_LP64(fld_d(src)); 3320 } 3321 } 3322 3323 void MacroAssembler::store_double(Address dst) { 3324 if (UseSSE >= 2) { 3325 movdbl(dst, xmm0); 3326 } else { 3327 LP64_ONLY(ShouldNotReachHere()); 3328 NOT_LP64(fstp_d(dst)); 3329 } 3330 } 3331 3332 void MacroAssembler::fremr(Register tmp) { 3333 save_rax(tmp); 3334 { Label L; 3335 bind(L); 3336 fprem(); 3337 fwait(); fnstsw_ax(); 3338 #ifdef _LP64 3339 testl(rax, 0x400); 3340 jcc(Assembler::notEqual, L); 3341 #else 3342 sahf(); 3343 jcc(Assembler::parity, L); 3344 #endif // _LP64 3345 } 3346 restore_rax(tmp); 3347 // Result is in ST0. 3348 // Note: fxch & fpop to get rid of ST1 3349 // (otherwise FPU stack could overflow eventually) 3350 fxch(1); 3351 fpop(); 3352 } 3353 3354 3355 void MacroAssembler::incrementl(AddressLiteral dst) { 3356 if (reachable(dst)) { 3357 incrementl(as_Address(dst)); 3358 } else { 3359 lea(rscratch1, dst); 3360 incrementl(Address(rscratch1, 0)); 3361 } 3362 } 3363 3364 void MacroAssembler::incrementl(ArrayAddress dst) { 3365 incrementl(as_Address(dst)); 3366 } 3367 3368 void MacroAssembler::incrementl(Register reg, int value) { 3369 if (value == min_jint) {addl(reg, value) ; return; } 3370 if (value < 0) { decrementl(reg, -value); return; } 3371 if (value == 0) { ; return; } 3372 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3373 /* else */ { addl(reg, value) ; return; } 3374 } 3375 3376 void MacroAssembler::incrementl(Address dst, int value) { 3377 if (value == min_jint) {addl(dst, value) ; return; } 3378 if (value < 0) { decrementl(dst, -value); return; } 3379 if (value == 0) { ; return; } 3380 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3381 /* else */ { addl(dst, value) ; return; } 3382 } 3383 3384 void MacroAssembler::jump(AddressLiteral dst) { 3385 if (reachable(dst)) { 3386 jmp_literal(dst.target(), dst.rspec()); 3387 } else { 3388 lea(rscratch1, dst); 3389 jmp(rscratch1); 3390 } 3391 } 3392 3393 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3394 if (reachable(dst)) { 3395 InstructionMark im(this); 3396 relocate(dst.reloc()); 3397 const int short_size = 2; 3398 const int long_size = 6; 3399 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3400 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3401 // 0111 tttn #8-bit disp 3402 emit_int8(0x70 | cc); 3403 emit_int8((offs - short_size) & 0xFF); 3404 } else { 3405 // 0000 1111 1000 tttn #32-bit disp 3406 emit_int8(0x0F); 3407 emit_int8((unsigned char)(0x80 | cc)); 3408 emit_int32(offs - long_size); 3409 } 3410 } else { 3411 #ifdef ASSERT 3412 warning("reversing conditional branch"); 3413 #endif /* ASSERT */ 3414 Label skip; 3415 jccb(reverse[cc], skip); 3416 lea(rscratch1, dst); 3417 Assembler::jmp(rscratch1); 3418 bind(skip); 3419 } 3420 } 3421 3422 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3423 if (reachable(src)) { 3424 Assembler::ldmxcsr(as_Address(src)); 3425 } else { 3426 lea(rscratch1, src); 3427 Assembler::ldmxcsr(Address(rscratch1, 0)); 3428 } 3429 } 3430 3431 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3432 int off; 3433 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3434 off = offset(); 3435 movsbl(dst, src); // movsxb 3436 } else { 3437 off = load_unsigned_byte(dst, src); 3438 shll(dst, 24); 3439 sarl(dst, 24); 3440 } 3441 return off; 3442 } 3443 3444 // Note: load_signed_short used to be called load_signed_word. 3445 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3446 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3447 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3448 int MacroAssembler::load_signed_short(Register dst, Address src) { 3449 int off; 3450 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3451 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3452 // version but this is what 64bit has always done. This seems to imply 3453 // that users are only using 32bits worth. 3454 off = offset(); 3455 movswl(dst, src); // movsxw 3456 } else { 3457 off = load_unsigned_short(dst, src); 3458 shll(dst, 16); 3459 sarl(dst, 16); 3460 } 3461 return off; 3462 } 3463 3464 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3465 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3466 // and "3.9 Partial Register Penalties", p. 22). 3467 int off; 3468 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3469 off = offset(); 3470 movzbl(dst, src); // movzxb 3471 } else { 3472 xorl(dst, dst); 3473 off = offset(); 3474 movb(dst, src); 3475 } 3476 return off; 3477 } 3478 3479 // Note: load_unsigned_short used to be called load_unsigned_word. 3480 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3481 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3482 // and "3.9 Partial Register Penalties", p. 22). 3483 int off; 3484 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3485 off = offset(); 3486 movzwl(dst, src); // movzxw 3487 } else { 3488 xorl(dst, dst); 3489 off = offset(); 3490 movw(dst, src); 3491 } 3492 return off; 3493 } 3494 3495 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3496 switch (size_in_bytes) { 3497 #ifndef _LP64 3498 case 8: 3499 assert(dst2 != noreg, "second dest register required"); 3500 movl(dst, src); 3501 movl(dst2, src.plus_disp(BytesPerInt)); 3502 break; 3503 #else 3504 case 8: movq(dst, src); break; 3505 #endif 3506 case 4: movl(dst, src); break; 3507 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3508 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3509 default: ShouldNotReachHere(); 3510 } 3511 } 3512 3513 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3514 switch (size_in_bytes) { 3515 #ifndef _LP64 3516 case 8: 3517 assert(src2 != noreg, "second source register required"); 3518 movl(dst, src); 3519 movl(dst.plus_disp(BytesPerInt), src2); 3520 break; 3521 #else 3522 case 8: movq(dst, src); break; 3523 #endif 3524 case 4: movl(dst, src); break; 3525 case 2: movw(dst, src); break; 3526 case 1: movb(dst, src); break; 3527 default: ShouldNotReachHere(); 3528 } 3529 } 3530 3531 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3532 if (reachable(dst)) { 3533 movl(as_Address(dst), src); 3534 } else { 3535 lea(rscratch1, dst); 3536 movl(Address(rscratch1, 0), src); 3537 } 3538 } 3539 3540 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3541 if (reachable(src)) { 3542 movl(dst, as_Address(src)); 3543 } else { 3544 lea(rscratch1, src); 3545 movl(dst, Address(rscratch1, 0)); 3546 } 3547 } 3548 3549 // C++ bool manipulation 3550 3551 void MacroAssembler::movbool(Register dst, Address src) { 3552 if(sizeof(bool) == 1) 3553 movb(dst, src); 3554 else if(sizeof(bool) == 2) 3555 movw(dst, src); 3556 else if(sizeof(bool) == 4) 3557 movl(dst, src); 3558 else 3559 // unsupported 3560 ShouldNotReachHere(); 3561 } 3562 3563 void MacroAssembler::movbool(Address dst, bool boolconst) { 3564 if(sizeof(bool) == 1) 3565 movb(dst, (int) boolconst); 3566 else if(sizeof(bool) == 2) 3567 movw(dst, (int) boolconst); 3568 else if(sizeof(bool) == 4) 3569 movl(dst, (int) boolconst); 3570 else 3571 // unsupported 3572 ShouldNotReachHere(); 3573 } 3574 3575 void MacroAssembler::movbool(Address dst, Register src) { 3576 if(sizeof(bool) == 1) 3577 movb(dst, src); 3578 else if(sizeof(bool) == 2) 3579 movw(dst, src); 3580 else if(sizeof(bool) == 4) 3581 movl(dst, src); 3582 else 3583 // unsupported 3584 ShouldNotReachHere(); 3585 } 3586 3587 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3588 movb(as_Address(dst), src); 3589 } 3590 3591 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3592 if (reachable(src)) { 3593 movdl(dst, as_Address(src)); 3594 } else { 3595 lea(rscratch1, src); 3596 movdl(dst, Address(rscratch1, 0)); 3597 } 3598 } 3599 3600 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3601 if (reachable(src)) { 3602 movq(dst, as_Address(src)); 3603 } else { 3604 lea(rscratch1, src); 3605 movq(dst, Address(rscratch1, 0)); 3606 } 3607 } 3608 3609 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3610 if (reachable(src)) { 3611 if (UseXmmLoadAndClearUpper) { 3612 movsd (dst, as_Address(src)); 3613 } else { 3614 movlpd(dst, as_Address(src)); 3615 } 3616 } else { 3617 lea(rscratch1, src); 3618 if (UseXmmLoadAndClearUpper) { 3619 movsd (dst, Address(rscratch1, 0)); 3620 } else { 3621 movlpd(dst, Address(rscratch1, 0)); 3622 } 3623 } 3624 } 3625 3626 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3627 if (reachable(src)) { 3628 movss(dst, as_Address(src)); 3629 } else { 3630 lea(rscratch1, src); 3631 movss(dst, Address(rscratch1, 0)); 3632 } 3633 } 3634 3635 void MacroAssembler::movptr(Register dst, Register src) { 3636 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3637 } 3638 3639 void MacroAssembler::movptr(Register dst, Address src) { 3640 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3641 } 3642 3643 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3644 void MacroAssembler::movptr(Register dst, intptr_t src) { 3645 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3646 } 3647 3648 void MacroAssembler::movptr(Address dst, Register src) { 3649 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3650 } 3651 3652 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3653 if (reachable(src)) { 3654 Assembler::movdqu(dst, as_Address(src)); 3655 } else { 3656 lea(rscratch1, src); 3657 Assembler::movdqu(dst, Address(rscratch1, 0)); 3658 } 3659 } 3660 3661 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3662 if (reachable(src)) { 3663 Assembler::movdqa(dst, as_Address(src)); 3664 } else { 3665 lea(rscratch1, src); 3666 Assembler::movdqa(dst, Address(rscratch1, 0)); 3667 } 3668 } 3669 3670 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3671 if (reachable(src)) { 3672 Assembler::movsd(dst, as_Address(src)); 3673 } else { 3674 lea(rscratch1, src); 3675 Assembler::movsd(dst, Address(rscratch1, 0)); 3676 } 3677 } 3678 3679 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3680 if (reachable(src)) { 3681 Assembler::movss(dst, as_Address(src)); 3682 } else { 3683 lea(rscratch1, src); 3684 Assembler::movss(dst, Address(rscratch1, 0)); 3685 } 3686 } 3687 3688 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3689 if (reachable(src)) { 3690 Assembler::mulsd(dst, as_Address(src)); 3691 } else { 3692 lea(rscratch1, src); 3693 Assembler::mulsd(dst, Address(rscratch1, 0)); 3694 } 3695 } 3696 3697 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3698 if (reachable(src)) { 3699 Assembler::mulss(dst, as_Address(src)); 3700 } else { 3701 lea(rscratch1, src); 3702 Assembler::mulss(dst, Address(rscratch1, 0)); 3703 } 3704 } 3705 3706 void MacroAssembler::null_check(Register reg, int offset) { 3707 if (needs_explicit_null_check(offset)) { 3708 // provoke OS NULL exception if reg = NULL by 3709 // accessing M[reg] w/o changing any (non-CC) registers 3710 // NOTE: cmpl is plenty here to provoke a segv 3711 cmpptr(rax, Address(reg, 0)); 3712 // Note: should probably use testl(rax, Address(reg, 0)); 3713 // may be shorter code (however, this version of 3714 // testl needs to be implemented first) 3715 } else { 3716 // nothing to do, (later) access of M[reg + offset] 3717 // will provoke OS NULL exception if reg = NULL 3718 } 3719 } 3720 3721 void MacroAssembler::os_breakpoint() { 3722 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3723 // (e.g., MSVC can't call ps() otherwise) 3724 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3725 } 3726 3727 void MacroAssembler::pop_CPU_state() { 3728 pop_FPU_state(); 3729 pop_IU_state(); 3730 } 3731 3732 void MacroAssembler::pop_FPU_state() { 3733 #ifndef _LP64 3734 frstor(Address(rsp, 0)); 3735 #else 3736 // AVX will continue to use the fxsave area. 3737 // EVEX needs to utilize the xsave area, which is under different 3738 // management. 3739 if(VM_Version::supports_evex()) { 3740 // EDX:EAX describe the XSAVE header and 3741 // are obtained while fetching info for XCR0 via cpuid. 3742 // These two registers make up 64-bits in the header for which bits 3743 // 62:10 are currently reserved for future implementations and unused. Bit 63 3744 // is unused for our implementation as we do not utilize 3745 // compressed XSAVE areas. Bits 9..8 are currently ignored as we do not use 3746 // the functionality for PKRU state and MSR tracing. 3747 // Ergo we are primarily concerned with bits 7..0, which define 3748 // which ISA extensions and features are enabled for a given machine and are 3749 // defined in XemXcr0Eax and is used to map the XSAVE area 3750 // for restoring registers as described via XCR0. 3751 movl(rdx,VM_Version::get_xsave_header_upper_segment()); 3752 movl(rax,VM_Version::get_xsave_header_lower_segment()); 3753 xrstor(Address(rsp, 0)); 3754 } else { 3755 fxrstor(Address(rsp, 0)); 3756 } 3757 #endif 3758 addptr(rsp, FPUStateSizeInWords * wordSize); 3759 } 3760 3761 void MacroAssembler::pop_IU_state() { 3762 popa(); 3763 LP64_ONLY(addq(rsp, 8)); 3764 popf(); 3765 } 3766 3767 // Save Integer and Float state 3768 // Warning: Stack must be 16 byte aligned (64bit) 3769 void MacroAssembler::push_CPU_state() { 3770 push_IU_state(); 3771 push_FPU_state(); 3772 } 3773 3774 #ifdef _LP64 3775 #define XSTATE_BV 0x200 3776 #endif 3777 3778 void MacroAssembler::push_FPU_state() { 3779 subptr(rsp, FPUStateSizeInWords * wordSize); 3780 #ifndef _LP64 3781 fnsave(Address(rsp, 0)); 3782 fwait(); 3783 #else 3784 // AVX will continue to use the fxsave area. 3785 // EVEX needs to utilize the xsave area, which is under different 3786 // management. 3787 if(VM_Version::supports_evex()) { 3788 // Save a copy of EAX and EDX 3789 push(rax); 3790 push(rdx); 3791 // EDX:EAX describe the XSAVE header and 3792 // are obtained while fetching info for XCR0 via cpuid. 3793 // These two registers make up 64-bits in the header for which bits 3794 // 62:10 are currently reserved for future implementations and unused. Bit 63 3795 // is unused for our implementation as we do not utilize 3796 // compressed XSAVE areas. Bits 9..8 are currently ignored as we do not use 3797 // the functionality for PKRU state and MSR tracing. 3798 // Ergo we are primarily concerned with bits 7..0, which define 3799 // which ISA extensions and features are enabled for a given machine and are 3800 // defined in XemXcr0Eax and is used to program XSAVE area 3801 // for saving the required registers as defined in XCR0. 3802 int xcr0_edx = VM_Version::get_xsave_header_upper_segment(); 3803 int xcr0_eax = VM_Version::get_xsave_header_lower_segment(); 3804 movl(rdx,xcr0_edx); 3805 movl(rax,xcr0_eax); 3806 xsave(Address(rsp, wordSize*2)); 3807 // now Apply control bits and clear bytes 8..23 in the header 3808 pop(rdx); 3809 pop(rax); 3810 movl(Address(rsp, XSTATE_BV), xcr0_eax); 3811 movl(Address(rsp, XSTATE_BV+4), xcr0_edx); 3812 andq(Address(rsp, XSTATE_BV+8), 0); 3813 andq(Address(rsp, XSTATE_BV+16), 0); 3814 } else { 3815 fxsave(Address(rsp, 0)); 3816 } 3817 #endif // LP64 3818 } 3819 3820 void MacroAssembler::push_IU_state() { 3821 // Push flags first because pusha kills them 3822 pushf(); 3823 // Make sure rsp stays 16-byte aligned 3824 LP64_ONLY(subq(rsp, 8)); 3825 pusha(); 3826 } 3827 3828 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { 3829 // determine java_thread register 3830 if (!java_thread->is_valid()) { 3831 java_thread = rdi; 3832 get_thread(java_thread); 3833 } 3834 // we must set sp to zero to clear frame 3835 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3836 if (clear_fp) { 3837 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3838 } 3839 3840 if (clear_pc) 3841 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3842 3843 } 3844 3845 void MacroAssembler::restore_rax(Register tmp) { 3846 if (tmp == noreg) pop(rax); 3847 else if (tmp != rax) mov(rax, tmp); 3848 } 3849 3850 void MacroAssembler::round_to(Register reg, int modulus) { 3851 addptr(reg, modulus - 1); 3852 andptr(reg, -modulus); 3853 } 3854 3855 void MacroAssembler::save_rax(Register tmp) { 3856 if (tmp == noreg) push(rax); 3857 else if (tmp != rax) mov(tmp, rax); 3858 } 3859 3860 // Write serialization page so VM thread can do a pseudo remote membar. 3861 // We use the current thread pointer to calculate a thread specific 3862 // offset to write to within the page. This minimizes bus traffic 3863 // due to cache line collision. 3864 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3865 movl(tmp, thread); 3866 shrl(tmp, os::get_serialize_page_shift_count()); 3867 andl(tmp, (os::vm_page_size() - sizeof(int))); 3868 3869 Address index(noreg, tmp, Address::times_1); 3870 ExternalAddress page(os::get_memory_serialize_page()); 3871 3872 // Size of store must match masking code above 3873 movl(as_Address(ArrayAddress(page, index)), tmp); 3874 } 3875 3876 // Calls to C land 3877 // 3878 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3879 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3880 // has to be reset to 0. This is required to allow proper stack traversal. 3881 void MacroAssembler::set_last_Java_frame(Register java_thread, 3882 Register last_java_sp, 3883 Register last_java_fp, 3884 address last_java_pc) { 3885 // determine java_thread register 3886 if (!java_thread->is_valid()) { 3887 java_thread = rdi; 3888 get_thread(java_thread); 3889 } 3890 // determine last_java_sp register 3891 if (!last_java_sp->is_valid()) { 3892 last_java_sp = rsp; 3893 } 3894 3895 // last_java_fp is optional 3896 3897 if (last_java_fp->is_valid()) { 3898 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3899 } 3900 3901 // last_java_pc is optional 3902 3903 if (last_java_pc != NULL) { 3904 lea(Address(java_thread, 3905 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3906 InternalAddress(last_java_pc)); 3907 3908 } 3909 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3910 } 3911 3912 void MacroAssembler::shlptr(Register dst, int imm8) { 3913 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3914 } 3915 3916 void MacroAssembler::shrptr(Register dst, int imm8) { 3917 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3918 } 3919 3920 void MacroAssembler::sign_extend_byte(Register reg) { 3921 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3922 movsbl(reg, reg); // movsxb 3923 } else { 3924 shll(reg, 24); 3925 sarl(reg, 24); 3926 } 3927 } 3928 3929 void MacroAssembler::sign_extend_short(Register reg) { 3930 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3931 movswl(reg, reg); // movsxw 3932 } else { 3933 shll(reg, 16); 3934 sarl(reg, 16); 3935 } 3936 } 3937 3938 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3939 assert(reachable(src), "Address should be reachable"); 3940 testl(dst, as_Address(src)); 3941 } 3942 3943 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 3944 if (reachable(src)) { 3945 Assembler::sqrtsd(dst, as_Address(src)); 3946 } else { 3947 lea(rscratch1, src); 3948 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 3949 } 3950 } 3951 3952 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 3953 if (reachable(src)) { 3954 Assembler::sqrtss(dst, as_Address(src)); 3955 } else { 3956 lea(rscratch1, src); 3957 Assembler::sqrtss(dst, Address(rscratch1, 0)); 3958 } 3959 } 3960 3961 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 3962 if (reachable(src)) { 3963 Assembler::subsd(dst, as_Address(src)); 3964 } else { 3965 lea(rscratch1, src); 3966 Assembler::subsd(dst, Address(rscratch1, 0)); 3967 } 3968 } 3969 3970 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 3971 if (reachable(src)) { 3972 Assembler::subss(dst, as_Address(src)); 3973 } else { 3974 lea(rscratch1, src); 3975 Assembler::subss(dst, Address(rscratch1, 0)); 3976 } 3977 } 3978 3979 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 3980 if (reachable(src)) { 3981 Assembler::ucomisd(dst, as_Address(src)); 3982 } else { 3983 lea(rscratch1, src); 3984 Assembler::ucomisd(dst, Address(rscratch1, 0)); 3985 } 3986 } 3987 3988 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 3989 if (reachable(src)) { 3990 Assembler::ucomiss(dst, as_Address(src)); 3991 } else { 3992 lea(rscratch1, src); 3993 Assembler::ucomiss(dst, Address(rscratch1, 0)); 3994 } 3995 } 3996 3997 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 3998 // Used in sign-bit flipping with aligned address. 3999 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4000 if (reachable(src)) { 4001 Assembler::xorpd(dst, as_Address(src)); 4002 } else { 4003 lea(rscratch1, src); 4004 Assembler::xorpd(dst, Address(rscratch1, 0)); 4005 } 4006 } 4007 4008 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4009 // Used in sign-bit flipping with aligned address. 4010 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4011 if (reachable(src)) { 4012 Assembler::xorps(dst, as_Address(src)); 4013 } else { 4014 lea(rscratch1, src); 4015 Assembler::xorps(dst, Address(rscratch1, 0)); 4016 } 4017 } 4018 4019 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4020 // Used in sign-bit flipping with aligned address. 4021 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4022 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4023 if (reachable(src)) { 4024 Assembler::pshufb(dst, as_Address(src)); 4025 } else { 4026 lea(rscratch1, src); 4027 Assembler::pshufb(dst, Address(rscratch1, 0)); 4028 } 4029 } 4030 4031 // AVX 3-operands instructions 4032 4033 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4034 if (reachable(src)) { 4035 vaddsd(dst, nds, as_Address(src)); 4036 } else { 4037 lea(rscratch1, src); 4038 vaddsd(dst, nds, Address(rscratch1, 0)); 4039 } 4040 } 4041 4042 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4043 if (reachable(src)) { 4044 vaddss(dst, nds, as_Address(src)); 4045 } else { 4046 lea(rscratch1, src); 4047 vaddss(dst, nds, Address(rscratch1, 0)); 4048 } 4049 } 4050 4051 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4052 if (reachable(src)) { 4053 vandpd(dst, nds, as_Address(src), vector_len); 4054 } else { 4055 lea(rscratch1, src); 4056 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 4057 } 4058 } 4059 4060 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4061 if (reachable(src)) { 4062 vandps(dst, nds, as_Address(src), vector_len); 4063 } else { 4064 lea(rscratch1, src); 4065 vandps(dst, nds, Address(rscratch1, 0), vector_len); 4066 } 4067 } 4068 4069 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4070 if (reachable(src)) { 4071 vdivsd(dst, nds, as_Address(src)); 4072 } else { 4073 lea(rscratch1, src); 4074 vdivsd(dst, nds, Address(rscratch1, 0)); 4075 } 4076 } 4077 4078 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4079 if (reachable(src)) { 4080 vdivss(dst, nds, as_Address(src)); 4081 } else { 4082 lea(rscratch1, src); 4083 vdivss(dst, nds, Address(rscratch1, 0)); 4084 } 4085 } 4086 4087 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4088 if (reachable(src)) { 4089 vmulsd(dst, nds, as_Address(src)); 4090 } else { 4091 lea(rscratch1, src); 4092 vmulsd(dst, nds, Address(rscratch1, 0)); 4093 } 4094 } 4095 4096 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4097 if (reachable(src)) { 4098 vmulss(dst, nds, as_Address(src)); 4099 } else { 4100 lea(rscratch1, src); 4101 vmulss(dst, nds, Address(rscratch1, 0)); 4102 } 4103 } 4104 4105 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4106 if (reachable(src)) { 4107 vsubsd(dst, nds, as_Address(src)); 4108 } else { 4109 lea(rscratch1, src); 4110 vsubsd(dst, nds, Address(rscratch1, 0)); 4111 } 4112 } 4113 4114 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4115 if (reachable(src)) { 4116 vsubss(dst, nds, as_Address(src)); 4117 } else { 4118 lea(rscratch1, src); 4119 vsubss(dst, nds, Address(rscratch1, 0)); 4120 } 4121 } 4122 4123 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4124 int nds_enc = nds->encoding(); 4125 int dst_enc = dst->encoding(); 4126 bool dst_upper_bank = (dst_enc > 15); 4127 bool nds_upper_bank = (nds_enc > 15); 4128 if (VM_Version::supports_avx512novl() && 4129 (nds_upper_bank || dst_upper_bank)) { 4130 if (dst_upper_bank) { 4131 subptr(rsp, 64); 4132 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4133 movflt(xmm0, nds); 4134 if (reachable(src)) { 4135 vxorps(xmm0, xmm0, as_Address(src), Assembler::AVX_128bit); 4136 } else { 4137 lea(rscratch1, src); 4138 vxorps(xmm0, xmm0, Address(rscratch1, 0), Assembler::AVX_128bit); 4139 } 4140 movflt(dst, xmm0); 4141 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4142 addptr(rsp, 64); 4143 } else { 4144 movflt(dst, nds); 4145 if (reachable(src)) { 4146 vxorps(dst, dst, as_Address(src), Assembler::AVX_128bit); 4147 } else { 4148 lea(rscratch1, src); 4149 vxorps(dst, dst, Address(rscratch1, 0), Assembler::AVX_128bit); 4150 } 4151 } 4152 } else { 4153 if (reachable(src)) { 4154 vxorps(dst, nds, as_Address(src), Assembler::AVX_128bit); 4155 } else { 4156 lea(rscratch1, src); 4157 vxorps(dst, nds, Address(rscratch1, 0), Assembler::AVX_128bit); 4158 } 4159 } 4160 } 4161 4162 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4163 int nds_enc = nds->encoding(); 4164 int dst_enc = dst->encoding(); 4165 bool dst_upper_bank = (dst_enc > 15); 4166 bool nds_upper_bank = (nds_enc > 15); 4167 if (VM_Version::supports_avx512novl() && 4168 (nds_upper_bank || dst_upper_bank)) { 4169 if (dst_upper_bank) { 4170 subptr(rsp, 64); 4171 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4172 movdbl(xmm0, nds); 4173 if (reachable(src)) { 4174 vxorps(xmm0, xmm0, as_Address(src), Assembler::AVX_128bit); 4175 } else { 4176 lea(rscratch1, src); 4177 vxorps(xmm0, xmm0, Address(rscratch1, 0), Assembler::AVX_128bit); 4178 } 4179 movdbl(dst, xmm0); 4180 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4181 addptr(rsp, 64); 4182 } else { 4183 movdbl(dst, nds); 4184 if (reachable(src)) { 4185 vxorps(dst, dst, as_Address(src), Assembler::AVX_128bit); 4186 } else { 4187 lea(rscratch1, src); 4188 vxorps(dst, dst, Address(rscratch1, 0), Assembler::AVX_128bit); 4189 } 4190 } 4191 } else { 4192 if (reachable(src)) { 4193 vxorpd(dst, nds, as_Address(src), Assembler::AVX_128bit); 4194 } else { 4195 lea(rscratch1, src); 4196 vxorpd(dst, nds, Address(rscratch1, 0), Assembler::AVX_128bit); 4197 } 4198 } 4199 } 4200 4201 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4202 if (reachable(src)) { 4203 vxorpd(dst, nds, as_Address(src), vector_len); 4204 } else { 4205 lea(rscratch1, src); 4206 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 4207 } 4208 } 4209 4210 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4211 if (reachable(src)) { 4212 vxorps(dst, nds, as_Address(src), vector_len); 4213 } else { 4214 lea(rscratch1, src); 4215 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 4216 } 4217 } 4218 4219 4220 ////////////////////////////////////////////////////////////////////////////////// 4221 #if INCLUDE_ALL_GCS 4222 4223 void MacroAssembler::g1_write_barrier_pre(Register obj, 4224 Register pre_val, 4225 Register thread, 4226 Register tmp, 4227 bool tosca_live, 4228 bool expand_call) { 4229 4230 // If expand_call is true then we expand the call_VM_leaf macro 4231 // directly to skip generating the check by 4232 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 4233 4234 #ifdef _LP64 4235 assert(thread == r15_thread, "must be"); 4236 #endif // _LP64 4237 4238 Label done; 4239 Label runtime; 4240 4241 assert(pre_val != noreg, "check this code"); 4242 4243 if (obj != noreg) { 4244 assert_different_registers(obj, pre_val, tmp); 4245 assert(pre_val != rax, "check this code"); 4246 } 4247 4248 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4249 PtrQueue::byte_offset_of_active())); 4250 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4251 PtrQueue::byte_offset_of_index())); 4252 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4253 PtrQueue::byte_offset_of_buf())); 4254 4255 4256 // Is marking active? 4257 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { 4258 cmpl(in_progress, 0); 4259 } else { 4260 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); 4261 cmpb(in_progress, 0); 4262 } 4263 jcc(Assembler::equal, done); 4264 4265 // Do we need to load the previous value? 4266 if (obj != noreg) { 4267 load_heap_oop(pre_val, Address(obj, 0)); 4268 } 4269 4270 // Is the previous value null? 4271 cmpptr(pre_val, (int32_t) NULL_WORD); 4272 jcc(Assembler::equal, done); 4273 4274 // Can we store original value in the thread's buffer? 4275 // Is index == 0? 4276 // (The index field is typed as size_t.) 4277 4278 movptr(tmp, index); // tmp := *index_adr 4279 cmpptr(tmp, 0); // tmp == 0? 4280 jcc(Assembler::equal, runtime); // If yes, goto runtime 4281 4282 subptr(tmp, wordSize); // tmp := tmp - wordSize 4283 movptr(index, tmp); // *index_adr := tmp 4284 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 4285 4286 // Record the previous value 4287 movptr(Address(tmp, 0), pre_val); 4288 jmp(done); 4289 4290 bind(runtime); 4291 // save the live input values 4292 if(tosca_live) push(rax); 4293 4294 if (obj != noreg && obj != rax) 4295 push(obj); 4296 4297 if (pre_val != rax) 4298 push(pre_val); 4299 4300 // Calling the runtime using the regular call_VM_leaf mechanism generates 4301 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 4302 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 4303 // 4304 // If we care generating the pre-barrier without a frame (e.g. in the 4305 // intrinsified Reference.get() routine) then ebp might be pointing to 4306 // the caller frame and so this check will most likely fail at runtime. 4307 // 4308 // Expanding the call directly bypasses the generation of the check. 4309 // So when we do not have have a full interpreter frame on the stack 4310 // expand_call should be passed true. 4311 4312 NOT_LP64( push(thread); ) 4313 4314 if (expand_call) { 4315 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 4316 pass_arg1(this, thread); 4317 pass_arg0(this, pre_val); 4318 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 4319 } else { 4320 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 4321 } 4322 4323 NOT_LP64( pop(thread); ) 4324 4325 // save the live input values 4326 if (pre_val != rax) 4327 pop(pre_val); 4328 4329 if (obj != noreg && obj != rax) 4330 pop(obj); 4331 4332 if(tosca_live) pop(rax); 4333 4334 bind(done); 4335 } 4336 4337 void MacroAssembler::g1_write_barrier_post(Register store_addr, 4338 Register new_val, 4339 Register thread, 4340 Register tmp, 4341 Register tmp2) { 4342 #ifdef _LP64 4343 assert(thread == r15_thread, "must be"); 4344 #endif // _LP64 4345 4346 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 4347 PtrQueue::byte_offset_of_index())); 4348 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 4349 PtrQueue::byte_offset_of_buf())); 4350 4351 CardTableModRefBS* ct = 4352 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 4353 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 4354 4355 Label done; 4356 Label runtime; 4357 4358 // Does store cross heap regions? 4359 4360 movptr(tmp, store_addr); 4361 xorptr(tmp, new_val); 4362 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 4363 jcc(Assembler::equal, done); 4364 4365 // crosses regions, storing NULL? 4366 4367 cmpptr(new_val, (int32_t) NULL_WORD); 4368 jcc(Assembler::equal, done); 4369 4370 // storing region crossing non-NULL, is card already dirty? 4371 4372 const Register card_addr = tmp; 4373 const Register cardtable = tmp2; 4374 4375 movptr(card_addr, store_addr); 4376 shrptr(card_addr, CardTableModRefBS::card_shift); 4377 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 4378 // a valid address and therefore is not properly handled by the relocation code. 4379 movptr(cardtable, (intptr_t)ct->byte_map_base); 4380 addptr(card_addr, cardtable); 4381 4382 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 4383 jcc(Assembler::equal, done); 4384 4385 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4386 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 4387 jcc(Assembler::equal, done); 4388 4389 4390 // storing a region crossing, non-NULL oop, card is clean. 4391 // dirty card and log. 4392 4393 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 4394 4395 cmpl(queue_index, 0); 4396 jcc(Assembler::equal, runtime); 4397 subl(queue_index, wordSize); 4398 movptr(tmp2, buffer); 4399 #ifdef _LP64 4400 movslq(rscratch1, queue_index); 4401 addq(tmp2, rscratch1); 4402 movq(Address(tmp2, 0), card_addr); 4403 #else 4404 addl(tmp2, queue_index); 4405 movl(Address(tmp2, 0), card_addr); 4406 #endif 4407 jmp(done); 4408 4409 bind(runtime); 4410 // save the live input values 4411 push(store_addr); 4412 push(new_val); 4413 #ifdef _LP64 4414 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 4415 #else 4416 push(thread); 4417 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 4418 pop(thread); 4419 #endif 4420 pop(new_val); 4421 pop(store_addr); 4422 4423 bind(done); 4424 } 4425 4426 #endif // INCLUDE_ALL_GCS 4427 ////////////////////////////////////////////////////////////////////////////////// 4428 4429 4430 void MacroAssembler::store_check(Register obj, Address dst) { 4431 store_check(obj); 4432 } 4433 4434 void MacroAssembler::store_check(Register obj) { 4435 // Does a store check for the oop in register obj. The content of 4436 // register obj is destroyed afterwards. 4437 BarrierSet* bs = Universe::heap()->barrier_set(); 4438 assert(bs->kind() == BarrierSet::CardTableForRS || 4439 bs->kind() == BarrierSet::CardTableExtension, 4440 "Wrong barrier set kind"); 4441 4442 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 4443 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 4444 4445 shrptr(obj, CardTableModRefBS::card_shift); 4446 4447 Address card_addr; 4448 4449 // The calculation for byte_map_base is as follows: 4450 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 4451 // So this essentially converts an address to a displacement and it will 4452 // never need to be relocated. On 64bit however the value may be too 4453 // large for a 32bit displacement. 4454 intptr_t disp = (intptr_t) ct->byte_map_base; 4455 if (is_simm32(disp)) { 4456 card_addr = Address(noreg, obj, Address::times_1, disp); 4457 } else { 4458 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 4459 // displacement and done in a single instruction given favorable mapping and a 4460 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 4461 // entry and that entry is not properly handled by the relocation code. 4462 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 4463 Address index(noreg, obj, Address::times_1); 4464 card_addr = as_Address(ArrayAddress(cardtable, index)); 4465 } 4466 4467 int dirty = CardTableModRefBS::dirty_card_val(); 4468 if (UseCondCardMark) { 4469 Label L_already_dirty; 4470 if (UseConcMarkSweepGC) { 4471 membar(Assembler::StoreLoad); 4472 } 4473 cmpb(card_addr, dirty); 4474 jcc(Assembler::equal, L_already_dirty); 4475 movb(card_addr, dirty); 4476 bind(L_already_dirty); 4477 } else { 4478 movb(card_addr, dirty); 4479 } 4480 } 4481 4482 void MacroAssembler::subptr(Register dst, int32_t imm32) { 4483 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 4484 } 4485 4486 // Force generation of a 4 byte immediate value even if it fits into 8bit 4487 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 4488 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 4489 } 4490 4491 void MacroAssembler::subptr(Register dst, Register src) { 4492 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 4493 } 4494 4495 // C++ bool manipulation 4496 void MacroAssembler::testbool(Register dst) { 4497 if(sizeof(bool) == 1) 4498 testb(dst, 0xff); 4499 else if(sizeof(bool) == 2) { 4500 // testw implementation needed for two byte bools 4501 ShouldNotReachHere(); 4502 } else if(sizeof(bool) == 4) 4503 testl(dst, dst); 4504 else 4505 // unsupported 4506 ShouldNotReachHere(); 4507 } 4508 4509 void MacroAssembler::testptr(Register dst, Register src) { 4510 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 4511 } 4512 4513 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 4514 void MacroAssembler::tlab_allocate(Register obj, 4515 Register var_size_in_bytes, 4516 int con_size_in_bytes, 4517 Register t1, 4518 Register t2, 4519 Label& slow_case) { 4520 assert_different_registers(obj, t1, t2); 4521 assert_different_registers(obj, var_size_in_bytes, t1); 4522 Register end = t2; 4523 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 4524 4525 verify_tlab(); 4526 4527 NOT_LP64(get_thread(thread)); 4528 4529 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 4530 if (var_size_in_bytes == noreg) { 4531 lea(end, Address(obj, con_size_in_bytes)); 4532 } else { 4533 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 4534 } 4535 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 4536 jcc(Assembler::above, slow_case); 4537 4538 // update the tlab top pointer 4539 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 4540 4541 // recover var_size_in_bytes if necessary 4542 if (var_size_in_bytes == end) { 4543 subptr(var_size_in_bytes, obj); 4544 } 4545 verify_tlab(); 4546 } 4547 4548 // Preserves rbx, and rdx. 4549 Register MacroAssembler::tlab_refill(Label& retry, 4550 Label& try_eden, 4551 Label& slow_case) { 4552 Register top = rax; 4553 Register t1 = rcx; 4554 Register t2 = rsi; 4555 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 4556 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 4557 Label do_refill, discard_tlab; 4558 4559 if (!Universe::heap()->supports_inline_contig_alloc()) { 4560 // No allocation in the shared eden. 4561 jmp(slow_case); 4562 } 4563 4564 NOT_LP64(get_thread(thread_reg)); 4565 4566 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4567 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 4568 4569 // calculate amount of free space 4570 subptr(t1, top); 4571 shrptr(t1, LogHeapWordSize); 4572 4573 // Retain tlab and allocate object in shared space if 4574 // the amount free in the tlab is too large to discard. 4575 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 4576 jcc(Assembler::lessEqual, discard_tlab); 4577 4578 // Retain 4579 // %%% yuck as movptr... 4580 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 4581 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 4582 if (TLABStats) { 4583 // increment number of slow_allocations 4584 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 4585 } 4586 jmp(try_eden); 4587 4588 bind(discard_tlab); 4589 if (TLABStats) { 4590 // increment number of refills 4591 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 4592 // accumulate wastage -- t1 is amount free in tlab 4593 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 4594 } 4595 4596 // if tlab is currently allocated (top or end != null) then 4597 // fill [top, end + alignment_reserve) with array object 4598 testptr(top, top); 4599 jcc(Assembler::zero, do_refill); 4600 4601 // set up the mark word 4602 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 4603 // set the length to the remaining space 4604 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 4605 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 4606 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 4607 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 4608 // set klass to intArrayKlass 4609 // dubious reloc why not an oop reloc? 4610 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 4611 // store klass last. concurrent gcs assumes klass length is valid if 4612 // klass field is not null. 4613 store_klass(top, t1); 4614 4615 movptr(t1, top); 4616 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 4617 incr_allocated_bytes(thread_reg, t1, 0); 4618 4619 // refill the tlab with an eden allocation 4620 bind(do_refill); 4621 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 4622 shlptr(t1, LogHeapWordSize); 4623 // allocate new tlab, address returned in top 4624 eden_allocate(top, t1, 0, t2, slow_case); 4625 4626 // Check that t1 was preserved in eden_allocate. 4627 #ifdef ASSERT 4628 if (UseTLAB) { 4629 Label ok; 4630 Register tsize = rsi; 4631 assert_different_registers(tsize, thread_reg, t1); 4632 push(tsize); 4633 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 4634 shlptr(tsize, LogHeapWordSize); 4635 cmpptr(t1, tsize); 4636 jcc(Assembler::equal, ok); 4637 STOP("assert(t1 != tlab size)"); 4638 should_not_reach_here(); 4639 4640 bind(ok); 4641 pop(tsize); 4642 } 4643 #endif 4644 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 4645 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 4646 addptr(top, t1); 4647 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 4648 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 4649 verify_tlab(); 4650 jmp(retry); 4651 4652 return thread_reg; // for use by caller 4653 } 4654 4655 void MacroAssembler::incr_allocated_bytes(Register thread, 4656 Register var_size_in_bytes, 4657 int con_size_in_bytes, 4658 Register t1) { 4659 if (!thread->is_valid()) { 4660 #ifdef _LP64 4661 thread = r15_thread; 4662 #else 4663 assert(t1->is_valid(), "need temp reg"); 4664 thread = t1; 4665 get_thread(thread); 4666 #endif 4667 } 4668 4669 #ifdef _LP64 4670 if (var_size_in_bytes->is_valid()) { 4671 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 4672 } else { 4673 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 4674 } 4675 #else 4676 if (var_size_in_bytes->is_valid()) { 4677 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 4678 } else { 4679 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 4680 } 4681 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 4682 #endif 4683 } 4684 4685 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { 4686 pusha(); 4687 4688 // if we are coming from c1, xmm registers may be live 4689 int off = 0; 4690 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8); 4691 if (UseAVX > 2) { 4692 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8); 4693 } 4694 4695 if (UseSSE == 1) { 4696 subptr(rsp, sizeof(jdouble)*8); 4697 for (int n = 0; n < 8; n++) { 4698 movflt(Address(rsp, off++*sizeof(jdouble)), as_XMMRegister(n)); 4699 } 4700 } else if (UseSSE >= 2) { 4701 if (UseAVX > 2) { 4702 push(rbx); 4703 movl(rbx, 0xffff); 4704 kmovwl(k1, rbx); 4705 pop(rbx); 4706 } 4707 #ifdef COMPILER2 4708 if (MaxVectorSize > 16) { 4709 if(UseAVX > 2) { 4710 // Save upper half of ZMM registes 4711 subptr(rsp, 32*num_xmm_regs); 4712 for (int n = 0; n < num_xmm_regs; n++) { 4713 vextractf64x4h(Address(rsp, off++*32), as_XMMRegister(n)); 4714 } 4715 off = 0; 4716 } 4717 assert(UseAVX > 0, "256 bit vectors are supported only with AVX"); 4718 // Save upper half of YMM registes 4719 subptr(rsp, 16*num_xmm_regs); 4720 for (int n = 0; n < num_xmm_regs; n++) { 4721 vextractf128h(Address(rsp, off++*16), as_XMMRegister(n)); 4722 } 4723 } 4724 #endif 4725 // Save whole 128bit (16 bytes) XMM registers 4726 subptr(rsp, 16*num_xmm_regs); 4727 off = 0; 4728 #ifdef _LP64 4729 if (VM_Version::supports_avx512novl()) { 4730 for (int n = 0; n < num_xmm_regs; n++) { 4731 vextractf32x4h(Address(rsp, off++*16), as_XMMRegister(n), 0); 4732 } 4733 } else { 4734 for (int n = 0; n < num_xmm_regs; n++) { 4735 movdqu(Address(rsp, off++*16), as_XMMRegister(n)); 4736 } 4737 } 4738 #else 4739 for (int n = 0; n < num_xmm_regs; n++) { 4740 movdqu(Address(rsp, off++*16), as_XMMRegister(n)); 4741 } 4742 #endif 4743 } 4744 4745 // Preserve registers across runtime call 4746 int incoming_argument_and_return_value_offset = -1; 4747 if (num_fpu_regs_in_use > 1) { 4748 // Must preserve all other FPU regs (could alternatively convert 4749 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash 4750 // FPU state, but can not trust C compiler) 4751 NEEDS_CLEANUP; 4752 // NOTE that in this case we also push the incoming argument(s) to 4753 // the stack and restore it later; we also use this stack slot to 4754 // hold the return value from dsin, dcos etc. 4755 for (int i = 0; i < num_fpu_regs_in_use; i++) { 4756 subptr(rsp, sizeof(jdouble)); 4757 fstp_d(Address(rsp, 0)); 4758 } 4759 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); 4760 for (int i = nb_args-1; i >= 0; i--) { 4761 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); 4762 } 4763 } 4764 4765 subptr(rsp, nb_args*sizeof(jdouble)); 4766 for (int i = 0; i < nb_args; i++) { 4767 fstp_d(Address(rsp, i*sizeof(jdouble))); 4768 } 4769 4770 #ifdef _LP64 4771 if (nb_args > 0) { 4772 movdbl(xmm0, Address(rsp, 0)); 4773 } 4774 if (nb_args > 1) { 4775 movdbl(xmm1, Address(rsp, sizeof(jdouble))); 4776 } 4777 assert(nb_args <= 2, "unsupported number of args"); 4778 #endif // _LP64 4779 4780 // NOTE: we must not use call_VM_leaf here because that requires a 4781 // complete interpreter frame in debug mode -- same bug as 4387334 4782 // MacroAssembler::call_VM_leaf_base is perfectly safe and will 4783 // do proper 64bit abi 4784 4785 NEEDS_CLEANUP; 4786 // Need to add stack banging before this runtime call if it needs to 4787 // be taken; however, there is no generic stack banging routine at 4788 // the MacroAssembler level 4789 4790 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); 4791 4792 #ifdef _LP64 4793 movsd(Address(rsp, 0), xmm0); 4794 fld_d(Address(rsp, 0)); 4795 #endif // _LP64 4796 addptr(rsp, sizeof(jdouble)*nb_args); 4797 if (num_fpu_regs_in_use > 1) { 4798 // Must save return value to stack and then restore entire FPU 4799 // stack except incoming arguments 4800 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); 4801 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { 4802 fld_d(Address(rsp, 0)); 4803 addptr(rsp, sizeof(jdouble)); 4804 } 4805 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); 4806 addptr(rsp, sizeof(jdouble)*nb_args); 4807 } 4808 4809 off = 0; 4810 if (UseSSE == 1) { 4811 for (int n = 0; n < 8; n++) { 4812 movflt(as_XMMRegister(n), Address(rsp, off++*sizeof(jdouble))); 4813 } 4814 addptr(rsp, sizeof(jdouble)*8); 4815 } else if (UseSSE >= 2) { 4816 // Restore whole 128bit (16 bytes) XMM regiters 4817 #ifdef _LP64 4818 if (VM_Version::supports_avx512novl()) { 4819 for (int n = 0; n < num_xmm_regs; n++) { 4820 vinsertf32x4h(as_XMMRegister(n), Address(rsp, off++*16), 0); 4821 } 4822 } 4823 else { 4824 for (int n = 0; n < num_xmm_regs; n++) { 4825 movdqu(as_XMMRegister(n), Address(rsp, off++*16)); 4826 } 4827 } 4828 #else 4829 for (int n = 0; n < num_xmm_regs; n++) { 4830 movdqu(as_XMMRegister(n), Address(rsp, off++ * 16)); 4831 } 4832 #endif 4833 addptr(rsp, 16*num_xmm_regs); 4834 4835 #ifdef COMPILER2 4836 if (MaxVectorSize > 16) { 4837 // Restore upper half of YMM registes. 4838 off = 0; 4839 for (int n = 0; n < num_xmm_regs; n++) { 4840 vinsertf128h(as_XMMRegister(n), Address(rsp, off++*16)); 4841 } 4842 addptr(rsp, 16*num_xmm_regs); 4843 if(UseAVX > 2) { 4844 off = 0; 4845 for (int n = 0; n < num_xmm_regs; n++) { 4846 vinsertf64x4h(as_XMMRegister(n), Address(rsp, off++*32)); 4847 } 4848 addptr(rsp, 32*num_xmm_regs); 4849 } 4850 } 4851 #endif 4852 } 4853 popa(); 4854 } 4855 4856 static const double pi_4 = 0.7853981633974483; 4857 4858 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { 4859 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) 4860 // was attempted in this code; unfortunately it appears that the 4861 // switch to 80-bit precision and back causes this to be 4862 // unprofitable compared with simply performing a runtime call if 4863 // the argument is out of the (-pi/4, pi/4) range. 4864 4865 Register tmp = noreg; 4866 if (!VM_Version::supports_cmov()) { 4867 // fcmp needs a temporary so preserve rbx, 4868 tmp = rbx; 4869 push(tmp); 4870 } 4871 4872 Label slow_case, done; 4873 4874 ExternalAddress pi4_adr = (address)&pi_4; 4875 if (reachable(pi4_adr)) { 4876 // x ?<= pi/4 4877 fld_d(pi4_adr); 4878 fld_s(1); // Stack: X PI/4 X 4879 fabs(); // Stack: |X| PI/4 X 4880 fcmp(tmp); 4881 jcc(Assembler::above, slow_case); 4882 4883 // fastest case: -pi/4 <= x <= pi/4 4884 switch(trig) { 4885 case 's': 4886 fsin(); 4887 break; 4888 case 'c': 4889 fcos(); 4890 break; 4891 case 't': 4892 ftan(); 4893 break; 4894 default: 4895 assert(false, "bad intrinsic"); 4896 break; 4897 } 4898 jmp(done); 4899 } 4900 4901 // slow case: runtime call 4902 bind(slow_case); 4903 4904 switch(trig) { 4905 case 's': 4906 { 4907 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); 4908 } 4909 break; 4910 case 'c': 4911 { 4912 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); 4913 } 4914 break; 4915 case 't': 4916 { 4917 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); 4918 } 4919 break; 4920 default: 4921 assert(false, "bad intrinsic"); 4922 break; 4923 } 4924 4925 // Come here with result in F-TOS 4926 bind(done); 4927 4928 if (tmp != noreg) { 4929 pop(tmp); 4930 } 4931 } 4932 4933 4934 // Look up the method for a megamorphic invokeinterface call. 4935 // The target method is determined by <intf_klass, itable_index>. 4936 // The receiver klass is in recv_klass. 4937 // On success, the result will be in method_result, and execution falls through. 4938 // On failure, execution transfers to the given label. 4939 void MacroAssembler::lookup_interface_method(Register recv_klass, 4940 Register intf_klass, 4941 RegisterOrConstant itable_index, 4942 Register method_result, 4943 Register scan_temp, 4944 Label& L_no_such_interface) { 4945 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 4946 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 4947 "caller must use same register for non-constant itable index as for method"); 4948 4949 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 4950 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; 4951 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 4952 int scan_step = itableOffsetEntry::size() * wordSize; 4953 int vte_size = vtableEntry::size() * wordSize; 4954 Address::ScaleFactor times_vte_scale = Address::times_ptr; 4955 assert(vte_size == wordSize, "else adjust times_vte_scale"); 4956 4957 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); 4958 4959 // %%% Could store the aligned, prescaled offset in the klassoop. 4960 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 4961 if (HeapWordsPerLong > 1) { 4962 // Round up to align_object_offset boundary 4963 // see code for InstanceKlass::start_of_itable! 4964 round_to(scan_temp, BytesPerLong); 4965 } 4966 4967 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 4968 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 4969 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 4970 4971 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 4972 // if (scan->interface() == intf) { 4973 // result = (klass + scan->offset() + itable_index); 4974 // } 4975 // } 4976 Label search, found_method; 4977 4978 for (int peel = 1; peel >= 0; peel--) { 4979 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 4980 cmpptr(intf_klass, method_result); 4981 4982 if (peel) { 4983 jccb(Assembler::equal, found_method); 4984 } else { 4985 jccb(Assembler::notEqual, search); 4986 // (invert the test to fall through to found_method...) 4987 } 4988 4989 if (!peel) break; 4990 4991 bind(search); 4992 4993 // Check that the previous entry is non-null. A null entry means that 4994 // the receiver class doesn't implement the interface, and wasn't the 4995 // same as when the caller was compiled. 4996 testptr(method_result, method_result); 4997 jcc(Assembler::zero, L_no_such_interface); 4998 addptr(scan_temp, scan_step); 4999 } 5000 5001 bind(found_method); 5002 5003 // Got a hit. 5004 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5005 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5006 } 5007 5008 5009 // virtual method calling 5010 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5011 RegisterOrConstant vtable_index, 5012 Register method_result) { 5013 const int base = InstanceKlass::vtable_start_offset() * wordSize; 5014 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5015 Address vtable_entry_addr(recv_klass, 5016 vtable_index, Address::times_ptr, 5017 base + vtableEntry::method_offset_in_bytes()); 5018 movptr(method_result, vtable_entry_addr); 5019 } 5020 5021 5022 void MacroAssembler::check_klass_subtype(Register sub_klass, 5023 Register super_klass, 5024 Register temp_reg, 5025 Label& L_success) { 5026 Label L_failure; 5027 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5028 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5029 bind(L_failure); 5030 } 5031 5032 5033 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5034 Register super_klass, 5035 Register temp_reg, 5036 Label* L_success, 5037 Label* L_failure, 5038 Label* L_slow_path, 5039 RegisterOrConstant super_check_offset) { 5040 assert_different_registers(sub_klass, super_klass, temp_reg); 5041 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5042 if (super_check_offset.is_register()) { 5043 assert_different_registers(sub_klass, super_klass, 5044 super_check_offset.as_register()); 5045 } else if (must_load_sco) { 5046 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5047 } 5048 5049 Label L_fallthrough; 5050 int label_nulls = 0; 5051 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5052 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5053 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5054 assert(label_nulls <= 1, "at most one NULL in the batch"); 5055 5056 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5057 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5058 Address super_check_offset_addr(super_klass, sco_offset); 5059 5060 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5061 // range of a jccb. If this routine grows larger, reconsider at 5062 // least some of these. 5063 #define local_jcc(assembler_cond, label) \ 5064 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5065 else jcc( assembler_cond, label) /*omit semi*/ 5066 5067 // Hacked jmp, which may only be used just before L_fallthrough. 5068 #define final_jmp(label) \ 5069 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5070 else jmp(label) /*omit semi*/ 5071 5072 // If the pointers are equal, we are done (e.g., String[] elements). 5073 // This self-check enables sharing of secondary supertype arrays among 5074 // non-primary types such as array-of-interface. Otherwise, each such 5075 // type would need its own customized SSA. 5076 // We move this check to the front of the fast path because many 5077 // type checks are in fact trivially successful in this manner, 5078 // so we get a nicely predicted branch right at the start of the check. 5079 cmpptr(sub_klass, super_klass); 5080 local_jcc(Assembler::equal, *L_success); 5081 5082 // Check the supertype display: 5083 if (must_load_sco) { 5084 // Positive movl does right thing on LP64. 5085 movl(temp_reg, super_check_offset_addr); 5086 super_check_offset = RegisterOrConstant(temp_reg); 5087 } 5088 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5089 cmpptr(super_klass, super_check_addr); // load displayed supertype 5090 5091 // This check has worked decisively for primary supers. 5092 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5093 // (Secondary supers are interfaces and very deeply nested subtypes.) 5094 // This works in the same check above because of a tricky aliasing 5095 // between the super_cache and the primary super display elements. 5096 // (The 'super_check_addr' can address either, as the case requires.) 5097 // Note that the cache is updated below if it does not help us find 5098 // what we need immediately. 5099 // So if it was a primary super, we can just fail immediately. 5100 // Otherwise, it's the slow path for us (no success at this point). 5101 5102 if (super_check_offset.is_register()) { 5103 local_jcc(Assembler::equal, *L_success); 5104 cmpl(super_check_offset.as_register(), sc_offset); 5105 if (L_failure == &L_fallthrough) { 5106 local_jcc(Assembler::equal, *L_slow_path); 5107 } else { 5108 local_jcc(Assembler::notEqual, *L_failure); 5109 final_jmp(*L_slow_path); 5110 } 5111 } else if (super_check_offset.as_constant() == sc_offset) { 5112 // Need a slow path; fast failure is impossible. 5113 if (L_slow_path == &L_fallthrough) { 5114 local_jcc(Assembler::equal, *L_success); 5115 } else { 5116 local_jcc(Assembler::notEqual, *L_slow_path); 5117 final_jmp(*L_success); 5118 } 5119 } else { 5120 // No slow path; it's a fast decision. 5121 if (L_failure == &L_fallthrough) { 5122 local_jcc(Assembler::equal, *L_success); 5123 } else { 5124 local_jcc(Assembler::notEqual, *L_failure); 5125 final_jmp(*L_success); 5126 } 5127 } 5128 5129 bind(L_fallthrough); 5130 5131 #undef local_jcc 5132 #undef final_jmp 5133 } 5134 5135 5136 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5137 Register super_klass, 5138 Register temp_reg, 5139 Register temp2_reg, 5140 Label* L_success, 5141 Label* L_failure, 5142 bool set_cond_codes) { 5143 assert_different_registers(sub_klass, super_klass, temp_reg); 5144 if (temp2_reg != noreg) 5145 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5146 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5147 5148 Label L_fallthrough; 5149 int label_nulls = 0; 5150 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5151 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5152 assert(label_nulls <= 1, "at most one NULL in the batch"); 5153 5154 // a couple of useful fields in sub_klass: 5155 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5156 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5157 Address secondary_supers_addr(sub_klass, ss_offset); 5158 Address super_cache_addr( sub_klass, sc_offset); 5159 5160 // Do a linear scan of the secondary super-klass chain. 5161 // This code is rarely used, so simplicity is a virtue here. 5162 // The repne_scan instruction uses fixed registers, which we must spill. 5163 // Don't worry too much about pre-existing connections with the input regs. 5164 5165 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5166 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5167 5168 // Get super_klass value into rax (even if it was in rdi or rcx). 5169 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5170 if (super_klass != rax || UseCompressedOops) { 5171 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5172 mov(rax, super_klass); 5173 } 5174 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5175 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5176 5177 #ifndef PRODUCT 5178 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5179 ExternalAddress pst_counter_addr((address) pst_counter); 5180 NOT_LP64( incrementl(pst_counter_addr) ); 5181 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5182 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5183 #endif //PRODUCT 5184 5185 // We will consult the secondary-super array. 5186 movptr(rdi, secondary_supers_addr); 5187 // Load the array length. (Positive movl does right thing on LP64.) 5188 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5189 // Skip to start of data. 5190 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5191 5192 // Scan RCX words at [RDI] for an occurrence of RAX. 5193 // Set NZ/Z based on last compare. 5194 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5195 // not change flags (only scas instruction which is repeated sets flags). 5196 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5197 5198 testptr(rax,rax); // Set Z = 0 5199 repne_scan(); 5200 5201 // Unspill the temp. registers: 5202 if (pushed_rdi) pop(rdi); 5203 if (pushed_rcx) pop(rcx); 5204 if (pushed_rax) pop(rax); 5205 5206 if (set_cond_codes) { 5207 // Special hack for the AD files: rdi is guaranteed non-zero. 5208 assert(!pushed_rdi, "rdi must be left non-NULL"); 5209 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5210 } 5211 5212 if (L_failure == &L_fallthrough) 5213 jccb(Assembler::notEqual, *L_failure); 5214 else jcc(Assembler::notEqual, *L_failure); 5215 5216 // Success. Cache the super we found and proceed in triumph. 5217 movptr(super_cache_addr, super_klass); 5218 5219 if (L_success != &L_fallthrough) { 5220 jmp(*L_success); 5221 } 5222 5223 #undef IS_A_TEMP 5224 5225 bind(L_fallthrough); 5226 } 5227 5228 5229 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5230 if (VM_Version::supports_cmov()) { 5231 cmovl(cc, dst, src); 5232 } else { 5233 Label L; 5234 jccb(negate_condition(cc), L); 5235 movl(dst, src); 5236 bind(L); 5237 } 5238 } 5239 5240 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5241 if (VM_Version::supports_cmov()) { 5242 cmovl(cc, dst, src); 5243 } else { 5244 Label L; 5245 jccb(negate_condition(cc), L); 5246 movl(dst, src); 5247 bind(L); 5248 } 5249 } 5250 5251 void MacroAssembler::verify_oop(Register reg, const char* s) { 5252 if (!VerifyOops) return; 5253 5254 // Pass register number to verify_oop_subroutine 5255 const char* b = NULL; 5256 { 5257 ResourceMark rm; 5258 stringStream ss; 5259 ss.print("verify_oop: %s: %s", reg->name(), s); 5260 b = code_string(ss.as_string()); 5261 } 5262 BLOCK_COMMENT("verify_oop {"); 5263 #ifdef _LP64 5264 push(rscratch1); // save r10, trashed by movptr() 5265 #endif 5266 push(rax); // save rax, 5267 push(reg); // pass register argument 5268 ExternalAddress buffer((address) b); 5269 // avoid using pushptr, as it modifies scratch registers 5270 // and our contract is not to modify anything 5271 movptr(rax, buffer.addr()); 5272 push(rax); 5273 // call indirectly to solve generation ordering problem 5274 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5275 call(rax); 5276 // Caller pops the arguments (oop, message) and restores rax, r10 5277 BLOCK_COMMENT("} verify_oop"); 5278 } 5279 5280 5281 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 5282 Register tmp, 5283 int offset) { 5284 intptr_t value = *delayed_value_addr; 5285 if (value != 0) 5286 return RegisterOrConstant(value + offset); 5287 5288 // load indirectly to solve generation ordering problem 5289 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 5290 5291 #ifdef ASSERT 5292 { Label L; 5293 testptr(tmp, tmp); 5294 if (WizardMode) { 5295 const char* buf = NULL; 5296 { 5297 ResourceMark rm; 5298 stringStream ss; 5299 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 5300 buf = code_string(ss.as_string()); 5301 } 5302 jcc(Assembler::notZero, L); 5303 STOP(buf); 5304 } else { 5305 jccb(Assembler::notZero, L); 5306 hlt(); 5307 } 5308 bind(L); 5309 } 5310 #endif 5311 5312 if (offset != 0) 5313 addptr(tmp, offset); 5314 5315 return RegisterOrConstant(tmp); 5316 } 5317 5318 5319 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 5320 int extra_slot_offset) { 5321 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 5322 int stackElementSize = Interpreter::stackElementSize; 5323 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 5324 #ifdef ASSERT 5325 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 5326 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 5327 #endif 5328 Register scale_reg = noreg; 5329 Address::ScaleFactor scale_factor = Address::no_scale; 5330 if (arg_slot.is_constant()) { 5331 offset += arg_slot.as_constant() * stackElementSize; 5332 } else { 5333 scale_reg = arg_slot.as_register(); 5334 scale_factor = Address::times(stackElementSize); 5335 } 5336 offset += wordSize; // return PC is on stack 5337 return Address(rsp, scale_reg, scale_factor, offset); 5338 } 5339 5340 5341 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 5342 if (!VerifyOops) return; 5343 5344 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 5345 // Pass register number to verify_oop_subroutine 5346 const char* b = NULL; 5347 { 5348 ResourceMark rm; 5349 stringStream ss; 5350 ss.print("verify_oop_addr: %s", s); 5351 b = code_string(ss.as_string()); 5352 } 5353 #ifdef _LP64 5354 push(rscratch1); // save r10, trashed by movptr() 5355 #endif 5356 push(rax); // save rax, 5357 // addr may contain rsp so we will have to adjust it based on the push 5358 // we just did (and on 64 bit we do two pushes) 5359 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 5360 // stores rax into addr which is backwards of what was intended. 5361 if (addr.uses(rsp)) { 5362 lea(rax, addr); 5363 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 5364 } else { 5365 pushptr(addr); 5366 } 5367 5368 ExternalAddress buffer((address) b); 5369 // pass msg argument 5370 // avoid using pushptr, as it modifies scratch registers 5371 // and our contract is not to modify anything 5372 movptr(rax, buffer.addr()); 5373 push(rax); 5374 5375 // call indirectly to solve generation ordering problem 5376 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5377 call(rax); 5378 // Caller pops the arguments (addr, message) and restores rax, r10. 5379 } 5380 5381 void MacroAssembler::verify_tlab() { 5382 #ifdef ASSERT 5383 if (UseTLAB && VerifyOops) { 5384 Label next, ok; 5385 Register t1 = rsi; 5386 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 5387 5388 push(t1); 5389 NOT_LP64(push(thread_reg)); 5390 NOT_LP64(get_thread(thread_reg)); 5391 5392 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5393 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5394 jcc(Assembler::aboveEqual, next); 5395 STOP("assert(top >= start)"); 5396 should_not_reach_here(); 5397 5398 bind(next); 5399 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5400 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5401 jcc(Assembler::aboveEqual, ok); 5402 STOP("assert(top <= end)"); 5403 should_not_reach_here(); 5404 5405 bind(ok); 5406 NOT_LP64(pop(thread_reg)); 5407 pop(t1); 5408 } 5409 #endif 5410 } 5411 5412 class ControlWord { 5413 public: 5414 int32_t _value; 5415 5416 int rounding_control() const { return (_value >> 10) & 3 ; } 5417 int precision_control() const { return (_value >> 8) & 3 ; } 5418 bool precision() const { return ((_value >> 5) & 1) != 0; } 5419 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5420 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5421 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5422 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5423 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5424 5425 void print() const { 5426 // rounding control 5427 const char* rc; 5428 switch (rounding_control()) { 5429 case 0: rc = "round near"; break; 5430 case 1: rc = "round down"; break; 5431 case 2: rc = "round up "; break; 5432 case 3: rc = "chop "; break; 5433 }; 5434 // precision control 5435 const char* pc; 5436 switch (precision_control()) { 5437 case 0: pc = "24 bits "; break; 5438 case 1: pc = "reserved"; break; 5439 case 2: pc = "53 bits "; break; 5440 case 3: pc = "64 bits "; break; 5441 }; 5442 // flags 5443 char f[9]; 5444 f[0] = ' '; 5445 f[1] = ' '; 5446 f[2] = (precision ()) ? 'P' : 'p'; 5447 f[3] = (underflow ()) ? 'U' : 'u'; 5448 f[4] = (overflow ()) ? 'O' : 'o'; 5449 f[5] = (zero_divide ()) ? 'Z' : 'z'; 5450 f[6] = (denormalized()) ? 'D' : 'd'; 5451 f[7] = (invalid ()) ? 'I' : 'i'; 5452 f[8] = '\x0'; 5453 // output 5454 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 5455 } 5456 5457 }; 5458 5459 class StatusWord { 5460 public: 5461 int32_t _value; 5462 5463 bool busy() const { return ((_value >> 15) & 1) != 0; } 5464 bool C3() const { return ((_value >> 14) & 1) != 0; } 5465 bool C2() const { return ((_value >> 10) & 1) != 0; } 5466 bool C1() const { return ((_value >> 9) & 1) != 0; } 5467 bool C0() const { return ((_value >> 8) & 1) != 0; } 5468 int top() const { return (_value >> 11) & 7 ; } 5469 bool error_status() const { return ((_value >> 7) & 1) != 0; } 5470 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 5471 bool precision() const { return ((_value >> 5) & 1) != 0; } 5472 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5473 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5474 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5475 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5476 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5477 5478 void print() const { 5479 // condition codes 5480 char c[5]; 5481 c[0] = (C3()) ? '3' : '-'; 5482 c[1] = (C2()) ? '2' : '-'; 5483 c[2] = (C1()) ? '1' : '-'; 5484 c[3] = (C0()) ? '0' : '-'; 5485 c[4] = '\x0'; 5486 // flags 5487 char f[9]; 5488 f[0] = (error_status()) ? 'E' : '-'; 5489 f[1] = (stack_fault ()) ? 'S' : '-'; 5490 f[2] = (precision ()) ? 'P' : '-'; 5491 f[3] = (underflow ()) ? 'U' : '-'; 5492 f[4] = (overflow ()) ? 'O' : '-'; 5493 f[5] = (zero_divide ()) ? 'Z' : '-'; 5494 f[6] = (denormalized()) ? 'D' : '-'; 5495 f[7] = (invalid ()) ? 'I' : '-'; 5496 f[8] = '\x0'; 5497 // output 5498 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 5499 } 5500 5501 }; 5502 5503 class TagWord { 5504 public: 5505 int32_t _value; 5506 5507 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 5508 5509 void print() const { 5510 printf("%04x", _value & 0xFFFF); 5511 } 5512 5513 }; 5514 5515 class FPU_Register { 5516 public: 5517 int32_t _m0; 5518 int32_t _m1; 5519 int16_t _ex; 5520 5521 bool is_indefinite() const { 5522 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 5523 } 5524 5525 void print() const { 5526 char sign = (_ex < 0) ? '-' : '+'; 5527 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 5528 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 5529 }; 5530 5531 }; 5532 5533 class FPU_State { 5534 public: 5535 enum { 5536 register_size = 10, 5537 number_of_registers = 8, 5538 register_mask = 7 5539 }; 5540 5541 ControlWord _control_word; 5542 StatusWord _status_word; 5543 TagWord _tag_word; 5544 int32_t _error_offset; 5545 int32_t _error_selector; 5546 int32_t _data_offset; 5547 int32_t _data_selector; 5548 int8_t _register[register_size * number_of_registers]; 5549 5550 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 5551 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 5552 5553 const char* tag_as_string(int tag) const { 5554 switch (tag) { 5555 case 0: return "valid"; 5556 case 1: return "zero"; 5557 case 2: return "special"; 5558 case 3: return "empty"; 5559 } 5560 ShouldNotReachHere(); 5561 return NULL; 5562 } 5563 5564 void print() const { 5565 // print computation registers 5566 { int t = _status_word.top(); 5567 for (int i = 0; i < number_of_registers; i++) { 5568 int j = (i - t) & register_mask; 5569 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 5570 st(j)->print(); 5571 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 5572 } 5573 } 5574 printf("\n"); 5575 // print control registers 5576 printf("ctrl = "); _control_word.print(); printf("\n"); 5577 printf("stat = "); _status_word .print(); printf("\n"); 5578 printf("tags = "); _tag_word .print(); printf("\n"); 5579 } 5580 5581 }; 5582 5583 class Flag_Register { 5584 public: 5585 int32_t _value; 5586 5587 bool overflow() const { return ((_value >> 11) & 1) != 0; } 5588 bool direction() const { return ((_value >> 10) & 1) != 0; } 5589 bool sign() const { return ((_value >> 7) & 1) != 0; } 5590 bool zero() const { return ((_value >> 6) & 1) != 0; } 5591 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 5592 bool parity() const { return ((_value >> 2) & 1) != 0; } 5593 bool carry() const { return ((_value >> 0) & 1) != 0; } 5594 5595 void print() const { 5596 // flags 5597 char f[8]; 5598 f[0] = (overflow ()) ? 'O' : '-'; 5599 f[1] = (direction ()) ? 'D' : '-'; 5600 f[2] = (sign ()) ? 'S' : '-'; 5601 f[3] = (zero ()) ? 'Z' : '-'; 5602 f[4] = (auxiliary_carry()) ? 'A' : '-'; 5603 f[5] = (parity ()) ? 'P' : '-'; 5604 f[6] = (carry ()) ? 'C' : '-'; 5605 f[7] = '\x0'; 5606 // output 5607 printf("%08x flags = %s", _value, f); 5608 } 5609 5610 }; 5611 5612 class IU_Register { 5613 public: 5614 int32_t _value; 5615 5616 void print() const { 5617 printf("%08x %11d", _value, _value); 5618 } 5619 5620 }; 5621 5622 class IU_State { 5623 public: 5624 Flag_Register _eflags; 5625 IU_Register _rdi; 5626 IU_Register _rsi; 5627 IU_Register _rbp; 5628 IU_Register _rsp; 5629 IU_Register _rbx; 5630 IU_Register _rdx; 5631 IU_Register _rcx; 5632 IU_Register _rax; 5633 5634 void print() const { 5635 // computation registers 5636 printf("rax, = "); _rax.print(); printf("\n"); 5637 printf("rbx, = "); _rbx.print(); printf("\n"); 5638 printf("rcx = "); _rcx.print(); printf("\n"); 5639 printf("rdx = "); _rdx.print(); printf("\n"); 5640 printf("rdi = "); _rdi.print(); printf("\n"); 5641 printf("rsi = "); _rsi.print(); printf("\n"); 5642 printf("rbp, = "); _rbp.print(); printf("\n"); 5643 printf("rsp = "); _rsp.print(); printf("\n"); 5644 printf("\n"); 5645 // control registers 5646 printf("flgs = "); _eflags.print(); printf("\n"); 5647 } 5648 }; 5649 5650 5651 class CPU_State { 5652 public: 5653 FPU_State _fpu_state; 5654 IU_State _iu_state; 5655 5656 void print() const { 5657 printf("--------------------------------------------------\n"); 5658 _iu_state .print(); 5659 printf("\n"); 5660 _fpu_state.print(); 5661 printf("--------------------------------------------------\n"); 5662 } 5663 5664 }; 5665 5666 5667 static void _print_CPU_state(CPU_State* state) { 5668 state->print(); 5669 }; 5670 5671 5672 void MacroAssembler::print_CPU_state() { 5673 push_CPU_state(); 5674 push(rsp); // pass CPU state 5675 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 5676 addptr(rsp, wordSize); // discard argument 5677 pop_CPU_state(); 5678 } 5679 5680 5681 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 5682 static int counter = 0; 5683 FPU_State* fs = &state->_fpu_state; 5684 counter++; 5685 // For leaf calls, only verify that the top few elements remain empty. 5686 // We only need 1 empty at the top for C2 code. 5687 if( stack_depth < 0 ) { 5688 if( fs->tag_for_st(7) != 3 ) { 5689 printf("FPR7 not empty\n"); 5690 state->print(); 5691 assert(false, "error"); 5692 return false; 5693 } 5694 return true; // All other stack states do not matter 5695 } 5696 5697 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 5698 "bad FPU control word"); 5699 5700 // compute stack depth 5701 int i = 0; 5702 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 5703 int d = i; 5704 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 5705 // verify findings 5706 if (i != FPU_State::number_of_registers) { 5707 // stack not contiguous 5708 printf("%s: stack not contiguous at ST%d\n", s, i); 5709 state->print(); 5710 assert(false, "error"); 5711 return false; 5712 } 5713 // check if computed stack depth corresponds to expected stack depth 5714 if (stack_depth < 0) { 5715 // expected stack depth is -stack_depth or less 5716 if (d > -stack_depth) { 5717 // too many elements on the stack 5718 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 5719 state->print(); 5720 assert(false, "error"); 5721 return false; 5722 } 5723 } else { 5724 // expected stack depth is stack_depth 5725 if (d != stack_depth) { 5726 // wrong stack depth 5727 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 5728 state->print(); 5729 assert(false, "error"); 5730 return false; 5731 } 5732 } 5733 // everything is cool 5734 return true; 5735 } 5736 5737 5738 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 5739 if (!VerifyFPU) return; 5740 push_CPU_state(); 5741 push(rsp); // pass CPU state 5742 ExternalAddress msg((address) s); 5743 // pass message string s 5744 pushptr(msg.addr()); 5745 push(stack_depth); // pass stack depth 5746 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 5747 addptr(rsp, 3 * wordSize); // discard arguments 5748 // check for error 5749 { Label L; 5750 testl(rax, rax); 5751 jcc(Assembler::notZero, L); 5752 int3(); // break if error condition 5753 bind(L); 5754 } 5755 pop_CPU_state(); 5756 } 5757 5758 void MacroAssembler::restore_cpu_control_state_after_jni() { 5759 // Either restore the MXCSR register after returning from the JNI Call 5760 // or verify that it wasn't changed (with -Xcheck:jni flag). 5761 if (VM_Version::supports_sse()) { 5762 if (RestoreMXCSROnJNICalls) { 5763 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 5764 } else if (CheckJNICalls) { 5765 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 5766 } 5767 } 5768 if (VM_Version::supports_avx()) { 5769 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 5770 vzeroupper(); 5771 } 5772 5773 #ifndef _LP64 5774 // Either restore the x87 floating pointer control word after returning 5775 // from the JNI call or verify that it wasn't changed. 5776 if (CheckJNICalls) { 5777 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 5778 } 5779 #endif // _LP64 5780 } 5781 5782 5783 void MacroAssembler::load_klass(Register dst, Register src) { 5784 #ifdef _LP64 5785 if (UseCompressedClassPointers) { 5786 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5787 decode_klass_not_null(dst); 5788 } else 5789 #endif 5790 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5791 } 5792 5793 void MacroAssembler::load_prototype_header(Register dst, Register src) { 5794 load_klass(dst, src); 5795 movptr(dst, Address(dst, Klass::prototype_header_offset())); 5796 } 5797 5798 void MacroAssembler::store_klass(Register dst, Register src) { 5799 #ifdef _LP64 5800 if (UseCompressedClassPointers) { 5801 encode_klass_not_null(src); 5802 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5803 } else 5804 #endif 5805 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5806 } 5807 5808 void MacroAssembler::load_heap_oop(Register dst, Address src) { 5809 #ifdef _LP64 5810 // FIXME: Must change all places where we try to load the klass. 5811 if (UseCompressedOops) { 5812 movl(dst, src); 5813 decode_heap_oop(dst); 5814 } else 5815 #endif 5816 movptr(dst, src); 5817 } 5818 5819 // Doesn't do verfication, generates fixed size code 5820 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 5821 #ifdef _LP64 5822 if (UseCompressedOops) { 5823 movl(dst, src); 5824 decode_heap_oop_not_null(dst); 5825 } else 5826 #endif 5827 movptr(dst, src); 5828 } 5829 5830 void MacroAssembler::store_heap_oop(Address dst, Register src) { 5831 #ifdef _LP64 5832 if (UseCompressedOops) { 5833 assert(!dst.uses(src), "not enough registers"); 5834 encode_heap_oop(src); 5835 movl(dst, src); 5836 } else 5837 #endif 5838 movptr(dst, src); 5839 } 5840 5841 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 5842 assert_different_registers(src1, tmp); 5843 #ifdef _LP64 5844 if (UseCompressedOops) { 5845 bool did_push = false; 5846 if (tmp == noreg) { 5847 tmp = rax; 5848 push(tmp); 5849 did_push = true; 5850 assert(!src2.uses(rsp), "can't push"); 5851 } 5852 load_heap_oop(tmp, src2); 5853 cmpptr(src1, tmp); 5854 if (did_push) pop(tmp); 5855 } else 5856 #endif 5857 cmpptr(src1, src2); 5858 } 5859 5860 // Used for storing NULLs. 5861 void MacroAssembler::store_heap_oop_null(Address dst) { 5862 #ifdef _LP64 5863 if (UseCompressedOops) { 5864 movl(dst, (int32_t)NULL_WORD); 5865 } else { 5866 movslq(dst, (int32_t)NULL_WORD); 5867 } 5868 #else 5869 movl(dst, (int32_t)NULL_WORD); 5870 #endif 5871 } 5872 5873 #ifdef _LP64 5874 void MacroAssembler::store_klass_gap(Register dst, Register src) { 5875 if (UseCompressedClassPointers) { 5876 // Store to klass gap in destination 5877 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 5878 } 5879 } 5880 5881 #ifdef ASSERT 5882 void MacroAssembler::verify_heapbase(const char* msg) { 5883 assert (UseCompressedOops, "should be compressed"); 5884 assert (Universe::heap() != NULL, "java heap should be initialized"); 5885 if (CheckCompressedOops) { 5886 Label ok; 5887 push(rscratch1); // cmpptr trashes rscratch1 5888 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 5889 jcc(Assembler::equal, ok); 5890 STOP(msg); 5891 bind(ok); 5892 pop(rscratch1); 5893 } 5894 } 5895 #endif 5896 5897 // Algorithm must match oop.inline.hpp encode_heap_oop. 5898 void MacroAssembler::encode_heap_oop(Register r) { 5899 #ifdef ASSERT 5900 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 5901 #endif 5902 verify_oop(r, "broken oop in encode_heap_oop"); 5903 if (Universe::narrow_oop_base() == NULL) { 5904 if (Universe::narrow_oop_shift() != 0) { 5905 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5906 shrq(r, LogMinObjAlignmentInBytes); 5907 } 5908 return; 5909 } 5910 testq(r, r); 5911 cmovq(Assembler::equal, r, r12_heapbase); 5912 subq(r, r12_heapbase); 5913 shrq(r, LogMinObjAlignmentInBytes); 5914 } 5915 5916 void MacroAssembler::encode_heap_oop_not_null(Register r) { 5917 #ifdef ASSERT 5918 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 5919 if (CheckCompressedOops) { 5920 Label ok; 5921 testq(r, r); 5922 jcc(Assembler::notEqual, ok); 5923 STOP("null oop passed to encode_heap_oop_not_null"); 5924 bind(ok); 5925 } 5926 #endif 5927 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 5928 if (Universe::narrow_oop_base() != NULL) { 5929 subq(r, r12_heapbase); 5930 } 5931 if (Universe::narrow_oop_shift() != 0) { 5932 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5933 shrq(r, LogMinObjAlignmentInBytes); 5934 } 5935 } 5936 5937 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 5938 #ifdef ASSERT 5939 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 5940 if (CheckCompressedOops) { 5941 Label ok; 5942 testq(src, src); 5943 jcc(Assembler::notEqual, ok); 5944 STOP("null oop passed to encode_heap_oop_not_null2"); 5945 bind(ok); 5946 } 5947 #endif 5948 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 5949 if (dst != src) { 5950 movq(dst, src); 5951 } 5952 if (Universe::narrow_oop_base() != NULL) { 5953 subq(dst, r12_heapbase); 5954 } 5955 if (Universe::narrow_oop_shift() != 0) { 5956 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5957 shrq(dst, LogMinObjAlignmentInBytes); 5958 } 5959 } 5960 5961 void MacroAssembler::decode_heap_oop(Register r) { 5962 #ifdef ASSERT 5963 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 5964 #endif 5965 if (Universe::narrow_oop_base() == NULL) { 5966 if (Universe::narrow_oop_shift() != 0) { 5967 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5968 shlq(r, LogMinObjAlignmentInBytes); 5969 } 5970 } else { 5971 Label done; 5972 shlq(r, LogMinObjAlignmentInBytes); 5973 jccb(Assembler::equal, done); 5974 addq(r, r12_heapbase); 5975 bind(done); 5976 } 5977 verify_oop(r, "broken oop in decode_heap_oop"); 5978 } 5979 5980 void MacroAssembler::decode_heap_oop_not_null(Register r) { 5981 // Note: it will change flags 5982 assert (UseCompressedOops, "should only be used for compressed headers"); 5983 assert (Universe::heap() != NULL, "java heap should be initialized"); 5984 // Cannot assert, unverified entry point counts instructions (see .ad file) 5985 // vtableStubs also counts instructions in pd_code_size_limit. 5986 // Also do not verify_oop as this is called by verify_oop. 5987 if (Universe::narrow_oop_shift() != 0) { 5988 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5989 shlq(r, LogMinObjAlignmentInBytes); 5990 if (Universe::narrow_oop_base() != NULL) { 5991 addq(r, r12_heapbase); 5992 } 5993 } else { 5994 assert (Universe::narrow_oop_base() == NULL, "sanity"); 5995 } 5996 } 5997 5998 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 5999 // Note: it will change flags 6000 assert (UseCompressedOops, "should only be used for compressed headers"); 6001 assert (Universe::heap() != NULL, "java heap should be initialized"); 6002 // Cannot assert, unverified entry point counts instructions (see .ad file) 6003 // vtableStubs also counts instructions in pd_code_size_limit. 6004 // Also do not verify_oop as this is called by verify_oop. 6005 if (Universe::narrow_oop_shift() != 0) { 6006 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6007 if (LogMinObjAlignmentInBytes == Address::times_8) { 6008 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6009 } else { 6010 if (dst != src) { 6011 movq(dst, src); 6012 } 6013 shlq(dst, LogMinObjAlignmentInBytes); 6014 if (Universe::narrow_oop_base() != NULL) { 6015 addq(dst, r12_heapbase); 6016 } 6017 } 6018 } else { 6019 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6020 if (dst != src) { 6021 movq(dst, src); 6022 } 6023 } 6024 } 6025 6026 void MacroAssembler::encode_klass_not_null(Register r) { 6027 if (Universe::narrow_klass_base() != NULL) { 6028 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6029 assert(r != r12_heapbase, "Encoding a klass in r12"); 6030 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6031 subq(r, r12_heapbase); 6032 } 6033 if (Universe::narrow_klass_shift() != 0) { 6034 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6035 shrq(r, LogKlassAlignmentInBytes); 6036 } 6037 if (Universe::narrow_klass_base() != NULL) { 6038 reinit_heapbase(); 6039 } 6040 } 6041 6042 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6043 if (dst == src) { 6044 encode_klass_not_null(src); 6045 } else { 6046 if (Universe::narrow_klass_base() != NULL) { 6047 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6048 negq(dst); 6049 addq(dst, src); 6050 } else { 6051 movptr(dst, src); 6052 } 6053 if (Universe::narrow_klass_shift() != 0) { 6054 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6055 shrq(dst, LogKlassAlignmentInBytes); 6056 } 6057 } 6058 } 6059 6060 // Function instr_size_for_decode_klass_not_null() counts the instructions 6061 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6062 // when (Universe::heap() != NULL). Hence, if the instructions they 6063 // generate change, then this method needs to be updated. 6064 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6065 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6066 if (Universe::narrow_klass_base() != NULL) { 6067 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6068 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6069 } else { 6070 // longest load decode klass function, mov64, leaq 6071 return 16; 6072 } 6073 } 6074 6075 // !!! If the instructions that get generated here change then function 6076 // instr_size_for_decode_klass_not_null() needs to get updated. 6077 void MacroAssembler::decode_klass_not_null(Register r) { 6078 // Note: it will change flags 6079 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6080 assert(r != r12_heapbase, "Decoding a klass in r12"); 6081 // Cannot assert, unverified entry point counts instructions (see .ad file) 6082 // vtableStubs also counts instructions in pd_code_size_limit. 6083 // Also do not verify_oop as this is called by verify_oop. 6084 if (Universe::narrow_klass_shift() != 0) { 6085 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6086 shlq(r, LogKlassAlignmentInBytes); 6087 } 6088 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6089 if (Universe::narrow_klass_base() != NULL) { 6090 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6091 addq(r, r12_heapbase); 6092 reinit_heapbase(); 6093 } 6094 } 6095 6096 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6097 // Note: it will change flags 6098 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6099 if (dst == src) { 6100 decode_klass_not_null(dst); 6101 } else { 6102 // Cannot assert, unverified entry point counts instructions (see .ad file) 6103 // vtableStubs also counts instructions in pd_code_size_limit. 6104 // Also do not verify_oop as this is called by verify_oop. 6105 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6106 if (Universe::narrow_klass_shift() != 0) { 6107 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6108 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6109 leaq(dst, Address(dst, src, Address::times_8, 0)); 6110 } else { 6111 addq(dst, src); 6112 } 6113 } 6114 } 6115 6116 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6117 assert (UseCompressedOops, "should only be used for compressed headers"); 6118 assert (Universe::heap() != NULL, "java heap should be initialized"); 6119 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6120 int oop_index = oop_recorder()->find_index(obj); 6121 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6122 mov_narrow_oop(dst, oop_index, rspec); 6123 } 6124 6125 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6126 assert (UseCompressedOops, "should only be used for compressed headers"); 6127 assert (Universe::heap() != NULL, "java heap should be initialized"); 6128 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6129 int oop_index = oop_recorder()->find_index(obj); 6130 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6131 mov_narrow_oop(dst, oop_index, rspec); 6132 } 6133 6134 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6135 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6136 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6137 int klass_index = oop_recorder()->find_index(k); 6138 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6139 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6140 } 6141 6142 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6143 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6144 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6145 int klass_index = oop_recorder()->find_index(k); 6146 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6147 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6148 } 6149 6150 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6151 assert (UseCompressedOops, "should only be used for compressed headers"); 6152 assert (Universe::heap() != NULL, "java heap should be initialized"); 6153 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6154 int oop_index = oop_recorder()->find_index(obj); 6155 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6156 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6157 } 6158 6159 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6160 assert (UseCompressedOops, "should only be used for compressed headers"); 6161 assert (Universe::heap() != NULL, "java heap should be initialized"); 6162 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6163 int oop_index = oop_recorder()->find_index(obj); 6164 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6165 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6166 } 6167 6168 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6169 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6170 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6171 int klass_index = oop_recorder()->find_index(k); 6172 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6173 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6174 } 6175 6176 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6177 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6178 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6179 int klass_index = oop_recorder()->find_index(k); 6180 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6181 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6182 } 6183 6184 void MacroAssembler::reinit_heapbase() { 6185 if (UseCompressedOops || UseCompressedClassPointers) { 6186 if (Universe::heap() != NULL) { 6187 if (Universe::narrow_oop_base() == NULL) { 6188 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6189 } else { 6190 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6191 } 6192 } else { 6193 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6194 } 6195 } 6196 } 6197 6198 #endif // _LP64 6199 6200 6201 // C2 compiled method's prolog code. 6202 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6203 6204 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6205 // NativeJump::patch_verified_entry will be able to patch out the entry 6206 // code safely. The push to verify stack depth is ok at 5 bytes, 6207 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6208 // stack bang then we must use the 6 byte frame allocation even if 6209 // we have no frame. :-( 6210 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6211 6212 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6213 // Remove word for return addr 6214 framesize -= wordSize; 6215 stack_bang_size -= wordSize; 6216 6217 // Calls to C2R adapters often do not accept exceptional returns. 6218 // We require that their callers must bang for them. But be careful, because 6219 // some VM calls (such as call site linkage) can use several kilobytes of 6220 // stack. But the stack safety zone should account for that. 6221 // See bugs 4446381, 4468289, 4497237. 6222 if (stack_bang_size > 0) { 6223 generate_stack_overflow_check(stack_bang_size); 6224 6225 // We always push rbp, so that on return to interpreter rbp, will be 6226 // restored correctly and we can correct the stack. 6227 push(rbp); 6228 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6229 if (PreserveFramePointer) { 6230 mov(rbp, rsp); 6231 } 6232 // Remove word for ebp 6233 framesize -= wordSize; 6234 6235 // Create frame 6236 if (framesize) { 6237 subptr(rsp, framesize); 6238 } 6239 } else { 6240 // Create frame (force generation of a 4 byte immediate value) 6241 subptr_imm32(rsp, framesize); 6242 6243 // Save RBP register now. 6244 framesize -= wordSize; 6245 movptr(Address(rsp, framesize), rbp); 6246 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6247 if (PreserveFramePointer) { 6248 movptr(rbp, rsp); 6249 if (framesize > 0) { 6250 addptr(rbp, framesize); 6251 } 6252 } 6253 } 6254 6255 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 6256 framesize -= wordSize; 6257 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 6258 } 6259 6260 #ifndef _LP64 6261 // If method sets FPU control word do it now 6262 if (fp_mode_24b) { 6263 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 6264 } 6265 if (UseSSE >= 2 && VerifyFPU) { 6266 verify_FPU(0, "FPU stack must be clean on entry"); 6267 } 6268 #endif 6269 6270 #ifdef ASSERT 6271 if (VerifyStackAtCalls) { 6272 Label L; 6273 push(rax); 6274 mov(rax, rsp); 6275 andptr(rax, StackAlignmentInBytes-1); 6276 cmpptr(rax, StackAlignmentInBytes-wordSize); 6277 pop(rax); 6278 jcc(Assembler::equal, L); 6279 STOP("Stack is not properly aligned!"); 6280 bind(L); 6281 } 6282 #endif 6283 6284 } 6285 6286 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) { 6287 // cnt - number of qwords (8-byte words). 6288 // base - start address, qword aligned. 6289 assert(base==rdi, "base register must be edi for rep stos"); 6290 assert(tmp==rax, "tmp register must be eax for rep stos"); 6291 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 6292 6293 xorptr(tmp, tmp); 6294 if (UseFastStosb) { 6295 shlptr(cnt,3); // convert to number of bytes 6296 rep_stosb(); 6297 } else { 6298 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM 6299 rep_stos(); 6300 } 6301 } 6302 6303 // IndexOf for constant substrings with size >= 8 chars 6304 // which don't need to be loaded through stack. 6305 void MacroAssembler::string_indexofC8(Register str1, Register str2, 6306 Register cnt1, Register cnt2, 6307 int int_cnt2, Register result, 6308 XMMRegister vec, Register tmp) { 6309 ShortBranchVerifier sbv(this); 6310 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 6311 6312 // This method uses pcmpestri instruction with bound registers 6313 // inputs: 6314 // xmm - substring 6315 // rax - substring length (elements count) 6316 // mem - scanned string 6317 // rdx - string length (elements count) 6318 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6319 // outputs: 6320 // rcx - matched index in string 6321 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6322 6323 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 6324 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 6325 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 6326 6327 // Note, inline_string_indexOf() generates checks: 6328 // if (substr.count > string.count) return -1; 6329 // if (substr.count == 0) return 0; 6330 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); 6331 6332 // Load substring. 6333 movdqu(vec, Address(str2, 0)); 6334 movl(cnt2, int_cnt2); 6335 movptr(result, str1); // string addr 6336 6337 if (int_cnt2 > 8) { 6338 jmpb(SCAN_TO_SUBSTR); 6339 6340 // Reload substr for rescan, this code 6341 // is executed only for large substrings (> 8 chars) 6342 bind(RELOAD_SUBSTR); 6343 movdqu(vec, Address(str2, 0)); 6344 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 6345 6346 bind(RELOAD_STR); 6347 // We came here after the beginning of the substring was 6348 // matched but the rest of it was not so we need to search 6349 // again. Start from the next element after the previous match. 6350 6351 // cnt2 is number of substring reminding elements and 6352 // cnt1 is number of string reminding elements when cmp failed. 6353 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 6354 subl(cnt1, cnt2); 6355 addl(cnt1, int_cnt2); 6356 movl(cnt2, int_cnt2); // Now restore cnt2 6357 6358 decrementl(cnt1); // Shift to next element 6359 cmpl(cnt1, cnt2); 6360 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6361 6362 addptr(result, 2); 6363 6364 } // (int_cnt2 > 8) 6365 6366 // Scan string for start of substr in 16-byte vectors 6367 bind(SCAN_TO_SUBSTR); 6368 pcmpestri(vec, Address(result, 0), 0x0d); 6369 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6370 subl(cnt1, 8); 6371 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6372 cmpl(cnt1, cnt2); 6373 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6374 addptr(result, 16); 6375 jmpb(SCAN_TO_SUBSTR); 6376 6377 // Found a potential substr 6378 bind(FOUND_CANDIDATE); 6379 // Matched whole vector if first element matched (tmp(rcx) == 0). 6380 if (int_cnt2 == 8) { 6381 jccb(Assembler::overflow, RET_FOUND); // OF == 1 6382 } else { // int_cnt2 > 8 6383 jccb(Assembler::overflow, FOUND_SUBSTR); 6384 } 6385 // After pcmpestri tmp(rcx) contains matched element index 6386 // Compute start addr of substr 6387 lea(result, Address(result, tmp, Address::times_2)); 6388 6389 // Make sure string is still long enough 6390 subl(cnt1, tmp); 6391 cmpl(cnt1, cnt2); 6392 if (int_cnt2 == 8) { 6393 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6394 } else { // int_cnt2 > 8 6395 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 6396 } 6397 // Left less then substring. 6398 6399 bind(RET_NOT_FOUND); 6400 movl(result, -1); 6401 jmpb(EXIT); 6402 6403 if (int_cnt2 > 8) { 6404 // This code is optimized for the case when whole substring 6405 // is matched if its head is matched. 6406 bind(MATCH_SUBSTR_HEAD); 6407 pcmpestri(vec, Address(result, 0), 0x0d); 6408 // Reload only string if does not match 6409 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 6410 6411 Label CONT_SCAN_SUBSTR; 6412 // Compare the rest of substring (> 8 chars). 6413 bind(FOUND_SUBSTR); 6414 // First 8 chars are already matched. 6415 negptr(cnt2); 6416 addptr(cnt2, 8); 6417 6418 bind(SCAN_SUBSTR); 6419 subl(cnt1, 8); 6420 cmpl(cnt2, -8); // Do not read beyond substring 6421 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 6422 // Back-up strings to avoid reading beyond substring: 6423 // cnt1 = cnt1 - cnt2 + 8 6424 addl(cnt1, cnt2); // cnt2 is negative 6425 addl(cnt1, 8); 6426 movl(cnt2, 8); negptr(cnt2); 6427 bind(CONT_SCAN_SUBSTR); 6428 if (int_cnt2 < (int)G) { 6429 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); 6430 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); 6431 } else { 6432 // calculate index in register to avoid integer overflow (int_cnt2*2) 6433 movl(tmp, int_cnt2); 6434 addptr(tmp, cnt2); 6435 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); 6436 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); 6437 } 6438 // Need to reload strings pointers if not matched whole vector 6439 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6440 addptr(cnt2, 8); 6441 jcc(Assembler::negative, SCAN_SUBSTR); 6442 // Fall through if found full substring 6443 6444 } // (int_cnt2 > 8) 6445 6446 bind(RET_FOUND); 6447 // Found result if we matched full small substring. 6448 // Compute substr offset 6449 subptr(result, str1); 6450 shrl(result, 1); // index 6451 bind(EXIT); 6452 6453 } // string_indexofC8 6454 6455 // Small strings are loaded through stack if they cross page boundary. 6456 void MacroAssembler::string_indexof(Register str1, Register str2, 6457 Register cnt1, Register cnt2, 6458 int int_cnt2, Register result, 6459 XMMRegister vec, Register tmp) { 6460 ShortBranchVerifier sbv(this); 6461 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 6462 // 6463 // int_cnt2 is length of small (< 8 chars) constant substring 6464 // or (-1) for non constant substring in which case its length 6465 // is in cnt2 register. 6466 // 6467 // Note, inline_string_indexOf() generates checks: 6468 // if (substr.count > string.count) return -1; 6469 // if (substr.count == 0) return 0; 6470 // 6471 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); 6472 6473 // This method uses pcmpestri instruction with bound registers 6474 // inputs: 6475 // xmm - substring 6476 // rax - substring length (elements count) 6477 // mem - scanned string 6478 // rdx - string length (elements count) 6479 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6480 // outputs: 6481 // rcx - matched index in string 6482 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6483 6484 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 6485 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 6486 FOUND_CANDIDATE; 6487 6488 { //======================================================== 6489 // We don't know where these strings are located 6490 // and we can't read beyond them. Load them through stack. 6491 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 6492 6493 movptr(tmp, rsp); // save old SP 6494 6495 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 6496 if (int_cnt2 == 1) { // One char 6497 load_unsigned_short(result, Address(str2, 0)); 6498 movdl(vec, result); // move 32 bits 6499 } else if (int_cnt2 == 2) { // Two chars 6500 movdl(vec, Address(str2, 0)); // move 32 bits 6501 } else if (int_cnt2 == 4) { // Four chars 6502 movq(vec, Address(str2, 0)); // move 64 bits 6503 } else { // cnt2 = { 3, 5, 6, 7 } 6504 // Array header size is 12 bytes in 32-bit VM 6505 // + 6 bytes for 3 chars == 18 bytes, 6506 // enough space to load vec and shift. 6507 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 6508 movdqu(vec, Address(str2, (int_cnt2*2)-16)); 6509 psrldq(vec, 16-(int_cnt2*2)); 6510 } 6511 } else { // not constant substring 6512 cmpl(cnt2, 8); 6513 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 6514 6515 // We can read beyond string if srt+16 does not cross page boundary 6516 // since heaps are aligned and mapped by pages. 6517 assert(os::vm_page_size() < (int)G, "default page should be small"); 6518 movl(result, str2); // We need only low 32 bits 6519 andl(result, (os::vm_page_size()-1)); 6520 cmpl(result, (os::vm_page_size()-16)); 6521 jccb(Assembler::belowEqual, CHECK_STR); 6522 6523 // Move small strings to stack to allow load 16 bytes into vec. 6524 subptr(rsp, 16); 6525 int stk_offset = wordSize-2; 6526 push(cnt2); 6527 6528 bind(COPY_SUBSTR); 6529 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); 6530 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 6531 decrement(cnt2); 6532 jccb(Assembler::notZero, COPY_SUBSTR); 6533 6534 pop(cnt2); 6535 movptr(str2, rsp); // New substring address 6536 } // non constant 6537 6538 bind(CHECK_STR); 6539 cmpl(cnt1, 8); 6540 jccb(Assembler::aboveEqual, BIG_STRINGS); 6541 6542 // Check cross page boundary. 6543 movl(result, str1); // We need only low 32 bits 6544 andl(result, (os::vm_page_size()-1)); 6545 cmpl(result, (os::vm_page_size()-16)); 6546 jccb(Assembler::belowEqual, BIG_STRINGS); 6547 6548 subptr(rsp, 16); 6549 int stk_offset = -2; 6550 if (int_cnt2 < 0) { // not constant 6551 push(cnt2); 6552 stk_offset += wordSize; 6553 } 6554 movl(cnt2, cnt1); 6555 6556 bind(COPY_STR); 6557 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); 6558 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 6559 decrement(cnt2); 6560 jccb(Assembler::notZero, COPY_STR); 6561 6562 if (int_cnt2 < 0) { // not constant 6563 pop(cnt2); 6564 } 6565 movptr(str1, rsp); // New string address 6566 6567 bind(BIG_STRINGS); 6568 // Load substring. 6569 if (int_cnt2 < 0) { // -1 6570 movdqu(vec, Address(str2, 0)); 6571 push(cnt2); // substr count 6572 push(str2); // substr addr 6573 push(str1); // string addr 6574 } else { 6575 // Small (< 8 chars) constant substrings are loaded already. 6576 movl(cnt2, int_cnt2); 6577 } 6578 push(tmp); // original SP 6579 6580 } // Finished loading 6581 6582 //======================================================== 6583 // Start search 6584 // 6585 6586 movptr(result, str1); // string addr 6587 6588 if (int_cnt2 < 0) { // Only for non constant substring 6589 jmpb(SCAN_TO_SUBSTR); 6590 6591 // SP saved at sp+0 6592 // String saved at sp+1*wordSize 6593 // Substr saved at sp+2*wordSize 6594 // Substr count saved at sp+3*wordSize 6595 6596 // Reload substr for rescan, this code 6597 // is executed only for large substrings (> 8 chars) 6598 bind(RELOAD_SUBSTR); 6599 movptr(str2, Address(rsp, 2*wordSize)); 6600 movl(cnt2, Address(rsp, 3*wordSize)); 6601 movdqu(vec, Address(str2, 0)); 6602 // We came here after the beginning of the substring was 6603 // matched but the rest of it was not so we need to search 6604 // again. Start from the next element after the previous match. 6605 subptr(str1, result); // Restore counter 6606 shrl(str1, 1); 6607 addl(cnt1, str1); 6608 decrementl(cnt1); // Shift to next element 6609 cmpl(cnt1, cnt2); 6610 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6611 6612 addptr(result, 2); 6613 } // non constant 6614 6615 // Scan string for start of substr in 16-byte vectors 6616 bind(SCAN_TO_SUBSTR); 6617 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6618 pcmpestri(vec, Address(result, 0), 0x0d); 6619 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6620 subl(cnt1, 8); 6621 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6622 cmpl(cnt1, cnt2); 6623 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6624 addptr(result, 16); 6625 6626 bind(ADJUST_STR); 6627 cmpl(cnt1, 8); // Do not read beyond string 6628 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6629 // Back-up string to avoid reading beyond string. 6630 lea(result, Address(result, cnt1, Address::times_2, -16)); 6631 movl(cnt1, 8); 6632 jmpb(SCAN_TO_SUBSTR); 6633 6634 // Found a potential substr 6635 bind(FOUND_CANDIDATE); 6636 // After pcmpestri tmp(rcx) contains matched element index 6637 6638 // Make sure string is still long enough 6639 subl(cnt1, tmp); 6640 cmpl(cnt1, cnt2); 6641 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 6642 // Left less then substring. 6643 6644 bind(RET_NOT_FOUND); 6645 movl(result, -1); 6646 jmpb(CLEANUP); 6647 6648 bind(FOUND_SUBSTR); 6649 // Compute start addr of substr 6650 lea(result, Address(result, tmp, Address::times_2)); 6651 6652 if (int_cnt2 > 0) { // Constant substring 6653 // Repeat search for small substring (< 8 chars) 6654 // from new point without reloading substring. 6655 // Have to check that we don't read beyond string. 6656 cmpl(tmp, 8-int_cnt2); 6657 jccb(Assembler::greater, ADJUST_STR); 6658 // Fall through if matched whole substring. 6659 } else { // non constant 6660 assert(int_cnt2 == -1, "should be != 0"); 6661 6662 addl(tmp, cnt2); 6663 // Found result if we matched whole substring. 6664 cmpl(tmp, 8); 6665 jccb(Assembler::lessEqual, RET_FOUND); 6666 6667 // Repeat search for small substring (<= 8 chars) 6668 // from new point 'str1' without reloading substring. 6669 cmpl(cnt2, 8); 6670 // Have to check that we don't read beyond string. 6671 jccb(Assembler::lessEqual, ADJUST_STR); 6672 6673 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 6674 // Compare the rest of substring (> 8 chars). 6675 movptr(str1, result); 6676 6677 cmpl(tmp, cnt2); 6678 // First 8 chars are already matched. 6679 jccb(Assembler::equal, CHECK_NEXT); 6680 6681 bind(SCAN_SUBSTR); 6682 pcmpestri(vec, Address(str1, 0), 0x0d); 6683 // Need to reload strings pointers if not matched whole vector 6684 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6685 6686 bind(CHECK_NEXT); 6687 subl(cnt2, 8); 6688 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 6689 addptr(str1, 16); 6690 addptr(str2, 16); 6691 subl(cnt1, 8); 6692 cmpl(cnt2, 8); // Do not read beyond substring 6693 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 6694 // Back-up strings to avoid reading beyond substring. 6695 lea(str2, Address(str2, cnt2, Address::times_2, -16)); 6696 lea(str1, Address(str1, cnt2, Address::times_2, -16)); 6697 subl(cnt1, cnt2); 6698 movl(cnt2, 8); 6699 addl(cnt1, 8); 6700 bind(CONT_SCAN_SUBSTR); 6701 movdqu(vec, Address(str2, 0)); 6702 jmpb(SCAN_SUBSTR); 6703 6704 bind(RET_FOUND_LONG); 6705 movptr(str1, Address(rsp, wordSize)); 6706 } // non constant 6707 6708 bind(RET_FOUND); 6709 // Compute substr offset 6710 subptr(result, str1); 6711 shrl(result, 1); // index 6712 6713 bind(CLEANUP); 6714 pop(rsp); // restore SP 6715 6716 } // string_indexof 6717 6718 // Compare strings. 6719 void MacroAssembler::string_compare(Register str1, Register str2, 6720 Register cnt1, Register cnt2, Register result, 6721 XMMRegister vec1) { 6722 ShortBranchVerifier sbv(this); 6723 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 6724 6725 // Compute the minimum of the string lengths and the 6726 // difference of the string lengths (stack). 6727 // Do the conditional move stuff 6728 movl(result, cnt1); 6729 subl(cnt1, cnt2); 6730 push(cnt1); 6731 cmov32(Assembler::lessEqual, cnt2, result); 6732 6733 // Is the minimum length zero? 6734 testl(cnt2, cnt2); 6735 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 6736 6737 // Compare first characters 6738 load_unsigned_short(result, Address(str1, 0)); 6739 load_unsigned_short(cnt1, Address(str2, 0)); 6740 subl(result, cnt1); 6741 jcc(Assembler::notZero, POP_LABEL); 6742 cmpl(cnt2, 1); 6743 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 6744 6745 // Check if the strings start at the same location. 6746 cmpptr(str1, str2); 6747 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 6748 6749 Address::ScaleFactor scale = Address::times_2; 6750 int stride = 8; 6751 6752 if (UseAVX >= 2 && UseSSE42Intrinsics) { 6753 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 6754 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 6755 Label COMPARE_TAIL_LONG; 6756 int pcmpmask = 0x19; 6757 6758 // Setup to compare 16-chars (32-bytes) vectors, 6759 // start from first character again because it has aligned address. 6760 int stride2 = 16; 6761 int adr_stride = stride << scale; 6762 6763 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 6764 // rax and rdx are used by pcmpestri as elements counters 6765 movl(result, cnt2); 6766 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 6767 jcc(Assembler::zero, COMPARE_TAIL_LONG); 6768 6769 // fast path : compare first 2 8-char vectors. 6770 bind(COMPARE_16_CHARS); 6771 movdqu(vec1, Address(str1, 0)); 6772 pcmpestri(vec1, Address(str2, 0), pcmpmask); 6773 jccb(Assembler::below, COMPARE_INDEX_CHAR); 6774 6775 movdqu(vec1, Address(str1, adr_stride)); 6776 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 6777 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 6778 addl(cnt1, stride); 6779 6780 // Compare the characters at index in cnt1 6781 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character 6782 load_unsigned_short(result, Address(str1, cnt1, scale)); 6783 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); 6784 subl(result, cnt2); 6785 jmp(POP_LABEL); 6786 6787 // Setup the registers to start vector comparison loop 6788 bind(COMPARE_WIDE_VECTORS); 6789 lea(str1, Address(str1, result, scale)); 6790 lea(str2, Address(str2, result, scale)); 6791 subl(result, stride2); 6792 subl(cnt2, stride2); 6793 jccb(Assembler::zero, COMPARE_WIDE_TAIL); 6794 negptr(result); 6795 6796 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 6797 bind(COMPARE_WIDE_VECTORS_LOOP); 6798 vmovdqu(vec1, Address(str1, result, scale)); 6799 vpxor(vec1, Address(str2, result, scale)); 6800 vptest(vec1, vec1); 6801 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); 6802 addptr(result, stride2); 6803 subl(cnt2, stride2); 6804 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 6805 // clean upper bits of YMM registers 6806 vpxor(vec1, vec1); 6807 6808 // compare wide vectors tail 6809 bind(COMPARE_WIDE_TAIL); 6810 testptr(result, result); 6811 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6812 6813 movl(result, stride2); 6814 movl(cnt2, result); 6815 negptr(result); 6816 jmpb(COMPARE_WIDE_VECTORS_LOOP); 6817 6818 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 6819 bind(VECTOR_NOT_EQUAL); 6820 // clean upper bits of YMM registers 6821 vpxor(vec1, vec1); 6822 lea(str1, Address(str1, result, scale)); 6823 lea(str2, Address(str2, result, scale)); 6824 jmp(COMPARE_16_CHARS); 6825 6826 // Compare tail chars, length between 1 to 15 chars 6827 bind(COMPARE_TAIL_LONG); 6828 movl(cnt2, result); 6829 cmpl(cnt2, stride); 6830 jccb(Assembler::less, COMPARE_SMALL_STR); 6831 6832 movdqu(vec1, Address(str1, 0)); 6833 pcmpestri(vec1, Address(str2, 0), pcmpmask); 6834 jcc(Assembler::below, COMPARE_INDEX_CHAR); 6835 subptr(cnt2, stride); 6836 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6837 lea(str1, Address(str1, result, scale)); 6838 lea(str2, Address(str2, result, scale)); 6839 negptr(cnt2); 6840 jmpb(WHILE_HEAD_LABEL); 6841 6842 bind(COMPARE_SMALL_STR); 6843 } else if (UseSSE42Intrinsics) { 6844 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 6845 int pcmpmask = 0x19; 6846 // Setup to compare 8-char (16-byte) vectors, 6847 // start from first character again because it has aligned address. 6848 movl(result, cnt2); 6849 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 6850 jccb(Assembler::zero, COMPARE_TAIL); 6851 6852 lea(str1, Address(str1, result, scale)); 6853 lea(str2, Address(str2, result, scale)); 6854 negptr(result); 6855 6856 // pcmpestri 6857 // inputs: 6858 // vec1- substring 6859 // rax - negative string length (elements count) 6860 // mem - scanned string 6861 // rdx - string length (elements count) 6862 // pcmpmask - cmp mode: 11000 (string compare with negated result) 6863 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 6864 // outputs: 6865 // rcx - first mismatched element index 6866 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 6867 6868 bind(COMPARE_WIDE_VECTORS); 6869 movdqu(vec1, Address(str1, result, scale)); 6870 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 6871 // After pcmpestri cnt1(rcx) contains mismatched element index 6872 6873 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 6874 addptr(result, stride); 6875 subptr(cnt2, stride); 6876 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 6877 6878 // compare wide vectors tail 6879 testptr(result, result); 6880 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6881 6882 movl(cnt2, stride); 6883 movl(result, stride); 6884 negptr(result); 6885 movdqu(vec1, Address(str1, result, scale)); 6886 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 6887 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 6888 6889 // Mismatched characters in the vectors 6890 bind(VECTOR_NOT_EQUAL); 6891 addptr(cnt1, result); 6892 load_unsigned_short(result, Address(str1, cnt1, scale)); 6893 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); 6894 subl(result, cnt2); 6895 jmpb(POP_LABEL); 6896 6897 bind(COMPARE_TAIL); // limit is zero 6898 movl(cnt2, result); 6899 // Fallthru to tail compare 6900 } 6901 // Shift str2 and str1 to the end of the arrays, negate min 6902 lea(str1, Address(str1, cnt2, scale)); 6903 lea(str2, Address(str2, cnt2, scale)); 6904 decrementl(cnt2); // first character was compared already 6905 negptr(cnt2); 6906 6907 // Compare the rest of the elements 6908 bind(WHILE_HEAD_LABEL); 6909 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); 6910 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); 6911 subl(result, cnt1); 6912 jccb(Assembler::notZero, POP_LABEL); 6913 increment(cnt2); 6914 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 6915 6916 // Strings are equal up to min length. Return the length difference. 6917 bind(LENGTH_DIFF_LABEL); 6918 pop(result); 6919 jmpb(DONE_LABEL); 6920 6921 // Discard the stored length difference 6922 bind(POP_LABEL); 6923 pop(cnt1); 6924 6925 // That's it 6926 bind(DONE_LABEL); 6927 } 6928 6929 // Compare char[] arrays aligned to 4 bytes or substrings. 6930 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 6931 Register limit, Register result, Register chr, 6932 XMMRegister vec1, XMMRegister vec2) { 6933 ShortBranchVerifier sbv(this); 6934 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; 6935 6936 int length_offset = arrayOopDesc::length_offset_in_bytes(); 6937 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 6938 6939 // Check the input args 6940 cmpptr(ary1, ary2); 6941 jcc(Assembler::equal, TRUE_LABEL); 6942 6943 if (is_array_equ) { 6944 // Need additional checks for arrays_equals. 6945 testptr(ary1, ary1); 6946 jcc(Assembler::zero, FALSE_LABEL); 6947 testptr(ary2, ary2); 6948 jcc(Assembler::zero, FALSE_LABEL); 6949 6950 // Check the lengths 6951 movl(limit, Address(ary1, length_offset)); 6952 cmpl(limit, Address(ary2, length_offset)); 6953 jcc(Assembler::notEqual, FALSE_LABEL); 6954 } 6955 6956 // count == 0 6957 testl(limit, limit); 6958 jcc(Assembler::zero, TRUE_LABEL); 6959 6960 if (is_array_equ) { 6961 // Load array address 6962 lea(ary1, Address(ary1, base_offset)); 6963 lea(ary2, Address(ary2, base_offset)); 6964 } 6965 6966 shll(limit, 1); // byte count != 0 6967 movl(result, limit); // copy 6968 6969 if (UseAVX >= 2) { 6970 // With AVX2, use 32-byte vector compare 6971 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 6972 6973 // Compare 32-byte vectors 6974 andl(result, 0x0000001e); // tail count (in bytes) 6975 andl(limit, 0xffffffe0); // vector count (in bytes) 6976 jccb(Assembler::zero, COMPARE_TAIL); 6977 6978 lea(ary1, Address(ary1, limit, Address::times_1)); 6979 lea(ary2, Address(ary2, limit, Address::times_1)); 6980 negptr(limit); 6981 6982 bind(COMPARE_WIDE_VECTORS); 6983 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 6984 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 6985 vpxor(vec1, vec2); 6986 6987 vptest(vec1, vec1); 6988 jccb(Assembler::notZero, FALSE_LABEL); 6989 addptr(limit, 32); 6990 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 6991 6992 testl(result, result); 6993 jccb(Assembler::zero, TRUE_LABEL); 6994 6995 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 6996 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 6997 vpxor(vec1, vec2); 6998 6999 vptest(vec1, vec1); 7000 jccb(Assembler::notZero, FALSE_LABEL); 7001 jmpb(TRUE_LABEL); 7002 7003 bind(COMPARE_TAIL); // limit is zero 7004 movl(limit, result); 7005 // Fallthru to tail compare 7006 } else if (UseSSE42Intrinsics) { 7007 // With SSE4.2, use double quad vector compare 7008 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 7009 7010 // Compare 16-byte vectors 7011 andl(result, 0x0000000e); // tail count (in bytes) 7012 andl(limit, 0xfffffff0); // vector count (in bytes) 7013 jccb(Assembler::zero, COMPARE_TAIL); 7014 7015 lea(ary1, Address(ary1, limit, Address::times_1)); 7016 lea(ary2, Address(ary2, limit, Address::times_1)); 7017 negptr(limit); 7018 7019 bind(COMPARE_WIDE_VECTORS); 7020 movdqu(vec1, Address(ary1, limit, Address::times_1)); 7021 movdqu(vec2, Address(ary2, limit, Address::times_1)); 7022 pxor(vec1, vec2); 7023 7024 ptest(vec1, vec1); 7025 jccb(Assembler::notZero, FALSE_LABEL); 7026 addptr(limit, 16); 7027 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 7028 7029 testl(result, result); 7030 jccb(Assembler::zero, TRUE_LABEL); 7031 7032 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 7033 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 7034 pxor(vec1, vec2); 7035 7036 ptest(vec1, vec1); 7037 jccb(Assembler::notZero, FALSE_LABEL); 7038 jmpb(TRUE_LABEL); 7039 7040 bind(COMPARE_TAIL); // limit is zero 7041 movl(limit, result); 7042 // Fallthru to tail compare 7043 } 7044 7045 // Compare 4-byte vectors 7046 andl(limit, 0xfffffffc); // vector count (in bytes) 7047 jccb(Assembler::zero, COMPARE_CHAR); 7048 7049 lea(ary1, Address(ary1, limit, Address::times_1)); 7050 lea(ary2, Address(ary2, limit, Address::times_1)); 7051 negptr(limit); 7052 7053 bind(COMPARE_VECTORS); 7054 movl(chr, Address(ary1, limit, Address::times_1)); 7055 cmpl(chr, Address(ary2, limit, Address::times_1)); 7056 jccb(Assembler::notEqual, FALSE_LABEL); 7057 addptr(limit, 4); 7058 jcc(Assembler::notZero, COMPARE_VECTORS); 7059 7060 // Compare trailing char (final 2 bytes), if any 7061 bind(COMPARE_CHAR); 7062 testl(result, 0x2); // tail char 7063 jccb(Assembler::zero, TRUE_LABEL); 7064 load_unsigned_short(chr, Address(ary1, 0)); 7065 load_unsigned_short(limit, Address(ary2, 0)); 7066 cmpl(chr, limit); 7067 jccb(Assembler::notEqual, FALSE_LABEL); 7068 7069 bind(TRUE_LABEL); 7070 movl(result, 1); // return true 7071 jmpb(DONE); 7072 7073 bind(FALSE_LABEL); 7074 xorl(result, result); // return false 7075 7076 // That's it 7077 bind(DONE); 7078 if (UseAVX >= 2) { 7079 // clean upper bits of YMM registers 7080 vpxor(vec1, vec1); 7081 vpxor(vec2, vec2); 7082 } 7083 } 7084 7085 void MacroAssembler::generate_fill(BasicType t, bool aligned, 7086 Register to, Register value, Register count, 7087 Register rtmp, XMMRegister xtmp) { 7088 ShortBranchVerifier sbv(this); 7089 assert_different_registers(to, value, count, rtmp); 7090 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 7091 Label L_fill_2_bytes, L_fill_4_bytes; 7092 7093 int shift = -1; 7094 switch (t) { 7095 case T_BYTE: 7096 shift = 2; 7097 break; 7098 case T_SHORT: 7099 shift = 1; 7100 break; 7101 case T_INT: 7102 shift = 0; 7103 break; 7104 default: ShouldNotReachHere(); 7105 } 7106 7107 if (t == T_BYTE) { 7108 andl(value, 0xff); 7109 movl(rtmp, value); 7110 shll(rtmp, 8); 7111 orl(value, rtmp); 7112 } 7113 if (t == T_SHORT) { 7114 andl(value, 0xffff); 7115 } 7116 if (t == T_BYTE || t == T_SHORT) { 7117 movl(rtmp, value); 7118 shll(rtmp, 16); 7119 orl(value, rtmp); 7120 } 7121 7122 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 7123 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 7124 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 7125 // align source address at 4 bytes address boundary 7126 if (t == T_BYTE) { 7127 // One byte misalignment happens only for byte arrays 7128 testptr(to, 1); 7129 jccb(Assembler::zero, L_skip_align1); 7130 movb(Address(to, 0), value); 7131 increment(to); 7132 decrement(count); 7133 BIND(L_skip_align1); 7134 } 7135 // Two bytes misalignment happens only for byte and short (char) arrays 7136 testptr(to, 2); 7137 jccb(Assembler::zero, L_skip_align2); 7138 movw(Address(to, 0), value); 7139 addptr(to, 2); 7140 subl(count, 1<<(shift-1)); 7141 BIND(L_skip_align2); 7142 } 7143 if (UseSSE < 2) { 7144 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 7145 // Fill 32-byte chunks 7146 subl(count, 8 << shift); 7147 jcc(Assembler::less, L_check_fill_8_bytes); 7148 align(16); 7149 7150 BIND(L_fill_32_bytes_loop); 7151 7152 for (int i = 0; i < 32; i += 4) { 7153 movl(Address(to, i), value); 7154 } 7155 7156 addptr(to, 32); 7157 subl(count, 8 << shift); 7158 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 7159 BIND(L_check_fill_8_bytes); 7160 addl(count, 8 << shift); 7161 jccb(Assembler::zero, L_exit); 7162 jmpb(L_fill_8_bytes); 7163 7164 // 7165 // length is too short, just fill qwords 7166 // 7167 BIND(L_fill_8_bytes_loop); 7168 movl(Address(to, 0), value); 7169 movl(Address(to, 4), value); 7170 addptr(to, 8); 7171 BIND(L_fill_8_bytes); 7172 subl(count, 1 << (shift + 1)); 7173 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 7174 // fall through to fill 4 bytes 7175 } else { 7176 Label L_fill_32_bytes; 7177 if (!UseUnalignedLoadStores) { 7178 // align to 8 bytes, we know we are 4 byte aligned to start 7179 testptr(to, 4); 7180 jccb(Assembler::zero, L_fill_32_bytes); 7181 movl(Address(to, 0), value); 7182 addptr(to, 4); 7183 subl(count, 1<<shift); 7184 } 7185 BIND(L_fill_32_bytes); 7186 { 7187 assert( UseSSE >= 2, "supported cpu only" ); 7188 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 7189 if (UseAVX > 2) { 7190 movl(rtmp, 0xffff); 7191 kmovwl(k1, rtmp); 7192 } 7193 movdl(xtmp, value); 7194 if (UseAVX > 2 && UseUnalignedLoadStores) { 7195 // Fill 64-byte chunks 7196 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 7197 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 7198 7199 subl(count, 16 << shift); 7200 jcc(Assembler::less, L_check_fill_32_bytes); 7201 align(16); 7202 7203 BIND(L_fill_64_bytes_loop); 7204 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 7205 addptr(to, 64); 7206 subl(count, 16 << shift); 7207 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 7208 7209 BIND(L_check_fill_32_bytes); 7210 addl(count, 8 << shift); 7211 jccb(Assembler::less, L_check_fill_8_bytes); 7212 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_256bit); 7213 addptr(to, 32); 7214 subl(count, 8 << shift); 7215 7216 BIND(L_check_fill_8_bytes); 7217 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 7218 // Fill 64-byte chunks 7219 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 7220 vpbroadcastd(xtmp, xtmp); 7221 7222 subl(count, 16 << shift); 7223 jcc(Assembler::less, L_check_fill_32_bytes); 7224 align(16); 7225 7226 BIND(L_fill_64_bytes_loop); 7227 vmovdqu(Address(to, 0), xtmp); 7228 vmovdqu(Address(to, 32), xtmp); 7229 addptr(to, 64); 7230 subl(count, 16 << shift); 7231 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 7232 7233 BIND(L_check_fill_32_bytes); 7234 addl(count, 8 << shift); 7235 jccb(Assembler::less, L_check_fill_8_bytes); 7236 vmovdqu(Address(to, 0), xtmp); 7237 addptr(to, 32); 7238 subl(count, 8 << shift); 7239 7240 BIND(L_check_fill_8_bytes); 7241 // clean upper bits of YMM registers 7242 movdl(xtmp, value); 7243 pshufd(xtmp, xtmp, 0); 7244 } else { 7245 // Fill 32-byte chunks 7246 pshufd(xtmp, xtmp, 0); 7247 7248 subl(count, 8 << shift); 7249 jcc(Assembler::less, L_check_fill_8_bytes); 7250 align(16); 7251 7252 BIND(L_fill_32_bytes_loop); 7253 7254 if (UseUnalignedLoadStores) { 7255 movdqu(Address(to, 0), xtmp); 7256 movdqu(Address(to, 16), xtmp); 7257 } else { 7258 movq(Address(to, 0), xtmp); 7259 movq(Address(to, 8), xtmp); 7260 movq(Address(to, 16), xtmp); 7261 movq(Address(to, 24), xtmp); 7262 } 7263 7264 addptr(to, 32); 7265 subl(count, 8 << shift); 7266 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 7267 7268 BIND(L_check_fill_8_bytes); 7269 } 7270 addl(count, 8 << shift); 7271 jccb(Assembler::zero, L_exit); 7272 jmpb(L_fill_8_bytes); 7273 7274 // 7275 // length is too short, just fill qwords 7276 // 7277 BIND(L_fill_8_bytes_loop); 7278 movq(Address(to, 0), xtmp); 7279 addptr(to, 8); 7280 BIND(L_fill_8_bytes); 7281 subl(count, 1 << (shift + 1)); 7282 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 7283 } 7284 } 7285 // fill trailing 4 bytes 7286 BIND(L_fill_4_bytes); 7287 testl(count, 1<<shift); 7288 jccb(Assembler::zero, L_fill_2_bytes); 7289 movl(Address(to, 0), value); 7290 if (t == T_BYTE || t == T_SHORT) { 7291 addptr(to, 4); 7292 BIND(L_fill_2_bytes); 7293 // fill trailing 2 bytes 7294 testl(count, 1<<(shift-1)); 7295 jccb(Assembler::zero, L_fill_byte); 7296 movw(Address(to, 0), value); 7297 if (t == T_BYTE) { 7298 addptr(to, 2); 7299 BIND(L_fill_byte); 7300 // fill trailing byte 7301 testl(count, 1); 7302 jccb(Assembler::zero, L_exit); 7303 movb(Address(to, 0), value); 7304 } else { 7305 BIND(L_fill_byte); 7306 } 7307 } else { 7308 BIND(L_fill_2_bytes); 7309 } 7310 BIND(L_exit); 7311 } 7312 7313 // encode char[] to byte[] in ISO_8859_1 7314 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 7315 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 7316 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 7317 Register tmp5, Register result) { 7318 // rsi: src 7319 // rdi: dst 7320 // rdx: len 7321 // rcx: tmp5 7322 // rax: result 7323 ShortBranchVerifier sbv(this); 7324 assert_different_registers(src, dst, len, tmp5, result); 7325 Label L_done, L_copy_1_char, L_copy_1_char_exit; 7326 7327 // set result 7328 xorl(result, result); 7329 // check for zero length 7330 testl(len, len); 7331 jcc(Assembler::zero, L_done); 7332 movl(result, len); 7333 7334 // Setup pointers 7335 lea(src, Address(src, len, Address::times_2)); // char[] 7336 lea(dst, Address(dst, len, Address::times_1)); // byte[] 7337 negptr(len); 7338 7339 if (UseSSE42Intrinsics || UseAVX >= 2) { 7340 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 7341 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 7342 7343 if (UseAVX >= 2) { 7344 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 7345 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 7346 movdl(tmp1Reg, tmp5); 7347 vpbroadcastd(tmp1Reg, tmp1Reg); 7348 jmpb(L_chars_32_check); 7349 7350 bind(L_copy_32_chars); 7351 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 7352 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 7353 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 7354 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7355 jccb(Assembler::notZero, L_copy_32_chars_exit); 7356 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 7357 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 7358 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 7359 7360 bind(L_chars_32_check); 7361 addptr(len, 32); 7362 jccb(Assembler::lessEqual, L_copy_32_chars); 7363 7364 bind(L_copy_32_chars_exit); 7365 subptr(len, 16); 7366 jccb(Assembler::greater, L_copy_16_chars_exit); 7367 7368 } else if (UseSSE42Intrinsics) { 7369 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 7370 movdl(tmp1Reg, tmp5); 7371 pshufd(tmp1Reg, tmp1Reg, 0); 7372 jmpb(L_chars_16_check); 7373 } 7374 7375 bind(L_copy_16_chars); 7376 if (UseAVX >= 2) { 7377 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 7378 vptest(tmp2Reg, tmp1Reg); 7379 jccb(Assembler::notZero, L_copy_16_chars_exit); 7380 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 7381 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 7382 } else { 7383 if (UseAVX > 0) { 7384 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 7385 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 7386 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 7387 } else { 7388 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 7389 por(tmp2Reg, tmp3Reg); 7390 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 7391 por(tmp2Reg, tmp4Reg); 7392 } 7393 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7394 jccb(Assembler::notZero, L_copy_16_chars_exit); 7395 packuswb(tmp3Reg, tmp4Reg); 7396 } 7397 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 7398 7399 bind(L_chars_16_check); 7400 addptr(len, 16); 7401 jccb(Assembler::lessEqual, L_copy_16_chars); 7402 7403 bind(L_copy_16_chars_exit); 7404 if (UseAVX >= 2) { 7405 // clean upper bits of YMM registers 7406 vpxor(tmp2Reg, tmp2Reg); 7407 vpxor(tmp3Reg, tmp3Reg); 7408 vpxor(tmp4Reg, tmp4Reg); 7409 movdl(tmp1Reg, tmp5); 7410 pshufd(tmp1Reg, tmp1Reg, 0); 7411 } 7412 subptr(len, 8); 7413 jccb(Assembler::greater, L_copy_8_chars_exit); 7414 7415 bind(L_copy_8_chars); 7416 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 7417 ptest(tmp3Reg, tmp1Reg); 7418 jccb(Assembler::notZero, L_copy_8_chars_exit); 7419 packuswb(tmp3Reg, tmp1Reg); 7420 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 7421 addptr(len, 8); 7422 jccb(Assembler::lessEqual, L_copy_8_chars); 7423 7424 bind(L_copy_8_chars_exit); 7425 subptr(len, 8); 7426 jccb(Assembler::zero, L_done); 7427 } 7428 7429 bind(L_copy_1_char); 7430 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 7431 testl(tmp5, 0xff00); // check if Unicode char 7432 jccb(Assembler::notZero, L_copy_1_char_exit); 7433 movb(Address(dst, len, Address::times_1, 0), tmp5); 7434 addptr(len, 1); 7435 jccb(Assembler::less, L_copy_1_char); 7436 7437 bind(L_copy_1_char_exit); 7438 addptr(result, len); // len is negative count of not processed elements 7439 bind(L_done); 7440 } 7441 7442 #ifdef _LP64 7443 /** 7444 * Helper for multiply_to_len(). 7445 */ 7446 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 7447 addq(dest_lo, src1); 7448 adcq(dest_hi, 0); 7449 addq(dest_lo, src2); 7450 adcq(dest_hi, 0); 7451 } 7452 7453 /** 7454 * Multiply 64 bit by 64 bit first loop. 7455 */ 7456 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 7457 Register y, Register y_idx, Register z, 7458 Register carry, Register product, 7459 Register idx, Register kdx) { 7460 // 7461 // jlong carry, x[], y[], z[]; 7462 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 7463 // huge_128 product = y[idx] * x[xstart] + carry; 7464 // z[kdx] = (jlong)product; 7465 // carry = (jlong)(product >>> 64); 7466 // } 7467 // z[xstart] = carry; 7468 // 7469 7470 Label L_first_loop, L_first_loop_exit; 7471 Label L_one_x, L_one_y, L_multiply; 7472 7473 decrementl(xstart); 7474 jcc(Assembler::negative, L_one_x); 7475 7476 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 7477 rorq(x_xstart, 32); // convert big-endian to little-endian 7478 7479 bind(L_first_loop); 7480 decrementl(idx); 7481 jcc(Assembler::negative, L_first_loop_exit); 7482 decrementl(idx); 7483 jcc(Assembler::negative, L_one_y); 7484 movq(y_idx, Address(y, idx, Address::times_4, 0)); 7485 rorq(y_idx, 32); // convert big-endian to little-endian 7486 bind(L_multiply); 7487 movq(product, x_xstart); 7488 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 7489 addq(product, carry); 7490 adcq(rdx, 0); 7491 subl(kdx, 2); 7492 movl(Address(z, kdx, Address::times_4, 4), product); 7493 shrq(product, 32); 7494 movl(Address(z, kdx, Address::times_4, 0), product); 7495 movq(carry, rdx); 7496 jmp(L_first_loop); 7497 7498 bind(L_one_y); 7499 movl(y_idx, Address(y, 0)); 7500 jmp(L_multiply); 7501 7502 bind(L_one_x); 7503 movl(x_xstart, Address(x, 0)); 7504 jmp(L_first_loop); 7505 7506 bind(L_first_loop_exit); 7507 } 7508 7509 /** 7510 * Multiply 64 bit by 64 bit and add 128 bit. 7511 */ 7512 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 7513 Register yz_idx, Register idx, 7514 Register carry, Register product, int offset) { 7515 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 7516 // z[kdx] = (jlong)product; 7517 7518 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 7519 rorq(yz_idx, 32); // convert big-endian to little-endian 7520 movq(product, x_xstart); 7521 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 7522 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 7523 rorq(yz_idx, 32); // convert big-endian to little-endian 7524 7525 add2_with_carry(rdx, product, carry, yz_idx); 7526 7527 movl(Address(z, idx, Address::times_4, offset+4), product); 7528 shrq(product, 32); 7529 movl(Address(z, idx, Address::times_4, offset), product); 7530 7531 } 7532 7533 /** 7534 * Multiply 128 bit by 128 bit. Unrolled inner loop. 7535 */ 7536 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 7537 Register yz_idx, Register idx, Register jdx, 7538 Register carry, Register product, 7539 Register carry2) { 7540 // jlong carry, x[], y[], z[]; 7541 // int kdx = ystart+1; 7542 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 7543 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 7544 // z[kdx+idx+1] = (jlong)product; 7545 // jlong carry2 = (jlong)(product >>> 64); 7546 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 7547 // z[kdx+idx] = (jlong)product; 7548 // carry = (jlong)(product >>> 64); 7549 // } 7550 // idx += 2; 7551 // if (idx > 0) { 7552 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 7553 // z[kdx+idx] = (jlong)product; 7554 // carry = (jlong)(product >>> 64); 7555 // } 7556 // 7557 7558 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 7559 7560 movl(jdx, idx); 7561 andl(jdx, 0xFFFFFFFC); 7562 shrl(jdx, 2); 7563 7564 bind(L_third_loop); 7565 subl(jdx, 1); 7566 jcc(Assembler::negative, L_third_loop_exit); 7567 subl(idx, 4); 7568 7569 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 7570 movq(carry2, rdx); 7571 7572 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 7573 movq(carry, rdx); 7574 jmp(L_third_loop); 7575 7576 bind (L_third_loop_exit); 7577 7578 andl (idx, 0x3); 7579 jcc(Assembler::zero, L_post_third_loop_done); 7580 7581 Label L_check_1; 7582 subl(idx, 2); 7583 jcc(Assembler::negative, L_check_1); 7584 7585 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 7586 movq(carry, rdx); 7587 7588 bind (L_check_1); 7589 addl (idx, 0x2); 7590 andl (idx, 0x1); 7591 subl(idx, 1); 7592 jcc(Assembler::negative, L_post_third_loop_done); 7593 7594 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 7595 movq(product, x_xstart); 7596 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 7597 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 7598 7599 add2_with_carry(rdx, product, yz_idx, carry); 7600 7601 movl(Address(z, idx, Address::times_4, 0), product); 7602 shrq(product, 32); 7603 7604 shlq(rdx, 32); 7605 orq(product, rdx); 7606 movq(carry, product); 7607 7608 bind(L_post_third_loop_done); 7609 } 7610 7611 /** 7612 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 7613 * 7614 */ 7615 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 7616 Register carry, Register carry2, 7617 Register idx, Register jdx, 7618 Register yz_idx1, Register yz_idx2, 7619 Register tmp, Register tmp3, Register tmp4) { 7620 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 7621 7622 // jlong carry, x[], y[], z[]; 7623 // int kdx = ystart+1; 7624 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 7625 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 7626 // jlong carry2 = (jlong)(tmp3 >>> 64); 7627 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 7628 // carry = (jlong)(tmp4 >>> 64); 7629 // z[kdx+idx+1] = (jlong)tmp3; 7630 // z[kdx+idx] = (jlong)tmp4; 7631 // } 7632 // idx += 2; 7633 // if (idx > 0) { 7634 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 7635 // z[kdx+idx] = (jlong)yz_idx1; 7636 // carry = (jlong)(yz_idx1 >>> 64); 7637 // } 7638 // 7639 7640 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 7641 7642 movl(jdx, idx); 7643 andl(jdx, 0xFFFFFFFC); 7644 shrl(jdx, 2); 7645 7646 bind(L_third_loop); 7647 subl(jdx, 1); 7648 jcc(Assembler::negative, L_third_loop_exit); 7649 subl(idx, 4); 7650 7651 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 7652 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 7653 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 7654 rorxq(yz_idx2, yz_idx2, 32); 7655 7656 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 7657 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 7658 7659 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 7660 rorxq(yz_idx1, yz_idx1, 32); 7661 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 7662 rorxq(yz_idx2, yz_idx2, 32); 7663 7664 if (VM_Version::supports_adx()) { 7665 adcxq(tmp3, carry); 7666 adoxq(tmp3, yz_idx1); 7667 7668 adcxq(tmp4, tmp); 7669 adoxq(tmp4, yz_idx2); 7670 7671 movl(carry, 0); // does not affect flags 7672 adcxq(carry2, carry); 7673 adoxq(carry2, carry); 7674 } else { 7675 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 7676 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 7677 } 7678 movq(carry, carry2); 7679 7680 movl(Address(z, idx, Address::times_4, 12), tmp3); 7681 shrq(tmp3, 32); 7682 movl(Address(z, idx, Address::times_4, 8), tmp3); 7683 7684 movl(Address(z, idx, Address::times_4, 4), tmp4); 7685 shrq(tmp4, 32); 7686 movl(Address(z, idx, Address::times_4, 0), tmp4); 7687 7688 jmp(L_third_loop); 7689 7690 bind (L_third_loop_exit); 7691 7692 andl (idx, 0x3); 7693 jcc(Assembler::zero, L_post_third_loop_done); 7694 7695 Label L_check_1; 7696 subl(idx, 2); 7697 jcc(Assembler::negative, L_check_1); 7698 7699 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 7700 rorxq(yz_idx1, yz_idx1, 32); 7701 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 7702 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 7703 rorxq(yz_idx2, yz_idx2, 32); 7704 7705 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 7706 7707 movl(Address(z, idx, Address::times_4, 4), tmp3); 7708 shrq(tmp3, 32); 7709 movl(Address(z, idx, Address::times_4, 0), tmp3); 7710 movq(carry, tmp4); 7711 7712 bind (L_check_1); 7713 addl (idx, 0x2); 7714 andl (idx, 0x1); 7715 subl(idx, 1); 7716 jcc(Assembler::negative, L_post_third_loop_done); 7717 movl(tmp4, Address(y, idx, Address::times_4, 0)); 7718 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 7719 movl(tmp4, Address(z, idx, Address::times_4, 0)); 7720 7721 add2_with_carry(carry2, tmp3, tmp4, carry); 7722 7723 movl(Address(z, idx, Address::times_4, 0), tmp3); 7724 shrq(tmp3, 32); 7725 7726 shlq(carry2, 32); 7727 orq(tmp3, carry2); 7728 movq(carry, tmp3); 7729 7730 bind(L_post_third_loop_done); 7731 } 7732 7733 /** 7734 * Code for BigInteger::multiplyToLen() instrinsic. 7735 * 7736 * rdi: x 7737 * rax: xlen 7738 * rsi: y 7739 * rcx: ylen 7740 * r8: z 7741 * r11: zlen 7742 * r12: tmp1 7743 * r13: tmp2 7744 * r14: tmp3 7745 * r15: tmp4 7746 * rbx: tmp5 7747 * 7748 */ 7749 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 7750 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 7751 ShortBranchVerifier sbv(this); 7752 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 7753 7754 push(tmp1); 7755 push(tmp2); 7756 push(tmp3); 7757 push(tmp4); 7758 push(tmp5); 7759 7760 push(xlen); 7761 push(zlen); 7762 7763 const Register idx = tmp1; 7764 const Register kdx = tmp2; 7765 const Register xstart = tmp3; 7766 7767 const Register y_idx = tmp4; 7768 const Register carry = tmp5; 7769 const Register product = xlen; 7770 const Register x_xstart = zlen; // reuse register 7771 7772 // First Loop. 7773 // 7774 // final static long LONG_MASK = 0xffffffffL; 7775 // int xstart = xlen - 1; 7776 // int ystart = ylen - 1; 7777 // long carry = 0; 7778 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 7779 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 7780 // z[kdx] = (int)product; 7781 // carry = product >>> 32; 7782 // } 7783 // z[xstart] = (int)carry; 7784 // 7785 7786 movl(idx, ylen); // idx = ylen; 7787 movl(kdx, zlen); // kdx = xlen+ylen; 7788 xorq(carry, carry); // carry = 0; 7789 7790 Label L_done; 7791 7792 movl(xstart, xlen); 7793 decrementl(xstart); 7794 jcc(Assembler::negative, L_done); 7795 7796 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 7797 7798 Label L_second_loop; 7799 testl(kdx, kdx); 7800 jcc(Assembler::zero, L_second_loop); 7801 7802 Label L_carry; 7803 subl(kdx, 1); 7804 jcc(Assembler::zero, L_carry); 7805 7806 movl(Address(z, kdx, Address::times_4, 0), carry); 7807 shrq(carry, 32); 7808 subl(kdx, 1); 7809 7810 bind(L_carry); 7811 movl(Address(z, kdx, Address::times_4, 0), carry); 7812 7813 // Second and third (nested) loops. 7814 // 7815 // for (int i = xstart-1; i >= 0; i--) { // Second loop 7816 // carry = 0; 7817 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 7818 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 7819 // (z[k] & LONG_MASK) + carry; 7820 // z[k] = (int)product; 7821 // carry = product >>> 32; 7822 // } 7823 // z[i] = (int)carry; 7824 // } 7825 // 7826 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 7827 7828 const Register jdx = tmp1; 7829 7830 bind(L_second_loop); 7831 xorl(carry, carry); // carry = 0; 7832 movl(jdx, ylen); // j = ystart+1 7833 7834 subl(xstart, 1); // i = xstart-1; 7835 jcc(Assembler::negative, L_done); 7836 7837 push (z); 7838 7839 Label L_last_x; 7840 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 7841 subl(xstart, 1); // i = xstart-1; 7842 jcc(Assembler::negative, L_last_x); 7843 7844 if (UseBMI2Instructions) { 7845 movq(rdx, Address(x, xstart, Address::times_4, 0)); 7846 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 7847 } else { 7848 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 7849 rorq(x_xstart, 32); // convert big-endian to little-endian 7850 } 7851 7852 Label L_third_loop_prologue; 7853 bind(L_third_loop_prologue); 7854 7855 push (x); 7856 push (xstart); 7857 push (ylen); 7858 7859 7860 if (UseBMI2Instructions) { 7861 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 7862 } else { // !UseBMI2Instructions 7863 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 7864 } 7865 7866 pop(ylen); 7867 pop(xlen); 7868 pop(x); 7869 pop(z); 7870 7871 movl(tmp3, xlen); 7872 addl(tmp3, 1); 7873 movl(Address(z, tmp3, Address::times_4, 0), carry); 7874 subl(tmp3, 1); 7875 jccb(Assembler::negative, L_done); 7876 7877 shrq(carry, 32); 7878 movl(Address(z, tmp3, Address::times_4, 0), carry); 7879 jmp(L_second_loop); 7880 7881 // Next infrequent code is moved outside loops. 7882 bind(L_last_x); 7883 if (UseBMI2Instructions) { 7884 movl(rdx, Address(x, 0)); 7885 } else { 7886 movl(x_xstart, Address(x, 0)); 7887 } 7888 jmp(L_third_loop_prologue); 7889 7890 bind(L_done); 7891 7892 pop(zlen); 7893 pop(xlen); 7894 7895 pop(tmp5); 7896 pop(tmp4); 7897 pop(tmp3); 7898 pop(tmp2); 7899 pop(tmp1); 7900 } 7901 7902 //Helper functions for square_to_len() 7903 7904 /** 7905 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 7906 * Preserves x and z and modifies rest of the registers. 7907 */ 7908 7909 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7910 // Perform square and right shift by 1 7911 // Handle odd xlen case first, then for even xlen do the following 7912 // jlong carry = 0; 7913 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 7914 // huge_128 product = x[j:j+1] * x[j:j+1]; 7915 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 7916 // z[i+2:i+3] = (jlong)(product >>> 1); 7917 // carry = (jlong)product; 7918 // } 7919 7920 xorq(tmp5, tmp5); // carry 7921 xorq(rdxReg, rdxReg); 7922 xorl(tmp1, tmp1); // index for x 7923 xorl(tmp4, tmp4); // index for z 7924 7925 Label L_first_loop, L_first_loop_exit; 7926 7927 testl(xlen, 1); 7928 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 7929 7930 // Square and right shift by 1 the odd element using 32 bit multiply 7931 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 7932 imulq(raxReg, raxReg); 7933 shrq(raxReg, 1); 7934 adcq(tmp5, 0); 7935 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 7936 incrementl(tmp1); 7937 addl(tmp4, 2); 7938 7939 // Square and right shift by 1 the rest using 64 bit multiply 7940 bind(L_first_loop); 7941 cmpptr(tmp1, xlen); 7942 jccb(Assembler::equal, L_first_loop_exit); 7943 7944 // Square 7945 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 7946 rorq(raxReg, 32); // convert big-endian to little-endian 7947 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 7948 7949 // Right shift by 1 and save carry 7950 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 7951 rcrq(rdxReg, 1); 7952 rcrq(raxReg, 1); 7953 adcq(tmp5, 0); 7954 7955 // Store result in z 7956 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 7957 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 7958 7959 // Update indices for x and z 7960 addl(tmp1, 2); 7961 addl(tmp4, 4); 7962 jmp(L_first_loop); 7963 7964 bind(L_first_loop_exit); 7965 } 7966 7967 7968 /** 7969 * Perform the following multiply add operation using BMI2 instructions 7970 * carry:sum = sum + op1*op2 + carry 7971 * op2 should be in rdx 7972 * op2 is preserved, all other registers are modified 7973 */ 7974 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 7975 // assert op2 is rdx 7976 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 7977 addq(sum, carry); 7978 adcq(tmp2, 0); 7979 addq(sum, op1); 7980 adcq(tmp2, 0); 7981 movq(carry, tmp2); 7982 } 7983 7984 /** 7985 * Perform the following multiply add operation: 7986 * carry:sum = sum + op1*op2 + carry 7987 * Preserves op1, op2 and modifies rest of registers 7988 */ 7989 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 7990 // rdx:rax = op1 * op2 7991 movq(raxReg, op2); 7992 mulq(op1); 7993 7994 // rdx:rax = sum + carry + rdx:rax 7995 addq(sum, carry); 7996 adcq(rdxReg, 0); 7997 addq(sum, raxReg); 7998 adcq(rdxReg, 0); 7999 8000 // carry:sum = rdx:sum 8001 movq(carry, rdxReg); 8002 } 8003 8004 /** 8005 * Add 64 bit long carry into z[] with carry propogation. 8006 * Preserves z and carry register values and modifies rest of registers. 8007 * 8008 */ 8009 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 8010 Label L_fourth_loop, L_fourth_loop_exit; 8011 8012 movl(tmp1, 1); 8013 subl(zlen, 2); 8014 addq(Address(z, zlen, Address::times_4, 0), carry); 8015 8016 bind(L_fourth_loop); 8017 jccb(Assembler::carryClear, L_fourth_loop_exit); 8018 subl(zlen, 2); 8019 jccb(Assembler::negative, L_fourth_loop_exit); 8020 addq(Address(z, zlen, Address::times_4, 0), tmp1); 8021 jmp(L_fourth_loop); 8022 bind(L_fourth_loop_exit); 8023 } 8024 8025 /** 8026 * Shift z[] left by 1 bit. 8027 * Preserves x, len, z and zlen registers and modifies rest of the registers. 8028 * 8029 */ 8030 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 8031 8032 Label L_fifth_loop, L_fifth_loop_exit; 8033 8034 // Fifth loop 8035 // Perform primitiveLeftShift(z, zlen, 1) 8036 8037 const Register prev_carry = tmp1; 8038 const Register new_carry = tmp4; 8039 const Register value = tmp2; 8040 const Register zidx = tmp3; 8041 8042 // int zidx, carry; 8043 // long value; 8044 // carry = 0; 8045 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 8046 // (carry:value) = (z[i] << 1) | carry ; 8047 // z[i] = value; 8048 // } 8049 8050 movl(zidx, zlen); 8051 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 8052 8053 bind(L_fifth_loop); 8054 decl(zidx); // Use decl to preserve carry flag 8055 decl(zidx); 8056 jccb(Assembler::negative, L_fifth_loop_exit); 8057 8058 if (UseBMI2Instructions) { 8059 movq(value, Address(z, zidx, Address::times_4, 0)); 8060 rclq(value, 1); 8061 rorxq(value, value, 32); 8062 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 8063 } 8064 else { 8065 // clear new_carry 8066 xorl(new_carry, new_carry); 8067 8068 // Shift z[i] by 1, or in previous carry and save new carry 8069 movq(value, Address(z, zidx, Address::times_4, 0)); 8070 shlq(value, 1); 8071 adcl(new_carry, 0); 8072 8073 orq(value, prev_carry); 8074 rorq(value, 0x20); 8075 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 8076 8077 // Set previous carry = new carry 8078 movl(prev_carry, new_carry); 8079 } 8080 jmp(L_fifth_loop); 8081 8082 bind(L_fifth_loop_exit); 8083 } 8084 8085 8086 /** 8087 * Code for BigInteger::squareToLen() intrinsic 8088 * 8089 * rdi: x 8090 * rsi: len 8091 * r8: z 8092 * rcx: zlen 8093 * r12: tmp1 8094 * r13: tmp2 8095 * r14: tmp3 8096 * r15: tmp4 8097 * rbx: tmp5 8098 * 8099 */ 8100 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8101 8102 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 8103 push(tmp1); 8104 push(tmp2); 8105 push(tmp3); 8106 push(tmp4); 8107 push(tmp5); 8108 8109 // First loop 8110 // Store the squares, right shifted one bit (i.e., divided by 2). 8111 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 8112 8113 // Add in off-diagonal sums. 8114 // 8115 // Second, third (nested) and fourth loops. 8116 // zlen +=2; 8117 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 8118 // carry = 0; 8119 // long op2 = x[xidx:xidx+1]; 8120 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 8121 // k -= 2; 8122 // long op1 = x[j:j+1]; 8123 // long sum = z[k:k+1]; 8124 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 8125 // z[k:k+1] = sum; 8126 // } 8127 // add_one_64(z, k, carry, tmp_regs); 8128 // } 8129 8130 const Register carry = tmp5; 8131 const Register sum = tmp3; 8132 const Register op1 = tmp4; 8133 Register op2 = tmp2; 8134 8135 push(zlen); 8136 push(len); 8137 addl(zlen,2); 8138 bind(L_second_loop); 8139 xorq(carry, carry); 8140 subl(zlen, 4); 8141 subl(len, 2); 8142 push(zlen); 8143 push(len); 8144 cmpl(len, 0); 8145 jccb(Assembler::lessEqual, L_second_loop_exit); 8146 8147 // Multiply an array by one 64 bit long. 8148 if (UseBMI2Instructions) { 8149 op2 = rdxReg; 8150 movq(op2, Address(x, len, Address::times_4, 0)); 8151 rorxq(op2, op2, 32); 8152 } 8153 else { 8154 movq(op2, Address(x, len, Address::times_4, 0)); 8155 rorq(op2, 32); 8156 } 8157 8158 bind(L_third_loop); 8159 decrementl(len); 8160 jccb(Assembler::negative, L_third_loop_exit); 8161 decrementl(len); 8162 jccb(Assembler::negative, L_last_x); 8163 8164 movq(op1, Address(x, len, Address::times_4, 0)); 8165 rorq(op1, 32); 8166 8167 bind(L_multiply); 8168 subl(zlen, 2); 8169 movq(sum, Address(z, zlen, Address::times_4, 0)); 8170 8171 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 8172 if (UseBMI2Instructions) { 8173 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 8174 } 8175 else { 8176 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8177 } 8178 8179 movq(Address(z, zlen, Address::times_4, 0), sum); 8180 8181 jmp(L_third_loop); 8182 bind(L_third_loop_exit); 8183 8184 // Fourth loop 8185 // Add 64 bit long carry into z with carry propogation. 8186 // Uses offsetted zlen. 8187 add_one_64(z, zlen, carry, tmp1); 8188 8189 pop(len); 8190 pop(zlen); 8191 jmp(L_second_loop); 8192 8193 // Next infrequent code is moved outside loops. 8194 bind(L_last_x); 8195 movl(op1, Address(x, 0)); 8196 jmp(L_multiply); 8197 8198 bind(L_second_loop_exit); 8199 pop(len); 8200 pop(zlen); 8201 pop(len); 8202 pop(zlen); 8203 8204 // Fifth loop 8205 // Shift z left 1 bit. 8206 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 8207 8208 // z[zlen-1] |= x[len-1] & 1; 8209 movl(tmp3, Address(x, len, Address::times_4, -4)); 8210 andl(tmp3, 1); 8211 orl(Address(z, zlen, Address::times_4, -4), tmp3); 8212 8213 pop(tmp5); 8214 pop(tmp4); 8215 pop(tmp3); 8216 pop(tmp2); 8217 pop(tmp1); 8218 } 8219 8220 /** 8221 * Helper function for mul_add() 8222 * Multiply the in[] by int k and add to out[] starting at offset offs using 8223 * 128 bit by 32 bit multiply and return the carry in tmp5. 8224 * Only quad int aligned length of in[] is operated on in this function. 8225 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 8226 * This function preserves out, in and k registers. 8227 * len and offset point to the appropriate index in "in" & "out" correspondingly 8228 * tmp5 has the carry. 8229 * other registers are temporary and are modified. 8230 * 8231 */ 8232 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 8233 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 8234 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8235 8236 Label L_first_loop, L_first_loop_exit; 8237 8238 movl(tmp1, len); 8239 shrl(tmp1, 2); 8240 8241 bind(L_first_loop); 8242 subl(tmp1, 1); 8243 jccb(Assembler::negative, L_first_loop_exit); 8244 8245 subl(len, 4); 8246 subl(offset, 4); 8247 8248 Register op2 = tmp2; 8249 const Register sum = tmp3; 8250 const Register op1 = tmp4; 8251 const Register carry = tmp5; 8252 8253 if (UseBMI2Instructions) { 8254 op2 = rdxReg; 8255 } 8256 8257 movq(op1, Address(in, len, Address::times_4, 8)); 8258 rorq(op1, 32); 8259 movq(sum, Address(out, offset, Address::times_4, 8)); 8260 rorq(sum, 32); 8261 if (UseBMI2Instructions) { 8262 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8263 } 8264 else { 8265 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8266 } 8267 // Store back in big endian from little endian 8268 rorq(sum, 0x20); 8269 movq(Address(out, offset, Address::times_4, 8), sum); 8270 8271 movq(op1, Address(in, len, Address::times_4, 0)); 8272 rorq(op1, 32); 8273 movq(sum, Address(out, offset, Address::times_4, 0)); 8274 rorq(sum, 32); 8275 if (UseBMI2Instructions) { 8276 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8277 } 8278 else { 8279 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8280 } 8281 // Store back in big endian from little endian 8282 rorq(sum, 0x20); 8283 movq(Address(out, offset, Address::times_4, 0), sum); 8284 8285 jmp(L_first_loop); 8286 bind(L_first_loop_exit); 8287 } 8288 8289 /** 8290 * Code for BigInteger::mulAdd() intrinsic 8291 * 8292 * rdi: out 8293 * rsi: in 8294 * r11: offs (out.length - offset) 8295 * rcx: len 8296 * r8: k 8297 * r12: tmp1 8298 * r13: tmp2 8299 * r14: tmp3 8300 * r15: tmp4 8301 * rbx: tmp5 8302 * Multiply the in[] by word k and add to out[], return the carry in rax 8303 */ 8304 void MacroAssembler::mul_add(Register out, Register in, Register offs, 8305 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 8306 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8307 8308 Label L_carry, L_last_in, L_done; 8309 8310 // carry = 0; 8311 // for (int j=len-1; j >= 0; j--) { 8312 // long product = (in[j] & LONG_MASK) * kLong + 8313 // (out[offs] & LONG_MASK) + carry; 8314 // out[offs--] = (int)product; 8315 // carry = product >>> 32; 8316 // } 8317 // 8318 push(tmp1); 8319 push(tmp2); 8320 push(tmp3); 8321 push(tmp4); 8322 push(tmp5); 8323 8324 Register op2 = tmp2; 8325 const Register sum = tmp3; 8326 const Register op1 = tmp4; 8327 const Register carry = tmp5; 8328 8329 if (UseBMI2Instructions) { 8330 op2 = rdxReg; 8331 movl(op2, k); 8332 } 8333 else { 8334 movl(op2, k); 8335 } 8336 8337 xorq(carry, carry); 8338 8339 //First loop 8340 8341 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 8342 //The carry is in tmp5 8343 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 8344 8345 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 8346 decrementl(len); 8347 jccb(Assembler::negative, L_carry); 8348 decrementl(len); 8349 jccb(Assembler::negative, L_last_in); 8350 8351 movq(op1, Address(in, len, Address::times_4, 0)); 8352 rorq(op1, 32); 8353 8354 subl(offs, 2); 8355 movq(sum, Address(out, offs, Address::times_4, 0)); 8356 rorq(sum, 32); 8357 8358 if (UseBMI2Instructions) { 8359 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8360 } 8361 else { 8362 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8363 } 8364 8365 // Store back in big endian from little endian 8366 rorq(sum, 0x20); 8367 movq(Address(out, offs, Address::times_4, 0), sum); 8368 8369 testl(len, len); 8370 jccb(Assembler::zero, L_carry); 8371 8372 //Multiply the last in[] entry, if any 8373 bind(L_last_in); 8374 movl(op1, Address(in, 0)); 8375 movl(sum, Address(out, offs, Address::times_4, -4)); 8376 8377 movl(raxReg, k); 8378 mull(op1); //tmp4 * eax -> edx:eax 8379 addl(sum, carry); 8380 adcl(rdxReg, 0); 8381 addl(sum, raxReg); 8382 adcl(rdxReg, 0); 8383 movl(carry, rdxReg); 8384 8385 movl(Address(out, offs, Address::times_4, -4), sum); 8386 8387 bind(L_carry); 8388 //return tmp5/carry as carry in rax 8389 movl(rax, carry); 8390 8391 bind(L_done); 8392 pop(tmp5); 8393 pop(tmp4); 8394 pop(tmp3); 8395 pop(tmp2); 8396 pop(tmp1); 8397 } 8398 #endif 8399 8400 /** 8401 * Emits code to update CRC-32 with a byte value according to constants in table 8402 * 8403 * @param [in,out]crc Register containing the crc. 8404 * @param [in]val Register containing the byte to fold into the CRC. 8405 * @param [in]table Register containing the table of crc constants. 8406 * 8407 * uint32_t crc; 8408 * val = crc_table[(val ^ crc) & 0xFF]; 8409 * crc = val ^ (crc >> 8); 8410 * 8411 */ 8412 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 8413 xorl(val, crc); 8414 andl(val, 0xFF); 8415 shrl(crc, 8); // unsigned shift 8416 xorl(crc, Address(table, val, Address::times_4, 0)); 8417 } 8418 8419 /** 8420 * Fold 128-bit data chunk 8421 */ 8422 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 8423 if (UseAVX > 0) { 8424 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 8425 vpclmulldq(xcrc, xK, xcrc); // [63:0] 8426 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 8427 pxor(xcrc, xtmp); 8428 } else { 8429 movdqa(xtmp, xcrc); 8430 pclmulhdq(xtmp, xK); // [123:64] 8431 pclmulldq(xcrc, xK); // [63:0] 8432 pxor(xcrc, xtmp); 8433 movdqu(xtmp, Address(buf, offset)); 8434 pxor(xcrc, xtmp); 8435 } 8436 } 8437 8438 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 8439 if (UseAVX > 0) { 8440 vpclmulhdq(xtmp, xK, xcrc); 8441 vpclmulldq(xcrc, xK, xcrc); 8442 pxor(xcrc, xbuf); 8443 pxor(xcrc, xtmp); 8444 } else { 8445 movdqa(xtmp, xcrc); 8446 pclmulhdq(xtmp, xK); 8447 pclmulldq(xcrc, xK); 8448 pxor(xcrc, xbuf); 8449 pxor(xcrc, xtmp); 8450 } 8451 } 8452 8453 /** 8454 * 8-bit folds to compute 32-bit CRC 8455 * 8456 * uint64_t xcrc; 8457 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 8458 */ 8459 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 8460 movdl(tmp, xcrc); 8461 andl(tmp, 0xFF); 8462 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 8463 psrldq(xcrc, 1); // unsigned shift one byte 8464 pxor(xcrc, xtmp); 8465 } 8466 8467 /** 8468 * uint32_t crc; 8469 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 8470 */ 8471 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 8472 movl(tmp, crc); 8473 andl(tmp, 0xFF); 8474 shrl(crc, 8); 8475 xorl(crc, Address(table, tmp, Address::times_4, 0)); 8476 } 8477 8478 /** 8479 * @param crc register containing existing CRC (32-bit) 8480 * @param buf register pointing to input byte buffer (byte*) 8481 * @param len register containing number of bytes 8482 * @param table register that will contain address of CRC table 8483 * @param tmp scratch register 8484 */ 8485 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 8486 assert_different_registers(crc, buf, len, table, tmp, rax); 8487 8488 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 8489 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 8490 8491 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 8492 // context for the registers used, where all instructions below are using 128-bit mode 8493 // On EVEX without VL and BW, these instructions will all be AVX. 8494 if (VM_Version::supports_avx512vlbw()) { 8495 movl(tmp, 0xffff); 8496 kmovwl(k1, tmp); 8497 } 8498 8499 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 8500 notl(crc); // ~crc 8501 cmpl(len, 16); 8502 jcc(Assembler::less, L_tail); 8503 8504 // Align buffer to 16 bytes 8505 movl(tmp, buf); 8506 andl(tmp, 0xF); 8507 jccb(Assembler::zero, L_aligned); 8508 subl(tmp, 16); 8509 addl(len, tmp); 8510 8511 align(4); 8512 BIND(L_align_loop); 8513 movsbl(rax, Address(buf, 0)); // load byte with sign extension 8514 update_byte_crc32(crc, rax, table); 8515 increment(buf); 8516 incrementl(tmp); 8517 jccb(Assembler::less, L_align_loop); 8518 8519 BIND(L_aligned); 8520 movl(tmp, len); // save 8521 shrl(len, 4); 8522 jcc(Assembler::zero, L_tail_restore); 8523 8524 // Fold crc into first bytes of vector 8525 movdqa(xmm1, Address(buf, 0)); 8526 movdl(rax, xmm1); 8527 xorl(crc, rax); 8528 pinsrd(xmm1, crc, 0); 8529 addptr(buf, 16); 8530 subl(len, 4); // len > 0 8531 jcc(Assembler::less, L_fold_tail); 8532 8533 movdqa(xmm2, Address(buf, 0)); 8534 movdqa(xmm3, Address(buf, 16)); 8535 movdqa(xmm4, Address(buf, 32)); 8536 addptr(buf, 48); 8537 subl(len, 3); 8538 jcc(Assembler::lessEqual, L_fold_512b); 8539 8540 // Fold total 512 bits of polynomial on each iteration, 8541 // 128 bits per each of 4 parallel streams. 8542 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 8543 8544 align(32); 8545 BIND(L_fold_512b_loop); 8546 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 8547 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 8548 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 8549 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 8550 addptr(buf, 64); 8551 subl(len, 4); 8552 jcc(Assembler::greater, L_fold_512b_loop); 8553 8554 // Fold 512 bits to 128 bits. 8555 BIND(L_fold_512b); 8556 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 8557 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 8558 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 8559 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 8560 8561 // Fold the rest of 128 bits data chunks 8562 BIND(L_fold_tail); 8563 addl(len, 3); 8564 jccb(Assembler::lessEqual, L_fold_128b); 8565 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 8566 8567 BIND(L_fold_tail_loop); 8568 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 8569 addptr(buf, 16); 8570 decrementl(len); 8571 jccb(Assembler::greater, L_fold_tail_loop); 8572 8573 // Fold 128 bits in xmm1 down into 32 bits in crc register. 8574 BIND(L_fold_128b); 8575 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 8576 if (UseAVX > 0) { 8577 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 8578 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 8579 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 8580 } else { 8581 movdqa(xmm2, xmm0); 8582 pclmulqdq(xmm2, xmm1, 0x1); 8583 movdqa(xmm3, xmm0); 8584 pand(xmm3, xmm2); 8585 pclmulqdq(xmm0, xmm3, 0x1); 8586 } 8587 psrldq(xmm1, 8); 8588 psrldq(xmm2, 4); 8589 pxor(xmm0, xmm1); 8590 pxor(xmm0, xmm2); 8591 8592 // 8 8-bit folds to compute 32-bit CRC. 8593 for (int j = 0; j < 4; j++) { 8594 fold_8bit_crc32(xmm0, table, xmm1, rax); 8595 } 8596 movdl(crc, xmm0); // mov 32 bits to general register 8597 for (int j = 0; j < 4; j++) { 8598 fold_8bit_crc32(crc, table, rax); 8599 } 8600 8601 BIND(L_tail_restore); 8602 movl(len, tmp); // restore 8603 BIND(L_tail); 8604 andl(len, 0xf); 8605 jccb(Assembler::zero, L_exit); 8606 8607 // Fold the rest of bytes 8608 align(4); 8609 BIND(L_tail_loop); 8610 movsbl(rax, Address(buf, 0)); // load byte with sign extension 8611 update_byte_crc32(crc, rax, table); 8612 increment(buf); 8613 decrementl(len); 8614 jccb(Assembler::greater, L_tail_loop); 8615 8616 BIND(L_exit); 8617 notl(crc); // ~c 8618 } 8619 8620 #ifdef _LP64 8621 // S. Gueron / Information Processing Letters 112 (2012) 184 8622 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 8623 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 8624 // Output: the 64-bit carry-less product of B * CONST 8625 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 8626 Register tmp1, Register tmp2, Register tmp3) { 8627 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 8628 if (n > 0) { 8629 addq(tmp3, n * 256 * 8); 8630 } 8631 // Q1 = TABLEExt[n][B & 0xFF]; 8632 movl(tmp1, in); 8633 andl(tmp1, 0x000000FF); 8634 shll(tmp1, 3); 8635 addq(tmp1, tmp3); 8636 movq(tmp1, Address(tmp1, 0)); 8637 8638 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 8639 movl(tmp2, in); 8640 shrl(tmp2, 8); 8641 andl(tmp2, 0x000000FF); 8642 shll(tmp2, 3); 8643 addq(tmp2, tmp3); 8644 movq(tmp2, Address(tmp2, 0)); 8645 8646 shlq(tmp2, 8); 8647 xorq(tmp1, tmp2); 8648 8649 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 8650 movl(tmp2, in); 8651 shrl(tmp2, 16); 8652 andl(tmp2, 0x000000FF); 8653 shll(tmp2, 3); 8654 addq(tmp2, tmp3); 8655 movq(tmp2, Address(tmp2, 0)); 8656 8657 shlq(tmp2, 16); 8658 xorq(tmp1, tmp2); 8659 8660 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 8661 shrl(in, 24); 8662 andl(in, 0x000000FF); 8663 shll(in, 3); 8664 addq(in, tmp3); 8665 movq(in, Address(in, 0)); 8666 8667 shlq(in, 24); 8668 xorq(in, tmp1); 8669 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 8670 } 8671 8672 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 8673 Register in_out, 8674 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 8675 XMMRegister w_xtmp2, 8676 Register tmp1, 8677 Register n_tmp2, Register n_tmp3) { 8678 if (is_pclmulqdq_supported) { 8679 movdl(w_xtmp1, in_out); // modified blindly 8680 8681 movl(tmp1, const_or_pre_comp_const_index); 8682 movdl(w_xtmp2, tmp1); 8683 pclmulqdq(w_xtmp1, w_xtmp2, 0); 8684 8685 movdq(in_out, w_xtmp1); 8686 } else { 8687 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 8688 } 8689 } 8690 8691 // Recombination Alternative 2: No bit-reflections 8692 // T1 = (CRC_A * U1) << 1 8693 // T2 = (CRC_B * U2) << 1 8694 // C1 = T1 >> 32 8695 // C2 = T2 >> 32 8696 // T1 = T1 & 0xFFFFFFFF 8697 // T2 = T2 & 0xFFFFFFFF 8698 // T1 = CRC32(0, T1) 8699 // T2 = CRC32(0, T2) 8700 // C1 = C1 ^ T1 8701 // C2 = C2 ^ T2 8702 // CRC = C1 ^ C2 ^ CRC_C 8703 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 8704 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8705 Register tmp1, Register tmp2, 8706 Register n_tmp3) { 8707 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8708 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8709 shlq(in_out, 1); 8710 movl(tmp1, in_out); 8711 shrq(in_out, 32); 8712 xorl(tmp2, tmp2); 8713 crc32(tmp2, tmp1, 4); 8714 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 8715 shlq(in1, 1); 8716 movl(tmp1, in1); 8717 shrq(in1, 32); 8718 xorl(tmp2, tmp2); 8719 crc32(tmp2, tmp1, 4); 8720 xorl(in1, tmp2); 8721 xorl(in_out, in1); 8722 xorl(in_out, in2); 8723 } 8724 8725 // Set N to predefined value 8726 // Subtract from a lenght of a buffer 8727 // execute in a loop: 8728 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 8729 // for i = 1 to N do 8730 // CRC_A = CRC32(CRC_A, A[i]) 8731 // CRC_B = CRC32(CRC_B, B[i]) 8732 // CRC_C = CRC32(CRC_C, C[i]) 8733 // end for 8734 // Recombine 8735 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 8736 Register in_out1, Register in_out2, Register in_out3, 8737 Register tmp1, Register tmp2, Register tmp3, 8738 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8739 Register tmp4, Register tmp5, 8740 Register n_tmp6) { 8741 Label L_processPartitions; 8742 Label L_processPartition; 8743 Label L_exit; 8744 8745 bind(L_processPartitions); 8746 cmpl(in_out1, 3 * size); 8747 jcc(Assembler::less, L_exit); 8748 xorl(tmp1, tmp1); 8749 xorl(tmp2, tmp2); 8750 movq(tmp3, in_out2); 8751 addq(tmp3, size); 8752 8753 bind(L_processPartition); 8754 crc32(in_out3, Address(in_out2, 0), 8); 8755 crc32(tmp1, Address(in_out2, size), 8); 8756 crc32(tmp2, Address(in_out2, size * 2), 8); 8757 addq(in_out2, 8); 8758 cmpq(in_out2, tmp3); 8759 jcc(Assembler::less, L_processPartition); 8760 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8761 w_xtmp1, w_xtmp2, w_xtmp3, 8762 tmp4, tmp5, 8763 n_tmp6); 8764 addq(in_out2, 2 * size); 8765 subl(in_out1, 3 * size); 8766 jmp(L_processPartitions); 8767 8768 bind(L_exit); 8769 } 8770 #else 8771 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 8772 Register tmp1, Register tmp2, Register tmp3, 8773 XMMRegister xtmp1, XMMRegister xtmp2) { 8774 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 8775 if (n > 0) { 8776 addl(tmp3, n * 256 * 8); 8777 } 8778 // Q1 = TABLEExt[n][B & 0xFF]; 8779 movl(tmp1, in_out); 8780 andl(tmp1, 0x000000FF); 8781 shll(tmp1, 3); 8782 addl(tmp1, tmp3); 8783 movq(xtmp1, Address(tmp1, 0)); 8784 8785 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 8786 movl(tmp2, in_out); 8787 shrl(tmp2, 8); 8788 andl(tmp2, 0x000000FF); 8789 shll(tmp2, 3); 8790 addl(tmp2, tmp3); 8791 movq(xtmp2, Address(tmp2, 0)); 8792 8793 psllq(xtmp2, 8); 8794 pxor(xtmp1, xtmp2); 8795 8796 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 8797 movl(tmp2, in_out); 8798 shrl(tmp2, 16); 8799 andl(tmp2, 0x000000FF); 8800 shll(tmp2, 3); 8801 addl(tmp2, tmp3); 8802 movq(xtmp2, Address(tmp2, 0)); 8803 8804 psllq(xtmp2, 16); 8805 pxor(xtmp1, xtmp2); 8806 8807 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 8808 shrl(in_out, 24); 8809 andl(in_out, 0x000000FF); 8810 shll(in_out, 3); 8811 addl(in_out, tmp3); 8812 movq(xtmp2, Address(in_out, 0)); 8813 8814 psllq(xtmp2, 24); 8815 pxor(xtmp1, xtmp2); // Result in CXMM 8816 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 8817 } 8818 8819 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 8820 Register in_out, 8821 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 8822 XMMRegister w_xtmp2, 8823 Register tmp1, 8824 Register n_tmp2, Register n_tmp3) { 8825 if (is_pclmulqdq_supported) { 8826 movdl(w_xtmp1, in_out); 8827 8828 movl(tmp1, const_or_pre_comp_const_index); 8829 movdl(w_xtmp2, tmp1); 8830 pclmulqdq(w_xtmp1, w_xtmp2, 0); 8831 // Keep result in XMM since GPR is 32 bit in length 8832 } else { 8833 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 8834 } 8835 } 8836 8837 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 8838 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8839 Register tmp1, Register tmp2, 8840 Register n_tmp3) { 8841 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8842 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8843 8844 psllq(w_xtmp1, 1); 8845 movdl(tmp1, w_xtmp1); 8846 psrlq(w_xtmp1, 32); 8847 movdl(in_out, w_xtmp1); 8848 8849 xorl(tmp2, tmp2); 8850 crc32(tmp2, tmp1, 4); 8851 xorl(in_out, tmp2); 8852 8853 psllq(w_xtmp2, 1); 8854 movdl(tmp1, w_xtmp2); 8855 psrlq(w_xtmp2, 32); 8856 movdl(in1, w_xtmp2); 8857 8858 xorl(tmp2, tmp2); 8859 crc32(tmp2, tmp1, 4); 8860 xorl(in1, tmp2); 8861 xorl(in_out, in1); 8862 xorl(in_out, in2); 8863 } 8864 8865 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 8866 Register in_out1, Register in_out2, Register in_out3, 8867 Register tmp1, Register tmp2, Register tmp3, 8868 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8869 Register tmp4, Register tmp5, 8870 Register n_tmp6) { 8871 Label L_processPartitions; 8872 Label L_processPartition; 8873 Label L_exit; 8874 8875 bind(L_processPartitions); 8876 cmpl(in_out1, 3 * size); 8877 jcc(Assembler::less, L_exit); 8878 xorl(tmp1, tmp1); 8879 xorl(tmp2, tmp2); 8880 movl(tmp3, in_out2); 8881 addl(tmp3, size); 8882 8883 bind(L_processPartition); 8884 crc32(in_out3, Address(in_out2, 0), 4); 8885 crc32(tmp1, Address(in_out2, size), 4); 8886 crc32(tmp2, Address(in_out2, size*2), 4); 8887 crc32(in_out3, Address(in_out2, 0+4), 4); 8888 crc32(tmp1, Address(in_out2, size+4), 4); 8889 crc32(tmp2, Address(in_out2, size*2+4), 4); 8890 addl(in_out2, 8); 8891 cmpl(in_out2, tmp3); 8892 jcc(Assembler::less, L_processPartition); 8893 8894 push(tmp3); 8895 push(in_out1); 8896 push(in_out2); 8897 tmp4 = tmp3; 8898 tmp5 = in_out1; 8899 n_tmp6 = in_out2; 8900 8901 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8902 w_xtmp1, w_xtmp2, w_xtmp3, 8903 tmp4, tmp5, 8904 n_tmp6); 8905 8906 pop(in_out2); 8907 pop(in_out1); 8908 pop(tmp3); 8909 8910 addl(in_out2, 2 * size); 8911 subl(in_out1, 3 * size); 8912 jmp(L_processPartitions); 8913 8914 bind(L_exit); 8915 } 8916 #endif //LP64 8917 8918 #ifdef _LP64 8919 // Algorithm 2: Pipelined usage of the CRC32 instruction. 8920 // Input: A buffer I of L bytes. 8921 // Output: the CRC32C value of the buffer. 8922 // Notations: 8923 // Write L = 24N + r, with N = floor (L/24). 8924 // r = L mod 24 (0 <= r < 24). 8925 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 8926 // N quadwords, and R consists of r bytes. 8927 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 8928 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 8929 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 8930 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 8931 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8932 Register tmp1, Register tmp2, Register tmp3, 8933 Register tmp4, Register tmp5, Register tmp6, 8934 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8935 bool is_pclmulqdq_supported) { 8936 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 8937 Label L_wordByWord; 8938 Label L_byteByByteProlog; 8939 Label L_byteByByte; 8940 Label L_exit; 8941 8942 if (is_pclmulqdq_supported ) { 8943 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8944 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 8945 8946 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8947 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8948 8949 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8950 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8951 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 8952 } else { 8953 const_or_pre_comp_const_index[0] = 1; 8954 const_or_pre_comp_const_index[1] = 0; 8955 8956 const_or_pre_comp_const_index[2] = 3; 8957 const_or_pre_comp_const_index[3] = 2; 8958 8959 const_or_pre_comp_const_index[4] = 5; 8960 const_or_pre_comp_const_index[5] = 4; 8961 } 8962 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8963 in2, in1, in_out, 8964 tmp1, tmp2, tmp3, 8965 w_xtmp1, w_xtmp2, w_xtmp3, 8966 tmp4, tmp5, 8967 tmp6); 8968 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8969 in2, in1, in_out, 8970 tmp1, tmp2, tmp3, 8971 w_xtmp1, w_xtmp2, w_xtmp3, 8972 tmp4, tmp5, 8973 tmp6); 8974 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8975 in2, in1, in_out, 8976 tmp1, tmp2, tmp3, 8977 w_xtmp1, w_xtmp2, w_xtmp3, 8978 tmp4, tmp5, 8979 tmp6); 8980 movl(tmp1, in2); 8981 andl(tmp1, 0x00000007); 8982 negl(tmp1); 8983 addl(tmp1, in2); 8984 addq(tmp1, in1); 8985 8986 BIND(L_wordByWord); 8987 cmpq(in1, tmp1); 8988 jcc(Assembler::greaterEqual, L_byteByByteProlog); 8989 crc32(in_out, Address(in1, 0), 4); 8990 addq(in1, 4); 8991 jmp(L_wordByWord); 8992 8993 BIND(L_byteByByteProlog); 8994 andl(in2, 0x00000007); 8995 movl(tmp2, 1); 8996 8997 BIND(L_byteByByte); 8998 cmpl(tmp2, in2); 8999 jccb(Assembler::greater, L_exit); 9000 crc32(in_out, Address(in1, 0), 1); 9001 incq(in1); 9002 incl(tmp2); 9003 jmp(L_byteByByte); 9004 9005 BIND(L_exit); 9006 } 9007 #else 9008 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 9009 Register tmp1, Register tmp2, Register tmp3, 9010 Register tmp4, Register tmp5, Register tmp6, 9011 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 9012 bool is_pclmulqdq_supported) { 9013 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 9014 Label L_wordByWord; 9015 Label L_byteByByteProlog; 9016 Label L_byteByByte; 9017 Label L_exit; 9018 9019 if (is_pclmulqdq_supported) { 9020 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 9021 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 9022 9023 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 9024 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 9025 9026 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 9027 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 9028 } else { 9029 const_or_pre_comp_const_index[0] = 1; 9030 const_or_pre_comp_const_index[1] = 0; 9031 9032 const_or_pre_comp_const_index[2] = 3; 9033 const_or_pre_comp_const_index[3] = 2; 9034 9035 const_or_pre_comp_const_index[4] = 5; 9036 const_or_pre_comp_const_index[5] = 4; 9037 } 9038 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 9039 in2, in1, in_out, 9040 tmp1, tmp2, tmp3, 9041 w_xtmp1, w_xtmp2, w_xtmp3, 9042 tmp4, tmp5, 9043 tmp6); 9044 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 9045 in2, in1, in_out, 9046 tmp1, tmp2, tmp3, 9047 w_xtmp1, w_xtmp2, w_xtmp3, 9048 tmp4, tmp5, 9049 tmp6); 9050 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 9051 in2, in1, in_out, 9052 tmp1, tmp2, tmp3, 9053 w_xtmp1, w_xtmp2, w_xtmp3, 9054 tmp4, tmp5, 9055 tmp6); 9056 movl(tmp1, in2); 9057 andl(tmp1, 0x00000007); 9058 negl(tmp1); 9059 addl(tmp1, in2); 9060 addl(tmp1, in1); 9061 9062 BIND(L_wordByWord); 9063 cmpl(in1, tmp1); 9064 jcc(Assembler::greaterEqual, L_byteByByteProlog); 9065 crc32(in_out, Address(in1,0), 4); 9066 addl(in1, 4); 9067 jmp(L_wordByWord); 9068 9069 BIND(L_byteByByteProlog); 9070 andl(in2, 0x00000007); 9071 movl(tmp2, 1); 9072 9073 BIND(L_byteByByte); 9074 cmpl(tmp2, in2); 9075 jccb(Assembler::greater, L_exit); 9076 movb(tmp1, Address(in1, 0)); 9077 crc32(in_out, tmp1, 1); 9078 incl(in1); 9079 incl(tmp2); 9080 jmp(L_byteByByte); 9081 9082 BIND(L_exit); 9083 } 9084 #endif // LP64 9085 #undef BIND 9086 #undef BLOCK_COMMENT 9087 9088 9089 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 9090 switch (cond) { 9091 // Note some conditions are synonyms for others 9092 case Assembler::zero: return Assembler::notZero; 9093 case Assembler::notZero: return Assembler::zero; 9094 case Assembler::less: return Assembler::greaterEqual; 9095 case Assembler::lessEqual: return Assembler::greater; 9096 case Assembler::greater: return Assembler::lessEqual; 9097 case Assembler::greaterEqual: return Assembler::less; 9098 case Assembler::below: return Assembler::aboveEqual; 9099 case Assembler::belowEqual: return Assembler::above; 9100 case Assembler::above: return Assembler::belowEqual; 9101 case Assembler::aboveEqual: return Assembler::below; 9102 case Assembler::overflow: return Assembler::noOverflow; 9103 case Assembler::noOverflow: return Assembler::overflow; 9104 case Assembler::negative: return Assembler::positive; 9105 case Assembler::positive: return Assembler::negative; 9106 case Assembler::parity: return Assembler::noParity; 9107 case Assembler::noParity: return Assembler::parity; 9108 } 9109 ShouldNotReachHere(); return Assembler::overflow; 9110 } 9111 9112 SkipIfEqual::SkipIfEqual( 9113 MacroAssembler* masm, const bool* flag_addr, bool value) { 9114 _masm = masm; 9115 _masm->cmp8(ExternalAddress((address)flag_addr), value); 9116 _masm->jcc(Assembler::equal, _label); 9117 } 9118 9119 SkipIfEqual::~SkipIfEqual() { 9120 _masm->bind(_label); 9121 } 9122 9123 // 32-bit Windows has its own fast-path implementation 9124 // of get_thread 9125 #if !defined(WIN32) || defined(_LP64) 9126 9127 // This is simply a call to Thread::current() 9128 void MacroAssembler::get_thread(Register thread) { 9129 if (thread != rax) { 9130 push(rax); 9131 } 9132 LP64_ONLY(push(rdi);) 9133 LP64_ONLY(push(rsi);) 9134 push(rdx); 9135 push(rcx); 9136 LP64_ONLY(push(r8);) 9137 LP64_ONLY(push(r9);) 9138 LP64_ONLY(push(r10);) 9139 LP64_ONLY(push(r11);) 9140 9141 call(RuntimeAddress(CAST_FROM_FN_PTR(address, Thread::current))); 9142 9143 LP64_ONLY(pop(r11);) 9144 LP64_ONLY(pop(r10);) 9145 LP64_ONLY(pop(r9);) 9146 LP64_ONLY(pop(r8);) 9147 pop(rcx); 9148 pop(rdx); 9149 LP64_ONLY(pop(rsi);) 9150 LP64_ONLY(pop(rdi);) 9151 if (thread != rax) { 9152 mov(thread, rax); 9153 pop(rax); 9154 } 9155 } 9156 9157 #endif