src/hotspot/cpu/arm/macroAssembler_arm.cpp

*** 1655,1666 ****
  #ifdef AARCH64
  
  // Serializes memory.
  // tmp register is not used on AArch64, this parameter is provided solely for better compatibility with 32-bit ARM
  void MacroAssembler::membar(Membar_mask_bits order_constraint, Register tmp) {
-   if (!os::is_MP()) return;
- 
    // TODO-AARCH64 investigate dsb vs dmb effects
    if (order_constraint == StoreStore) {
      dmb(DMB_st);
    } else if ((order_constraint & ~(LoadLoad | LoadStore)) == 0) {
      dmb(DMB_ld);
--- 1655,1664 ----
*** 1677,1687 ****
  // load_tgt is an ordered load target in a LoadStore case only, to create dependency between the load operation and conditional branch. Optional.
  void MacroAssembler::membar(Membar_mask_bits order_constraint,
                              Register tmp,
                              bool preserve_flags,
                              Register load_tgt) {
-   if (!os::is_MP()) return;
  
    if (order_constraint == StoreStore) {
      dmb(DMB_st, tmp);
    } else if ((order_constraint & StoreLoad)  ||
               (order_constraint & LoadLoad)   ||
--- 1675,1684 ----