1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableBarrierSet.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "nativeInst_x86.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "vmreg_x86.inline.hpp"
  44 
  45 
  46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  47 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  48 // fast versions of NegF/NegD and AbsF/AbsD.
  49 
  50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  52   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  53   // of 128-bits operands for SSE instructions.
  54   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  55   // Store the value to a 128-bits operand.
  56   operand[0] = lo;
  57   operand[1] = hi;
  58   return operand;
  59 }
  60 
  61 // Buffer for 128-bits masks used by SSE instructions.
  62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  63 
  64 // Static initialization during VM startup.
  65 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  67 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  69 
  70 
  71 
  72 NEEDS_CLEANUP // remove this definitions ?
  73 const Register IC_Klass    = rax;   // where the IC klass is cached
  74 const Register SYNC_header = rax;   // synchronization header
  75 const Register SHIFT_count = rcx;   // where count for shift operations must be
  76 
  77 #define __ _masm->
  78 
  79 
  80 static void select_different_registers(Register preserve,
  81                                        Register extra,
  82                                        Register &tmp1,
  83                                        Register &tmp2) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, extra);
  89     tmp2 = extra;
  90   }
  91   assert_different_registers(preserve, tmp1, tmp2);
  92 }
  93 
  94 
  95 
  96 static void select_different_registers(Register preserve,
  97                                        Register extra,
  98                                        Register &tmp1,
  99                                        Register &tmp2,
 100                                        Register &tmp3) {
 101   if (tmp1 == preserve) {
 102     assert_different_registers(tmp1, tmp2, tmp3, extra);
 103     tmp1 = extra;
 104   } else if (tmp2 == preserve) {
 105     assert_different_registers(tmp1, tmp2, tmp3, extra);
 106     tmp2 = extra;
 107   } else if (tmp3 == preserve) {
 108     assert_different_registers(tmp1, tmp2, tmp3, extra);
 109     tmp3 = extra;
 110   }
 111   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 112 }
 113 
 114 
 115 
 116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 117   if (opr->is_constant()) {
 118     LIR_Const* constant = opr->as_constant_ptr();
 119     switch (constant->type()) {
 120       case T_INT: {
 121         return true;
 122       }
 123 
 124       default:
 125         return false;
 126     }
 127   }
 128   return false;
 129 }
 130 
 131 
 132 LIR_Opr LIR_Assembler::receiverOpr() {
 133   return FrameMap::receiver_opr;
 134 }
 135 
 136 LIR_Opr LIR_Assembler::osrBufferPointer() {
 137   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 138 }
 139 
 140 //--------------fpu register translations-----------------------
 141 
 142 
 143 address LIR_Assembler::float_constant(float f) {
 144   address const_addr = __ float_constant(f);
 145   if (const_addr == NULL) {
 146     bailout("const section overflow");
 147     return __ code()->consts()->start();
 148   } else {
 149     return const_addr;
 150   }
 151 }
 152 
 153 
 154 address LIR_Assembler::double_constant(double d) {
 155   address const_addr = __ double_constant(d);
 156   if (const_addr == NULL) {
 157     bailout("const section overflow");
 158     return __ code()->consts()->start();
 159   } else {
 160     return const_addr;
 161   }
 162 }
 163 
 164 
 165 void LIR_Assembler::set_24bit_FPU() {
 166   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 167 }
 168 
 169 void LIR_Assembler::reset_FPU() {
 170   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 171 }
 172 
 173 void LIR_Assembler::fpop() {
 174   __ fpop();
 175 }
 176 
 177 void LIR_Assembler::fxch(int i) {
 178   __ fxch(i);
 179 }
 180 
 181 void LIR_Assembler::fld(int i) {
 182   __ fld_s(i);
 183 }
 184 
 185 void LIR_Assembler::ffree(int i) {
 186   __ ffree(i);
 187 }
 188 
 189 void LIR_Assembler::breakpoint() {
 190   __ int3();
 191 }
 192 
 193 void LIR_Assembler::push(LIR_Opr opr) {
 194   if (opr->is_single_cpu()) {
 195     __ push_reg(opr->as_register());
 196   } else if (opr->is_double_cpu()) {
 197     NOT_LP64(__ push_reg(opr->as_register_hi()));
 198     __ push_reg(opr->as_register_lo());
 199   } else if (opr->is_stack()) {
 200     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 201   } else if (opr->is_constant()) {
 202     LIR_Const* const_opr = opr->as_constant_ptr();
 203     if (const_opr->type() == T_OBJECT) {
 204       __ push_oop(const_opr->as_jobject());
 205     } else if (const_opr->type() == T_INT) {
 206       __ push_jint(const_opr->as_jint());
 207     } else {
 208       ShouldNotReachHere();
 209     }
 210 
 211   } else {
 212     ShouldNotReachHere();
 213   }
 214 }
 215 
 216 void LIR_Assembler::pop(LIR_Opr opr) {
 217   if (opr->is_single_cpu()) {
 218     __ pop_reg(opr->as_register());
 219   } else {
 220     ShouldNotReachHere();
 221   }
 222 }
 223 
 224 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 225   return addr->base()->is_illegal() && addr->index()->is_illegal();
 226 }
 227 
 228 //-------------------------------------------
 229 
 230 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 231   return as_Address(addr, rscratch1);
 232 }
 233 
 234 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 235   if (addr->base()->is_illegal()) {
 236     assert(addr->index()->is_illegal(), "must be illegal too");
 237     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 238     if (! __ reachable(laddr)) {
 239       __ movptr(tmp, laddr.addr());
 240       Address res(tmp, 0);
 241       return res;
 242     } else {
 243       return __ as_Address(laddr);
 244     }
 245   }
 246 
 247   Register base = addr->base()->as_pointer_register();
 248 
 249   if (addr->index()->is_illegal()) {
 250     return Address( base, addr->disp());
 251   } else if (addr->index()->is_cpu_register()) {
 252     Register index = addr->index()->as_pointer_register();
 253     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 254   } else if (addr->index()->is_constant()) {
 255     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 256     assert(Assembler::is_simm32(addr_offset), "must be");
 257 
 258     return Address(base, addr_offset);
 259   } else {
 260     Unimplemented();
 261     return Address();
 262   }
 263 }
 264 
 265 
 266 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 267   Address base = as_Address(addr);
 268   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 269 }
 270 
 271 
 272 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 273   return as_Address(addr);
 274 }
 275 
 276 
 277 void LIR_Assembler::osr_entry() {
 278   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 279   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 280   ValueStack* entry_state = osr_entry->state();
 281   int number_of_locks = entry_state->locks_size();
 282 
 283   // we jump here if osr happens with the interpreter
 284   // state set up to continue at the beginning of the
 285   // loop that triggered osr - in particular, we have
 286   // the following registers setup:
 287   //
 288   // rcx: osr buffer
 289   //
 290 
 291   // build frame
 292   ciMethod* m = compilation()->method();
 293   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 294 
 295   // OSR buffer is
 296   //
 297   // locals[nlocals-1..0]
 298   // monitors[0..number_of_locks]
 299   //
 300   // locals is a direct copy of the interpreter frame so in the osr buffer
 301   // so first slot in the local array is the last local from the interpreter
 302   // and last slot is local[0] (receiver) from the interpreter
 303   //
 304   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 305   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 306   // in the interpreter frame (the method lock if a sync method)
 307 
 308   // Initialize monitors in the compiled activation.
 309   //   rcx: pointer to osr buffer
 310   //
 311   // All other registers are dead at this point and the locals will be
 312   // copied into place by code emitted in the IR.
 313 
 314   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 315   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 316     int monitor_offset = BytesPerWord * method()->max_locals() +
 317       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 318     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 319     // the OSR buffer using 2 word entries: first the lock and then
 320     // the oop.
 321     for (int i = 0; i < number_of_locks; i++) {
 322       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 323 #ifdef ASSERT
 324       // verify the interpreter's monitor has a non-null object
 325       {
 326         Label L;
 327         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 328         __ jcc(Assembler::notZero, L);
 329         __ stop("locked object is NULL");
 330         __ bind(L);
 331       }
 332 #endif
 333       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 334       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 335       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 336       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 337     }
 338   }
 339 }
 340 
 341 
 342 // inline cache check; done before the frame is built.
 343 int LIR_Assembler::check_icache() {
 344   Register receiver = FrameMap::receiver_opr->as_register();
 345   Register ic_klass = IC_Klass;
 346   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 347   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 348   if (!do_post_padding) {
 349     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 350     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 351   }
 352   int offset = __ offset();
 353   __ inline_cache_check(receiver, IC_Klass);
 354   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 355   if (do_post_padding) {
 356     // force alignment after the cache check.
 357     // It's been verified to be aligned if !VerifyOops
 358     __ align(CodeEntryAlignment);
 359   }
 360   return offset;
 361 }
 362 
 363 
 364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 365   jobject o = NULL;
 366   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 367   __ movoop(reg, o);
 368   patching_epilog(patch, lir_patch_normal, reg, info);
 369 }
 370 
 371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 372   Metadata* o = NULL;
 373   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 374   __ mov_metadata(reg, o);
 375   patching_epilog(patch, lir_patch_normal, reg, info);
 376 }
 377 
 378 // This specifies the rsp decrement needed to build the frame
 379 int LIR_Assembler::initial_frame_size_in_bytes() const {
 380   // if rounding, must let FrameMap know!
 381 
 382   // The frame_map records size in slots (32bit word)
 383 
 384   // subtract two words to account for return address and link
 385   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 386 }
 387 
 388 
 389 int LIR_Assembler::emit_exception_handler() {
 390   // if the last instruction is a call (typically to do a throw which
 391   // is coming at the end after block reordering) the return address
 392   // must still point into the code area in order to avoid assertion
 393   // failures when searching for the corresponding bci => add a nop
 394   // (was bug 5/14/1999 - gri)
 395   __ nop();
 396 
 397   // generate code for exception handler
 398   address handler_base = __ start_a_stub(exception_handler_size());
 399   if (handler_base == NULL) {
 400     // not enough space left for the handler
 401     bailout("exception handler overflow");
 402     return -1;
 403   }
 404 
 405   int offset = code_offset();
 406 
 407   // the exception oop and pc are in rax, and rdx
 408   // no other registers need to be preserved, so invalidate them
 409   __ invalidate_registers(false, true, true, false, true, true);
 410 
 411   // check that there is really an exception
 412   __ verify_not_null_oop(rax);
 413 
 414   // search an exception handler (rax: exception oop, rdx: throwing pc)
 415   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 416   __ should_not_reach_here();
 417   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 418   __ end_a_stub();
 419 
 420   return offset;
 421 }
 422 
 423 
 424 // Emit the code to remove the frame from the stack in the exception
 425 // unwind path.
 426 int LIR_Assembler::emit_unwind_handler() {
 427 #ifndef PRODUCT
 428   if (CommentedAssembly) {
 429     _masm->block_comment("Unwind handler");
 430   }
 431 #endif
 432 
 433   int offset = code_offset();
 434 
 435   // Fetch the exception from TLS and clear out exception related thread state
 436   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 437   NOT_LP64(__ get_thread(rsi));
 438   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 439   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 440   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 441 
 442   __ bind(_unwind_handler_entry);
 443   __ verify_not_null_oop(rax);
 444   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 445     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 446   }
 447 
 448   // Preform needed unlocking
 449   MonitorExitStub* stub = NULL;
 450   if (method()->is_synchronized()) {
 451     monitor_address(0, FrameMap::rax_opr);
 452     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 453     __ unlock_object(rdi, rsi, rax, *stub->entry());
 454     __ bind(*stub->continuation());
 455   }
 456 
 457   if (compilation()->env()->dtrace_method_probes()) {
 458 #ifdef _LP64
 459     __ mov(rdi, r15_thread);
 460     __ mov_metadata(rsi, method()->constant_encoding());
 461 #else
 462     __ get_thread(rax);
 463     __ movptr(Address(rsp, 0), rax);
 464     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 465 #endif
 466     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 467   }
 468 
 469   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 470     __ mov(rax, rbx);  // Restore the exception
 471   }
 472 
 473   // remove the activation and dispatch to the unwind handler
 474   __ remove_frame(initial_frame_size_in_bytes());
 475   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 476 
 477   // Emit the slow path assembly
 478   if (stub != NULL) {
 479     stub->emit_code(this);
 480   }
 481 
 482   return offset;
 483 }
 484 
 485 
 486 int LIR_Assembler::emit_deopt_handler() {
 487   // if the last instruction is a call (typically to do a throw which
 488   // is coming at the end after block reordering) the return address
 489   // must still point into the code area in order to avoid assertion
 490   // failures when searching for the corresponding bci => add a nop
 491   // (was bug 5/14/1999 - gri)
 492   __ nop();
 493 
 494   // generate code for exception handler
 495   address handler_base = __ start_a_stub(deopt_handler_size());
 496   if (handler_base == NULL) {
 497     // not enough space left for the handler
 498     bailout("deopt handler overflow");
 499     return -1;
 500   }
 501 
 502   int offset = code_offset();
 503   InternalAddress here(__ pc());
 504 
 505   __ pushptr(here.addr());
 506   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 507   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 508   __ end_a_stub();
 509 
 510   return offset;
 511 }
 512 
 513 
 514 void LIR_Assembler::return_op(LIR_Opr result) {
 515   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 516   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 517     assert(result->fpu() == 0, "result must already be on TOS");
 518   }
 519 
 520   // Pop the stack before the safepoint code
 521   __ remove_frame(initial_frame_size_in_bytes());
 522 
 523   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 524     __ reserved_stack_check();
 525   }
 526 
 527   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 528 
 529   // Note: we do not need to round double result; float result has the right precision
 530   // the poll sets the condition code, but no data registers
 531 
 532   if (SafepointMechanism::uses_thread_local_poll()) {
 533 #ifdef _LP64
 534     const Register poll_addr = rscratch1;
 535     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 536 #else
 537     const Register poll_addr = rbx;
 538     assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
 539     __ get_thread(poll_addr);
 540     __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
 541 #endif
 542     __ relocate(relocInfo::poll_return_type);
 543     __ testl(rax, Address(poll_addr, 0));
 544   } else {
 545     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
 546 
 547     if (Assembler::is_polling_page_far()) {
 548       __ lea(rscratch1, polling_page);
 549       __ relocate(relocInfo::poll_return_type);
 550       __ testl(rax, Address(rscratch1, 0));
 551     } else {
 552       __ testl(rax, polling_page);
 553     }
 554   }
 555   __ ret(0);
 556 }
 557 
 558 
 559 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 560   guarantee(info != NULL, "Shouldn't be NULL");
 561   int offset = __ offset();
 562   if (SafepointMechanism::uses_thread_local_poll()) {
 563 #ifdef _LP64
 564     const Register poll_addr = rscratch1;
 565     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 566 #else
 567     assert(tmp->is_cpu_register(), "needed");
 568     const Register poll_addr = tmp->as_register();
 569     __ get_thread(poll_addr);
 570     __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
 571 #endif
 572     add_debug_info_for_branch(info);
 573     __ relocate(relocInfo::poll_type);
 574     address pre_pc = __ pc();
 575     __ testl(rax, Address(poll_addr, 0));
 576     address post_pc = __ pc();
 577     guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 578   } else {
 579     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
 580     if (Assembler::is_polling_page_far()) {
 581       __ lea(rscratch1, polling_page);
 582       offset = __ offset();
 583       add_debug_info_for_branch(info);
 584       __ relocate(relocInfo::poll_type);
 585       __ testl(rax, Address(rscratch1, 0));
 586     } else {
 587       add_debug_info_for_branch(info);
 588       __ testl(rax, polling_page);
 589     }
 590   }
 591   return offset;
 592 }
 593 
 594 
 595 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 596   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 597 }
 598 
 599 void LIR_Assembler::swap_reg(Register a, Register b) {
 600   __ xchgptr(a, b);
 601 }
 602 
 603 
 604 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 605   assert(src->is_constant(), "should not call otherwise");
 606   assert(dest->is_register(), "should not call otherwise");
 607   LIR_Const* c = src->as_constant_ptr();
 608 
 609   switch (c->type()) {
 610     case T_INT: {
 611       assert(patch_code == lir_patch_none, "no patching handled here");
 612       __ movl(dest->as_register(), c->as_jint());
 613       break;
 614     }
 615 
 616     case T_ADDRESS: {
 617       assert(patch_code == lir_patch_none, "no patching handled here");
 618       __ movptr(dest->as_register(), c->as_jint());
 619       break;
 620     }
 621 
 622     case T_LONG: {
 623       assert(patch_code == lir_patch_none, "no patching handled here");
 624 #ifdef _LP64
 625       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 626 #else
 627       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 628       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 629 #endif // _LP64
 630       break;
 631     }
 632 
 633     case T_OBJECT: {
 634       if (patch_code != lir_patch_none) {
 635         jobject2reg_with_patching(dest->as_register(), info);
 636       } else {
 637         __ movoop(dest->as_register(), c->as_jobject());
 638       }
 639       break;
 640     }
 641 
 642     case T_METADATA: {
 643       if (patch_code != lir_patch_none) {
 644         klass2reg_with_patching(dest->as_register(), info);
 645       } else {
 646         __ mov_metadata(dest->as_register(), c->as_metadata());
 647       }
 648       break;
 649     }
 650 
 651     case T_FLOAT: {
 652       if (dest->is_single_xmm()) {
 653         if (c->is_zero_float()) {
 654           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 655         } else {
 656           __ movflt(dest->as_xmm_float_reg(),
 657                    InternalAddress(float_constant(c->as_jfloat())));
 658         }
 659       } else {
 660         assert(dest->is_single_fpu(), "must be");
 661         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 662         if (c->is_zero_float()) {
 663           __ fldz();
 664         } else if (c->is_one_float()) {
 665           __ fld1();
 666         } else {
 667           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 668         }
 669       }
 670       break;
 671     }
 672 
 673     case T_DOUBLE: {
 674       if (dest->is_double_xmm()) {
 675         if (c->is_zero_double()) {
 676           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 677         } else {
 678           __ movdbl(dest->as_xmm_double_reg(),
 679                     InternalAddress(double_constant(c->as_jdouble())));
 680         }
 681       } else {
 682         assert(dest->is_double_fpu(), "must be");
 683         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 684         if (c->is_zero_double()) {
 685           __ fldz();
 686         } else if (c->is_one_double()) {
 687           __ fld1();
 688         } else {
 689           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 690         }
 691       }
 692       break;
 693     }
 694 
 695     default:
 696       ShouldNotReachHere();
 697   }
 698 }
 699 
 700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 701   assert(src->is_constant(), "should not call otherwise");
 702   assert(dest->is_stack(), "should not call otherwise");
 703   LIR_Const* c = src->as_constant_ptr();
 704 
 705   switch (c->type()) {
 706     case T_INT:  // fall through
 707     case T_FLOAT:
 708       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 709       break;
 710 
 711     case T_ADDRESS:
 712       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 713       break;
 714 
 715     case T_OBJECT:
 716       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 717       break;
 718 
 719     case T_LONG:  // fall through
 720     case T_DOUBLE:
 721 #ifdef _LP64
 722       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 723                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 724 #else
 725       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 726                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 727       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 728                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 729 #endif // _LP64
 730       break;
 731 
 732     default:
 733       ShouldNotReachHere();
 734   }
 735 }
 736 
 737 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 738   assert(src->is_constant(), "should not call otherwise");
 739   assert(dest->is_address(), "should not call otherwise");
 740   LIR_Const* c = src->as_constant_ptr();
 741   LIR_Address* addr = dest->as_address_ptr();
 742 
 743   int null_check_here = code_offset();
 744   switch (type) {
 745     case T_INT:    // fall through
 746     case T_FLOAT:
 747       __ movl(as_Address(addr), c->as_jint_bits());
 748       break;
 749 
 750     case T_ADDRESS:
 751       __ movptr(as_Address(addr), c->as_jint_bits());
 752       break;
 753 
 754     case T_OBJECT:  // fall through
 755     case T_ARRAY:
 756       if (c->as_jobject() == NULL) {
 757         if (UseCompressedOops && !wide) {
 758           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 759         } else {
 760 #ifdef _LP64
 761           __ xorptr(rscratch1, rscratch1);
 762           null_check_here = code_offset();
 763           __ movptr(as_Address(addr), rscratch1);
 764 #else
 765           __ movptr(as_Address(addr), NULL_WORD);
 766 #endif
 767         }
 768       } else {
 769         if (is_literal_address(addr)) {
 770           ShouldNotReachHere();
 771           __ movoop(as_Address(addr, noreg), c->as_jobject());
 772         } else {
 773 #ifdef _LP64
 774           __ movoop(rscratch1, c->as_jobject());
 775           if (UseCompressedOops && !wide) {
 776             __ encode_heap_oop(rscratch1);
 777             null_check_here = code_offset();
 778             __ movl(as_Address_lo(addr), rscratch1);
 779           } else {
 780             null_check_here = code_offset();
 781             __ movptr(as_Address_lo(addr), rscratch1);
 782           }
 783 #else
 784           __ movoop(as_Address(addr), c->as_jobject());
 785 #endif
 786         }
 787       }
 788       break;
 789 
 790     case T_LONG:    // fall through
 791     case T_DOUBLE:
 792 #ifdef _LP64
 793       if (is_literal_address(addr)) {
 794         ShouldNotReachHere();
 795         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 796       } else {
 797         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 798         null_check_here = code_offset();
 799         __ movptr(as_Address_lo(addr), r10);
 800       }
 801 #else
 802       // Always reachable in 32bit so this doesn't produce useless move literal
 803       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 804       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 805 #endif // _LP64
 806       break;
 807 
 808     case T_BOOLEAN: // fall through
 809     case T_BYTE:
 810       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 811       break;
 812 
 813     case T_CHAR:    // fall through
 814     case T_SHORT:
 815       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 816       break;
 817 
 818     default:
 819       ShouldNotReachHere();
 820   };
 821 
 822   if (info != NULL) {
 823     add_debug_info_for_null_check(null_check_here, info);
 824   }
 825 }
 826 
 827 
 828 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 829   assert(src->is_register(), "should not call otherwise");
 830   assert(dest->is_register(), "should not call otherwise");
 831 
 832   // move between cpu-registers
 833   if (dest->is_single_cpu()) {
 834 #ifdef _LP64
 835     if (src->type() == T_LONG) {
 836       // Can do LONG -> OBJECT
 837       move_regs(src->as_register_lo(), dest->as_register());
 838       return;
 839     }
 840 #endif
 841     assert(src->is_single_cpu(), "must match");
 842     if (src->type() == T_OBJECT) {
 843       __ verify_oop(src->as_register());
 844     }
 845     move_regs(src->as_register(), dest->as_register());
 846 
 847   } else if (dest->is_double_cpu()) {
 848 #ifdef _LP64
 849     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 850       // Surprising to me but we can see move of a long to t_object
 851       __ verify_oop(src->as_register());
 852       move_regs(src->as_register(), dest->as_register_lo());
 853       return;
 854     }
 855 #endif
 856     assert(src->is_double_cpu(), "must match");
 857     Register f_lo = src->as_register_lo();
 858     Register f_hi = src->as_register_hi();
 859     Register t_lo = dest->as_register_lo();
 860     Register t_hi = dest->as_register_hi();
 861 #ifdef _LP64
 862     assert(f_hi == f_lo, "must be same");
 863     assert(t_hi == t_lo, "must be same");
 864     move_regs(f_lo, t_lo);
 865 #else
 866     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 867 
 868 
 869     if (f_lo == t_hi && f_hi == t_lo) {
 870       swap_reg(f_lo, f_hi);
 871     } else if (f_hi == t_lo) {
 872       assert(f_lo != t_hi, "overwriting register");
 873       move_regs(f_hi, t_hi);
 874       move_regs(f_lo, t_lo);
 875     } else {
 876       assert(f_hi != t_lo, "overwriting register");
 877       move_regs(f_lo, t_lo);
 878       move_regs(f_hi, t_hi);
 879     }
 880 #endif // LP64
 881 
 882     // special moves from fpu-register to xmm-register
 883     // necessary for method results
 884   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 885     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 886     __ fld_s(Address(rsp, 0));
 887   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 888     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 889     __ fld_d(Address(rsp, 0));
 890   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 891     __ fstp_s(Address(rsp, 0));
 892     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 893   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 894     __ fstp_d(Address(rsp, 0));
 895     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 896 
 897     // move between xmm-registers
 898   } else if (dest->is_single_xmm()) {
 899     assert(src->is_single_xmm(), "must match");
 900     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 901   } else if (dest->is_double_xmm()) {
 902     assert(src->is_double_xmm(), "must match");
 903     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 904 
 905     // move between fpu-registers (no instruction necessary because of fpu-stack)
 906   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 907     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 908     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 909   } else {
 910     ShouldNotReachHere();
 911   }
 912 }
 913 
 914 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 915   assert(src->is_register(), "should not call otherwise");
 916   assert(dest->is_stack(), "should not call otherwise");
 917 
 918   if (src->is_single_cpu()) {
 919     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 920     if (type == T_OBJECT || type == T_ARRAY) {
 921       __ verify_oop(src->as_register());
 922       __ movptr (dst, src->as_register());
 923     } else if (type == T_METADATA) {
 924       __ movptr (dst, src->as_register());
 925     } else {
 926       __ movl (dst, src->as_register());
 927     }
 928 
 929   } else if (src->is_double_cpu()) {
 930     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 931     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 932     __ movptr (dstLO, src->as_register_lo());
 933     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 934 
 935   } else if (src->is_single_xmm()) {
 936     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 937     __ movflt(dst_addr, src->as_xmm_float_reg());
 938 
 939   } else if (src->is_double_xmm()) {
 940     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 941     __ movdbl(dst_addr, src->as_xmm_double_reg());
 942 
 943   } else if (src->is_single_fpu()) {
 944     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 945     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 946     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 947     else                   __ fst_s  (dst_addr);
 948 
 949   } else if (src->is_double_fpu()) {
 950     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 951     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 952     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 953     else                   __ fst_d  (dst_addr);
 954 
 955   } else {
 956     ShouldNotReachHere();
 957   }
 958 }
 959 
 960 
 961 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 962   LIR_Address* to_addr = dest->as_address_ptr();
 963   PatchingStub* patch = NULL;
 964   Register compressed_src = rscratch1;
 965 
 966   if (type == T_ARRAY || type == T_OBJECT) {
 967     __ verify_oop(src->as_register());
 968 #ifdef _LP64
 969     if (UseCompressedOops && !wide) {
 970       __ movptr(compressed_src, src->as_register());
 971       __ encode_heap_oop(compressed_src);
 972       if (patch_code != lir_patch_none) {
 973         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 974       }
 975     }
 976 #endif
 977   }
 978 
 979   if (patch_code != lir_patch_none) {
 980     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 981     Address toa = as_Address(to_addr);
 982     assert(toa.disp() != 0, "must have");
 983   }
 984 
 985   int null_check_here = code_offset();
 986   switch (type) {
 987     case T_FLOAT: {
 988       if (src->is_single_xmm()) {
 989         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 990       } else {
 991         assert(src->is_single_fpu(), "must be");
 992         assert(src->fpu_regnr() == 0, "argument must be on TOS");
 993         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
 994         else                    __ fst_s (as_Address(to_addr));
 995       }
 996       break;
 997     }
 998 
 999     case T_DOUBLE: {
1000       if (src->is_double_xmm()) {
1001         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1002       } else {
1003         assert(src->is_double_fpu(), "must be");
1004         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1005         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1006         else                    __ fst_d (as_Address(to_addr));
1007       }
1008       break;
1009     }
1010 
1011     case T_ARRAY:   // fall through
1012     case T_OBJECT:  // fall through
1013       if (UseCompressedOops && !wide) {
1014         __ movl(as_Address(to_addr), compressed_src);
1015       } else {
1016         __ movptr(as_Address(to_addr), src->as_register());
1017       }
1018       break;
1019     case T_METADATA:
1020       // We get here to store a method pointer to the stack to pass to
1021       // a dtrace runtime call. This can't work on 64 bit with
1022       // compressed klass ptrs: T_METADATA can be a compressed klass
1023       // ptr or a 64 bit method pointer.
1024       LP64_ONLY(ShouldNotReachHere());
1025       __ movptr(as_Address(to_addr), src->as_register());
1026       break;
1027     case T_ADDRESS:
1028       __ movptr(as_Address(to_addr), src->as_register());
1029       break;
1030     case T_INT:
1031       __ movl(as_Address(to_addr), src->as_register());
1032       break;
1033 
1034     case T_LONG: {
1035       Register from_lo = src->as_register_lo();
1036       Register from_hi = src->as_register_hi();
1037 #ifdef _LP64
1038       __ movptr(as_Address_lo(to_addr), from_lo);
1039 #else
1040       Register base = to_addr->base()->as_register();
1041       Register index = noreg;
1042       if (to_addr->index()->is_register()) {
1043         index = to_addr->index()->as_register();
1044       }
1045       if (base == from_lo || index == from_lo) {
1046         assert(base != from_hi, "can't be");
1047         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1048         __ movl(as_Address_hi(to_addr), from_hi);
1049         if (patch != NULL) {
1050           patching_epilog(patch, lir_patch_high, base, info);
1051           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1052           patch_code = lir_patch_low;
1053         }
1054         __ movl(as_Address_lo(to_addr), from_lo);
1055       } else {
1056         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1057         __ movl(as_Address_lo(to_addr), from_lo);
1058         if (patch != NULL) {
1059           patching_epilog(patch, lir_patch_low, base, info);
1060           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1061           patch_code = lir_patch_high;
1062         }
1063         __ movl(as_Address_hi(to_addr), from_hi);
1064       }
1065 #endif // _LP64
1066       break;
1067     }
1068 
1069     case T_BYTE:    // fall through
1070     case T_BOOLEAN: {
1071       Register src_reg = src->as_register();
1072       Address dst_addr = as_Address(to_addr);
1073       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1074       __ movb(dst_addr, src_reg);
1075       break;
1076     }
1077 
1078     case T_CHAR:    // fall through
1079     case T_SHORT:
1080       __ movw(as_Address(to_addr), src->as_register());
1081       break;
1082 
1083     default:
1084       ShouldNotReachHere();
1085   }
1086   if (info != NULL) {
1087     add_debug_info_for_null_check(null_check_here, info);
1088   }
1089 
1090   if (patch_code != lir_patch_none) {
1091     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1092   }
1093 }
1094 
1095 
1096 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1097   assert(src->is_stack(), "should not call otherwise");
1098   assert(dest->is_register(), "should not call otherwise");
1099 
1100   if (dest->is_single_cpu()) {
1101     if (type == T_ARRAY || type == T_OBJECT) {
1102       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1103       __ verify_oop(dest->as_register());
1104     } else if (type == T_METADATA) {
1105       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1106     } else {
1107       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1108     }
1109 
1110   } else if (dest->is_double_cpu()) {
1111     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1112     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1113     __ movptr(dest->as_register_lo(), src_addr_LO);
1114     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1115 
1116   } else if (dest->is_single_xmm()) {
1117     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1118     __ movflt(dest->as_xmm_float_reg(), src_addr);
1119 
1120   } else if (dest->is_double_xmm()) {
1121     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1122     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1123 
1124   } else if (dest->is_single_fpu()) {
1125     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1126     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1127     __ fld_s(src_addr);
1128 
1129   } else if (dest->is_double_fpu()) {
1130     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1131     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1132     __ fld_d(src_addr);
1133 
1134   } else {
1135     ShouldNotReachHere();
1136   }
1137 }
1138 
1139 
1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1141   if (src->is_single_stack()) {
1142     if (type == T_OBJECT || type == T_ARRAY) {
1143       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1144       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1145     } else {
1146 #ifndef _LP64
1147       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1148       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1149 #else
1150       //no pushl on 64bits
1151       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1152       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1153 #endif
1154     }
1155 
1156   } else if (src->is_double_stack()) {
1157 #ifdef _LP64
1158     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1159     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1160 #else
1161     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1162     // push and pop the part at src + wordSize, adding wordSize for the previous push
1163     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1164     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1165     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1166 #endif // _LP64
1167 
1168   } else {
1169     ShouldNotReachHere();
1170   }
1171 }
1172 
1173 
1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1175   assert(src->is_address(), "should not call otherwise");
1176   assert(dest->is_register(), "should not call otherwise");
1177 
1178   LIR_Address* addr = src->as_address_ptr();
1179   Address from_addr = as_Address(addr);
1180 
1181   if (addr->base()->type() == T_OBJECT) {
1182     __ verify_oop(addr->base()->as_pointer_register());
1183   }
1184 
1185   switch (type) {
1186     case T_BOOLEAN: // fall through
1187     case T_BYTE:    // fall through
1188     case T_CHAR:    // fall through
1189     case T_SHORT:
1190       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1191         // on pre P6 processors we may get partial register stalls
1192         // so blow away the value of to_rinfo before loading a
1193         // partial word into it.  Do it here so that it precedes
1194         // the potential patch point below.
1195         __ xorptr(dest->as_register(), dest->as_register());
1196       }
1197       break;
1198    default:
1199      break;
1200   }
1201 
1202   PatchingStub* patch = NULL;
1203   if (patch_code != lir_patch_none) {
1204     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1205     assert(from_addr.disp() != 0, "must have");
1206   }
1207   if (info != NULL) {
1208     add_debug_info_for_null_check_here(info);
1209   }
1210 
1211   switch (type) {
1212     case T_FLOAT: {
1213       if (dest->is_single_xmm()) {
1214         __ movflt(dest->as_xmm_float_reg(), from_addr);
1215       } else {
1216         assert(dest->is_single_fpu(), "must be");
1217         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1218         __ fld_s(from_addr);
1219       }
1220       break;
1221     }
1222 
1223     case T_DOUBLE: {
1224       if (dest->is_double_xmm()) {
1225         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1226       } else {
1227         assert(dest->is_double_fpu(), "must be");
1228         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1229         __ fld_d(from_addr);
1230       }
1231       break;
1232     }
1233 
1234     case T_OBJECT:  // fall through
1235     case T_ARRAY:   // fall through
1236       if (UseCompressedOops && !wide) {
1237         __ movl(dest->as_register(), from_addr);
1238       } else {
1239         __ movptr(dest->as_register(), from_addr);
1240       }
1241       break;
1242 
1243     case T_ADDRESS:
1244       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1245         __ movl(dest->as_register(), from_addr);
1246       } else {
1247         __ movptr(dest->as_register(), from_addr);
1248       }
1249       break;
1250     case T_INT:
1251       __ movl(dest->as_register(), from_addr);
1252       break;
1253 
1254     case T_LONG: {
1255       Register to_lo = dest->as_register_lo();
1256       Register to_hi = dest->as_register_hi();
1257 #ifdef _LP64
1258       __ movptr(to_lo, as_Address_lo(addr));
1259 #else
1260       Register base = addr->base()->as_register();
1261       Register index = noreg;
1262       if (addr->index()->is_register()) {
1263         index = addr->index()->as_register();
1264       }
1265       if ((base == to_lo && index == to_hi) ||
1266           (base == to_hi && index == to_lo)) {
1267         // addresses with 2 registers are only formed as a result of
1268         // array access so this code will never have to deal with
1269         // patches or null checks.
1270         assert(info == NULL && patch == NULL, "must be");
1271         __ lea(to_hi, as_Address(addr));
1272         __ movl(to_lo, Address(to_hi, 0));
1273         __ movl(to_hi, Address(to_hi, BytesPerWord));
1274       } else if (base == to_lo || index == to_lo) {
1275         assert(base != to_hi, "can't be");
1276         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1277         __ movl(to_hi, as_Address_hi(addr));
1278         if (patch != NULL) {
1279           patching_epilog(patch, lir_patch_high, base, info);
1280           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1281           patch_code = lir_patch_low;
1282         }
1283         __ movl(to_lo, as_Address_lo(addr));
1284       } else {
1285         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1286         __ movl(to_lo, as_Address_lo(addr));
1287         if (patch != NULL) {
1288           patching_epilog(patch, lir_patch_low, base, info);
1289           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1290           patch_code = lir_patch_high;
1291         }
1292         __ movl(to_hi, as_Address_hi(addr));
1293       }
1294 #endif // _LP64
1295       break;
1296     }
1297 
1298     case T_BOOLEAN: // fall through
1299     case T_BYTE: {
1300       Register dest_reg = dest->as_register();
1301       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1302       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1303         __ movsbl(dest_reg, from_addr);
1304       } else {
1305         __ movb(dest_reg, from_addr);
1306         __ shll(dest_reg, 24);
1307         __ sarl(dest_reg, 24);
1308       }
1309       break;
1310     }
1311 
1312     case T_CHAR: {
1313       Register dest_reg = dest->as_register();
1314       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316         __ movzwl(dest_reg, from_addr);
1317       } else {
1318         __ movw(dest_reg, from_addr);
1319       }
1320       break;
1321     }
1322 
1323     case T_SHORT: {
1324       Register dest_reg = dest->as_register();
1325       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326         __ movswl(dest_reg, from_addr);
1327       } else {
1328         __ movw(dest_reg, from_addr);
1329         __ shll(dest_reg, 16);
1330         __ sarl(dest_reg, 16);
1331       }
1332       break;
1333     }
1334 
1335     default:
1336       ShouldNotReachHere();
1337   }
1338 
1339   if (patch != NULL) {
1340     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1341   }
1342 
1343   if (type == T_ARRAY || type == T_OBJECT) {
1344 #ifdef _LP64
1345     if (UseCompressedOops && !wide) {
1346       __ decode_heap_oop(dest->as_register());
1347     }
1348 #endif
1349 
1350     // Load barrier has not yet been applied, so ZGC can't verify the oop here
1351     if (!UseZGC) {
1352       __ verify_oop(dest->as_register());
1353     }
1354   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1355 #ifdef _LP64
1356     if (UseCompressedClassPointers) {
1357       __ decode_klass_not_null(dest->as_register());
1358     }
1359 #endif
1360   }
1361 }
1362 
1363 
1364 NEEDS_CLEANUP; // This could be static?
1365 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1366   int elem_size = type2aelembytes(type);
1367   switch (elem_size) {
1368     case 1: return Address::times_1;
1369     case 2: return Address::times_2;
1370     case 4: return Address::times_4;
1371     case 8: return Address::times_8;
1372   }
1373   ShouldNotReachHere();
1374   return Address::no_scale;
1375 }
1376 
1377 
1378 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1379   switch (op->code()) {
1380     case lir_idiv:
1381     case lir_irem:
1382       arithmetic_idiv(op->code(),
1383                       op->in_opr1(),
1384                       op->in_opr2(),
1385                       op->in_opr3(),
1386                       op->result_opr(),
1387                       op->info());
1388       break;
1389     case lir_fmad:
1390       __ fmad(op->result_opr()->as_xmm_double_reg(),
1391               op->in_opr1()->as_xmm_double_reg(),
1392               op->in_opr2()->as_xmm_double_reg(),
1393               op->in_opr3()->as_xmm_double_reg());
1394       break;
1395     case lir_fmaf:
1396       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1397               op->in_opr1()->as_xmm_float_reg(),
1398               op->in_opr2()->as_xmm_float_reg(),
1399               op->in_opr3()->as_xmm_float_reg());
1400       break;
1401     default:      ShouldNotReachHere(); break;
1402   }
1403 }
1404 
1405 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1406 #ifdef ASSERT
1407   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1408   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1409   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1410 #endif
1411 
1412   if (op->cond() == lir_cond_always) {
1413     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1414     __ jmp (*(op->label()));
1415   } else {
1416     Assembler::Condition acond = Assembler::zero;
1417     if (op->code() == lir_cond_float_branch) {
1418       assert(op->ublock() != NULL, "must have unordered successor");
1419       __ jcc(Assembler::parity, *(op->ublock()->label()));
1420       switch(op->cond()) {
1421         case lir_cond_equal:        acond = Assembler::equal;      break;
1422         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1423         case lir_cond_less:         acond = Assembler::below;      break;
1424         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1425         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1426         case lir_cond_greater:      acond = Assembler::above;      break;
1427         default:                         ShouldNotReachHere();
1428       }
1429     } else {
1430       switch (op->cond()) {
1431         case lir_cond_equal:        acond = Assembler::equal;       break;
1432         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1433         case lir_cond_less:         acond = Assembler::less;        break;
1434         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1435         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1436         case lir_cond_greater:      acond = Assembler::greater;     break;
1437         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1438         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1439         default:                         ShouldNotReachHere();
1440       }
1441     }
1442     __ jcc(acond,*(op->label()));
1443   }
1444 }
1445 
1446 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1447   LIR_Opr src  = op->in_opr();
1448   LIR_Opr dest = op->result_opr();
1449 
1450   switch (op->bytecode()) {
1451     case Bytecodes::_i2l:
1452 #ifdef _LP64
1453       __ movl2ptr(dest->as_register_lo(), src->as_register());
1454 #else
1455       move_regs(src->as_register(), dest->as_register_lo());
1456       move_regs(src->as_register(), dest->as_register_hi());
1457       __ sarl(dest->as_register_hi(), 31);
1458 #endif // LP64
1459       break;
1460 
1461     case Bytecodes::_l2i:
1462 #ifdef _LP64
1463       __ movl(dest->as_register(), src->as_register_lo());
1464 #else
1465       move_regs(src->as_register_lo(), dest->as_register());
1466 #endif
1467       break;
1468 
1469     case Bytecodes::_i2b:
1470       move_regs(src->as_register(), dest->as_register());
1471       __ sign_extend_byte(dest->as_register());
1472       break;
1473 
1474     case Bytecodes::_i2c:
1475       move_regs(src->as_register(), dest->as_register());
1476       __ andl(dest->as_register(), 0xFFFF);
1477       break;
1478 
1479     case Bytecodes::_i2s:
1480       move_regs(src->as_register(), dest->as_register());
1481       __ sign_extend_short(dest->as_register());
1482       break;
1483 
1484 
1485     case Bytecodes::_f2d:
1486     case Bytecodes::_d2f:
1487       if (dest->is_single_xmm()) {
1488         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1489       } else if (dest->is_double_xmm()) {
1490         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1491       } else {
1492         assert(src->fpu() == dest->fpu(), "register must be equal");
1493         // do nothing (float result is rounded later through spilling)
1494       }
1495       break;
1496 
1497     case Bytecodes::_i2f:
1498     case Bytecodes::_i2d:
1499       if (dest->is_single_xmm()) {
1500         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1501       } else if (dest->is_double_xmm()) {
1502         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1503       } else {
1504         assert(dest->fpu() == 0, "result must be on TOS");
1505         __ movl(Address(rsp, 0), src->as_register());
1506         __ fild_s(Address(rsp, 0));
1507       }
1508       break;
1509 
1510     case Bytecodes::_f2i:
1511     case Bytecodes::_d2i:
1512       if (src->is_single_xmm()) {
1513         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1514       } else if (src->is_double_xmm()) {
1515         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1516       } else {
1517         assert(src->fpu() == 0, "input must be on TOS");
1518         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1519         __ fist_s(Address(rsp, 0));
1520         __ movl(dest->as_register(), Address(rsp, 0));
1521         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1522       }
1523 
1524       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1525       assert(op->stub() != NULL, "stub required");
1526       __ cmpl(dest->as_register(), 0x80000000);
1527       __ jcc(Assembler::equal, *op->stub()->entry());
1528       __ bind(*op->stub()->continuation());
1529       break;
1530 
1531     case Bytecodes::_l2f:
1532     case Bytecodes::_l2d:
1533       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1534       assert(dest->fpu() == 0, "result must be on TOS");
1535 
1536       __ movptr(Address(rsp, 0),            src->as_register_lo());
1537       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1538       __ fild_d(Address(rsp, 0));
1539       // float result is rounded later through spilling
1540       break;
1541 
1542     case Bytecodes::_f2l:
1543     case Bytecodes::_d2l:
1544       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1545       assert(src->fpu() == 0, "input must be on TOS");
1546       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1547 
1548       // instruction sequence too long to inline it here
1549       {
1550         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1551       }
1552       break;
1553 
1554     default: ShouldNotReachHere();
1555   }
1556 }
1557 
1558 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1559   if (op->init_check()) {
1560     add_debug_info_for_null_check_here(op->stub()->info());
1561     __ cmpb(Address(op->klass()->as_register(),
1562                     InstanceKlass::init_state_offset()),
1563                     InstanceKlass::fully_initialized);
1564     __ jcc(Assembler::notEqual, *op->stub()->entry());
1565   }
1566   __ allocate_object(op->obj()->as_register(),
1567                      op->tmp1()->as_register(),
1568                      op->tmp2()->as_register(),
1569                      op->header_size(),
1570                      op->object_size(),
1571                      op->klass()->as_register(),
1572                      *op->stub()->entry());
1573   __ bind(*op->stub()->continuation());
1574 }
1575 
1576 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1577   Register len =  op->len()->as_register();
1578   LP64_ONLY( __ movslq(len, len); )
1579 
1580   if (UseSlowPath ||
1581       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1582       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1583     __ jmp(*op->stub()->entry());
1584   } else {
1585     Register tmp1 = op->tmp1()->as_register();
1586     Register tmp2 = op->tmp2()->as_register();
1587     Register tmp3 = op->tmp3()->as_register();
1588     if (len == tmp1) {
1589       tmp1 = tmp3;
1590     } else if (len == tmp2) {
1591       tmp2 = tmp3;
1592     } else if (len == tmp3) {
1593       // everything is ok
1594     } else {
1595       __ mov(tmp3, len);
1596     }
1597     __ allocate_array(op->obj()->as_register(),
1598                       len,
1599                       tmp1,
1600                       tmp2,
1601                       arrayOopDesc::header_size(op->type()),
1602                       array_element_size(op->type()),
1603                       op->klass()->as_register(),
1604                       *op->stub()->entry());
1605   }
1606   __ bind(*op->stub()->continuation());
1607 }
1608 
1609 void LIR_Assembler::type_profile_helper(Register mdo,
1610                                         ciMethodData *md, ciProfileData *data,
1611                                         Register recv, Label* update_done) {
1612   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1613     Label next_test;
1614     // See if the receiver is receiver[n].
1615     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1616     __ jccb(Assembler::notEqual, next_test);
1617     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1618     __ addptr(data_addr, DataLayout::counter_increment);
1619     __ jmp(*update_done);
1620     __ bind(next_test);
1621   }
1622 
1623   // Didn't find receiver; find next empty slot and fill it in
1624   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1625     Label next_test;
1626     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1627     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1628     __ jccb(Assembler::notEqual, next_test);
1629     __ movptr(recv_addr, recv);
1630     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1631     __ jmp(*update_done);
1632     __ bind(next_test);
1633   }
1634 }
1635 
1636 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1637   // we always need a stub for the failure case.
1638   CodeStub* stub = op->stub();
1639   Register obj = op->object()->as_register();
1640   Register k_RInfo = op->tmp1()->as_register();
1641   Register klass_RInfo = op->tmp2()->as_register();
1642   Register dst = op->result_opr()->as_register();
1643   ciKlass* k = op->klass();
1644   Register Rtmp1 = noreg;
1645 
1646   // check if it needs to be profiled
1647   ciMethodData* md = NULL;
1648   ciProfileData* data = NULL;
1649 
1650   if (op->should_profile()) {
1651     ciMethod* method = op->profiled_method();
1652     assert(method != NULL, "Should have method");
1653     int bci = op->profiled_bci();
1654     md = method->method_data_or_null();
1655     assert(md != NULL, "Sanity");
1656     data = md->bci_to_data(bci);
1657     assert(data != NULL,                "need data for type check");
1658     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1659   }
1660   Label profile_cast_success, profile_cast_failure;
1661   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1662   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1663 
1664   if (obj == k_RInfo) {
1665     k_RInfo = dst;
1666   } else if (obj == klass_RInfo) {
1667     klass_RInfo = dst;
1668   }
1669   if (k->is_loaded() && !UseCompressedClassPointers) {
1670     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1671   } else {
1672     Rtmp1 = op->tmp3()->as_register();
1673     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1674   }
1675 
1676   assert_different_registers(obj, k_RInfo, klass_RInfo);
1677 
1678   __ cmpptr(obj, (int32_t)NULL_WORD);
1679   if (op->should_profile()) {
1680     Label not_null;
1681     __ jccb(Assembler::notEqual, not_null);
1682     // Object is null; update MDO and exit
1683     Register mdo  = klass_RInfo;
1684     __ mov_metadata(mdo, md->constant_encoding());
1685     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1686     int header_bits = BitData::null_seen_byte_constant();
1687     __ orb(data_addr, header_bits);
1688     __ jmp(*obj_is_null);
1689     __ bind(not_null);
1690   } else {
1691     __ jcc(Assembler::equal, *obj_is_null);
1692   }
1693 
1694   if (!k->is_loaded()) {
1695     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1696   } else {
1697 #ifdef _LP64
1698     __ mov_metadata(k_RInfo, k->constant_encoding());
1699 #endif // _LP64
1700   }
1701   __ verify_oop(obj);
1702 
1703   if (op->fast_check()) {
1704     // get object class
1705     // not a safepoint as obj null check happens earlier
1706 #ifdef _LP64
1707     if (UseCompressedClassPointers) {
1708       __ load_klass(Rtmp1, obj);
1709       __ cmpptr(k_RInfo, Rtmp1);
1710     } else {
1711       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1712     }
1713 #else
1714     if (k->is_loaded()) {
1715       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1716     } else {
1717       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1718     }
1719 #endif
1720     __ jcc(Assembler::notEqual, *failure_target);
1721     // successful cast, fall through to profile or jump
1722   } else {
1723     // get object class
1724     // not a safepoint as obj null check happens earlier
1725     __ load_klass(klass_RInfo, obj);
1726     if (k->is_loaded()) {
1727       // See if we get an immediate positive hit
1728 #ifdef _LP64
1729       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1730 #else
1731       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1732 #endif // _LP64
1733       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1734         __ jcc(Assembler::notEqual, *failure_target);
1735         // successful cast, fall through to profile or jump
1736       } else {
1737         // See if we get an immediate positive hit
1738         __ jcc(Assembler::equal, *success_target);
1739         // check for self
1740 #ifdef _LP64
1741         __ cmpptr(klass_RInfo, k_RInfo);
1742 #else
1743         __ cmpklass(klass_RInfo, k->constant_encoding());
1744 #endif // _LP64
1745         __ jcc(Assembler::equal, *success_target);
1746 
1747         __ push(klass_RInfo);
1748 #ifdef _LP64
1749         __ push(k_RInfo);
1750 #else
1751         __ pushklass(k->constant_encoding());
1752 #endif // _LP64
1753         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1754         __ pop(klass_RInfo);
1755         __ pop(klass_RInfo);
1756         // result is a boolean
1757         __ cmpl(klass_RInfo, 0);
1758         __ jcc(Assembler::equal, *failure_target);
1759         // successful cast, fall through to profile or jump
1760       }
1761     } else {
1762       // perform the fast part of the checking logic
1763       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1764       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1765       __ push(klass_RInfo);
1766       __ push(k_RInfo);
1767       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1768       __ pop(klass_RInfo);
1769       __ pop(k_RInfo);
1770       // result is a boolean
1771       __ cmpl(k_RInfo, 0);
1772       __ jcc(Assembler::equal, *failure_target);
1773       // successful cast, fall through to profile or jump
1774     }
1775   }
1776   if (op->should_profile()) {
1777     Register mdo  = klass_RInfo, recv = k_RInfo;
1778     __ bind(profile_cast_success);
1779     __ mov_metadata(mdo, md->constant_encoding());
1780     __ load_klass(recv, obj);
1781     type_profile_helper(mdo, md, data, recv, success);
1782     __ jmp(*success);
1783 
1784     __ bind(profile_cast_failure);
1785     __ mov_metadata(mdo, md->constant_encoding());
1786     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1787     __ subptr(counter_addr, DataLayout::counter_increment);
1788     __ jmp(*failure);
1789   }
1790   __ jmp(*success);
1791 }
1792 
1793 
1794 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1795   LIR_Code code = op->code();
1796   if (code == lir_store_check) {
1797     Register value = op->object()->as_register();
1798     Register array = op->array()->as_register();
1799     Register k_RInfo = op->tmp1()->as_register();
1800     Register klass_RInfo = op->tmp2()->as_register();
1801     Register Rtmp1 = op->tmp3()->as_register();
1802 
1803     CodeStub* stub = op->stub();
1804 
1805     // check if it needs to be profiled
1806     ciMethodData* md = NULL;
1807     ciProfileData* data = NULL;
1808 
1809     if (op->should_profile()) {
1810       ciMethod* method = op->profiled_method();
1811       assert(method != NULL, "Should have method");
1812       int bci = op->profiled_bci();
1813       md = method->method_data_or_null();
1814       assert(md != NULL, "Sanity");
1815       data = md->bci_to_data(bci);
1816       assert(data != NULL,                "need data for type check");
1817       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1818     }
1819     Label profile_cast_success, profile_cast_failure, done;
1820     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1821     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1822 
1823     __ cmpptr(value, (int32_t)NULL_WORD);
1824     if (op->should_profile()) {
1825       Label not_null;
1826       __ jccb(Assembler::notEqual, not_null);
1827       // Object is null; update MDO and exit
1828       Register mdo  = klass_RInfo;
1829       __ mov_metadata(mdo, md->constant_encoding());
1830       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1831       int header_bits = BitData::null_seen_byte_constant();
1832       __ orb(data_addr, header_bits);
1833       __ jmp(done);
1834       __ bind(not_null);
1835     } else {
1836       __ jcc(Assembler::equal, done);
1837     }
1838 
1839     add_debug_info_for_null_check_here(op->info_for_exception());
1840     __ load_klass(k_RInfo, array);
1841     __ load_klass(klass_RInfo, value);
1842 
1843     // get instance klass (it's already uncompressed)
1844     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1845     // perform the fast part of the checking logic
1846     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1847     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1848     __ push(klass_RInfo);
1849     __ push(k_RInfo);
1850     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1851     __ pop(klass_RInfo);
1852     __ pop(k_RInfo);
1853     // result is a boolean
1854     __ cmpl(k_RInfo, 0);
1855     __ jcc(Assembler::equal, *failure_target);
1856     // fall through to the success case
1857 
1858     if (op->should_profile()) {
1859       Register mdo  = klass_RInfo, recv = k_RInfo;
1860       __ bind(profile_cast_success);
1861       __ mov_metadata(mdo, md->constant_encoding());
1862       __ load_klass(recv, value);
1863       type_profile_helper(mdo, md, data, recv, &done);
1864       __ jmpb(done);
1865 
1866       __ bind(profile_cast_failure);
1867       __ mov_metadata(mdo, md->constant_encoding());
1868       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1869       __ subptr(counter_addr, DataLayout::counter_increment);
1870       __ jmp(*stub->entry());
1871     }
1872 
1873     __ bind(done);
1874   } else
1875     if (code == lir_checkcast) {
1876       Register obj = op->object()->as_register();
1877       Register dst = op->result_opr()->as_register();
1878       Label success;
1879       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1880       __ bind(success);
1881       if (dst != obj) {
1882         __ mov(dst, obj);
1883       }
1884     } else
1885       if (code == lir_instanceof) {
1886         Register obj = op->object()->as_register();
1887         Register dst = op->result_opr()->as_register();
1888         Label success, failure, done;
1889         emit_typecheck_helper(op, &success, &failure, &failure);
1890         __ bind(failure);
1891         __ xorptr(dst, dst);
1892         __ jmpb(done);
1893         __ bind(success);
1894         __ movptr(dst, 1);
1895         __ bind(done);
1896       } else {
1897         ShouldNotReachHere();
1898       }
1899 
1900 }
1901 
1902 
1903 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1904   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1905     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1906     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1907     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1908     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1909     Register addr = op->addr()->as_register();
1910     __ lock();
1911     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1912 
1913   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1914     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1915     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1916     Register newval = op->new_value()->as_register();
1917     Register cmpval = op->cmp_value()->as_register();
1918     assert(cmpval == rax, "wrong register");
1919     assert(newval != NULL, "new val must be register");
1920     assert(cmpval != newval, "cmp and new values must be in different registers");
1921     assert(cmpval != addr, "cmp and addr must be in different registers");
1922     assert(newval != addr, "new value and addr must be in different registers");
1923 
1924     if ( op->code() == lir_cas_obj) {
1925 #ifdef _LP64
1926       if (UseCompressedOops) {
1927         __ encode_heap_oop(cmpval);
1928         __ mov(rscratch1, newval);
1929         __ encode_heap_oop(rscratch1);
1930         __ lock();
1931         // cmpval (rax) is implicitly used by this instruction
1932         __ cmpxchgl(rscratch1, Address(addr, 0));
1933       } else
1934 #endif
1935       {
1936         __ lock();
1937         __ cmpxchgptr(newval, Address(addr, 0));
1938       }
1939     } else {
1940       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1941       __ lock();
1942       __ cmpxchgl(newval, Address(addr, 0));
1943     }
1944 #ifdef _LP64
1945   } else if (op->code() == lir_cas_long) {
1946     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1947     Register newval = op->new_value()->as_register_lo();
1948     Register cmpval = op->cmp_value()->as_register_lo();
1949     assert(cmpval == rax, "wrong register");
1950     assert(newval != NULL, "new val must be register");
1951     assert(cmpval != newval, "cmp and new values must be in different registers");
1952     assert(cmpval != addr, "cmp and addr must be in different registers");
1953     assert(newval != addr, "new value and addr must be in different registers");
1954     __ lock();
1955     __ cmpxchgq(newval, Address(addr, 0));
1956 #endif // _LP64
1957   } else {
1958     Unimplemented();
1959   }
1960 }
1961 
1962 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1963   Assembler::Condition acond, ncond;
1964   switch (condition) {
1965     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1966     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1967     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
1968     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
1969     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
1970     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
1971     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
1972     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
1973     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
1974                                 ShouldNotReachHere();
1975   }
1976 
1977   if (opr1->is_cpu_register()) {
1978     reg2reg(opr1, result);
1979   } else if (opr1->is_stack()) {
1980     stack2reg(opr1, result, result->type());
1981   } else if (opr1->is_constant()) {
1982     const2reg(opr1, result, lir_patch_none, NULL);
1983   } else {
1984     ShouldNotReachHere();
1985   }
1986 
1987   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1988     // optimized version that does not require a branch
1989     if (opr2->is_single_cpu()) {
1990       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1991       __ cmov(ncond, result->as_register(), opr2->as_register());
1992     } else if (opr2->is_double_cpu()) {
1993       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1994       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1995       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1996       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1997     } else if (opr2->is_single_stack()) {
1998       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1999     } else if (opr2->is_double_stack()) {
2000       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2001       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2002     } else {
2003       ShouldNotReachHere();
2004     }
2005 
2006   } else {
2007     Label skip;
2008     __ jcc (acond, skip);
2009     if (opr2->is_cpu_register()) {
2010       reg2reg(opr2, result);
2011     } else if (opr2->is_stack()) {
2012       stack2reg(opr2, result, result->type());
2013     } else if (opr2->is_constant()) {
2014       const2reg(opr2, result, lir_patch_none, NULL);
2015     } else {
2016       ShouldNotReachHere();
2017     }
2018     __ bind(skip);
2019   }
2020 }
2021 
2022 
2023 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2024   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2025 
2026   if (left->is_single_cpu()) {
2027     assert(left == dest, "left and dest must be equal");
2028     Register lreg = left->as_register();
2029 
2030     if (right->is_single_cpu()) {
2031       // cpu register - cpu register
2032       Register rreg = right->as_register();
2033       switch (code) {
2034         case lir_add: __ addl (lreg, rreg); break;
2035         case lir_sub: __ subl (lreg, rreg); break;
2036         case lir_mul: __ imull(lreg, rreg); break;
2037         default:      ShouldNotReachHere();
2038       }
2039 
2040     } else if (right->is_stack()) {
2041       // cpu register - stack
2042       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2043       switch (code) {
2044         case lir_add: __ addl(lreg, raddr); break;
2045         case lir_sub: __ subl(lreg, raddr); break;
2046         default:      ShouldNotReachHere();
2047       }
2048 
2049     } else if (right->is_constant()) {
2050       // cpu register - constant
2051       jint c = right->as_constant_ptr()->as_jint();
2052       switch (code) {
2053         case lir_add: {
2054           __ incrementl(lreg, c);
2055           break;
2056         }
2057         case lir_sub: {
2058           __ decrementl(lreg, c);
2059           break;
2060         }
2061         default: ShouldNotReachHere();
2062       }
2063 
2064     } else {
2065       ShouldNotReachHere();
2066     }
2067 
2068   } else if (left->is_double_cpu()) {
2069     assert(left == dest, "left and dest must be equal");
2070     Register lreg_lo = left->as_register_lo();
2071     Register lreg_hi = left->as_register_hi();
2072 
2073     if (right->is_double_cpu()) {
2074       // cpu register - cpu register
2075       Register rreg_lo = right->as_register_lo();
2076       Register rreg_hi = right->as_register_hi();
2077       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2078       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2079       switch (code) {
2080         case lir_add:
2081           __ addptr(lreg_lo, rreg_lo);
2082           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2083           break;
2084         case lir_sub:
2085           __ subptr(lreg_lo, rreg_lo);
2086           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2087           break;
2088         case lir_mul:
2089 #ifdef _LP64
2090           __ imulq(lreg_lo, rreg_lo);
2091 #else
2092           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2093           __ imull(lreg_hi, rreg_lo);
2094           __ imull(rreg_hi, lreg_lo);
2095           __ addl (rreg_hi, lreg_hi);
2096           __ mull (rreg_lo);
2097           __ addl (lreg_hi, rreg_hi);
2098 #endif // _LP64
2099           break;
2100         default:
2101           ShouldNotReachHere();
2102       }
2103 
2104     } else if (right->is_constant()) {
2105       // cpu register - constant
2106 #ifdef _LP64
2107       jlong c = right->as_constant_ptr()->as_jlong_bits();
2108       __ movptr(r10, (intptr_t) c);
2109       switch (code) {
2110         case lir_add:
2111           __ addptr(lreg_lo, r10);
2112           break;
2113         case lir_sub:
2114           __ subptr(lreg_lo, r10);
2115           break;
2116         default:
2117           ShouldNotReachHere();
2118       }
2119 #else
2120       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2121       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2122       switch (code) {
2123         case lir_add:
2124           __ addptr(lreg_lo, c_lo);
2125           __ adcl(lreg_hi, c_hi);
2126           break;
2127         case lir_sub:
2128           __ subptr(lreg_lo, c_lo);
2129           __ sbbl(lreg_hi, c_hi);
2130           break;
2131         default:
2132           ShouldNotReachHere();
2133       }
2134 #endif // _LP64
2135 
2136     } else {
2137       ShouldNotReachHere();
2138     }
2139 
2140   } else if (left->is_single_xmm()) {
2141     assert(left == dest, "left and dest must be equal");
2142     XMMRegister lreg = left->as_xmm_float_reg();
2143 
2144     if (right->is_single_xmm()) {
2145       XMMRegister rreg = right->as_xmm_float_reg();
2146       switch (code) {
2147         case lir_add: __ addss(lreg, rreg);  break;
2148         case lir_sub: __ subss(lreg, rreg);  break;
2149         case lir_mul_strictfp: // fall through
2150         case lir_mul: __ mulss(lreg, rreg);  break;
2151         case lir_div_strictfp: // fall through
2152         case lir_div: __ divss(lreg, rreg);  break;
2153         default: ShouldNotReachHere();
2154       }
2155     } else {
2156       Address raddr;
2157       if (right->is_single_stack()) {
2158         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2159       } else if (right->is_constant()) {
2160         // hack for now
2161         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2162       } else {
2163         ShouldNotReachHere();
2164       }
2165       switch (code) {
2166         case lir_add: __ addss(lreg, raddr);  break;
2167         case lir_sub: __ subss(lreg, raddr);  break;
2168         case lir_mul_strictfp: // fall through
2169         case lir_mul: __ mulss(lreg, raddr);  break;
2170         case lir_div_strictfp: // fall through
2171         case lir_div: __ divss(lreg, raddr);  break;
2172         default: ShouldNotReachHere();
2173       }
2174     }
2175 
2176   } else if (left->is_double_xmm()) {
2177     assert(left == dest, "left and dest must be equal");
2178 
2179     XMMRegister lreg = left->as_xmm_double_reg();
2180     if (right->is_double_xmm()) {
2181       XMMRegister rreg = right->as_xmm_double_reg();
2182       switch (code) {
2183         case lir_add: __ addsd(lreg, rreg);  break;
2184         case lir_sub: __ subsd(lreg, rreg);  break;
2185         case lir_mul_strictfp: // fall through
2186         case lir_mul: __ mulsd(lreg, rreg);  break;
2187         case lir_div_strictfp: // fall through
2188         case lir_div: __ divsd(lreg, rreg);  break;
2189         default: ShouldNotReachHere();
2190       }
2191     } else {
2192       Address raddr;
2193       if (right->is_double_stack()) {
2194         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2195       } else if (right->is_constant()) {
2196         // hack for now
2197         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2198       } else {
2199         ShouldNotReachHere();
2200       }
2201       switch (code) {
2202         case lir_add: __ addsd(lreg, raddr);  break;
2203         case lir_sub: __ subsd(lreg, raddr);  break;
2204         case lir_mul_strictfp: // fall through
2205         case lir_mul: __ mulsd(lreg, raddr);  break;
2206         case lir_div_strictfp: // fall through
2207         case lir_div: __ divsd(lreg, raddr);  break;
2208         default: ShouldNotReachHere();
2209       }
2210     }
2211 
2212   } else if (left->is_single_fpu()) {
2213     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2214 
2215     if (right->is_single_fpu()) {
2216       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2217 
2218     } else {
2219       assert(left->fpu_regnr() == 0, "left must be on TOS");
2220       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2221 
2222       Address raddr;
2223       if (right->is_single_stack()) {
2224         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2225       } else if (right->is_constant()) {
2226         address const_addr = float_constant(right->as_jfloat());
2227         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2228         // hack for now
2229         raddr = __ as_Address(InternalAddress(const_addr));
2230       } else {
2231         ShouldNotReachHere();
2232       }
2233 
2234       switch (code) {
2235         case lir_add: __ fadd_s(raddr); break;
2236         case lir_sub: __ fsub_s(raddr); break;
2237         case lir_mul_strictfp: // fall through
2238         case lir_mul: __ fmul_s(raddr); break;
2239         case lir_div_strictfp: // fall through
2240         case lir_div: __ fdiv_s(raddr); break;
2241         default:      ShouldNotReachHere();
2242       }
2243     }
2244 
2245   } else if (left->is_double_fpu()) {
2246     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2247 
2248     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2249       // Double values require special handling for strictfp mul/div on x86
2250       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2251       __ fmulp(left->fpu_regnrLo() + 1);
2252     }
2253 
2254     if (right->is_double_fpu()) {
2255       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2256 
2257     } else {
2258       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2259       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2260 
2261       Address raddr;
2262       if (right->is_double_stack()) {
2263         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2264       } else if (right->is_constant()) {
2265         // hack for now
2266         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2267       } else {
2268         ShouldNotReachHere();
2269       }
2270 
2271       switch (code) {
2272         case lir_add: __ fadd_d(raddr); break;
2273         case lir_sub: __ fsub_d(raddr); break;
2274         case lir_mul_strictfp: // fall through
2275         case lir_mul: __ fmul_d(raddr); break;
2276         case lir_div_strictfp: // fall through
2277         case lir_div: __ fdiv_d(raddr); break;
2278         default: ShouldNotReachHere();
2279       }
2280     }
2281 
2282     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2283       // Double values require special handling for strictfp mul/div on x86
2284       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2285       __ fmulp(dest->fpu_regnrLo() + 1);
2286     }
2287 
2288   } else if (left->is_single_stack() || left->is_address()) {
2289     assert(left == dest, "left and dest must be equal");
2290 
2291     Address laddr;
2292     if (left->is_single_stack()) {
2293       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2294     } else if (left->is_address()) {
2295       laddr = as_Address(left->as_address_ptr());
2296     } else {
2297       ShouldNotReachHere();
2298     }
2299 
2300     if (right->is_single_cpu()) {
2301       Register rreg = right->as_register();
2302       switch (code) {
2303         case lir_add: __ addl(laddr, rreg); break;
2304         case lir_sub: __ subl(laddr, rreg); break;
2305         default:      ShouldNotReachHere();
2306       }
2307     } else if (right->is_constant()) {
2308       jint c = right->as_constant_ptr()->as_jint();
2309       switch (code) {
2310         case lir_add: {
2311           __ incrementl(laddr, c);
2312           break;
2313         }
2314         case lir_sub: {
2315           __ decrementl(laddr, c);
2316           break;
2317         }
2318         default: ShouldNotReachHere();
2319       }
2320     } else {
2321       ShouldNotReachHere();
2322     }
2323 
2324   } else {
2325     ShouldNotReachHere();
2326   }
2327 }
2328 
2329 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2330   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2331   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2332   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2333 
2334   bool left_is_tos = (left_index == 0);
2335   bool dest_is_tos = (dest_index == 0);
2336   int non_tos_index = (left_is_tos ? right_index : left_index);
2337 
2338   switch (code) {
2339     case lir_add:
2340       if (pop_fpu_stack)       __ faddp(non_tos_index);
2341       else if (dest_is_tos)    __ fadd (non_tos_index);
2342       else                     __ fadda(non_tos_index);
2343       break;
2344 
2345     case lir_sub:
2346       if (left_is_tos) {
2347         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2348         else if (dest_is_tos)  __ fsub  (non_tos_index);
2349         else                   __ fsubra(non_tos_index);
2350       } else {
2351         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2352         else if (dest_is_tos)  __ fsubr (non_tos_index);
2353         else                   __ fsuba (non_tos_index);
2354       }
2355       break;
2356 
2357     case lir_mul_strictfp: // fall through
2358     case lir_mul:
2359       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2360       else if (dest_is_tos)    __ fmul (non_tos_index);
2361       else                     __ fmula(non_tos_index);
2362       break;
2363 
2364     case lir_div_strictfp: // fall through
2365     case lir_div:
2366       if (left_is_tos) {
2367         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2368         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2369         else                   __ fdivra(non_tos_index);
2370       } else {
2371         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2372         else if (dest_is_tos)  __ fdivr (non_tos_index);
2373         else                   __ fdiva (non_tos_index);
2374       }
2375       break;
2376 
2377     case lir_rem:
2378       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2379       __ fremr(noreg);
2380       break;
2381 
2382     default:
2383       ShouldNotReachHere();
2384   }
2385 }
2386 
2387 
2388 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2389   if (value->is_double_xmm()) {
2390     switch(code) {
2391       case lir_abs :
2392         {
2393           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2394             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2395           }
2396           __ andpd(dest->as_xmm_double_reg(),
2397                     ExternalAddress((address)double_signmask_pool));
2398         }
2399         break;
2400 
2401       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2402       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2403       default      : ShouldNotReachHere();
2404     }
2405 
2406   } else if (value->is_double_fpu()) {
2407     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2408     switch(code) {
2409       case lir_abs   : __ fabs() ; break;
2410       case lir_sqrt  : __ fsqrt(); break;
2411       default      : ShouldNotReachHere();
2412     }
2413   } else {
2414     Unimplemented();
2415   }
2416 }
2417 
2418 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2419   // assert(left->destroys_register(), "check");
2420   if (left->is_single_cpu()) {
2421     Register reg = left->as_register();
2422     if (right->is_constant()) {
2423       int val = right->as_constant_ptr()->as_jint();
2424       switch (code) {
2425         case lir_logic_and: __ andl (reg, val); break;
2426         case lir_logic_or:  __ orl  (reg, val); break;
2427         case lir_logic_xor: __ xorl (reg, val); break;
2428         default: ShouldNotReachHere();
2429       }
2430     } else if (right->is_stack()) {
2431       // added support for stack operands
2432       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2433       switch (code) {
2434         case lir_logic_and: __ andl (reg, raddr); break;
2435         case lir_logic_or:  __ orl  (reg, raddr); break;
2436         case lir_logic_xor: __ xorl (reg, raddr); break;
2437         default: ShouldNotReachHere();
2438       }
2439     } else {
2440       Register rright = right->as_register();
2441       switch (code) {
2442         case lir_logic_and: __ andptr (reg, rright); break;
2443         case lir_logic_or : __ orptr  (reg, rright); break;
2444         case lir_logic_xor: __ xorptr (reg, rright); break;
2445         default: ShouldNotReachHere();
2446       }
2447     }
2448     move_regs(reg, dst->as_register());
2449   } else {
2450     Register l_lo = left->as_register_lo();
2451     Register l_hi = left->as_register_hi();
2452     if (right->is_constant()) {
2453 #ifdef _LP64
2454       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2455       switch (code) {
2456         case lir_logic_and:
2457           __ andq(l_lo, rscratch1);
2458           break;
2459         case lir_logic_or:
2460           __ orq(l_lo, rscratch1);
2461           break;
2462         case lir_logic_xor:
2463           __ xorq(l_lo, rscratch1);
2464           break;
2465         default: ShouldNotReachHere();
2466       }
2467 #else
2468       int r_lo = right->as_constant_ptr()->as_jint_lo();
2469       int r_hi = right->as_constant_ptr()->as_jint_hi();
2470       switch (code) {
2471         case lir_logic_and:
2472           __ andl(l_lo, r_lo);
2473           __ andl(l_hi, r_hi);
2474           break;
2475         case lir_logic_or:
2476           __ orl(l_lo, r_lo);
2477           __ orl(l_hi, r_hi);
2478           break;
2479         case lir_logic_xor:
2480           __ xorl(l_lo, r_lo);
2481           __ xorl(l_hi, r_hi);
2482           break;
2483         default: ShouldNotReachHere();
2484       }
2485 #endif // _LP64
2486     } else {
2487 #ifdef _LP64
2488       Register r_lo;
2489       if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2490         r_lo = right->as_register();
2491       } else {
2492         r_lo = right->as_register_lo();
2493       }
2494 #else
2495       Register r_lo = right->as_register_lo();
2496       Register r_hi = right->as_register_hi();
2497       assert(l_lo != r_hi, "overwriting registers");
2498 #endif
2499       switch (code) {
2500         case lir_logic_and:
2501           __ andptr(l_lo, r_lo);
2502           NOT_LP64(__ andptr(l_hi, r_hi);)
2503           break;
2504         case lir_logic_or:
2505           __ orptr(l_lo, r_lo);
2506           NOT_LP64(__ orptr(l_hi, r_hi);)
2507           break;
2508         case lir_logic_xor:
2509           __ xorptr(l_lo, r_lo);
2510           NOT_LP64(__ xorptr(l_hi, r_hi);)
2511           break;
2512         default: ShouldNotReachHere();
2513       }
2514     }
2515 
2516     Register dst_lo = dst->as_register_lo();
2517     Register dst_hi = dst->as_register_hi();
2518 
2519 #ifdef _LP64
2520     move_regs(l_lo, dst_lo);
2521 #else
2522     if (dst_lo == l_hi) {
2523       assert(dst_hi != l_lo, "overwriting registers");
2524       move_regs(l_hi, dst_hi);
2525       move_regs(l_lo, dst_lo);
2526     } else {
2527       assert(dst_lo != l_hi, "overwriting registers");
2528       move_regs(l_lo, dst_lo);
2529       move_regs(l_hi, dst_hi);
2530     }
2531 #endif // _LP64
2532   }
2533 }
2534 
2535 
2536 // we assume that rax, and rdx can be overwritten
2537 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2538 
2539   assert(left->is_single_cpu(),   "left must be register");
2540   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2541   assert(result->is_single_cpu(), "result must be register");
2542 
2543   //  assert(left->destroys_register(), "check");
2544   //  assert(right->destroys_register(), "check");
2545 
2546   Register lreg = left->as_register();
2547   Register dreg = result->as_register();
2548 
2549   if (right->is_constant()) {
2550     int divisor = right->as_constant_ptr()->as_jint();
2551     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2552     if (code == lir_idiv) {
2553       assert(lreg == rax, "must be rax,");
2554       assert(temp->as_register() == rdx, "tmp register must be rdx");
2555       __ cdql(); // sign extend into rdx:rax
2556       if (divisor == 2) {
2557         __ subl(lreg, rdx);
2558       } else {
2559         __ andl(rdx, divisor - 1);
2560         __ addl(lreg, rdx);
2561       }
2562       __ sarl(lreg, log2_intptr(divisor));
2563       move_regs(lreg, dreg);
2564     } else if (code == lir_irem) {
2565       Label done;
2566       __ mov(dreg, lreg);
2567       __ andl(dreg, 0x80000000 | (divisor - 1));
2568       __ jcc(Assembler::positive, done);
2569       __ decrement(dreg);
2570       __ orl(dreg, ~(divisor - 1));
2571       __ increment(dreg);
2572       __ bind(done);
2573     } else {
2574       ShouldNotReachHere();
2575     }
2576   } else {
2577     Register rreg = right->as_register();
2578     assert(lreg == rax, "left register must be rax,");
2579     assert(rreg != rdx, "right register must not be rdx");
2580     assert(temp->as_register() == rdx, "tmp register must be rdx");
2581 
2582     move_regs(lreg, rax);
2583 
2584     int idivl_offset = __ corrected_idivl(rreg);
2585     if (ImplicitDiv0Checks) {
2586       add_debug_info_for_div0(idivl_offset, info);
2587     }
2588     if (code == lir_irem) {
2589       move_regs(rdx, dreg); // result is in rdx
2590     } else {
2591       move_regs(rax, dreg);
2592     }
2593   }
2594 }
2595 
2596 
2597 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2598   if (opr1->is_single_cpu()) {
2599     Register reg1 = opr1->as_register();
2600     if (opr2->is_single_cpu()) {
2601       // cpu register - cpu register
2602       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2603         __ cmpoop(reg1, opr2->as_register());
2604       } else {
2605         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2606         __ cmpl(reg1, opr2->as_register());
2607       }
2608     } else if (opr2->is_stack()) {
2609       // cpu register - stack
2610       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2611         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2612       } else {
2613         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2614       }
2615     } else if (opr2->is_constant()) {
2616       // cpu register - constant
2617       LIR_Const* c = opr2->as_constant_ptr();
2618       if (c->type() == T_INT) {
2619         __ cmpl(reg1, c->as_jint());
2620       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2621         // In 64bit oops are single register
2622         jobject o = c->as_jobject();
2623         if (o == NULL) {
2624           __ cmpptr(reg1, (int32_t)NULL_WORD);
2625         } else {
2626           __ cmpoop(reg1, o);
2627         }
2628       } else {
2629         fatal("unexpected type: %s", basictype_to_str(c->type()));
2630       }
2631       // cpu register - address
2632     } else if (opr2->is_address()) {
2633       if (op->info() != NULL) {
2634         add_debug_info_for_null_check_here(op->info());
2635       }
2636       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2637     } else {
2638       ShouldNotReachHere();
2639     }
2640 
2641   } else if(opr1->is_double_cpu()) {
2642     Register xlo = opr1->as_register_lo();
2643     Register xhi = opr1->as_register_hi();
2644     if (opr2->is_double_cpu()) {
2645 #ifdef _LP64
2646       __ cmpptr(xlo, opr2->as_register_lo());
2647 #else
2648       // cpu register - cpu register
2649       Register ylo = opr2->as_register_lo();
2650       Register yhi = opr2->as_register_hi();
2651       __ subl(xlo, ylo);
2652       __ sbbl(xhi, yhi);
2653       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2654         __ orl(xhi, xlo);
2655       }
2656 #endif // _LP64
2657     } else if (opr2->is_constant()) {
2658       // cpu register - constant 0
2659       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2660 #ifdef _LP64
2661       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2662 #else
2663       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2664       __ orl(xhi, xlo);
2665 #endif // _LP64
2666     } else {
2667       ShouldNotReachHere();
2668     }
2669 
2670   } else if (opr1->is_single_xmm()) {
2671     XMMRegister reg1 = opr1->as_xmm_float_reg();
2672     if (opr2->is_single_xmm()) {
2673       // xmm register - xmm register
2674       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2675     } else if (opr2->is_stack()) {
2676       // xmm register - stack
2677       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2678     } else if (opr2->is_constant()) {
2679       // xmm register - constant
2680       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2681     } else if (opr2->is_address()) {
2682       // xmm register - address
2683       if (op->info() != NULL) {
2684         add_debug_info_for_null_check_here(op->info());
2685       }
2686       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2687     } else {
2688       ShouldNotReachHere();
2689     }
2690 
2691   } else if (opr1->is_double_xmm()) {
2692     XMMRegister reg1 = opr1->as_xmm_double_reg();
2693     if (opr2->is_double_xmm()) {
2694       // xmm register - xmm register
2695       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2696     } else if (opr2->is_stack()) {
2697       // xmm register - stack
2698       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2699     } else if (opr2->is_constant()) {
2700       // xmm register - constant
2701       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2702     } else if (opr2->is_address()) {
2703       // xmm register - address
2704       if (op->info() != NULL) {
2705         add_debug_info_for_null_check_here(op->info());
2706       }
2707       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2708     } else {
2709       ShouldNotReachHere();
2710     }
2711 
2712   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2713     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2714     assert(opr2->is_fpu_register(), "both must be registers");
2715     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2716 
2717   } else if (opr1->is_address() && opr2->is_constant()) {
2718     LIR_Const* c = opr2->as_constant_ptr();
2719 #ifdef _LP64
2720     if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2721       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2722       __ movoop(rscratch1, c->as_jobject());
2723     }
2724 #endif // LP64
2725     if (op->info() != NULL) {
2726       add_debug_info_for_null_check_here(op->info());
2727     }
2728     // special case: address - constant
2729     LIR_Address* addr = opr1->as_address_ptr();
2730     if (c->type() == T_INT) {
2731       __ cmpl(as_Address(addr), c->as_jint());
2732     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2733 #ifdef _LP64
2734       // %%% Make this explode if addr isn't reachable until we figure out a
2735       // better strategy by giving noreg as the temp for as_Address
2736       __ cmpoop(rscratch1, as_Address(addr, noreg));
2737 #else
2738       __ cmpoop(as_Address(addr), c->as_jobject());
2739 #endif // _LP64
2740     } else {
2741       ShouldNotReachHere();
2742     }
2743 
2744   } else {
2745     ShouldNotReachHere();
2746   }
2747 }
2748 
2749 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2750   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2751     if (left->is_single_xmm()) {
2752       assert(right->is_single_xmm(), "must match");
2753       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2754     } else if (left->is_double_xmm()) {
2755       assert(right->is_double_xmm(), "must match");
2756       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2757 
2758     } else {
2759       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2760       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2761 
2762       assert(left->fpu() == 0, "left must be on TOS");
2763       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2764                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2765     }
2766   } else {
2767     assert(code == lir_cmp_l2i, "check");
2768 #ifdef _LP64
2769     Label done;
2770     Register dest = dst->as_register();
2771     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2772     __ movl(dest, -1);
2773     __ jccb(Assembler::less, done);
2774     __ set_byte_if_not_zero(dest);
2775     __ movzbl(dest, dest);
2776     __ bind(done);
2777 #else
2778     __ lcmp2int(left->as_register_hi(),
2779                 left->as_register_lo(),
2780                 right->as_register_hi(),
2781                 right->as_register_lo());
2782     move_regs(left->as_register_hi(), dst->as_register());
2783 #endif // _LP64
2784   }
2785 }
2786 
2787 
2788 void LIR_Assembler::align_call(LIR_Code code) {
2789   // make sure that the displacement word of the call ends up word aligned
2790   int offset = __ offset();
2791   switch (code) {
2792   case lir_static_call:
2793   case lir_optvirtual_call:
2794   case lir_dynamic_call:
2795     offset += NativeCall::displacement_offset;
2796     break;
2797   case lir_icvirtual_call:
2798     offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2799     break;
2800   case lir_virtual_call:  // currently, sparc-specific for niagara
2801   default: ShouldNotReachHere();
2802   }
2803   __ align(BytesPerWord, offset);
2804 }
2805 
2806 
2807 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2808   assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2809          "must be aligned");
2810   __ call(AddressLiteral(op->addr(), rtype));
2811   add_call_info(code_offset(), op->info());
2812 }
2813 
2814 
2815 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2816   __ ic_call(op->addr());
2817   add_call_info(code_offset(), op->info());
2818   assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2819          "must be aligned");
2820 }
2821 
2822 
2823 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2824 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2825   ShouldNotReachHere();
2826 }
2827 
2828 
2829 void LIR_Assembler::emit_static_call_stub() {
2830   address call_pc = __ pc();
2831   address stub = __ start_a_stub(call_stub_size());
2832   if (stub == NULL) {
2833     bailout("static call stub overflow");
2834     return;
2835   }
2836 
2837   int start = __ offset();
2838 
2839   // make sure that the displacement word of the call ends up word aligned
2840   __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2841   __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2842   __ mov_metadata(rbx, (Metadata*)NULL);
2843   // must be set to -1 at code generation time
2844   assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2845   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2846   __ jump(RuntimeAddress(__ pc()));
2847 
2848   if (UseAOT) {
2849     // Trampoline to aot code
2850     __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2851 #ifdef _LP64
2852     __ mov64(rax, CONST64(0));  // address is zapped till fixup time.
2853 #else
2854     __ movl(rax, 0xdeadffff);  // address is zapped till fixup time.
2855 #endif
2856     __ jmp(rax);
2857   }
2858   assert(__ offset() - start <= call_stub_size(), "stub too big");
2859   __ end_a_stub();
2860 }
2861 
2862 
2863 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2864   assert(exceptionOop->as_register() == rax, "must match");
2865   assert(exceptionPC->as_register() == rdx, "must match");
2866 
2867   // exception object is not added to oop map by LinearScan
2868   // (LinearScan assumes that no oops are in fixed registers)
2869   info->add_register_oop(exceptionOop);
2870   Runtime1::StubID unwind_id;
2871 
2872   // get current pc information
2873   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2874   int pc_for_athrow_offset = __ offset();
2875   InternalAddress pc_for_athrow(__ pc());
2876   __ lea(exceptionPC->as_register(), pc_for_athrow);
2877   add_call_info(pc_for_athrow_offset, info); // for exception handler
2878 
2879   __ verify_not_null_oop(rax);
2880   // search an exception handler (rax: exception oop, rdx: throwing pc)
2881   if (compilation()->has_fpu_code()) {
2882     unwind_id = Runtime1::handle_exception_id;
2883   } else {
2884     unwind_id = Runtime1::handle_exception_nofpu_id;
2885   }
2886   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2887 
2888   // enough room for two byte trap
2889   __ nop();
2890 }
2891 
2892 
2893 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2894   assert(exceptionOop->as_register() == rax, "must match");
2895 
2896   __ jmp(_unwind_handler_entry);
2897 }
2898 
2899 
2900 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2901 
2902   // optimized version for linear scan:
2903   // * count must be already in ECX (guaranteed by LinearScan)
2904   // * left and dest must be equal
2905   // * tmp must be unused
2906   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2907   assert(left == dest, "left and dest must be equal");
2908   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2909 
2910   if (left->is_single_cpu()) {
2911     Register value = left->as_register();
2912     assert(value != SHIFT_count, "left cannot be ECX");
2913 
2914     switch (code) {
2915       case lir_shl:  __ shll(value); break;
2916       case lir_shr:  __ sarl(value); break;
2917       case lir_ushr: __ shrl(value); break;
2918       default: ShouldNotReachHere();
2919     }
2920   } else if (left->is_double_cpu()) {
2921     Register lo = left->as_register_lo();
2922     Register hi = left->as_register_hi();
2923     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2924 #ifdef _LP64
2925     switch (code) {
2926       case lir_shl:  __ shlptr(lo);        break;
2927       case lir_shr:  __ sarptr(lo);        break;
2928       case lir_ushr: __ shrptr(lo);        break;
2929       default: ShouldNotReachHere();
2930     }
2931 #else
2932 
2933     switch (code) {
2934       case lir_shl:  __ lshl(hi, lo);        break;
2935       case lir_shr:  __ lshr(hi, lo, true);  break;
2936       case lir_ushr: __ lshr(hi, lo, false); break;
2937       default: ShouldNotReachHere();
2938     }
2939 #endif // LP64
2940   } else {
2941     ShouldNotReachHere();
2942   }
2943 }
2944 
2945 
2946 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2947   if (dest->is_single_cpu()) {
2948     // first move left into dest so that left is not destroyed by the shift
2949     Register value = dest->as_register();
2950     count = count & 0x1F; // Java spec
2951 
2952     move_regs(left->as_register(), value);
2953     switch (code) {
2954       case lir_shl:  __ shll(value, count); break;
2955       case lir_shr:  __ sarl(value, count); break;
2956       case lir_ushr: __ shrl(value, count); break;
2957       default: ShouldNotReachHere();
2958     }
2959   } else if (dest->is_double_cpu()) {
2960 #ifndef _LP64
2961     Unimplemented();
2962 #else
2963     // first move left into dest so that left is not destroyed by the shift
2964     Register value = dest->as_register_lo();
2965     count = count & 0x1F; // Java spec
2966 
2967     move_regs(left->as_register_lo(), value);
2968     switch (code) {
2969       case lir_shl:  __ shlptr(value, count); break;
2970       case lir_shr:  __ sarptr(value, count); break;
2971       case lir_ushr: __ shrptr(value, count); break;
2972       default: ShouldNotReachHere();
2973     }
2974 #endif // _LP64
2975   } else {
2976     ShouldNotReachHere();
2977   }
2978 }
2979 
2980 
2981 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2982   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2983   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2984   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2985   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2986 }
2987 
2988 
2989 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2990   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2991   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2992   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2993   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2994 }
2995 
2996 
2997 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2998   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2999   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3000   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3001   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3002 }
3003 
3004 
3005 void LIR_Assembler::store_parameter(Metadata* m,  int offset_from_rsp_in_words) {
3006   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3007   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3008   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3009   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3010 }
3011 
3012 
3013 // This code replaces a call to arraycopy; no exception may
3014 // be thrown in this code, they must be thrown in the System.arraycopy
3015 // activation frame; we could save some checks if this would not be the case
3016 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3017   ciArrayKlass* default_type = op->expected_type();
3018   Register src = op->src()->as_register();
3019   Register dst = op->dst()->as_register();
3020   Register src_pos = op->src_pos()->as_register();
3021   Register dst_pos = op->dst_pos()->as_register();
3022   Register length  = op->length()->as_register();
3023   Register tmp = op->tmp()->as_register();
3024 
3025   __ resolve(ACCESS_READ, src);
3026   __ resolve(ACCESS_WRITE, dst);
3027 
3028   CodeStub* stub = op->stub();
3029   int flags = op->flags();
3030   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3031   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3032 
3033   // if we don't know anything, just go through the generic arraycopy
3034   if (default_type == NULL) {
3035     // save outgoing arguments on stack in case call to System.arraycopy is needed
3036     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3037     // for interpreter calling conventions. Now we have to do it in new style conventions.
3038     // For the moment until C1 gets the new register allocator I just force all the
3039     // args to the right place (except the register args) and then on the back side
3040     // reload the register args properly if we go slow path. Yuck
3041 
3042     // These are proper for the calling convention
3043     store_parameter(length, 2);
3044     store_parameter(dst_pos, 1);
3045     store_parameter(dst, 0);
3046 
3047     // these are just temporary placements until we need to reload
3048     store_parameter(src_pos, 3);
3049     store_parameter(src, 4);
3050     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3051 
3052     address copyfunc_addr = StubRoutines::generic_arraycopy();
3053     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3054 
3055     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3056 #ifdef _LP64
3057     // The arguments are in java calling convention so we can trivially shift them to C
3058     // convention
3059     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3060     __ mov(c_rarg0, j_rarg0);
3061     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3062     __ mov(c_rarg1, j_rarg1);
3063     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3064     __ mov(c_rarg2, j_rarg2);
3065     assert_different_registers(c_rarg3, j_rarg4);
3066     __ mov(c_rarg3, j_rarg3);
3067 #ifdef _WIN64
3068     // Allocate abi space for args but be sure to keep stack aligned
3069     __ subptr(rsp, 6*wordSize);
3070     store_parameter(j_rarg4, 4);
3071 #ifndef PRODUCT
3072     if (PrintC1Statistics) {
3073       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3074     }
3075 #endif
3076     __ call(RuntimeAddress(copyfunc_addr));
3077     __ addptr(rsp, 6*wordSize);
3078 #else
3079     __ mov(c_rarg4, j_rarg4);
3080 #ifndef PRODUCT
3081     if (PrintC1Statistics) {
3082       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3083     }
3084 #endif
3085     __ call(RuntimeAddress(copyfunc_addr));
3086 #endif // _WIN64
3087 #else
3088     __ push(length);
3089     __ push(dst_pos);
3090     __ push(dst);
3091     __ push(src_pos);
3092     __ push(src);
3093 
3094 #ifndef PRODUCT
3095     if (PrintC1Statistics) {
3096       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3097     }
3098 #endif
3099     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3100 
3101 #endif // _LP64
3102 
3103     __ cmpl(rax, 0);
3104     __ jcc(Assembler::equal, *stub->continuation());
3105 
3106     __ mov(tmp, rax);
3107     __ xorl(tmp, -1);
3108 
3109     // Reload values from the stack so they are where the stub
3110     // expects them.
3111     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3112     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3113     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3114     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3115     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3116 
3117     __ subl(length, tmp);
3118     __ addl(src_pos, tmp);
3119     __ addl(dst_pos, tmp);
3120     __ jmp(*stub->entry());
3121 
3122     __ bind(*stub->continuation());
3123     return;
3124   }
3125 
3126   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3127 
3128   int elem_size = type2aelembytes(basic_type);
3129   Address::ScaleFactor scale;
3130 
3131   switch (elem_size) {
3132     case 1 :
3133       scale = Address::times_1;
3134       break;
3135     case 2 :
3136       scale = Address::times_2;
3137       break;
3138     case 4 :
3139       scale = Address::times_4;
3140       break;
3141     case 8 :
3142       scale = Address::times_8;
3143       break;
3144     default:
3145       scale = Address::no_scale;
3146       ShouldNotReachHere();
3147   }
3148 
3149   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3150   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3151   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3152   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3153 
3154   // length and pos's are all sign extended at this point on 64bit
3155 
3156   // test for NULL
3157   if (flags & LIR_OpArrayCopy::src_null_check) {
3158     __ testptr(src, src);
3159     __ jcc(Assembler::zero, *stub->entry());
3160   }
3161   if (flags & LIR_OpArrayCopy::dst_null_check) {
3162     __ testptr(dst, dst);
3163     __ jcc(Assembler::zero, *stub->entry());
3164   }
3165 
3166   // If the compiler was not able to prove that exact type of the source or the destination
3167   // of the arraycopy is an array type, check at runtime if the source or the destination is
3168   // an instance type.
3169   if (flags & LIR_OpArrayCopy::type_check) {
3170     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3171       __ load_klass(tmp, dst);
3172       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3173       __ jcc(Assembler::greaterEqual, *stub->entry());
3174     }
3175 
3176     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3177       __ load_klass(tmp, src);
3178       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3179       __ jcc(Assembler::greaterEqual, *stub->entry());
3180     }
3181   }
3182 
3183   // check if negative
3184   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3185     __ testl(src_pos, src_pos);
3186     __ jcc(Assembler::less, *stub->entry());
3187   }
3188   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3189     __ testl(dst_pos, dst_pos);
3190     __ jcc(Assembler::less, *stub->entry());
3191   }
3192 
3193   if (flags & LIR_OpArrayCopy::src_range_check) {
3194     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3195     __ cmpl(tmp, src_length_addr);
3196     __ jcc(Assembler::above, *stub->entry());
3197   }
3198   if (flags & LIR_OpArrayCopy::dst_range_check) {
3199     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3200     __ cmpl(tmp, dst_length_addr);
3201     __ jcc(Assembler::above, *stub->entry());
3202   }
3203 
3204   if (flags & LIR_OpArrayCopy::length_positive_check) {
3205     __ testl(length, length);
3206     __ jcc(Assembler::less, *stub->entry());
3207   }
3208 
3209 #ifdef _LP64
3210   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3211   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3212 #endif
3213 
3214   if (flags & LIR_OpArrayCopy::type_check) {
3215     // We don't know the array types are compatible
3216     if (basic_type != T_OBJECT) {
3217       // Simple test for basic type arrays
3218       if (UseCompressedClassPointers) {
3219         __ movl(tmp, src_klass_addr);
3220         __ cmpl(tmp, dst_klass_addr);
3221       } else {
3222         __ movptr(tmp, src_klass_addr);
3223         __ cmpptr(tmp, dst_klass_addr);
3224       }
3225       __ jcc(Assembler::notEqual, *stub->entry());
3226     } else {
3227       // For object arrays, if src is a sub class of dst then we can
3228       // safely do the copy.
3229       Label cont, slow;
3230 
3231       __ push(src);
3232       __ push(dst);
3233 
3234       __ load_klass(src, src);
3235       __ load_klass(dst, dst);
3236 
3237       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3238 
3239       __ push(src);
3240       __ push(dst);
3241       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3242       __ pop(dst);
3243       __ pop(src);
3244 
3245       __ cmpl(src, 0);
3246       __ jcc(Assembler::notEqual, cont);
3247 
3248       __ bind(slow);
3249       __ pop(dst);
3250       __ pop(src);
3251 
3252       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3253       if (copyfunc_addr != NULL) { // use stub if available
3254         // src is not a sub class of dst so we have to do a
3255         // per-element check.
3256 
3257         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3258         if ((flags & mask) != mask) {
3259           // Check that at least both of them object arrays.
3260           assert(flags & mask, "one of the two should be known to be an object array");
3261 
3262           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3263             __ load_klass(tmp, src);
3264           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3265             __ load_klass(tmp, dst);
3266           }
3267           int lh_offset = in_bytes(Klass::layout_helper_offset());
3268           Address klass_lh_addr(tmp, lh_offset);
3269           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3270           __ cmpl(klass_lh_addr, objArray_lh);
3271           __ jcc(Assembler::notEqual, *stub->entry());
3272         }
3273 
3274        // Spill because stubs can use any register they like and it's
3275        // easier to restore just those that we care about.
3276        store_parameter(dst, 0);
3277        store_parameter(dst_pos, 1);
3278        store_parameter(length, 2);
3279        store_parameter(src_pos, 3);
3280        store_parameter(src, 4);
3281 
3282 #ifndef _LP64
3283         __ movptr(tmp, dst_klass_addr);
3284         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3285         __ push(tmp);
3286         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3287         __ push(tmp);
3288         __ push(length);
3289         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3290         __ push(tmp);
3291         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3292         __ push(tmp);
3293 
3294         __ call_VM_leaf(copyfunc_addr, 5);
3295 #else
3296         __ movl2ptr(length, length); //higher 32bits must be null
3297 
3298         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3299         assert_different_registers(c_rarg0, dst, dst_pos, length);
3300         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3301         assert_different_registers(c_rarg1, dst, length);
3302 
3303         __ mov(c_rarg2, length);
3304         assert_different_registers(c_rarg2, dst);
3305 
3306 #ifdef _WIN64
3307         // Allocate abi space for args but be sure to keep stack aligned
3308         __ subptr(rsp, 6*wordSize);
3309         __ load_klass(c_rarg3, dst);
3310         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3311         store_parameter(c_rarg3, 4);
3312         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3313         __ call(RuntimeAddress(copyfunc_addr));
3314         __ addptr(rsp, 6*wordSize);
3315 #else
3316         __ load_klass(c_rarg4, dst);
3317         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3318         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3319         __ call(RuntimeAddress(copyfunc_addr));
3320 #endif
3321 
3322 #endif
3323 
3324 #ifndef PRODUCT
3325         if (PrintC1Statistics) {
3326           Label failed;
3327           __ testl(rax, rax);
3328           __ jcc(Assembler::notZero, failed);
3329           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3330           __ bind(failed);
3331         }
3332 #endif
3333 
3334         __ testl(rax, rax);
3335         __ jcc(Assembler::zero, *stub->continuation());
3336 
3337 #ifndef PRODUCT
3338         if (PrintC1Statistics) {
3339           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3340         }
3341 #endif
3342 
3343         __ mov(tmp, rax);
3344 
3345         __ xorl(tmp, -1);
3346 
3347         // Restore previously spilled arguments
3348         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3349         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3350         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3351         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3352         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3353 
3354 
3355         __ subl(length, tmp);
3356         __ addl(src_pos, tmp);
3357         __ addl(dst_pos, tmp);
3358       }
3359 
3360       __ jmp(*stub->entry());
3361 
3362       __ bind(cont);
3363       __ pop(dst);
3364       __ pop(src);
3365     }
3366   }
3367 
3368 #ifdef ASSERT
3369   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3370     // Sanity check the known type with the incoming class.  For the
3371     // primitive case the types must match exactly with src.klass and
3372     // dst.klass each exactly matching the default type.  For the
3373     // object array case, if no type check is needed then either the
3374     // dst type is exactly the expected type and the src type is a
3375     // subtype which we can't check or src is the same array as dst
3376     // but not necessarily exactly of type default_type.
3377     Label known_ok, halt;
3378     __ mov_metadata(tmp, default_type->constant_encoding());
3379 #ifdef _LP64
3380     if (UseCompressedClassPointers) {
3381       __ encode_klass_not_null(tmp);
3382     }
3383 #endif
3384 
3385     if (basic_type != T_OBJECT) {
3386 
3387       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3388       else                   __ cmpptr(tmp, dst_klass_addr);
3389       __ jcc(Assembler::notEqual, halt);
3390       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3391       else                   __ cmpptr(tmp, src_klass_addr);
3392       __ jcc(Assembler::equal, known_ok);
3393     } else {
3394       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3395       else                   __ cmpptr(tmp, dst_klass_addr);
3396       __ jcc(Assembler::equal, known_ok);
3397       __ cmpptr(src, dst);
3398       __ jcc(Assembler::equal, known_ok);
3399     }
3400     __ bind(halt);
3401     __ stop("incorrect type information in arraycopy");
3402     __ bind(known_ok);
3403   }
3404 #endif
3405 
3406 #ifndef PRODUCT
3407   if (PrintC1Statistics) {
3408     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3409   }
3410 #endif
3411 
3412 #ifdef _LP64
3413   assert_different_registers(c_rarg0, dst, dst_pos, length);
3414   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3415   assert_different_registers(c_rarg1, length);
3416   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3417   __ mov(c_rarg2, length);
3418 
3419 #else
3420   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3421   store_parameter(tmp, 0);
3422   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3423   store_parameter(tmp, 1);
3424   store_parameter(length, 2);
3425 #endif // _LP64
3426 
3427   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3428   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3429   const char *name;
3430   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3431   __ call_VM_leaf(entry, 0);
3432 
3433   __ bind(*stub->continuation());
3434 }
3435 
3436 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3437   assert(op->crc()->is_single_cpu(),  "crc must be register");
3438   assert(op->val()->is_single_cpu(),  "byte value must be register");
3439   assert(op->result_opr()->is_single_cpu(), "result must be register");
3440   Register crc = op->crc()->as_register();
3441   Register val = op->val()->as_register();
3442   Register res = op->result_opr()->as_register();
3443 
3444   assert_different_registers(val, crc, res);
3445 
3446   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3447   __ notl(crc); // ~crc
3448   __ update_byte_crc32(crc, val, res);
3449   __ notl(crc); // ~crc
3450   __ mov(res, crc);
3451 }
3452 
3453 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3454   Register obj = op->obj_opr()->as_register();  // may not be an oop
3455   Register hdr = op->hdr_opr()->as_register();
3456   Register lock = op->lock_opr()->as_register();
3457   if (!UseFastLocking) {
3458     __ jmp(*op->stub()->entry());
3459   } else if (op->code() == lir_lock) {
3460     Register scratch = noreg;
3461     if (UseBiasedLocking) {
3462       scratch = op->scratch_opr()->as_register();
3463     }
3464     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3465     __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3466     // add debug info for NullPointerException only if one is possible
3467     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3468     if (op->info() != NULL) {
3469       add_debug_info_for_null_check(null_check_offset, op->info());
3470     }
3471     // done
3472   } else if (op->code() == lir_unlock) {
3473     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3474     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3475   } else {
3476     Unimplemented();
3477   }
3478   __ bind(*op->stub()->continuation());
3479 }
3480 
3481 
3482 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3483   ciMethod* method = op->profiled_method();
3484   int bci          = op->profiled_bci();
3485   ciMethod* callee = op->profiled_callee();
3486 
3487   // Update counter for all call types
3488   ciMethodData* md = method->method_data_or_null();
3489   assert(md != NULL, "Sanity");
3490   ciProfileData* data = md->bci_to_data(bci);
3491   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3492   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3493   Register mdo  = op->mdo()->as_register();
3494   __ mov_metadata(mdo, md->constant_encoding());
3495   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3496   // Perform additional virtual call profiling for invokevirtual and
3497   // invokeinterface bytecodes
3498   if (op->should_profile_receiver_type()) {
3499     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3500     Register recv = op->recv()->as_register();
3501     assert_different_registers(mdo, recv);
3502     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3503     ciKlass* known_klass = op->known_holder();
3504     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3505       // We know the type that will be seen at this call site; we can
3506       // statically update the MethodData* rather than needing to do
3507       // dynamic tests on the receiver type
3508 
3509       // NOTE: we should probably put a lock around this search to
3510       // avoid collisions by concurrent compilations
3511       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3512       uint i;
3513       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3514         ciKlass* receiver = vc_data->receiver(i);
3515         if (known_klass->equals(receiver)) {
3516           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3517           __ addptr(data_addr, DataLayout::counter_increment);
3518           return;
3519         }
3520       }
3521 
3522       // Receiver type not found in profile data; select an empty slot
3523 
3524       // Note that this is less efficient than it should be because it
3525       // always does a write to the receiver part of the
3526       // VirtualCallData rather than just the first time
3527       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3528         ciKlass* receiver = vc_data->receiver(i);
3529         if (receiver == NULL) {
3530           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3531           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3532           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3533           __ addptr(data_addr, DataLayout::counter_increment);
3534           return;
3535         }
3536       }
3537     } else {
3538       __ load_klass(recv, recv);
3539       Label update_done;
3540       type_profile_helper(mdo, md, data, recv, &update_done);
3541       // Receiver did not match any saved receiver and there is no empty row for it.
3542       // Increment total counter to indicate polymorphic case.
3543       __ addptr(counter_addr, DataLayout::counter_increment);
3544 
3545       __ bind(update_done);
3546     }
3547   } else {
3548     // Static call
3549     __ addptr(counter_addr, DataLayout::counter_increment);
3550   }
3551 }
3552 
3553 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3554   Register obj = op->obj()->as_register();
3555   Register tmp = op->tmp()->as_pointer_register();
3556   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3557   ciKlass* exact_klass = op->exact_klass();
3558   intptr_t current_klass = op->current_klass();
3559   bool not_null = op->not_null();
3560   bool no_conflict = op->no_conflict();
3561 
3562   Label update, next, none;
3563 
3564   bool do_null = !not_null;
3565   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3566   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3567 
3568   assert(do_null || do_update, "why are we here?");
3569   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3570 
3571   __ verify_oop(obj);
3572 
3573   if (tmp != obj) {
3574     __ mov(tmp, obj);
3575   }
3576   if (do_null) {
3577     __ testptr(tmp, tmp);
3578     __ jccb(Assembler::notZero, update);
3579     if (!TypeEntries::was_null_seen(current_klass)) {
3580       __ orptr(mdo_addr, TypeEntries::null_seen);
3581     }
3582     if (do_update) {
3583 #ifndef ASSERT
3584       __ jmpb(next);
3585     }
3586 #else
3587       __ jmp(next);
3588     }
3589   } else {
3590     __ testptr(tmp, tmp);
3591     __ jcc(Assembler::notZero, update);
3592     __ stop("unexpect null obj");
3593 #endif
3594   }
3595 
3596   __ bind(update);
3597 
3598   if (do_update) {
3599 #ifdef ASSERT
3600     if (exact_klass != NULL) {
3601       Label ok;
3602       __ load_klass(tmp, tmp);
3603       __ push(tmp);
3604       __ mov_metadata(tmp, exact_klass->constant_encoding());
3605       __ cmpptr(tmp, Address(rsp, 0));
3606       __ jcc(Assembler::equal, ok);
3607       __ stop("exact klass and actual klass differ");
3608       __ bind(ok);
3609       __ pop(tmp);
3610     }
3611 #endif
3612     if (!no_conflict) {
3613       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3614         if (exact_klass != NULL) {
3615           __ mov_metadata(tmp, exact_klass->constant_encoding());
3616         } else {
3617           __ load_klass(tmp, tmp);
3618         }
3619 
3620         __ xorptr(tmp, mdo_addr);
3621         __ testptr(tmp, TypeEntries::type_klass_mask);
3622         // klass seen before, nothing to do. The unknown bit may have been
3623         // set already but no need to check.
3624         __ jccb(Assembler::zero, next);
3625 
3626         __ testptr(tmp, TypeEntries::type_unknown);
3627         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3628 
3629         if (TypeEntries::is_type_none(current_klass)) {
3630           __ cmpptr(mdo_addr, 0);
3631           __ jccb(Assembler::equal, none);
3632           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3633           __ jccb(Assembler::equal, none);
3634           // There is a chance that the checks above (re-reading profiling
3635           // data from memory) fail if another thread has just set the
3636           // profiling to this obj's klass
3637           __ xorptr(tmp, mdo_addr);
3638           __ testptr(tmp, TypeEntries::type_klass_mask);
3639           __ jccb(Assembler::zero, next);
3640         }
3641       } else {
3642         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3643                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3644 
3645         __ movptr(tmp, mdo_addr);
3646         __ testptr(tmp, TypeEntries::type_unknown);
3647         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3648       }
3649 
3650       // different than before. Cannot keep accurate profile.
3651       __ orptr(mdo_addr, TypeEntries::type_unknown);
3652 
3653       if (TypeEntries::is_type_none(current_klass)) {
3654         __ jmpb(next);
3655 
3656         __ bind(none);
3657         // first time here. Set profile type.
3658         __ movptr(mdo_addr, tmp);
3659       }
3660     } else {
3661       // There's a single possible klass at this profile point
3662       assert(exact_klass != NULL, "should be");
3663       if (TypeEntries::is_type_none(current_klass)) {
3664         __ mov_metadata(tmp, exact_klass->constant_encoding());
3665         __ xorptr(tmp, mdo_addr);
3666         __ testptr(tmp, TypeEntries::type_klass_mask);
3667 #ifdef ASSERT
3668         __ jcc(Assembler::zero, next);
3669 
3670         {
3671           Label ok;
3672           __ push(tmp);
3673           __ cmpptr(mdo_addr, 0);
3674           __ jcc(Assembler::equal, ok);
3675           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3676           __ jcc(Assembler::equal, ok);
3677           // may have been set by another thread
3678           __ mov_metadata(tmp, exact_klass->constant_encoding());
3679           __ xorptr(tmp, mdo_addr);
3680           __ testptr(tmp, TypeEntries::type_mask);
3681           __ jcc(Assembler::zero, ok);
3682 
3683           __ stop("unexpected profiling mismatch");
3684           __ bind(ok);
3685           __ pop(tmp);
3686         }
3687 #else
3688         __ jccb(Assembler::zero, next);
3689 #endif
3690         // first time here. Set profile type.
3691         __ movptr(mdo_addr, tmp);
3692       } else {
3693         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3694                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3695 
3696         __ movptr(tmp, mdo_addr);
3697         __ testptr(tmp, TypeEntries::type_unknown);
3698         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3699 
3700         __ orptr(mdo_addr, TypeEntries::type_unknown);
3701       }
3702     }
3703 
3704     __ bind(next);
3705   }
3706 }
3707 
3708 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3709   Unimplemented();
3710 }
3711 
3712 
3713 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3714   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3715 }
3716 
3717 
3718 void LIR_Assembler::align_backward_branch_target() {
3719   __ align(BytesPerWord);
3720 }
3721 
3722 
3723 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3724   if (left->is_single_cpu()) {
3725     __ negl(left->as_register());
3726     move_regs(left->as_register(), dest->as_register());
3727 
3728   } else if (left->is_double_cpu()) {
3729     Register lo = left->as_register_lo();
3730 #ifdef _LP64
3731     Register dst = dest->as_register_lo();
3732     __ movptr(dst, lo);
3733     __ negptr(dst);
3734 #else
3735     Register hi = left->as_register_hi();
3736     __ lneg(hi, lo);
3737     if (dest->as_register_lo() == hi) {
3738       assert(dest->as_register_hi() != lo, "destroying register");
3739       move_regs(hi, dest->as_register_hi());
3740       move_regs(lo, dest->as_register_lo());
3741     } else {
3742       move_regs(lo, dest->as_register_lo());
3743       move_regs(hi, dest->as_register_hi());
3744     }
3745 #endif // _LP64
3746 
3747   } else if (dest->is_single_xmm()) {
3748     if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3749       __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3750     }
3751     if (UseAVX > 0) {
3752       __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3753                    ExternalAddress((address)float_signflip_pool));
3754     } else {
3755       __ xorps(dest->as_xmm_float_reg(),
3756                ExternalAddress((address)float_signflip_pool));
3757     }
3758   } else if (dest->is_double_xmm()) {
3759     if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3760       __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3761     }
3762     if (UseAVX > 0) {
3763       __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3764                    ExternalAddress((address)double_signflip_pool));
3765     } else {
3766       __ xorpd(dest->as_xmm_double_reg(),
3767                ExternalAddress((address)double_signflip_pool));
3768     }
3769   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3770     assert(left->fpu() == 0, "arg must be on TOS");
3771     assert(dest->fpu() == 0, "dest must be TOS");
3772     __ fchs();
3773 
3774   } else {
3775     ShouldNotReachHere();
3776   }
3777 }
3778 
3779 
3780 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3781   assert(src->is_address(), "must be an address");
3782   assert(dest->is_register(), "must be a register");
3783 
3784   PatchingStub* patch = NULL;
3785   if (patch_code != lir_patch_none) {
3786     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3787   }
3788 
3789   Register reg = dest->as_pointer_register();
3790   LIR_Address* addr = src->as_address_ptr();
3791   __ lea(reg, as_Address(addr));
3792 
3793   if (patch != NULL) {
3794     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3795   }
3796 }
3797 
3798 
3799 
3800 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3801   assert(!tmp->is_valid(), "don't need temporary");
3802   __ call(RuntimeAddress(dest));
3803   if (info != NULL) {
3804     add_call_info_here(info);
3805   }
3806 }
3807 
3808 
3809 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3810   assert(type == T_LONG, "only for volatile long fields");
3811 
3812   if (info != NULL) {
3813     add_debug_info_for_null_check_here(info);
3814   }
3815 
3816   if (src->is_double_xmm()) {
3817     if (dest->is_double_cpu()) {
3818 #ifdef _LP64
3819       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3820 #else
3821       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3822       __ psrlq(src->as_xmm_double_reg(), 32);
3823       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3824 #endif // _LP64
3825     } else if (dest->is_double_stack()) {
3826       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3827     } else if (dest->is_address()) {
3828       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3829     } else {
3830       ShouldNotReachHere();
3831     }
3832 
3833   } else if (dest->is_double_xmm()) {
3834     if (src->is_double_stack()) {
3835       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3836     } else if (src->is_address()) {
3837       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3838     } else {
3839       ShouldNotReachHere();
3840     }
3841 
3842   } else if (src->is_double_fpu()) {
3843     assert(src->fpu_regnrLo() == 0, "must be TOS");
3844     if (dest->is_double_stack()) {
3845       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3846     } else if (dest->is_address()) {
3847       __ fistp_d(as_Address(dest->as_address_ptr()));
3848     } else {
3849       ShouldNotReachHere();
3850     }
3851 
3852   } else if (dest->is_double_fpu()) {
3853     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3854     if (src->is_double_stack()) {
3855       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3856     } else if (src->is_address()) {
3857       __ fild_d(as_Address(src->as_address_ptr()));
3858     } else {
3859       ShouldNotReachHere();
3860     }
3861   } else {
3862     ShouldNotReachHere();
3863   }
3864 }
3865 
3866 #ifdef ASSERT
3867 // emit run-time assertion
3868 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3869   assert(op->code() == lir_assert, "must be");
3870 
3871   if (op->in_opr1()->is_valid()) {
3872     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3873     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3874   } else {
3875     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3876     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3877   }
3878 
3879   Label ok;
3880   if (op->condition() != lir_cond_always) {
3881     Assembler::Condition acond = Assembler::zero;
3882     switch (op->condition()) {
3883       case lir_cond_equal:        acond = Assembler::equal;       break;
3884       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3885       case lir_cond_less:         acond = Assembler::less;        break;
3886       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3887       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3888       case lir_cond_greater:      acond = Assembler::greater;     break;
3889       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3890       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3891       default:                    ShouldNotReachHere();
3892     }
3893     __ jcc(acond, ok);
3894   }
3895   if (op->halt()) {
3896     const char* str = __ code_string(op->msg());
3897     __ stop(str);
3898   } else {
3899     breakpoint();
3900   }
3901   __ bind(ok);
3902 }
3903 #endif
3904 
3905 void LIR_Assembler::membar() {
3906   // QQQ sparc TSO uses this,
3907   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3908 }
3909 
3910 void LIR_Assembler::membar_acquire() {
3911   // No x86 machines currently require load fences
3912 }
3913 
3914 void LIR_Assembler::membar_release() {
3915   // No x86 machines currently require store fences
3916 }
3917 
3918 void LIR_Assembler::membar_loadload() {
3919   // no-op
3920   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3921 }
3922 
3923 void LIR_Assembler::membar_storestore() {
3924   // no-op
3925   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3926 }
3927 
3928 void LIR_Assembler::membar_loadstore() {
3929   // no-op
3930   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3931 }
3932 
3933 void LIR_Assembler::membar_storeload() {
3934   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3935 }
3936 
3937 void LIR_Assembler::on_spin_wait() {
3938   __ pause ();
3939 }
3940 
3941 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3942   assert(result_reg->is_register(), "check");
3943 #ifdef _LP64
3944   // __ get_thread(result_reg->as_register_lo());
3945   __ mov(result_reg->as_register(), r15_thread);
3946 #else
3947   __ get_thread(result_reg->as_register());
3948 #endif // _LP64
3949 }
3950 
3951 
3952 void LIR_Assembler::peephole(LIR_List*) {
3953   // do nothing for now
3954 }
3955 
3956 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3957   assert(data == dest, "xchg/xadd uses only 2 operands");
3958 
3959   if (data->type() == T_INT) {
3960     if (code == lir_xadd) {
3961       __ lock();
3962       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3963     } else {
3964       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3965     }
3966   } else if (data->is_oop()) {
3967     assert (code == lir_xchg, "xadd for oops");
3968     Register obj = data->as_register();
3969 #ifdef _LP64
3970     if (UseCompressedOops) {
3971       __ encode_heap_oop(obj);
3972       __ xchgl(obj, as_Address(src->as_address_ptr()));
3973       __ decode_heap_oop(obj);
3974     } else {
3975       __ xchgptr(obj, as_Address(src->as_address_ptr()));
3976     }
3977 #else
3978     __ xchgl(obj, as_Address(src->as_address_ptr()));
3979 #endif
3980   } else if (data->type() == T_LONG) {
3981 #ifdef _LP64
3982     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3983     if (code == lir_xadd) {
3984       __ lock();
3985       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3986     } else {
3987       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3988     }
3989 #else
3990     ShouldNotReachHere();
3991 #endif
3992   } else {
3993     ShouldNotReachHere();
3994   }
3995 }
3996 
3997 #undef __