1 /*
2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_HPP
26 #define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_HPP
27
28 // Included in orderAccess.hpp header file.
29
30 #include "runtime/os.hpp"
31 #include "vm_version_arm.hpp"
32
33 // Implementation of class OrderAccess.
34 // - we define the high level barriers below and use the general
35 // implementation in orderAccess.hpp, with customizations
36 // on AARCH64 via the specialized_* template functions
37
38 // Memory Ordering on ARM is weak.
39 //
40 // Implement all 4 memory ordering barriers by DMB, since it is a
41 // lighter version of DSB.
42 // dmb_sy implies full system shareability domain. RD/WR access type.
43 // dmb_st implies full system shareability domain. WR only access type.
44 //
45 // NOP on < ARMv6 (MP not supported)
46 //
47 // Non mcr instructions can be used if we build for armv7 or higher arch
48 // __asm__ __volatile__ ("dmb" : : : "memory");
49 // __asm__ __volatile__ ("dsb" : : : "memory");
50 //
51 // inline void _OrderAccess_dsb() {
52 // volatile intptr_t dummy = 0;
53 // __asm__ volatile (
54 // "mcr p15, 0, %0, c7, c10, 4"
55 // : : "r" (dummy) : "memory");
56 // }
57
58 inline static void dmb_sy() {
59 #ifdef AARCH64
60 __asm__ __volatile__ ("dmb sy" : : : "memory");
61 #else
62 if (VM_Version::arm_arch() >= 7) {
63 #ifdef __thumb__
64 __asm__ volatile (
65 "dmb sy": : : "memory");
66 #else
67 __asm__ volatile (
68 ".word 0xF57FF050 | 0xf" : : : "memory");
69 #endif
70 } else {
71 intptr_t zero = 0;
72 __asm__ volatile (
73 "mcr p15, 0, %0, c7, c10, 5"
74 : : "r" (zero) : "memory");
75 }
76 #endif
77 }
78
79 inline static void dmb_st() {
80 #ifdef AARCH64
81 __asm__ __volatile__ ("dmb st" : : : "memory");
82 #else
83 if (VM_Version::arm_arch() >= 7) {
84 #ifdef __thumb__
85 __asm__ volatile (
86 "dmb st": : : "memory");
87 #else
88 __asm__ volatile (
89 ".word 0xF57FF050 | 0xe" : : : "memory");
90 #endif
91 } else {
92 intptr_t zero = 0;
93 __asm__ volatile (
94 "mcr p15, 0, %0, c7, c10, 5"
95 : : "r" (zero) : "memory");
96 }
97 #endif
98 }
99
100 // Load-Load/Store barrier
101 inline static void dmb_ld() {
102 #ifdef AARCH64
103 __asm__ __volatile__ ("dmb ld" : : : "memory");
104 #else
105 dmb_sy();
106 #endif
107 }
108
109
110 inline void OrderAccess::loadload() { dmb_ld(); }
111 inline void OrderAccess::loadstore() { dmb_ld(); }
112 inline void OrderAccess::acquire() { dmb_ld(); }
113 inline void OrderAccess::storestore() { dmb_st(); }
114 inline void OrderAccess::storeload() { dmb_sy(); }
115 inline void OrderAccess::release() { dmb_sy(); }
116 inline void OrderAccess::fence() { dmb_sy(); }
117
118 // specializations for Aarch64
119 // TODO-AARCH64: evaluate effectiveness of ldar*/stlr* implementations compared to 32-bit ARM approach
120
121 #ifdef AARCH64
122
123 template<>
124 struct OrderAccess::PlatformOrderedLoad<1, X_ACQUIRE>
125 {
126 template <typename T>
127 T operator()(const volatile T* p) const {
128 volatile T result;
129 __asm__ volatile(
130 "ldarb %w[res], [%[ptr]]"
131 : [res] "=&r" (result)
132 : [ptr] "r" (p)
133 : "memory");
134 return result;
135 }
136 };
137
138 template<>
139 struct OrderAccess::PlatformOrderedLoad<2, X_ACQUIRE>
140 {
141 template <typename T>
142 T operator()(const volatile T* p) const {
143 volatile T result;
144 __asm__ volatile(
145 "ldarh %w[res], [%[ptr]]"
146 : [res] "=&r" (result)
147 : [ptr] "r" (p)
148 : "memory");
149 return result;
150 }
151 };
152
153 template<>
154 struct OrderAccess::PlatformOrderedLoad<4, X_ACQUIRE>
155 {
156 template <typename T>
157 T operator()(const volatile T* p) const {
158 volatile T result;
159 __asm__ volatile(
160 "ldar %w[res], [%[ptr]]"
161 : [res] "=&r" (result)
162 : [ptr] "r" (p)
163 : "memory");
164 return result;
165 }
166 };
167
168 template<>
169 struct OrderAccess::PlatformOrderedLoad<8, X_ACQUIRE>
170 {
171 template <typename T>
172 T operator()(const volatile T* p) const {
173 volatile T result;
174 __asm__ volatile(
175 "ldar %[res], [%[ptr]]"
176 : [res] "=&r" (result)
177 : [ptr] "r" (p)
178 : "memory");
179 return result;
180 }
181 };
182
183 template<>
184 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE>
185 {
186 template <typename T>
187 void operator()(T v, volatile T* p) const {
188 __asm__ volatile(
189 "stlrb %w[val], [%[ptr]]"
190 :
191 : [ptr] "r" (p), [val] "r" (v)
192 : "memory");
193 }
194 };
195
196 template<>
197 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE>
198 {
199 template <typename T>
200 void operator()(T v, volatile T* p) const {
201 __asm__ volatile(
202 "stlrh %w[val], [%[ptr]]"
203 :
204 : [ptr] "r" (p), [val] "r" (v)
205 : "memory");
206 }
207 };
208
209 template<>
210 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE>
211 {
212 template <typename T>
213 void operator()(T v, volatile T* p) const {
214 __asm__ volatile(
215 "stlr %w[val], [%[ptr]]"
216 :
217 : [ptr] "r" (p), [val] "r" (v)
218 : "memory");
219 }
220 };
221
222 template<>
223 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE>
224 {
225 template <typename T>
226 void operator()(T v, volatile T* p) const {
227 __asm__ volatile(
228 "stlr %[val], [%[ptr]]"
229 :
230 : [ptr] "r" (p), [val] "r" (v)
231 : "memory");
232 }
233 };
234
235 #endif // AARCH64
236
237 #endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_HPP