1 /* 2 * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 */ 23 24 25 package org.graalvm.compiler.lir.amd64; 26 27 import static jdk.vm.ci.amd64.AMD64.k1; 28 import static jdk.vm.ci.amd64.AMD64.k2; 29 import static jdk.vm.ci.amd64.AMD64.rdi; 30 import static jdk.vm.ci.amd64.AMD64.rdx; 31 import static jdk.vm.ci.amd64.AMD64.rsi; 32 33 import static jdk.vm.ci.code.ValueUtil.asRegister; 34 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG; 35 36 import jdk.vm.ci.amd64.AMD64; 37 import org.graalvm.compiler.asm.Label; 38 import org.graalvm.compiler.asm.amd64.AMD64Address; 39 import org.graalvm.compiler.asm.amd64.AMD64Assembler; 40 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler; 41 import org.graalvm.compiler.core.common.LIRKind; 42 import org.graalvm.compiler.lir.LIRInstructionClass; 43 import org.graalvm.compiler.lir.Opcode; 44 import org.graalvm.compiler.lir.asm.CompilationResultBuilder; 45 import org.graalvm.compiler.lir.gen.LIRGeneratorTool; 46 47 import jdk.vm.ci.amd64.AMD64Kind; 48 import jdk.vm.ci.code.Register; 49 import jdk.vm.ci.meta.Value; 50 51 @Opcode("AMD64_STRING_INFLATE") 52 public final class AMD64StringLatin1InflateOp extends AMD64LIRInstruction { 53 public static final LIRInstructionClass<AMD64StringLatin1InflateOp> TYPE = LIRInstructionClass.create(AMD64StringLatin1InflateOp.class); 54 55 @Alive({REG}) private Value rsrc; 56 @Alive({REG}) private Value rdst; 57 @Alive({REG}) private Value rlen; 58 59 @Temp({REG}) private Value vtmp1; 60 @Temp({REG}) private Value rtmp2; 61 62 public AMD64StringLatin1InflateOp(LIRGeneratorTool tool, Value src, Value dst, Value len) { 63 super(TYPE); 64 65 assert asRegister(src).equals(rsi); 66 assert asRegister(dst).equals(rdi); 67 assert asRegister(len).equals(rdx); 68 69 rsrc = src; 70 rdst = dst; 71 rlen = len; 72 73 vtmp1 = tool.newVariable(LIRKind.value(AMD64Kind.V512_BYTE)); 74 rtmp2 = tool.newVariable(LIRKind.value(AMD64Kind.DWORD)); 75 } 76 77 @Override 78 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { 79 Register src = asRegister(rsrc); 80 Register dst = asRegister(rdst); 81 Register len = asRegister(rlen); 82 83 Register tmp1 = asRegister(vtmp1); 84 Register tmp2 = asRegister(rtmp2); 85 86 byteArrayInflate(masm, src, dst, len, tmp1, tmp2); 87 } 88 89 /** 90 * Inflate a Latin1 string using a byte[] array representation into a UTF16 string using a 91 * char[] array representation. 92 * 93 * @param masm the assembler 94 * @param src (rsi) the start address of source byte[] to be inflated 95 * @param dst (rdi) the start address of destination char[] array 96 * @param len (rdx) the length 97 * @param vtmp (xmm) temporary xmm register 98 * @param tmp (gpr) temporary gpr register 99 */ 100 private static void byteArrayInflate(AMD64MacroAssembler masm, Register src, Register dst, Register len, Register vtmp, Register tmp) { 101 assert vtmp.getRegisterCategory().equals(AMD64.XMM); 102 103 Label labelDone = new Label(); 104 Label labelBelowThreshold = new Label(); 105 106 assert src.number != dst.number && src.number != len.number && src.number != tmp.number; 107 assert dst.number != len.number && dst.number != tmp.number; 108 assert len.number != tmp.number; 109 110 if (masm.supports(AMD64.CPUFeature.AVX512BW) && 111 masm.supports(AMD64.CPUFeature.AVX512VL) && 112 masm.supports(AMD64.CPUFeature.BMI2)) { 113 114 // If the length of the string is less than 16, we chose not to use the 115 // AVX512 instructions. 116 masm.testl(len, -16); 117 masm.jcc(AMD64Assembler.ConditionFlag.Zero, labelBelowThreshold); 118 119 Label labelAvx512Tail = new Label(); 120 // Test for suitable number chunks with respect to the size of the vector 121 // operation, mask off remaining number of chars (bytes) to inflate (such 122 // that 'len' will always hold the number of bytes left to inflate) after 123 // committing to the vector loop. 124 // Adjust vector pointers to upper address bounds and inverse loop index. 125 // This will keep the loop condition simple. 126 // 127 // NOTE: The above idiom/pattern is used in all the loops below. 128 129 masm.movl(tmp, len); 130 masm.andl(tmp, -32); // The vector count (in chars). 131 masm.jccb(AMD64Assembler.ConditionFlag.Zero, labelAvx512Tail); 132 masm.andl(len, 32 - 1); // The tail count (in chars). 133 134 masm.leaq(src, new AMD64Address(src, tmp, AMD64Address.Scale.Times1)); 135 masm.leaq(dst, new AMD64Address(dst, tmp, AMD64Address.Scale.Times2)); 136 masm.negq(tmp); 137 138 Label labelAvx512Loop = new Label(); 139 // Inflate 32 chars per iteration, reading 256-bit compact vectors 140 // and writing 512-bit inflated ditto. 141 masm.bind(labelAvx512Loop); 142 masm.evpmovzxbw(vtmp, new AMD64Address(src, tmp, AMD64Address.Scale.Times1)); 143 masm.evmovdqu16(new AMD64Address(dst, tmp, AMD64Address.Scale.Times2), vtmp); 144 masm.addq(tmp, 32); 145 masm.jcc(AMD64Assembler.ConditionFlag.NotZero, labelAvx512Loop); 146 147 masm.bind(labelAvx512Tail); 148 // All done if the tail count is zero. 149 masm.testl(len, len); 150 masm.jcc(AMD64Assembler.ConditionFlag.Zero, labelDone); 151 152 masm.kmovq(k2, k1); // Save k1 153 154 // Compute (1 << N) - 1 = ~(~0 << N), where N is the remaining number 155 // of characters to process. 156 masm.movl(tmp, -1); 157 masm.shlxl(tmp, tmp, len); 158 masm.notl(tmp); 159 160 masm.kmovd(k1, tmp); 161 masm.evpmovzxbw(vtmp, k1, new AMD64Address(src)); 162 masm.evmovdqu16(new AMD64Address(dst), k1, vtmp); 163 masm.kmovq(k1, k2); // Restore k1 164 masm.jmp(labelDone); 165 } 166 167 if (masm.supports(AMD64.CPUFeature.SSE4_1)) { 168 169 Label labelSSETail = new Label(); 170 171 if (masm.supports(AMD64.CPUFeature.AVX2)) { 172 173 Label labelAvx2Tail = new Label(); 174 175 masm.movl(tmp, len); 176 masm.andl(tmp, -16); 177 masm.jccb(AMD64Assembler.ConditionFlag.Zero, labelAvx2Tail); 178 masm.andl(len, 16 - 1); 179 180 masm.leaq(src, new AMD64Address(src, tmp, AMD64Address.Scale.Times1)); 181 masm.leaq(dst, new AMD64Address(dst, tmp, AMD64Address.Scale.Times2)); 182 masm.negq(tmp); 183 184 Label labelAvx2Loop = new Label(); 185 // Inflate 16 bytes (chars) per iteration, reading 128-bit compact vectors 186 // and writing 256-bit inflated ditto. 187 masm.bind(labelAvx2Loop); 188 masm.vpmovzxbw(vtmp, new AMD64Address(src, tmp, AMD64Address.Scale.Times1)); 189 masm.vmovdqu(new AMD64Address(dst, tmp, AMD64Address.Scale.Times2), vtmp); 190 masm.addq(tmp, 16); 191 masm.jcc(AMD64Assembler.ConditionFlag.NotZero, labelAvx2Loop); 192 193 masm.bind(labelBelowThreshold); 194 masm.bind(labelAvx2Tail); 195 196 masm.movl(tmp, len); 197 masm.andl(tmp, -8); 198 masm.jccb(AMD64Assembler.ConditionFlag.Zero, labelSSETail); 199 masm.andl(len, 8 - 1); 200 201 // Inflate another 8 bytes before final tail copy. 202 masm.pmovzxbw(vtmp, new AMD64Address(src)); 203 masm.movdqu(new AMD64Address(dst), vtmp); 204 masm.addq(src, 8); 205 masm.addq(dst, 16); 206 207 // Fall-through to labelSSETail. 208 } else { 209 // When there is no AVX2 support available, we use AVX/SSE support to 210 // inflate into maximum 128-bits per operation. 211 212 masm.movl(tmp, len); 213 masm.andl(tmp, -8); 214 masm.jccb(AMD64Assembler.ConditionFlag.Zero, labelSSETail); 215 masm.andl(len, 8 - 1); 216 217 masm.leaq(src, new AMD64Address(src, tmp, AMD64Address.Scale.Times1)); 218 masm.leaq(dst, new AMD64Address(dst, tmp, AMD64Address.Scale.Times2)); 219 masm.negq(tmp); 220 221 Label labelSSECopy8Loop = new Label(); 222 // Inflate 8 bytes (chars) per iteration, reading 64-bit compact vectors 223 // and writing 128-bit inflated ditto. 224 masm.bind(labelSSECopy8Loop); 225 masm.pmovzxbw(vtmp, new AMD64Address(src, tmp, AMD64Address.Scale.Times1)); 226 masm.movdqu(new AMD64Address(dst, tmp, AMD64Address.Scale.Times2), vtmp); 227 masm.addq(tmp, 8); 228 masm.jcc(AMD64Assembler.ConditionFlag.NotZero, labelSSECopy8Loop); 229 230 // Fall-through to labelSSETail. 231 } 232 233 Label labelCopyChars = new Label(); 234 235 masm.bind(labelSSETail); 236 masm.cmpl(len, 4); 237 masm.jccb(AMD64Assembler.ConditionFlag.Less, labelCopyChars); 238 239 masm.movdl(vtmp, new AMD64Address(src)); 240 masm.pmovzxbw(vtmp, vtmp); 241 masm.movq(new AMD64Address(dst), vtmp); 242 masm.subq(len, 4); 243 masm.addq(src, 4); 244 masm.addq(dst, 8); 245 246 masm.bind(labelCopyChars); 247 } 248 249 // Inflate any remaining characters (bytes) using a vanilla implementation. 250 masm.testl(len, len); 251 masm.jccb(AMD64Assembler.ConditionFlag.Zero, labelDone); 252 masm.leaq(src, new AMD64Address(src, len, AMD64Address.Scale.Times1)); 253 masm.leaq(dst, new AMD64Address(dst, len, AMD64Address.Scale.Times2)); 254 masm.negq(len); 255 256 Label labelCopyCharsLoop = new Label(); 257 // Inflate a single byte (char) per iteration. 258 masm.bind(labelCopyCharsLoop); 259 masm.movzbl(tmp, new AMD64Address(src, len, AMD64Address.Scale.Times1)); 260 masm.movw(new AMD64Address(dst, len, AMD64Address.Scale.Times2), tmp); 261 masm.incrementq(len, 1); 262 masm.jcc(AMD64Assembler.ConditionFlag.NotZero, labelCopyCharsLoop); 263 264 masm.bind(labelDone); 265 } 266 267 }