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src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/AMD64BaseAssembler.java

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rev 52889 : 8214023: Update Graal


 704                 // [00 reg 100][00 100 101] disp32
 705                 emitByte(0x04 | regenc);
 706                 emitByte(0x25);
 707                 emitInt(disp);
 708             }
 709         }
 710     }
 711 
 712     private interface SIMDEncoder {
 713 
 714         void simdPrefix(Register xreg, Register nds, AMD64Address adr, int sizePrefix, int opcodeEscapePrefix, boolean isRexW);
 715 
 716         void simdPrefix(Register dst, Register nds, Register src, int sizePrefix, int opcodeEscapePrefix, boolean isRexW);
 717 
 718     }
 719 
 720     private class SSEEncoderImpl implements SIMDEncoder {
 721 
 722         @Override
 723         public void simdPrefix(Register xreg, Register nds, AMD64Address adr, int sizePrefix, int opcodeEscapePrefix, boolean isRexW) {

 724             if (sizePrefix > 0) {
 725                 emitByte(sizePrefix);
 726             }
 727             if (isRexW) {
 728                 prefixq(adr, xreg);
 729             } else {
 730                 prefix(adr, xreg);
 731             }
 732             if (opcodeEscapePrefix > 0xFF) {
 733                 emitShort(opcodeEscapePrefix);
 734             } else if (opcodeEscapePrefix > 0) {
 735                 emitByte(opcodeEscapePrefix);
 736             }
 737         }
 738 
 739         @Override
 740         public void simdPrefix(Register dst, Register nds, Register src, int sizePrefix, int opcodeEscapePrefix, boolean isRexW) {

 741             if (sizePrefix > 0) {
 742                 emitByte(sizePrefix);
 743             }
 744             if (isRexW) {
 745                 prefixq(dst, src);
 746             } else {
 747                 prefix(dst, src);
 748             }
 749             if (opcodeEscapePrefix > 0xFF) {
 750                 emitShort(opcodeEscapePrefix);
 751             } else if (opcodeEscapePrefix > 0) {
 752                 emitByte(opcodeEscapePrefix);
 753             }
 754         }
 755     }
 756 
 757     public static final class VEXPrefixConfig {
 758         public static final int L128 = 0;
 759         public static final int L256 = 1;
 760         public static final int LZ = 0;




 704                 // [00 reg 100][00 100 101] disp32
 705                 emitByte(0x04 | regenc);
 706                 emitByte(0x25);
 707                 emitInt(disp);
 708             }
 709         }
 710     }
 711 
 712     private interface SIMDEncoder {
 713 
 714         void simdPrefix(Register xreg, Register nds, AMD64Address adr, int sizePrefix, int opcodeEscapePrefix, boolean isRexW);
 715 
 716         void simdPrefix(Register dst, Register nds, Register src, int sizePrefix, int opcodeEscapePrefix, boolean isRexW);
 717 
 718     }
 719 
 720     private class SSEEncoderImpl implements SIMDEncoder {
 721 
 722         @Override
 723         public void simdPrefix(Register xreg, Register nds, AMD64Address adr, int sizePrefix, int opcodeEscapePrefix, boolean isRexW) {
 724             assert (!nds.isValid()) || nds.equals(xreg);
 725             if (sizePrefix > 0) {
 726                 emitByte(sizePrefix);
 727             }
 728             if (isRexW) {
 729                 prefixq(adr, xreg);
 730             } else {
 731                 prefix(adr, xreg);
 732             }
 733             if (opcodeEscapePrefix > 0xFF) {
 734                 emitShort(opcodeEscapePrefix);
 735             } else if (opcodeEscapePrefix > 0) {
 736                 emitByte(opcodeEscapePrefix);
 737             }
 738         }
 739 
 740         @Override
 741         public void simdPrefix(Register dst, Register nds, Register src, int sizePrefix, int opcodeEscapePrefix, boolean isRexW) {
 742             assert (!nds.isValid()) || nds.equals(dst) || nds.equals(src);
 743             if (sizePrefix > 0) {
 744                 emitByte(sizePrefix);
 745             }
 746             if (isRexW) {
 747                 prefixq(dst, src);
 748             } else {
 749                 prefix(dst, src);
 750             }
 751             if (opcodeEscapePrefix > 0xFF) {
 752                 emitShort(opcodeEscapePrefix);
 753             } else if (opcodeEscapePrefix > 0) {
 754                 emitByte(opcodeEscapePrefix);
 755             }
 756         }
 757     }
 758 
 759     public static final class VEXPrefixConfig {
 760         public static final int L128 = 0;
 761         public static final int L256 = 1;
 762         public static final int LZ = 0;


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