1 //
2 // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers
173 reg_class all_reg(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP and RBP)
191 reg_class any_reg_with_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RBP, RBP_H,
194 RDI, RDI_H,
195 RSI, RSI_H,
196 RCX, RCX_H,
197 RBX, RBX_H,
198 RSP, RSP_H,
199 R8, R8_H,
200 R9, R9_H,
201 R10, R10_H,
202 R11, R11_H,
203 R12, R12_H,
204 R13, R13_H,
205 R14, R14_H,
206 R15, R15_H);
207
208 // Class for all pointer registers (including RSP, but excluding RBP)
209 reg_class any_reg_no_rbp(RAX, RAX_H,
210 RDX, RDX_H,
211 RDI, RDI_H,
212 RSI, RSI_H,
213 RCX, RCX_H,
214 RBX, RBX_H,
215 RSP, RSP_H,
216 R8, R8_H,
217 R9, R9_H,
218 R10, R10_H,
219 R11, R11_H,
220 R12, R12_H,
221 R13, R13_H,
222 R14, R14_H,
223 R15, R15_H);
224
225 // Dynamic register class that selects at runtime between register classes
226 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
227 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
228 reg_class_dynamic any_reg0(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
229
230 // Class for all pointer registers (excluding RSP)
231 reg_class ptr_reg_with_rbp(RAX, RAX_H,
232 RDX, RDX_H,
233 RBP, RBP_H,
234 RDI, RDI_H,
235 RSI, RSI_H,
236 RCX, RCX_H,
237 RBX, RBX_H,
238 R8, R8_H,
239 R9, R9_H,
240 R10, R10_H,
241 R11, R11_H,
242 R13, R13_H,
243 R14, R14_H);
244
245 // Class for all pointer registers (excluding RSP and RBP)
246 reg_class ptr_reg_no_rbp0(RAX, RAX_H,
247 RDX, RDX_H,
248 RDI, RDI_H,
249 RSI, RSI_H,
250 RCX, RCX_H,
251 RBX, RBX_H,
252 R8, R8_H,
253 R9, R9_H,
254 R10, R10_H,
255 R11, R11_H,
256 R13, R13_H,
257 R14, R14_H);
258
259 // Dynamic register class that selects between ptr_reg_no_rbp0 and ptr_reg_with_rbp.
260 reg_class_dynamic ptr_reg0(ptr_reg_no_rbp0, ptr_reg_with_rbp, %{ PreserveFramePointer %});
261
262 // Class for all pointer registers
263 reg_class any_reg %{
264 return _ANY_REG_mask;
265 %}
266
267 // Class for all pointer registers (excluding RSP)
268 reg_class ptr_reg %{
269 return _PTR_REG_mask;
270 %}
271
272 // Class for all pointer registers (excluding RSP and RBP)
273 reg_class ptr_reg_no_rbp %{
274 return _PTR_REG_NO_RBP_mask;
275 %}
276
277 // Class for all pointer registers (excluding RAX and RSP)
278 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
279 RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
290
291 // Class for all pointer registers (excluding RAX, RSP, and RBP)
292 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RCX, RCX_H,
296 RBX, RBX_H,
297 R8, R8_H,
298 R9, R9_H,
299 R10, R10_H,
300 R11, R11_H,
301 R13, R13_H,
302 R14, R14_H);
303
304 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
305 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
306
307 // Class for all pointer registers (excluding RAX, RBX, and RSP)
308 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
309 RBP, RBP_H,
310 RDI, RDI_H,
311 RSI, RSI_H,
312 RCX, RCX_H,
313 R8, R8_H,
314 R9, R9_H,
315 R10, R10_H,
316 R11, R11_H,
317 R13, R13_H,
318 R14, R14_H);
319
320 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
321 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
322 RDI, RDI_H,
323 RSI, RSI_H,
324 RCX, RCX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R13, R13_H,
330 R14, R14_H);
331
332 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
333 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
334
335 // Singleton class for RAX pointer register
336 reg_class ptr_rax_reg(RAX, RAX_H);
337
338 // Singleton class for RBX pointer register
339 reg_class ptr_rbx_reg(RBX, RBX_H);
340
341 // Singleton class for RSI pointer register
342 reg_class ptr_rsi_reg(RSI, RSI_H);
343
344 // Singleton class for RDI pointer register
345 reg_class ptr_rdi_reg(RDI, RDI_H);
346
347 // Singleton class for stack pointer
348 reg_class ptr_rsp_reg(RSP, RSP_H);
349
350 // Singleton class for TLS pointer
351 reg_class ptr_r15_reg(R15, R15_H);
352
353 // Class for all long registers (excluding RSP)
354 reg_class long_reg_with_rbp(RAX, RAX_H,
355 RDX, RDX_H,
356 RBP, RBP_H,
357 RDI, RDI_H,
358 RSI, RSI_H,
359 RCX, RCX_H,
360 RBX, RBX_H,
361 R8, R8_H,
362 R9, R9_H,
363 R10, R10_H,
364 R11, R11_H,
365 R13, R13_H,
366 R14, R14_H);
367
368 // Class for all long registers (excluding RSP and RBP)
369 reg_class long_reg_no_rbp(RAX, RAX_H,
370 RDX, RDX_H,
371 RDI, RDI_H,
372 RSI, RSI_H,
373 RCX, RCX_H,
374 RBX, RBX_H,
375 R8, R8_H,
376 R9, R9_H,
377 R10, R10_H,
378 R11, R11_H,
379 R13, R13_H,
380 R14, R14_H);
381
382 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
383 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
384
385 // Class for all long registers (excluding RAX, RDX and RSP)
386 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
387 RDI, RDI_H,
388 RSI, RSI_H,
389 RCX, RCX_H,
390 RBX, RBX_H,
391 R8, R8_H,
392 R9, R9_H,
393 R10, R10_H,
394 R11, R11_H,
395 R13, R13_H,
396 R14, R14_H);
397
398 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
399 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
400 RSI, RSI_H,
401 RCX, RCX_H,
402 RBX, RBX_H,
403 R8, R8_H,
404 R9, R9_H,
405 R10, R10_H,
406 R11, R11_H,
407 R13, R13_H,
408 R14, R14_H);
409
410 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
411 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
412
413 // Class for all long registers (excluding RCX and RSP)
414 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
415 RDI, RDI_H,
416 RSI, RSI_H,
417 RAX, RAX_H,
418 RDX, RDX_H,
419 RBX, RBX_H,
420 R8, R8_H,
421 R9, R9_H,
422 R10, R10_H,
423 R11, R11_H,
424 R13, R13_H,
425 R14, R14_H);
426
427 // Class for all long registers (excluding RCX, RSP, and RBP)
428 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
429 RSI, RSI_H,
430 RAX, RAX_H,
431 RDX, RDX_H,
432 RBX, RBX_H,
433 R8, R8_H,
434 R9, R9_H,
435 R10, R10_H,
436 R11, R11_H,
437 R13, R13_H,
438 R14, R14_H);
439
440 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
441 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
442
443 // Singleton class for RAX long register
444 reg_class long_rax_reg(RAX, RAX_H);
445
446 // Singleton class for RCX long register
447 reg_class long_rcx_reg(RCX, RCX_H);
448
449 // Singleton class for RDX long register
450 reg_class long_rdx_reg(RDX, RDX_H);
451
452 // Class for all int registers (excluding RSP)
453 reg_class int_reg_with_rbp(RAX,
454 RDX,
455 RBP,
456 RDI,
457 RSI,
458 RCX,
459 RBX,
460 R8,
461 R9,
462 R10,
463 R11,
464 R13,
465 R14);
466
467 // Class for all int registers (excluding RSP and RBP)
468 reg_class int_reg_no_rbp(RAX,
469 RDX,
470 RDI,
471 RSI,
472 RCX,
473 RBX,
474 R8,
475 R9,
476 R10,
477 R11,
478 R13,
479 R14);
480
481 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
482 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
483
484 // Class for all int registers (excluding RCX and RSP)
485 reg_class int_no_rcx_reg_with_rbp(RAX,
486 RDX,
487 RBP,
488 RDI,
489 RSI,
490 RBX,
491 R8,
492 R9,
493 R10,
494 R11,
495 R13,
496 R14);
497
498 // Class for all int registers (excluding RCX, RSP, and RBP)
499 reg_class int_no_rcx_reg_no_rbp(RAX,
500 RDX,
501 RDI,
502 RSI,
503 RBX,
504 R8,
505 R9,
506 R10,
507 R11,
508 R13,
509 R14);
510
511 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
512 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
513
514 // Class for all int registers (excluding RAX, RDX, and RSP)
515 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
516 RDI,
517 RSI,
518 RCX,
519 RBX,
520 R8,
521 R9,
522 R10,
523 R11,
524 R13,
525 R14);
526
527 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
528 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
529 RSI,
530 RCX,
531 RBX,
532 R8,
533 R9,
534 R10,
535 R11,
536 R13,
537 R14);
538
539 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
540 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
541
542 // Singleton class for RAX int register
543 reg_class int_rax_reg(RAX);
544
545 // Singleton class for RBX int register
546 reg_class int_rbx_reg(RBX);
547
548 // Singleton class for RCX int register
549 reg_class int_rcx_reg(RCX);
550
551 // Singleton class for RCX int register
552 reg_class int_rdx_reg(RDX);
553
554 // Singleton class for RCX int register
555 reg_class int_rdi_reg(RDI);
556
557 // Singleton class for instruction pointer
558 // reg_class ip_reg(RIP);
559
560 %}
561
562 //----------SOURCE BLOCK-------------------------------------------------------
563 // This is a block of C++ code which provides values, functions, and
564 // definitions necessary in the rest of the architecture description
565 source_hpp %{
566 extern RegMask _ANY_REG_mask;
567 extern RegMask _PTR_REG_mask;
568 extern RegMask _PTR_REG_NO_RBP_mask;
569 extern RegMask _STACK_OR_PTR_REG_mask;
570 inline const RegMask &STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
571 %}
572
573 source %{
574 #define RELOC_IMM64 Assembler::imm_operand
575 #define RELOC_DISP32 Assembler::disp32_operand
576
577 #define __ _masm.
578
579 RegMask _ANY_REG_mask;
580 RegMask _PTR_REG_mask;
581 RegMask _PTR_REG_NO_RBP_mask;
582 RegMask _STACK_OR_PTR_REG_mask;
583
584 #ifdef ASSERT
585 static bool same_mask(const RegMask &a, const RegMask &b) {
586 RegMask a_sub_b = a; a_sub_b.SUBTRACT(b);
587 RegMask b_sub_a = b; b_sub_a.SUBTRACT(a);
588 return a_sub_b.Size() == 0 && b_sub_a.Size() == 0;
589 }
590 #endif
591
592 void reg_mask_init() {
593 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
594 // We derive a number of subsets from it.
595 _ANY_REG_mask = _ALL_REG_mask;
596 if (PreserveFramePointer) {
597 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
598 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
599 }
600
601 _PTR_REG_mask = _ANY_REG_mask;
602 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15_thread->as_VMReg()));
603 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15_thread->as_VMReg()->next()));
604 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
605 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
606 if (UseCompressedOops || UseCompressedClassPointers || UseZGC) {
607 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r12_heapbase->as_VMReg()));
608 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r12_heapbase->as_VMReg()->next()));
609 }
610 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
611 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
612 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
613 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
614 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
615 assert(same_mask(_ANY_REG_mask, ANY_REG0_mask()), "!");
616 assert(same_mask(_PTR_REG_mask, PTR_REG0_mask()), "!");
617 assert(same_mask(_PTR_REG_NO_RBP_mask, PTR_REG_NO_RBP0_mask()), "!");
618 }
619
620 static bool generate_vzeroupper(Compile* C) {
621 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
622 }
623
624 static int clear_avx_size() {
625 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
626 }
627
628 // !!!!! Special hack to get all types of calls to specify the byte offset
629 // from the start of the call to the point where the return address
630 // will point.
631 int MachCallStaticJavaNode::ret_addr_offset()
632 {
633 int offset = 5; // 5 bytes from start of call to where return address points
634 offset += clear_avx_size();
635 return offset;
636 }
637
638 int MachCallDynamicJavaNode::ret_addr_offset()
639 {
640 int offset = 15; // 15 bytes from start of call to where return address points
641 offset += clear_avx_size();
642 return offset;
643 }
644
645 int MachCallRuntimeNode::ret_addr_offset() {
646 int offset = 13; // movq r10,#addr; callq (r10)
647 offset += clear_avx_size();
648 return offset;
649 }
650
651 // Indicate if the safepoint node needs the polling page as an input,
652 // it does if the polling page is more than disp32 away.
653 bool SafePointNode::needs_polling_address_input()
654 {
655 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
656 }
657
658 //
659 // Compute padding required for nodes which need alignment
660 //
661
662 // The address of the call instruction needs to be 4-byte aligned to
663 // ensure that it does not span a cache line so that it can be patched.
664 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
665 {
666 current_offset += clear_avx_size(); // skip vzeroupper
667 current_offset += 1; // skip call opcode byte
668 return align_up(current_offset, alignment_required()) - current_offset;
669 }
670
671 // The address of the call instruction needs to be 4-byte aligned to
672 // ensure that it does not span a cache line so that it can be patched.
673 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
674 {
675 current_offset += clear_avx_size(); // skip vzeroupper
676 current_offset += 11; // skip movq instruction + call opcode byte
677 return align_up(current_offset, alignment_required()) - current_offset;
678 }
679
680 // EMIT_RM()
681 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
682 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
683 cbuf.insts()->emit_int8(c);
684 }
685
686 // EMIT_CC()
687 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
688 unsigned char c = (unsigned char) (f1 | f2);
689 cbuf.insts()->emit_int8(c);
690 }
691
692 // EMIT_OPCODE()
693 void emit_opcode(CodeBuffer &cbuf, int code) {
694 cbuf.insts()->emit_int8((unsigned char) code);
695 }
696
697 // EMIT_OPCODE() w/ relocation information
698 void emit_opcode(CodeBuffer &cbuf,
699 int code, relocInfo::relocType reloc, int offset, int format)
700 {
701 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
702 emit_opcode(cbuf, code);
703 }
704
705 // EMIT_D8()
706 void emit_d8(CodeBuffer &cbuf, int d8) {
707 cbuf.insts()->emit_int8((unsigned char) d8);
708 }
709
710 // EMIT_D16()
711 void emit_d16(CodeBuffer &cbuf, int d16) {
712 cbuf.insts()->emit_int16(d16);
713 }
714
715 // EMIT_D32()
716 void emit_d32(CodeBuffer &cbuf, int d32) {
717 cbuf.insts()->emit_int32(d32);
718 }
719
720 // EMIT_D64()
721 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
722 cbuf.insts()->emit_int64(d64);
723 }
724
725 // emit 32 bit value and construct relocation entry from relocInfo::relocType
726 void emit_d32_reloc(CodeBuffer& cbuf,
727 int d32,
728 relocInfo::relocType reloc,
729 int format)
730 {
731 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
732 cbuf.relocate(cbuf.insts_mark(), reloc, format);
733 cbuf.insts()->emit_int32(d32);
734 }
735
736 // emit 32 bit value and construct relocation entry from RelocationHolder
737 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
738 #ifdef ASSERT
739 if (rspec.reloc()->type() == relocInfo::oop_type &&
740 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
741 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
742 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
743 }
744 #endif
745 cbuf.relocate(cbuf.insts_mark(), rspec, format);
746 cbuf.insts()->emit_int32(d32);
747 }
748
749 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
750 address next_ip = cbuf.insts_end() + 4;
751 emit_d32_reloc(cbuf, (int) (addr - next_ip),
752 external_word_Relocation::spec(addr),
753 RELOC_DISP32);
754 }
755
756
757 // emit 64 bit value and construct relocation entry from relocInfo::relocType
758 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
759 cbuf.relocate(cbuf.insts_mark(), reloc, format);
760 cbuf.insts()->emit_int64(d64);
761 }
762
763 // emit 64 bit value and construct relocation entry from RelocationHolder
764 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
765 #ifdef ASSERT
766 if (rspec.reloc()->type() == relocInfo::oop_type &&
767 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
768 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
769 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
770 "cannot embed scavengable oops in code");
771 }
772 #endif
773 cbuf.relocate(cbuf.insts_mark(), rspec, format);
774 cbuf.insts()->emit_int64(d64);
775 }
776
777 // Access stack slot for load or store
778 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
779 {
780 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
781 if (-0x80 <= disp && disp < 0x80) {
782 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
783 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
784 emit_d8(cbuf, disp); // Displacement // R/M byte
785 } else {
786 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
787 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
788 emit_d32(cbuf, disp); // Displacement // R/M byte
789 }
790 }
791
792 // rRegI ereg, memory mem) %{ // emit_reg_mem
793 void encode_RegMem(CodeBuffer &cbuf,
794 int reg,
795 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
796 {
797 assert(disp_reloc == relocInfo::none, "cannot have disp");
798 int regenc = reg & 7;
799 int baseenc = base & 7;
800 int indexenc = index & 7;
801
802 // There is no index & no scale, use form without SIB byte
803 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
804 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
805 if (disp == 0 && base != RBP_enc && base != R13_enc) {
806 emit_rm(cbuf, 0x0, regenc, baseenc); // *
807 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
808 // If 8-bit displacement, mode 0x1
809 emit_rm(cbuf, 0x1, regenc, baseenc); // *
810 emit_d8(cbuf, disp);
811 } else {
812 // If 32-bit displacement
813 if (base == -1) { // Special flag for absolute address
814 emit_rm(cbuf, 0x0, regenc, 0x5); // *
815 if (disp_reloc != relocInfo::none) {
816 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
817 } else {
818 emit_d32(cbuf, disp);
819 }
820 } else {
821 // Normal base + offset
822 emit_rm(cbuf, 0x2, regenc, baseenc); // *
823 if (disp_reloc != relocInfo::none) {
824 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
825 } else {
826 emit_d32(cbuf, disp);
827 }
828 }
829 }
830 } else {
831 // Else, encode with the SIB byte
832 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
833 if (disp == 0 && base != RBP_enc && base != R13_enc) {
834 // If no displacement
835 emit_rm(cbuf, 0x0, regenc, 0x4); // *
836 emit_rm(cbuf, scale, indexenc, baseenc);
837 } else {
838 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
839 // If 8-bit displacement, mode 0x1
840 emit_rm(cbuf, 0x1, regenc, 0x4); // *
841 emit_rm(cbuf, scale, indexenc, baseenc);
842 emit_d8(cbuf, disp);
843 } else {
844 // If 32-bit displacement
845 if (base == 0x04 ) {
846 emit_rm(cbuf, 0x2, regenc, 0x4);
847 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
848 } else {
849 emit_rm(cbuf, 0x2, regenc, 0x4);
850 emit_rm(cbuf, scale, indexenc, baseenc); // *
851 }
852 if (disp_reloc != relocInfo::none) {
853 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
854 } else {
855 emit_d32(cbuf, disp);
856 }
857 }
858 }
859 }
860 }
861
862 // This could be in MacroAssembler but it's fairly C2 specific
863 void emit_cmpfp_fixup(MacroAssembler& _masm) {
864 Label exit;
865 __ jccb(Assembler::noParity, exit);
866 __ pushf();
867 //
868 // comiss/ucomiss instructions set ZF,PF,CF flags and
869 // zero OF,AF,SF for NaN values.
870 // Fixup flags by zeroing ZF,PF so that compare of NaN
871 // values returns 'less than' result (CF is set).
872 // Leave the rest of flags unchanged.
873 //
874 // 7 6 5 4 3 2 1 0
875 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
876 // 0 0 1 0 1 0 1 1 (0x2B)
877 //
878 __ andq(Address(rsp, 0), 0xffffff2b);
879 __ popf();
880 __ bind(exit);
881 }
882
883 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
884 Label done;
885 __ movl(dst, -1);
886 __ jcc(Assembler::parity, done);
887 __ jcc(Assembler::below, done);
888 __ setb(Assembler::notEqual, dst);
889 __ movzbl(dst, dst);
890 __ bind(done);
891 }
892
893
894 //=============================================================================
895 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
896
897 int Compile::ConstantTable::calculate_table_base_offset() const {
898 return 0; // absolute addressing, no offset
899 }
900
901 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
902 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
903 ShouldNotReachHere();
904 }
905
906 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
907 // Empty encoding
908 }
909
910 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
911 return 0;
912 }
913
914 #ifndef PRODUCT
915 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
916 st->print("# MachConstantBaseNode (empty encoding)");
917 }
918 #endif
919
920
921 //=============================================================================
922 #ifndef PRODUCT
923 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
924 Compile* C = ra_->C;
925
926 int framesize = C->frame_size_in_bytes();
927 int bangsize = C->bang_size_in_bytes();
928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
929 // Remove wordSize for return addr which is already pushed.
930 framesize -= wordSize;
931
932 if (C->need_stack_bang(bangsize)) {
933 framesize -= wordSize;
934 st->print("# stack bang (%d bytes)", bangsize);
935 st->print("\n\t");
936 st->print("pushq rbp\t# Save rbp");
937 if (PreserveFramePointer) {
938 st->print("\n\t");
939 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
940 }
941 if (framesize) {
942 st->print("\n\t");
943 st->print("subq rsp, #%d\t# Create frame",framesize);
944 }
945 } else {
946 st->print("subq rsp, #%d\t# Create frame",framesize);
947 st->print("\n\t");
948 framesize -= wordSize;
949 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
950 if (PreserveFramePointer) {
951 st->print("\n\t");
952 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
953 if (framesize > 0) {
954 st->print("\n\t");
955 st->print("addq rbp, #%d", framesize);
956 }
957 }
958 }
959
960 if (VerifyStackAtCalls) {
961 st->print("\n\t");
962 framesize -= wordSize;
963 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
964 #ifdef ASSERT
965 st->print("\n\t");
966 st->print("# stack alignment check");
967 #endif
968 }
969 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
970 st->print("\n\t");
971 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
972 st->print("\n\t");
973 st->print("je fast_entry\t");
974 st->print("\n\t");
975 st->print("call #nmethod_entry_barrier_stub\t");
976 st->print("\n\tfast_entry:");
977 }
978 st->cr();
979 }
980 #endif
981
982 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
983 Compile* C = ra_->C;
984 MacroAssembler _masm(&cbuf);
985
986 int framesize = C->frame_size_in_bytes();
987 int bangsize = C->bang_size_in_bytes();
988
989 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
990
991 C->set_frame_complete(cbuf.insts_size());
992
993 if (C->has_mach_constant_base_node()) {
994 // NOTE: We set the table base offset here because users might be
995 // emitted before MachConstantBaseNode.
996 Compile::ConstantTable& constant_table = C->constant_table();
997 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
998 }
999 }
1000
1001 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1002 {
1003 return MachNode::size(ra_); // too many variables; just compute it
1004 // the hard way
1005 }
1006
1007 int MachPrologNode::reloc() const
1008 {
1009 return 0; // a large enough number
1010 }
1011
1012 //=============================================================================
1013 #ifndef PRODUCT
1014 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1015 {
1016 Compile* C = ra_->C;
1017 if (generate_vzeroupper(C)) {
1018 st->print("vzeroupper");
1019 st->cr(); st->print("\t");
1020 }
1021
1022 int framesize = C->frame_size_in_bytes();
1023 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1024 // Remove word for return adr already pushed
1025 // and RBP
1026 framesize -= 2*wordSize;
1027
1028 if (framesize) {
1029 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
1030 st->print("\t");
1031 }
1032
1033 st->print_cr("popq rbp");
1034 if (do_polling() && C->is_method_compilation()) {
1035 st->print("\t");
1036 if (SafepointMechanism::uses_thread_local_poll()) {
1037 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
1038 "testl rax, [rscratch1]\t"
1039 "# Safepoint: poll for GC");
1040 } else if (Assembler::is_polling_page_far()) {
1041 st->print_cr("movq rscratch1, #polling_page_address\n\t"
1042 "testl rax, [rscratch1]\t"
1043 "# Safepoint: poll for GC");
1044 } else {
1045 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
1046 "# Safepoint: poll for GC");
1047 }
1048 }
1049 }
1050 #endif
1051
1052 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1053 {
1054 Compile* C = ra_->C;
1055 MacroAssembler _masm(&cbuf);
1056
1057 if (generate_vzeroupper(C)) {
1058 // Clear upper bits of YMM registers when current compiled code uses
1059 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1060 __ vzeroupper();
1061 }
1062
1063 int framesize = C->frame_size_in_bytes();
1064 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1065 // Remove word for return adr already pushed
1066 // and RBP
1067 framesize -= 2*wordSize;
1068
1069 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1070
1071 if (framesize) {
1072 emit_opcode(cbuf, Assembler::REX_W);
1073 if (framesize < 0x80) {
1074 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1075 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1076 emit_d8(cbuf, framesize);
1077 } else {
1078 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1079 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1080 emit_d32(cbuf, framesize);
1081 }
1082 }
1083
1084 // popq rbp
1085 emit_opcode(cbuf, 0x58 | RBP_enc);
1086
1087 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1088 __ reserved_stack_check();
1089 }
1090
1091 if (do_polling() && C->is_method_compilation()) {
1092 MacroAssembler _masm(&cbuf);
1093 if (SafepointMechanism::uses_thread_local_poll()) {
1094 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1095 __ relocate(relocInfo::poll_return_type);
1096 __ testl(rax, Address(rscratch1, 0));
1097 } else {
1098 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1099 if (Assembler::is_polling_page_far()) {
1100 __ lea(rscratch1, polling_page);
1101 __ relocate(relocInfo::poll_return_type);
1102 __ testl(rax, Address(rscratch1, 0));
1103 } else {
1104 __ testl(rax, polling_page);
1105 }
1106 }
1107 }
1108 }
1109
1110 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1111 {
1112 return MachNode::size(ra_); // too many variables; just compute it
1113 // the hard way
1114 }
1115
1116 int MachEpilogNode::reloc() const
1117 {
1118 return 2; // a large enough number
1119 }
1120
1121 const Pipeline* MachEpilogNode::pipeline() const
1122 {
1123 return MachNode::pipeline_class();
1124 }
1125
1126 int MachEpilogNode::safepoint_offset() const
1127 {
1128 return 0;
1129 }
1130
1131 //=============================================================================
1132
1133 enum RC {
1134 rc_bad,
1135 rc_int,
1136 rc_float,
1137 rc_stack
1138 };
1139
1140 static enum RC rc_class(OptoReg::Name reg)
1141 {
1142 if( !OptoReg::is_valid(reg) ) return rc_bad;
1143
1144 if (OptoReg::is_stack(reg)) return rc_stack;
1145
1146 VMReg r = OptoReg::as_VMReg(reg);
1147
1148 if (r->is_Register()) return rc_int;
1149
1150 assert(r->is_XMMRegister(), "must be");
1151 return rc_float;
1152 }
1153
1154 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1155 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1156 int src_hi, int dst_hi, uint ireg, outputStream* st);
1157
1158 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1159 int stack_offset, int reg, uint ireg, outputStream* st);
1160
1161 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1162 int dst_offset, uint ireg, outputStream* st) {
1163 if (cbuf) {
1164 MacroAssembler _masm(cbuf);
1165 switch (ireg) {
1166 case Op_VecS:
1167 __ movq(Address(rsp, -8), rax);
1168 __ movl(rax, Address(rsp, src_offset));
1169 __ movl(Address(rsp, dst_offset), rax);
1170 __ movq(rax, Address(rsp, -8));
1171 break;
1172 case Op_VecD:
1173 __ pushq(Address(rsp, src_offset));
1174 __ popq (Address(rsp, dst_offset));
1175 break;
1176 case Op_VecX:
1177 __ pushq(Address(rsp, src_offset));
1178 __ popq (Address(rsp, dst_offset));
1179 __ pushq(Address(rsp, src_offset+8));
1180 __ popq (Address(rsp, dst_offset+8));
1181 break;
1182 case Op_VecY:
1183 __ vmovdqu(Address(rsp, -32), xmm0);
1184 __ vmovdqu(xmm0, Address(rsp, src_offset));
1185 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1186 __ vmovdqu(xmm0, Address(rsp, -32));
1187 break;
1188 case Op_VecZ:
1189 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1190 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1191 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1192 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1193 break;
1194 default:
1195 ShouldNotReachHere();
1196 }
1197 #ifndef PRODUCT
1198 } else {
1199 switch (ireg) {
1200 case Op_VecS:
1201 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1202 "movl rax, [rsp + #%d]\n\t"
1203 "movl [rsp + #%d], rax\n\t"
1204 "movq rax, [rsp - #8]",
1205 src_offset, dst_offset);
1206 break;
1207 case Op_VecD:
1208 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1209 "popq [rsp + #%d]",
1210 src_offset, dst_offset);
1211 break;
1212 case Op_VecX:
1213 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1214 "popq [rsp + #%d]\n\t"
1215 "pushq [rsp + #%d]\n\t"
1216 "popq [rsp + #%d]",
1217 src_offset, dst_offset, src_offset+8, dst_offset+8);
1218 break;
1219 case Op_VecY:
1220 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1221 "vmovdqu xmm0, [rsp + #%d]\n\t"
1222 "vmovdqu [rsp + #%d], xmm0\n\t"
1223 "vmovdqu xmm0, [rsp - #32]",
1224 src_offset, dst_offset);
1225 break;
1226 case Op_VecZ:
1227 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1228 "vmovdqu xmm0, [rsp + #%d]\n\t"
1229 "vmovdqu [rsp + #%d], xmm0\n\t"
1230 "vmovdqu xmm0, [rsp - #64]",
1231 src_offset, dst_offset);
1232 break;
1233 default:
1234 ShouldNotReachHere();
1235 }
1236 #endif
1237 }
1238 }
1239
1240 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1241 PhaseRegAlloc* ra_,
1242 bool do_size,
1243 outputStream* st) const {
1244 assert(cbuf != NULL || st != NULL, "sanity");
1245 // Get registers to move
1246 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1247 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1248 OptoReg::Name dst_second = ra_->get_reg_second(this);
1249 OptoReg::Name dst_first = ra_->get_reg_first(this);
1250
1251 enum RC src_second_rc = rc_class(src_second);
1252 enum RC src_first_rc = rc_class(src_first);
1253 enum RC dst_second_rc = rc_class(dst_second);
1254 enum RC dst_first_rc = rc_class(dst_first);
1255
1256 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1257 "must move at least 1 register" );
1258
1259 if (src_first == dst_first && src_second == dst_second) {
1260 // Self copy, no move
1261 return 0;
1262 }
1263 if (bottom_type()->isa_vect() != NULL) {
1264 uint ireg = ideal_reg();
1265 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1266 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1267 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1268 // mem -> mem
1269 int src_offset = ra_->reg2offset(src_first);
1270 int dst_offset = ra_->reg2offset(dst_first);
1271 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1272 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1273 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1274 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1275 int stack_offset = ra_->reg2offset(dst_first);
1276 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1277 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1278 int stack_offset = ra_->reg2offset(src_first);
1279 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1280 } else {
1281 ShouldNotReachHere();
1282 }
1283 return 0;
1284 }
1285 if (src_first_rc == rc_stack) {
1286 // mem ->
1287 if (dst_first_rc == rc_stack) {
1288 // mem -> mem
1289 assert(src_second != dst_first, "overlap");
1290 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1291 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1292 // 64-bit
1293 int src_offset = ra_->reg2offset(src_first);
1294 int dst_offset = ra_->reg2offset(dst_first);
1295 if (cbuf) {
1296 MacroAssembler _masm(cbuf);
1297 __ pushq(Address(rsp, src_offset));
1298 __ popq (Address(rsp, dst_offset));
1299 #ifndef PRODUCT
1300 } else {
1301 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1302 "popq [rsp + #%d]",
1303 src_offset, dst_offset);
1304 #endif
1305 }
1306 } else {
1307 // 32-bit
1308 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1309 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1310 // No pushl/popl, so:
1311 int src_offset = ra_->reg2offset(src_first);
1312 int dst_offset = ra_->reg2offset(dst_first);
1313 if (cbuf) {
1314 MacroAssembler _masm(cbuf);
1315 __ movq(Address(rsp, -8), rax);
1316 __ movl(rax, Address(rsp, src_offset));
1317 __ movl(Address(rsp, dst_offset), rax);
1318 __ movq(rax, Address(rsp, -8));
1319 #ifndef PRODUCT
1320 } else {
1321 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1322 "movl rax, [rsp + #%d]\n\t"
1323 "movl [rsp + #%d], rax\n\t"
1324 "movq rax, [rsp - #8]",
1325 src_offset, dst_offset);
1326 #endif
1327 }
1328 }
1329 return 0;
1330 } else if (dst_first_rc == rc_int) {
1331 // mem -> gpr
1332 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1333 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1334 // 64-bit
1335 int offset = ra_->reg2offset(src_first);
1336 if (cbuf) {
1337 MacroAssembler _masm(cbuf);
1338 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1339 #ifndef PRODUCT
1340 } else {
1341 st->print("movq %s, [rsp + #%d]\t# spill",
1342 Matcher::regName[dst_first],
1343 offset);
1344 #endif
1345 }
1346 } else {
1347 // 32-bit
1348 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1349 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1350 int offset = ra_->reg2offset(src_first);
1351 if (cbuf) {
1352 MacroAssembler _masm(cbuf);
1353 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1354 #ifndef PRODUCT
1355 } else {
1356 st->print("movl %s, [rsp + #%d]\t# spill",
1357 Matcher::regName[dst_first],
1358 offset);
1359 #endif
1360 }
1361 }
1362 return 0;
1363 } else if (dst_first_rc == rc_float) {
1364 // mem-> xmm
1365 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1366 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1367 // 64-bit
1368 int offset = ra_->reg2offset(src_first);
1369 if (cbuf) {
1370 MacroAssembler _masm(cbuf);
1371 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1372 #ifndef PRODUCT
1373 } else {
1374 st->print("%s %s, [rsp + #%d]\t# spill",
1375 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1376 Matcher::regName[dst_first],
1377 offset);
1378 #endif
1379 }
1380 } else {
1381 // 32-bit
1382 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1383 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1384 int offset = ra_->reg2offset(src_first);
1385 if (cbuf) {
1386 MacroAssembler _masm(cbuf);
1387 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1388 #ifndef PRODUCT
1389 } else {
1390 st->print("movss %s, [rsp + #%d]\t# spill",
1391 Matcher::regName[dst_first],
1392 offset);
1393 #endif
1394 }
1395 }
1396 return 0;
1397 }
1398 } else if (src_first_rc == rc_int) {
1399 // gpr ->
1400 if (dst_first_rc == rc_stack) {
1401 // gpr -> mem
1402 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1403 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1404 // 64-bit
1405 int offset = ra_->reg2offset(dst_first);
1406 if (cbuf) {
1407 MacroAssembler _masm(cbuf);
1408 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1409 #ifndef PRODUCT
1410 } else {
1411 st->print("movq [rsp + #%d], %s\t# spill",
1412 offset,
1413 Matcher::regName[src_first]);
1414 #endif
1415 }
1416 } else {
1417 // 32-bit
1418 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1419 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1420 int offset = ra_->reg2offset(dst_first);
1421 if (cbuf) {
1422 MacroAssembler _masm(cbuf);
1423 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1424 #ifndef PRODUCT
1425 } else {
1426 st->print("movl [rsp + #%d], %s\t# spill",
1427 offset,
1428 Matcher::regName[src_first]);
1429 #endif
1430 }
1431 }
1432 return 0;
1433 } else if (dst_first_rc == rc_int) {
1434 // gpr -> gpr
1435 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1436 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1437 // 64-bit
1438 if (cbuf) {
1439 MacroAssembler _masm(cbuf);
1440 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1441 as_Register(Matcher::_regEncode[src_first]));
1442 #ifndef PRODUCT
1443 } else {
1444 st->print("movq %s, %s\t# spill",
1445 Matcher::regName[dst_first],
1446 Matcher::regName[src_first]);
1447 #endif
1448 }
1449 return 0;
1450 } else {
1451 // 32-bit
1452 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1453 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1454 if (cbuf) {
1455 MacroAssembler _masm(cbuf);
1456 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1457 as_Register(Matcher::_regEncode[src_first]));
1458 #ifndef PRODUCT
1459 } else {
1460 st->print("movl %s, %s\t# spill",
1461 Matcher::regName[dst_first],
1462 Matcher::regName[src_first]);
1463 #endif
1464 }
1465 return 0;
1466 }
1467 } else if (dst_first_rc == rc_float) {
1468 // gpr -> xmm
1469 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1470 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471 // 64-bit
1472 if (cbuf) {
1473 MacroAssembler _masm(cbuf);
1474 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1475 #ifndef PRODUCT
1476 } else {
1477 st->print("movdq %s, %s\t# spill",
1478 Matcher::regName[dst_first],
1479 Matcher::regName[src_first]);
1480 #endif
1481 }
1482 } else {
1483 // 32-bit
1484 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1485 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1486 if (cbuf) {
1487 MacroAssembler _masm(cbuf);
1488 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1489 #ifndef PRODUCT
1490 } else {
1491 st->print("movdl %s, %s\t# spill",
1492 Matcher::regName[dst_first],
1493 Matcher::regName[src_first]);
1494 #endif
1495 }
1496 }
1497 return 0;
1498 }
1499 } else if (src_first_rc == rc_float) {
1500 // xmm ->
1501 if (dst_first_rc == rc_stack) {
1502 // xmm -> mem
1503 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1504 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1505 // 64-bit
1506 int offset = ra_->reg2offset(dst_first);
1507 if (cbuf) {
1508 MacroAssembler _masm(cbuf);
1509 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1510 #ifndef PRODUCT
1511 } else {
1512 st->print("movsd [rsp + #%d], %s\t# spill",
1513 offset,
1514 Matcher::regName[src_first]);
1515 #endif
1516 }
1517 } else {
1518 // 32-bit
1519 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1520 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1521 int offset = ra_->reg2offset(dst_first);
1522 if (cbuf) {
1523 MacroAssembler _masm(cbuf);
1524 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1525 #ifndef PRODUCT
1526 } else {
1527 st->print("movss [rsp + #%d], %s\t# spill",
1528 offset,
1529 Matcher::regName[src_first]);
1530 #endif
1531 }
1532 }
1533 return 0;
1534 } else if (dst_first_rc == rc_int) {
1535 // xmm -> gpr
1536 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1537 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1538 // 64-bit
1539 if (cbuf) {
1540 MacroAssembler _masm(cbuf);
1541 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1542 #ifndef PRODUCT
1543 } else {
1544 st->print("movdq %s, %s\t# spill",
1545 Matcher::regName[dst_first],
1546 Matcher::regName[src_first]);
1547 #endif
1548 }
1549 } else {
1550 // 32-bit
1551 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1552 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1553 if (cbuf) {
1554 MacroAssembler _masm(cbuf);
1555 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1556 #ifndef PRODUCT
1557 } else {
1558 st->print("movdl %s, %s\t# spill",
1559 Matcher::regName[dst_first],
1560 Matcher::regName[src_first]);
1561 #endif
1562 }
1563 }
1564 return 0;
1565 } else if (dst_first_rc == rc_float) {
1566 // xmm -> xmm
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1568 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1569 // 64-bit
1570 if (cbuf) {
1571 MacroAssembler _masm(cbuf);
1572 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1573 #ifndef PRODUCT
1574 } else {
1575 st->print("%s %s, %s\t# spill",
1576 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1577 Matcher::regName[dst_first],
1578 Matcher::regName[src_first]);
1579 #endif
1580 }
1581 } else {
1582 // 32-bit
1583 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1584 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1585 if (cbuf) {
1586 MacroAssembler _masm(cbuf);
1587 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1588 #ifndef PRODUCT
1589 } else {
1590 st->print("%s %s, %s\t# spill",
1591 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1592 Matcher::regName[dst_first],
1593 Matcher::regName[src_first]);
1594 #endif
1595 }
1596 }
1597 return 0;
1598 }
1599 }
1600
1601 assert(0," foo ");
1602 Unimplemented();
1603 return 0;
1604 }
1605
1606 #ifndef PRODUCT
1607 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1608 implementation(NULL, ra_, false, st);
1609 }
1610 #endif
1611
1612 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1613 implementation(&cbuf, ra_, false, NULL);
1614 }
1615
1616 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1617 return MachNode::size(ra_);
1618 }
1619
1620 //=============================================================================
1621 #ifndef PRODUCT
1622 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1623 {
1624 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1625 int reg = ra_->get_reg_first(this);
1626 st->print("leaq %s, [rsp + #%d]\t# box lock",
1627 Matcher::regName[reg], offset);
1628 }
1629 #endif
1630
1631 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1632 {
1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1634 int reg = ra_->get_encode(this);
1635 if (offset >= 0x80) {
1636 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1637 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1638 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1639 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1640 emit_d32(cbuf, offset);
1641 } else {
1642 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1643 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1644 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1645 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1646 emit_d8(cbuf, offset);
1647 }
1648 }
1649
1650 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1651 {
1652 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1653 return (offset < 0x80) ? 5 : 8; // REX
1654 }
1655
1656 //=============================================================================
1657 #ifndef PRODUCT
1658 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1659 {
1660 if (UseCompressedClassPointers) {
1661 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1662 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1663 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1664 } else {
1665 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1666 "# Inline cache check");
1667 }
1668 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1669 st->print_cr("\tnop\t# nops to align entry point");
1670 }
1671 #endif
1672
1673 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1674 {
1675 MacroAssembler masm(&cbuf);
1676 uint insts_size = cbuf.insts_size();
1677 if (UseCompressedClassPointers) {
1678 masm.load_klass(rscratch1, j_rarg0);
1679 masm.cmpptr(rax, rscratch1);
1680 } else {
1681 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1682 }
1683
1684 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1685
1686 /* WARNING these NOPs are critical so that verified entry point is properly
1687 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1688 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1689 if (OptoBreakpoint) {
1690 // Leave space for int3
1691 nops_cnt -= 1;
1692 }
1693 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1694 if (nops_cnt > 0)
1695 masm.nop(nops_cnt);
1696 }
1697
1698 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1699 {
1700 return MachNode::size(ra_); // too many variables; just compute it
1701 // the hard way
1702 }
1703
1704
1705 //=============================================================================
1706
1707 int Matcher::regnum_to_fpu_offset(int regnum)
1708 {
1709 return regnum - 32; // The FP registers are in the second chunk
1710 }
1711
1712 // This is UltraSparc specific, true just means we have fast l2f conversion
1713 const bool Matcher::convL2FSupported(void) {
1714 return true;
1715 }
1716
1717 // Is this branch offset short enough that a short branch can be used?
1718 //
1719 // NOTE: If the platform does not provide any short branch variants, then
1720 // this method should return false for offset 0.
1721 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1722 // The passed offset is relative to address of the branch.
1723 // On 86 a branch displacement is calculated relative to address
1724 // of a next instruction.
1725 offset -= br_size;
1726
1727 // the short version of jmpConUCF2 contains multiple branches,
1728 // making the reach slightly less
1729 if (rule == jmpConUCF2_rule)
1730 return (-126 <= offset && offset <= 125);
1731 return (-128 <= offset && offset <= 127);
1732 }
1733
1734 const bool Matcher::isSimpleConstant64(jlong value) {
1735 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1736 //return value == (int) value; // Cf. storeImmL and immL32.
1737
1738 // Probably always true, even if a temp register is required.
1739 return true;
1740 }
1741
1742 // The ecx parameter to rep stosq for the ClearArray node is in words.
1743 const bool Matcher::init_array_count_is_in_bytes = false;
1744
1745 // No additional cost for CMOVL.
1746 const int Matcher::long_cmove_cost() { return 0; }
1747
1748 // No CMOVF/CMOVD with SSE2
1749 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1750
1751 // Does the CPU require late expand (see block.cpp for description of late expand)?
1752 const bool Matcher::require_postalloc_expand = false;
1753
1754 // Do we need to mask the count passed to shift instructions or does
1755 // the cpu only look at the lower 5/6 bits anyway?
1756 const bool Matcher::need_masked_shift_count = false;
1757
1758 bool Matcher::narrow_oop_use_complex_address() {
1759 assert(UseCompressedOops, "only for compressed oops code");
1760 return (LogMinObjAlignmentInBytes <= 3);
1761 }
1762
1763 bool Matcher::narrow_klass_use_complex_address() {
1764 assert(UseCompressedClassPointers, "only for compressed klass code");
1765 return (LogKlassAlignmentInBytes <= 3);
1766 }
1767
1768 bool Matcher::const_oop_prefer_decode() {
1769 // Prefer ConN+DecodeN over ConP.
1770 return true;
1771 }
1772
1773 bool Matcher::const_klass_prefer_decode() {
1774 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1775 // or condisider the following:
1776 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1777 //return Universe::narrow_klass_base() == NULL;
1778 return true;
1779 }
1780
1781 // Is it better to copy float constants, or load them directly from
1782 // memory? Intel can load a float constant from a direct address,
1783 // requiring no extra registers. Most RISCs will have to materialize
1784 // an address into a register first, so they would do better to copy
1785 // the constant from stack.
1786 const bool Matcher::rematerialize_float_constants = true; // XXX
1787
1788 // If CPU can load and store mis-aligned doubles directly then no
1789 // fixup is needed. Else we split the double into 2 integer pieces
1790 // and move it piece-by-piece. Only happens when passing doubles into
1791 // C code as the Java calling convention forces doubles to be aligned.
1792 const bool Matcher::misaligned_doubles_ok = true;
1793
1794 // No-op on amd64
1795 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1796
1797 // Advertise here if the CPU requires explicit rounding operations to
1798 // implement the UseStrictFP mode.
1799 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1800
1801 // Are floats conerted to double when stored to stack during deoptimization?
1802 // On x64 it is stored without convertion so we can use normal access.
1803 bool Matcher::float_in_double() { return false; }
1804
1805 // Do ints take an entire long register or just half?
1806 const bool Matcher::int_in_long = true;
1807
1808 // Return whether or not this register is ever used as an argument.
1809 // This function is used on startup to build the trampoline stubs in
1810 // generateOptoStub. Registers not mentioned will be killed by the VM
1811 // call in the trampoline, and arguments in those registers not be
1812 // available to the callee.
1813 bool Matcher::can_be_java_arg(int reg)
1814 {
1815 return
1816 reg == RDI_num || reg == RDI_H_num ||
1817 reg == RSI_num || reg == RSI_H_num ||
1818 reg == RDX_num || reg == RDX_H_num ||
1819 reg == RCX_num || reg == RCX_H_num ||
1820 reg == R8_num || reg == R8_H_num ||
1821 reg == R9_num || reg == R9_H_num ||
1822 reg == R12_num || reg == R12_H_num ||
1823 reg == XMM0_num || reg == XMM0b_num ||
1824 reg == XMM1_num || reg == XMM1b_num ||
1825 reg == XMM2_num || reg == XMM2b_num ||
1826 reg == XMM3_num || reg == XMM3b_num ||
1827 reg == XMM4_num || reg == XMM4b_num ||
1828 reg == XMM5_num || reg == XMM5b_num ||
1829 reg == XMM6_num || reg == XMM6b_num ||
1830 reg == XMM7_num || reg == XMM7b_num;
1831 }
1832
1833 bool Matcher::is_spillable_arg(int reg)
1834 {
1835 return can_be_java_arg(reg);
1836 }
1837
1838 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1839 // In 64 bit mode a code which use multiply when
1840 // devisor is constant is faster than hardware
1841 // DIV instruction (it uses MulHiL).
1842 return false;
1843 }
1844
1845 // Register for DIVI projection of divmodI
1846 RegMask Matcher::divI_proj_mask() {
1847 return INT_RAX_REG_mask();
1848 }
1849
1850 // Register for MODI projection of divmodI
1851 RegMask Matcher::modI_proj_mask() {
1852 return INT_RDX_REG_mask();
1853 }
1854
1855 // Register for DIVL projection of divmodL
1856 RegMask Matcher::divL_proj_mask() {
1857 return LONG_RAX_REG_mask();
1858 }
1859
1860 // Register for MODL projection of divmodL
1861 RegMask Matcher::modL_proj_mask() {
1862 return LONG_RDX_REG_mask();
1863 }
1864
1865 // Register for saving SP into on method handle invokes. Not used on x86_64.
1866 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1867 return NO_REG_mask();
1868 }
1869
1870 %}
1871
1872 //----------ENCODING BLOCK-----------------------------------------------------
1873 // This block specifies the encoding classes used by the compiler to
1874 // output byte streams. Encoding classes are parameterized macros
1875 // used by Machine Instruction Nodes in order to generate the bit
1876 // encoding of the instruction. Operands specify their base encoding
1877 // interface with the interface keyword. There are currently
1878 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1879 // COND_INTER. REG_INTER causes an operand to generate a function
1880 // which returns its register number when queried. CONST_INTER causes
1881 // an operand to generate a function which returns the value of the
1882 // constant when queried. MEMORY_INTER causes an operand to generate
1883 // four functions which return the Base Register, the Index Register,
1884 // the Scale Value, and the Offset Value of the operand when queried.
1885 // COND_INTER causes an operand to generate six functions which return
1886 // the encoding code (ie - encoding bits for the instruction)
1887 // associated with each basic boolean condition for a conditional
1888 // instruction.
1889 //
1890 // Instructions specify two basic values for encoding. Again, a
1891 // function is available to check if the constant displacement is an
1892 // oop. They use the ins_encode keyword to specify their encoding
1893 // classes (which must be a sequence of enc_class names, and their
1894 // parameters, specified in the encoding block), and they use the
1895 // opcode keyword to specify, in order, their primary, secondary, and
1896 // tertiary opcode. Only the opcode sections which a particular
1897 // instruction needs for encoding need to be specified.
1898 encode %{
1899 // Build emit functions for each basic byte or larger field in the
1900 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1901 // from C++ code in the enc_class source block. Emit functions will
1902 // live in the main source block for now. In future, we can
1903 // generalize this by adding a syntax that specifies the sizes of
1904 // fields in an order, so that the adlc can build the emit functions
1905 // automagically
1906
1907 // Emit primary opcode
1908 enc_class OpcP
1909 %{
1910 emit_opcode(cbuf, $primary);
1911 %}
1912
1913 // Emit secondary opcode
1914 enc_class OpcS
1915 %{
1916 emit_opcode(cbuf, $secondary);
1917 %}
1918
1919 // Emit tertiary opcode
1920 enc_class OpcT
1921 %{
1922 emit_opcode(cbuf, $tertiary);
1923 %}
1924
1925 // Emit opcode directly
1926 enc_class Opcode(immI d8)
1927 %{
1928 emit_opcode(cbuf, $d8$$constant);
1929 %}
1930
1931 // Emit size prefix
1932 enc_class SizePrefix
1933 %{
1934 emit_opcode(cbuf, 0x66);
1935 %}
1936
1937 enc_class reg(rRegI reg)
1938 %{
1939 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1940 %}
1941
1942 enc_class reg_reg(rRegI dst, rRegI src)
1943 %{
1944 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1945 %}
1946
1947 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1948 %{
1949 emit_opcode(cbuf, $opcode$$constant);
1950 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1951 %}
1952
1953 enc_class cdql_enc(no_rax_rdx_RegI div)
1954 %{
1955 // Full implementation of Java idiv and irem; checks for
1956 // special case as described in JVM spec., p.243 & p.271.
1957 //
1958 // normal case special case
1959 //
1960 // input : rax: dividend min_int
1961 // reg: divisor -1
1962 //
1963 // output: rax: quotient (= rax idiv reg) min_int
1964 // rdx: remainder (= rax irem reg) 0
1965 //
1966 // Code sequnce:
1967 //
1968 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1969 // 5: 75 07/08 jne e <normal>
1970 // 7: 33 d2 xor %edx,%edx
1971 // [div >= 8 -> offset + 1]
1972 // [REX_B]
1973 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1974 // c: 74 03/04 je 11 <done>
1975 // 000000000000000e <normal>:
1976 // e: 99 cltd
1977 // [div >= 8 -> offset + 1]
1978 // [REX_B]
1979 // f: f7 f9 idiv $div
1980 // 0000000000000011 <done>:
1981
1982 // cmp $0x80000000,%eax
1983 emit_opcode(cbuf, 0x3d);
1984 emit_d8(cbuf, 0x00);
1985 emit_d8(cbuf, 0x00);
1986 emit_d8(cbuf, 0x00);
1987 emit_d8(cbuf, 0x80);
1988
1989 // jne e <normal>
1990 emit_opcode(cbuf, 0x75);
1991 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1992
1993 // xor %edx,%edx
1994 emit_opcode(cbuf, 0x33);
1995 emit_d8(cbuf, 0xD2);
1996
1997 // cmp $0xffffffffffffffff,%ecx
1998 if ($div$$reg >= 8) {
1999 emit_opcode(cbuf, Assembler::REX_B);
2000 }
2001 emit_opcode(cbuf, 0x83);
2002 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2003 emit_d8(cbuf, 0xFF);
2004
2005 // je 11 <done>
2006 emit_opcode(cbuf, 0x74);
2007 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2008
2009 // <normal>
2010 // cltd
2011 emit_opcode(cbuf, 0x99);
2012
2013 // idivl (note: must be emitted by the user of this rule)
2014 // <done>
2015 %}
2016
2017 enc_class cdqq_enc(no_rax_rdx_RegL div)
2018 %{
2019 // Full implementation of Java ldiv and lrem; checks for
2020 // special case as described in JVM spec., p.243 & p.271.
2021 //
2022 // normal case special case
2023 //
2024 // input : rax: dividend min_long
2025 // reg: divisor -1
2026 //
2027 // output: rax: quotient (= rax idiv reg) min_long
2028 // rdx: remainder (= rax irem reg) 0
2029 //
2030 // Code sequnce:
2031 //
2032 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2033 // 7: 00 00 80
2034 // a: 48 39 d0 cmp %rdx,%rax
2035 // d: 75 08 jne 17 <normal>
2036 // f: 33 d2 xor %edx,%edx
2037 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2038 // 15: 74 05 je 1c <done>
2039 // 0000000000000017 <normal>:
2040 // 17: 48 99 cqto
2041 // 19: 48 f7 f9 idiv $div
2042 // 000000000000001c <done>:
2043
2044 // mov $0x8000000000000000,%rdx
2045 emit_opcode(cbuf, Assembler::REX_W);
2046 emit_opcode(cbuf, 0xBA);
2047 emit_d8(cbuf, 0x00);
2048 emit_d8(cbuf, 0x00);
2049 emit_d8(cbuf, 0x00);
2050 emit_d8(cbuf, 0x00);
2051 emit_d8(cbuf, 0x00);
2052 emit_d8(cbuf, 0x00);
2053 emit_d8(cbuf, 0x00);
2054 emit_d8(cbuf, 0x80);
2055
2056 // cmp %rdx,%rax
2057 emit_opcode(cbuf, Assembler::REX_W);
2058 emit_opcode(cbuf, 0x39);
2059 emit_d8(cbuf, 0xD0);
2060
2061 // jne 17 <normal>
2062 emit_opcode(cbuf, 0x75);
2063 emit_d8(cbuf, 0x08);
2064
2065 // xor %edx,%edx
2066 emit_opcode(cbuf, 0x33);
2067 emit_d8(cbuf, 0xD2);
2068
2069 // cmp $0xffffffffffffffff,$div
2070 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2071 emit_opcode(cbuf, 0x83);
2072 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2073 emit_d8(cbuf, 0xFF);
2074
2075 // je 1e <done>
2076 emit_opcode(cbuf, 0x74);
2077 emit_d8(cbuf, 0x05);
2078
2079 // <normal>
2080 // cqto
2081 emit_opcode(cbuf, Assembler::REX_W);
2082 emit_opcode(cbuf, 0x99);
2083
2084 // idivq (note: must be emitted by the user of this rule)
2085 // <done>
2086 %}
2087
2088 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2089 enc_class OpcSE(immI imm)
2090 %{
2091 // Emit primary opcode and set sign-extend bit
2092 // Check for 8-bit immediate, and set sign extend bit in opcode
2093 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2094 emit_opcode(cbuf, $primary | 0x02);
2095 } else {
2096 // 32-bit immediate
2097 emit_opcode(cbuf, $primary);
2098 }
2099 %}
2100
2101 enc_class OpcSErm(rRegI dst, immI imm)
2102 %{
2103 // OpcSEr/m
2104 int dstenc = $dst$$reg;
2105 if (dstenc >= 8) {
2106 emit_opcode(cbuf, Assembler::REX_B);
2107 dstenc -= 8;
2108 }
2109 // Emit primary opcode and set sign-extend bit
2110 // Check for 8-bit immediate, and set sign extend bit in opcode
2111 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2112 emit_opcode(cbuf, $primary | 0x02);
2113 } else {
2114 // 32-bit immediate
2115 emit_opcode(cbuf, $primary);
2116 }
2117 // Emit r/m byte with secondary opcode, after primary opcode.
2118 emit_rm(cbuf, 0x3, $secondary, dstenc);
2119 %}
2120
2121 enc_class OpcSErm_wide(rRegL dst, immI imm)
2122 %{
2123 // OpcSEr/m
2124 int dstenc = $dst$$reg;
2125 if (dstenc < 8) {
2126 emit_opcode(cbuf, Assembler::REX_W);
2127 } else {
2128 emit_opcode(cbuf, Assembler::REX_WB);
2129 dstenc -= 8;
2130 }
2131 // Emit primary opcode and set sign-extend bit
2132 // Check for 8-bit immediate, and set sign extend bit in opcode
2133 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2134 emit_opcode(cbuf, $primary | 0x02);
2135 } else {
2136 // 32-bit immediate
2137 emit_opcode(cbuf, $primary);
2138 }
2139 // Emit r/m byte with secondary opcode, after primary opcode.
2140 emit_rm(cbuf, 0x3, $secondary, dstenc);
2141 %}
2142
2143 enc_class Con8or32(immI imm)
2144 %{
2145 // Check for 8-bit immediate, and set sign extend bit in opcode
2146 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2147 $$$emit8$imm$$constant;
2148 } else {
2149 // 32-bit immediate
2150 $$$emit32$imm$$constant;
2151 }
2152 %}
2153
2154 enc_class opc2_reg(rRegI dst)
2155 %{
2156 // BSWAP
2157 emit_cc(cbuf, $secondary, $dst$$reg);
2158 %}
2159
2160 enc_class opc3_reg(rRegI dst)
2161 %{
2162 // BSWAP
2163 emit_cc(cbuf, $tertiary, $dst$$reg);
2164 %}
2165
2166 enc_class reg_opc(rRegI div)
2167 %{
2168 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2169 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2170 %}
2171
2172 enc_class enc_cmov(cmpOp cop)
2173 %{
2174 // CMOV
2175 $$$emit8$primary;
2176 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2177 %}
2178
2179 enc_class enc_PartialSubtypeCheck()
2180 %{
2181 Register Rrdi = as_Register(RDI_enc); // result register
2182 Register Rrax = as_Register(RAX_enc); // super class
2183 Register Rrcx = as_Register(RCX_enc); // killed
2184 Register Rrsi = as_Register(RSI_enc); // sub class
2185 Label miss;
2186 const bool set_cond_codes = true;
2187
2188 MacroAssembler _masm(&cbuf);
2189 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2190 NULL, &miss,
2191 /*set_cond_codes:*/ true);
2192 if ($primary) {
2193 __ xorptr(Rrdi, Rrdi);
2194 }
2195 __ bind(miss);
2196 %}
2197
2198 enc_class clear_avx %{
2199 debug_only(int off0 = cbuf.insts_size());
2200 if (generate_vzeroupper(Compile::current())) {
2201 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2202 // Clear upper bits of YMM registers when current compiled code uses
2203 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2204 MacroAssembler _masm(&cbuf);
2205 __ vzeroupper();
2206 }
2207 debug_only(int off1 = cbuf.insts_size());
2208 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2209 %}
2210
2211 enc_class Java_To_Runtime(method meth) %{
2212 // No relocation needed
2213 MacroAssembler _masm(&cbuf);
2214 __ mov64(r10, (int64_t) $meth$$method);
2215 __ call(r10);
2216 %}
2217
2218 enc_class Java_To_Interpreter(method meth)
2219 %{
2220 // CALL Java_To_Interpreter
2221 // This is the instruction starting address for relocation info.
2222 cbuf.set_insts_mark();
2223 $$$emit8$primary;
2224 // CALL directly to the runtime
2225 emit_d32_reloc(cbuf,
2226 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2227 runtime_call_Relocation::spec(),
2228 RELOC_DISP32);
2229 %}
2230
2231 enc_class Java_Static_Call(method meth)
2232 %{
2233 // JAVA STATIC CALL
2234 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2235 // determine who we intended to call.
2236 cbuf.set_insts_mark();
2237 $$$emit8$primary;
2238
2239 if (!_method) {
2240 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2241 runtime_call_Relocation::spec(),
2242 RELOC_DISP32);
2243 } else {
2244 int method_index = resolved_method_index(cbuf);
2245 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2246 : static_call_Relocation::spec(method_index);
2247 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2248 rspec, RELOC_DISP32);
2249 // Emit stubs for static call.
2250 address mark = cbuf.insts_mark();
2251 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2252 if (stub == NULL) {
2253 ciEnv::current()->record_failure("CodeCache is full");
2254 return;
2255 }
2256 #if INCLUDE_AOT
2257 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2258 #endif
2259 }
2260 %}
2261
2262 enc_class Java_Dynamic_Call(method meth) %{
2263 MacroAssembler _masm(&cbuf);
2264 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2265 %}
2266
2267 enc_class Java_Compiled_Call(method meth)
2268 %{
2269 // JAVA COMPILED CALL
2270 int disp = in_bytes(Method:: from_compiled_offset());
2271
2272 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2273 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2274
2275 // callq *disp(%rax)
2276 cbuf.set_insts_mark();
2277 $$$emit8$primary;
2278 if (disp < 0x80) {
2279 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2280 emit_d8(cbuf, disp); // Displacement
2281 } else {
2282 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2283 emit_d32(cbuf, disp); // Displacement
2284 }
2285 %}
2286
2287 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2288 %{
2289 // SAL, SAR, SHR
2290 int dstenc = $dst$$reg;
2291 if (dstenc >= 8) {
2292 emit_opcode(cbuf, Assembler::REX_B);
2293 dstenc -= 8;
2294 }
2295 $$$emit8$primary;
2296 emit_rm(cbuf, 0x3, $secondary, dstenc);
2297 $$$emit8$shift$$constant;
2298 %}
2299
2300 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2301 %{
2302 // SAL, SAR, SHR
2303 int dstenc = $dst$$reg;
2304 if (dstenc < 8) {
2305 emit_opcode(cbuf, Assembler::REX_W);
2306 } else {
2307 emit_opcode(cbuf, Assembler::REX_WB);
2308 dstenc -= 8;
2309 }
2310 $$$emit8$primary;
2311 emit_rm(cbuf, 0x3, $secondary, dstenc);
2312 $$$emit8$shift$$constant;
2313 %}
2314
2315 enc_class load_immI(rRegI dst, immI src)
2316 %{
2317 int dstenc = $dst$$reg;
2318 if (dstenc >= 8) {
2319 emit_opcode(cbuf, Assembler::REX_B);
2320 dstenc -= 8;
2321 }
2322 emit_opcode(cbuf, 0xB8 | dstenc);
2323 $$$emit32$src$$constant;
2324 %}
2325
2326 enc_class load_immL(rRegL dst, immL src)
2327 %{
2328 int dstenc = $dst$$reg;
2329 if (dstenc < 8) {
2330 emit_opcode(cbuf, Assembler::REX_W);
2331 } else {
2332 emit_opcode(cbuf, Assembler::REX_WB);
2333 dstenc -= 8;
2334 }
2335 emit_opcode(cbuf, 0xB8 | dstenc);
2336 emit_d64(cbuf, $src$$constant);
2337 %}
2338
2339 enc_class load_immUL32(rRegL dst, immUL32 src)
2340 %{
2341 // same as load_immI, but this time we care about zeroes in the high word
2342 int dstenc = $dst$$reg;
2343 if (dstenc >= 8) {
2344 emit_opcode(cbuf, Assembler::REX_B);
2345 dstenc -= 8;
2346 }
2347 emit_opcode(cbuf, 0xB8 | dstenc);
2348 $$$emit32$src$$constant;
2349 %}
2350
2351 enc_class load_immL32(rRegL dst, immL32 src)
2352 %{
2353 int dstenc = $dst$$reg;
2354 if (dstenc < 8) {
2355 emit_opcode(cbuf, Assembler::REX_W);
2356 } else {
2357 emit_opcode(cbuf, Assembler::REX_WB);
2358 dstenc -= 8;
2359 }
2360 emit_opcode(cbuf, 0xC7);
2361 emit_rm(cbuf, 0x03, 0x00, dstenc);
2362 $$$emit32$src$$constant;
2363 %}
2364
2365 enc_class load_immP31(rRegP dst, immP32 src)
2366 %{
2367 // same as load_immI, but this time we care about zeroes in the high word
2368 int dstenc = $dst$$reg;
2369 if (dstenc >= 8) {
2370 emit_opcode(cbuf, Assembler::REX_B);
2371 dstenc -= 8;
2372 }
2373 emit_opcode(cbuf, 0xB8 | dstenc);
2374 $$$emit32$src$$constant;
2375 %}
2376
2377 enc_class load_immP(rRegP dst, immP src)
2378 %{
2379 int dstenc = $dst$$reg;
2380 if (dstenc < 8) {
2381 emit_opcode(cbuf, Assembler::REX_W);
2382 } else {
2383 emit_opcode(cbuf, Assembler::REX_WB);
2384 dstenc -= 8;
2385 }
2386 emit_opcode(cbuf, 0xB8 | dstenc);
2387 // This next line should be generated from ADLC
2388 if ($src->constant_reloc() != relocInfo::none) {
2389 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2390 } else {
2391 emit_d64(cbuf, $src$$constant);
2392 }
2393 %}
2394
2395 enc_class Con32(immI src)
2396 %{
2397 // Output immediate
2398 $$$emit32$src$$constant;
2399 %}
2400
2401 enc_class Con32F_as_bits(immF src)
2402 %{
2403 // Output Float immediate bits
2404 jfloat jf = $src$$constant;
2405 jint jf_as_bits = jint_cast(jf);
2406 emit_d32(cbuf, jf_as_bits);
2407 %}
2408
2409 enc_class Con16(immI src)
2410 %{
2411 // Output immediate
2412 $$$emit16$src$$constant;
2413 %}
2414
2415 // How is this different from Con32??? XXX
2416 enc_class Con_d32(immI src)
2417 %{
2418 emit_d32(cbuf,$src$$constant);
2419 %}
2420
2421 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2422 // Output immediate memory reference
2423 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2424 emit_d32(cbuf, 0x00);
2425 %}
2426
2427 enc_class lock_prefix()
2428 %{
2429 emit_opcode(cbuf, 0xF0); // lock
2430 %}
2431
2432 enc_class REX_mem(memory mem)
2433 %{
2434 if ($mem$$base >= 8) {
2435 if ($mem$$index < 8) {
2436 emit_opcode(cbuf, Assembler::REX_B);
2437 } else {
2438 emit_opcode(cbuf, Assembler::REX_XB);
2439 }
2440 } else {
2441 if ($mem$$index >= 8) {
2442 emit_opcode(cbuf, Assembler::REX_X);
2443 }
2444 }
2445 %}
2446
2447 enc_class REX_mem_wide(memory mem)
2448 %{
2449 if ($mem$$base >= 8) {
2450 if ($mem$$index < 8) {
2451 emit_opcode(cbuf, Assembler::REX_WB);
2452 } else {
2453 emit_opcode(cbuf, Assembler::REX_WXB);
2454 }
2455 } else {
2456 if ($mem$$index < 8) {
2457 emit_opcode(cbuf, Assembler::REX_W);
2458 } else {
2459 emit_opcode(cbuf, Assembler::REX_WX);
2460 }
2461 }
2462 %}
2463
2464 // for byte regs
2465 enc_class REX_breg(rRegI reg)
2466 %{
2467 if ($reg$$reg >= 4) {
2468 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2469 }
2470 %}
2471
2472 // for byte regs
2473 enc_class REX_reg_breg(rRegI dst, rRegI src)
2474 %{
2475 if ($dst$$reg < 8) {
2476 if ($src$$reg >= 4) {
2477 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2478 }
2479 } else {
2480 if ($src$$reg < 8) {
2481 emit_opcode(cbuf, Assembler::REX_R);
2482 } else {
2483 emit_opcode(cbuf, Assembler::REX_RB);
2484 }
2485 }
2486 %}
2487
2488 // for byte regs
2489 enc_class REX_breg_mem(rRegI reg, memory mem)
2490 %{
2491 if ($reg$$reg < 8) {
2492 if ($mem$$base < 8) {
2493 if ($mem$$index >= 8) {
2494 emit_opcode(cbuf, Assembler::REX_X);
2495 } else if ($reg$$reg >= 4) {
2496 emit_opcode(cbuf, Assembler::REX);
2497 }
2498 } else {
2499 if ($mem$$index < 8) {
2500 emit_opcode(cbuf, Assembler::REX_B);
2501 } else {
2502 emit_opcode(cbuf, Assembler::REX_XB);
2503 }
2504 }
2505 } else {
2506 if ($mem$$base < 8) {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_R);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_RX);
2511 }
2512 } else {
2513 if ($mem$$index < 8) {
2514 emit_opcode(cbuf, Assembler::REX_RB);
2515 } else {
2516 emit_opcode(cbuf, Assembler::REX_RXB);
2517 }
2518 }
2519 }
2520 %}
2521
2522 enc_class REX_reg(rRegI reg)
2523 %{
2524 if ($reg$$reg >= 8) {
2525 emit_opcode(cbuf, Assembler::REX_B);
2526 }
2527 %}
2528
2529 enc_class REX_reg_wide(rRegI reg)
2530 %{
2531 if ($reg$$reg < 8) {
2532 emit_opcode(cbuf, Assembler::REX_W);
2533 } else {
2534 emit_opcode(cbuf, Assembler::REX_WB);
2535 }
2536 %}
2537
2538 enc_class REX_reg_reg(rRegI dst, rRegI src)
2539 %{
2540 if ($dst$$reg < 8) {
2541 if ($src$$reg >= 8) {
2542 emit_opcode(cbuf, Assembler::REX_B);
2543 }
2544 } else {
2545 if ($src$$reg < 8) {
2546 emit_opcode(cbuf, Assembler::REX_R);
2547 } else {
2548 emit_opcode(cbuf, Assembler::REX_RB);
2549 }
2550 }
2551 %}
2552
2553 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2554 %{
2555 if ($dst$$reg < 8) {
2556 if ($src$$reg < 8) {
2557 emit_opcode(cbuf, Assembler::REX_W);
2558 } else {
2559 emit_opcode(cbuf, Assembler::REX_WB);
2560 }
2561 } else {
2562 if ($src$$reg < 8) {
2563 emit_opcode(cbuf, Assembler::REX_WR);
2564 } else {
2565 emit_opcode(cbuf, Assembler::REX_WRB);
2566 }
2567 }
2568 %}
2569
2570 enc_class REX_reg_mem(rRegI reg, memory mem)
2571 %{
2572 if ($reg$$reg < 8) {
2573 if ($mem$$base < 8) {
2574 if ($mem$$index >= 8) {
2575 emit_opcode(cbuf, Assembler::REX_X);
2576 }
2577 } else {
2578 if ($mem$$index < 8) {
2579 emit_opcode(cbuf, Assembler::REX_B);
2580 } else {
2581 emit_opcode(cbuf, Assembler::REX_XB);
2582 }
2583 }
2584 } else {
2585 if ($mem$$base < 8) {
2586 if ($mem$$index < 8) {
2587 emit_opcode(cbuf, Assembler::REX_R);
2588 } else {
2589 emit_opcode(cbuf, Assembler::REX_RX);
2590 }
2591 } else {
2592 if ($mem$$index < 8) {
2593 emit_opcode(cbuf, Assembler::REX_RB);
2594 } else {
2595 emit_opcode(cbuf, Assembler::REX_RXB);
2596 }
2597 }
2598 }
2599 %}
2600
2601 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2602 %{
2603 if ($reg$$reg < 8) {
2604 if ($mem$$base < 8) {
2605 if ($mem$$index < 8) {
2606 emit_opcode(cbuf, Assembler::REX_W);
2607 } else {
2608 emit_opcode(cbuf, Assembler::REX_WX);
2609 }
2610 } else {
2611 if ($mem$$index < 8) {
2612 emit_opcode(cbuf, Assembler::REX_WB);
2613 } else {
2614 emit_opcode(cbuf, Assembler::REX_WXB);
2615 }
2616 }
2617 } else {
2618 if ($mem$$base < 8) {
2619 if ($mem$$index < 8) {
2620 emit_opcode(cbuf, Assembler::REX_WR);
2621 } else {
2622 emit_opcode(cbuf, Assembler::REX_WRX);
2623 }
2624 } else {
2625 if ($mem$$index < 8) {
2626 emit_opcode(cbuf, Assembler::REX_WRB);
2627 } else {
2628 emit_opcode(cbuf, Assembler::REX_WRXB);
2629 }
2630 }
2631 }
2632 %}
2633
2634 enc_class reg_mem(rRegI ereg, memory mem)
2635 %{
2636 // High registers handle in encode_RegMem
2637 int reg = $ereg$$reg;
2638 int base = $mem$$base;
2639 int index = $mem$$index;
2640 int scale = $mem$$scale;
2641 int disp = $mem$$disp;
2642 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2643
2644 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2645 %}
2646
2647 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2648 %{
2649 int rm_byte_opcode = $rm_opcode$$constant;
2650
2651 // High registers handle in encode_RegMem
2652 int base = $mem$$base;
2653 int index = $mem$$index;
2654 int scale = $mem$$scale;
2655 int displace = $mem$$disp;
2656
2657 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2658 // working with static
2659 // globals
2660 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2661 disp_reloc);
2662 %}
2663
2664 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2665 %{
2666 int reg_encoding = $dst$$reg;
2667 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2668 int index = 0x04; // 0x04 indicates no index
2669 int scale = 0x00; // 0x00 indicates no scale
2670 int displace = $src1$$constant; // 0x00 indicates no displacement
2671 relocInfo::relocType disp_reloc = relocInfo::none;
2672 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2673 disp_reloc);
2674 %}
2675
2676 enc_class neg_reg(rRegI dst)
2677 %{
2678 int dstenc = $dst$$reg;
2679 if (dstenc >= 8) {
2680 emit_opcode(cbuf, Assembler::REX_B);
2681 dstenc -= 8;
2682 }
2683 // NEG $dst
2684 emit_opcode(cbuf, 0xF7);
2685 emit_rm(cbuf, 0x3, 0x03, dstenc);
2686 %}
2687
2688 enc_class neg_reg_wide(rRegI dst)
2689 %{
2690 int dstenc = $dst$$reg;
2691 if (dstenc < 8) {
2692 emit_opcode(cbuf, Assembler::REX_W);
2693 } else {
2694 emit_opcode(cbuf, Assembler::REX_WB);
2695 dstenc -= 8;
2696 }
2697 // NEG $dst
2698 emit_opcode(cbuf, 0xF7);
2699 emit_rm(cbuf, 0x3, 0x03, dstenc);
2700 %}
2701
2702 enc_class setLT_reg(rRegI dst)
2703 %{
2704 int dstenc = $dst$$reg;
2705 if (dstenc >= 8) {
2706 emit_opcode(cbuf, Assembler::REX_B);
2707 dstenc -= 8;
2708 } else if (dstenc >= 4) {
2709 emit_opcode(cbuf, Assembler::REX);
2710 }
2711 // SETLT $dst
2712 emit_opcode(cbuf, 0x0F);
2713 emit_opcode(cbuf, 0x9C);
2714 emit_rm(cbuf, 0x3, 0x0, dstenc);
2715 %}
2716
2717 enc_class setNZ_reg(rRegI dst)
2718 %{
2719 int dstenc = $dst$$reg;
2720 if (dstenc >= 8) {
2721 emit_opcode(cbuf, Assembler::REX_B);
2722 dstenc -= 8;
2723 } else if (dstenc >= 4) {
2724 emit_opcode(cbuf, Assembler::REX);
2725 }
2726 // SETNZ $dst
2727 emit_opcode(cbuf, 0x0F);
2728 emit_opcode(cbuf, 0x95);
2729 emit_rm(cbuf, 0x3, 0x0, dstenc);
2730 %}
2731
2732
2733 // Compare the lonogs and set -1, 0, or 1 into dst
2734 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2735 %{
2736 int src1enc = $src1$$reg;
2737 int src2enc = $src2$$reg;
2738 int dstenc = $dst$$reg;
2739
2740 // cmpq $src1, $src2
2741 if (src1enc < 8) {
2742 if (src2enc < 8) {
2743 emit_opcode(cbuf, Assembler::REX_W);
2744 } else {
2745 emit_opcode(cbuf, Assembler::REX_WB);
2746 }
2747 } else {
2748 if (src2enc < 8) {
2749 emit_opcode(cbuf, Assembler::REX_WR);
2750 } else {
2751 emit_opcode(cbuf, Assembler::REX_WRB);
2752 }
2753 }
2754 emit_opcode(cbuf, 0x3B);
2755 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2756
2757 // movl $dst, -1
2758 if (dstenc >= 8) {
2759 emit_opcode(cbuf, Assembler::REX_B);
2760 }
2761 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2762 emit_d32(cbuf, -1);
2763
2764 // jl,s done
2765 emit_opcode(cbuf, 0x7C);
2766 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2767
2768 // setne $dst
2769 if (dstenc >= 4) {
2770 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2771 }
2772 emit_opcode(cbuf, 0x0F);
2773 emit_opcode(cbuf, 0x95);
2774 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2775
2776 // movzbl $dst, $dst
2777 if (dstenc >= 4) {
2778 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2779 }
2780 emit_opcode(cbuf, 0x0F);
2781 emit_opcode(cbuf, 0xB6);
2782 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2783 %}
2784
2785 enc_class Push_ResultXD(regD dst) %{
2786 MacroAssembler _masm(&cbuf);
2787 __ fstp_d(Address(rsp, 0));
2788 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2789 __ addptr(rsp, 8);
2790 %}
2791
2792 enc_class Push_SrcXD(regD src) %{
2793 MacroAssembler _masm(&cbuf);
2794 __ subptr(rsp, 8);
2795 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2796 __ fld_d(Address(rsp, 0));
2797 %}
2798
2799
2800 enc_class enc_rethrow()
2801 %{
2802 cbuf.set_insts_mark();
2803 emit_opcode(cbuf, 0xE9); // jmp entry
2804 emit_d32_reloc(cbuf,
2805 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2806 runtime_call_Relocation::spec(),
2807 RELOC_DISP32);
2808 %}
2809
2810 %}
2811
2812
2813
2814 //----------FRAME--------------------------------------------------------------
2815 // Definition of frame structure and management information.
2816 //
2817 // S T A C K L A Y O U T Allocators stack-slot number
2818 // | (to get allocators register number
2819 // G Owned by | | v add OptoReg::stack0())
2820 // r CALLER | |
2821 // o | +--------+ pad to even-align allocators stack-slot
2822 // w V | pad0 | numbers; owned by CALLER
2823 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2824 // h ^ | in | 5
2825 // | | args | 4 Holes in incoming args owned by SELF
2826 // | | | | 3
2827 // | | +--------+
2828 // V | | old out| Empty on Intel, window on Sparc
2829 // | old |preserve| Must be even aligned.
2830 // | SP-+--------+----> Matcher::_old_SP, even aligned
2831 // | | in | 3 area for Intel ret address
2832 // Owned by |preserve| Empty on Sparc.
2833 // SELF +--------+
2834 // | | pad2 | 2 pad to align old SP
2835 // | +--------+ 1
2836 // | | locks | 0
2837 // | +--------+----> OptoReg::stack0(), even aligned
2838 // | | pad1 | 11 pad to align new SP
2839 // | +--------+
2840 // | | | 10
2841 // | | spills | 9 spills
2842 // V | | 8 (pad0 slot for callee)
2843 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2844 // ^ | out | 7
2845 // | | args | 6 Holes in outgoing args owned by CALLEE
2846 // Owned by +--------+
2847 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2848 // | new |preserve| Must be even-aligned.
2849 // | SP-+--------+----> Matcher::_new_SP, even aligned
2850 // | | |
2851 //
2852 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2853 // known from SELF's arguments and the Java calling convention.
2854 // Region 6-7 is determined per call site.
2855 // Note 2: If the calling convention leaves holes in the incoming argument
2856 // area, those holes are owned by SELF. Holes in the outgoing area
2857 // are owned by the CALLEE. Holes should not be nessecary in the
2858 // incoming area, as the Java calling convention is completely under
2859 // the control of the AD file. Doubles can be sorted and packed to
2860 // avoid holes. Holes in the outgoing arguments may be nessecary for
2861 // varargs C calling conventions.
2862 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2863 // even aligned with pad0 as needed.
2864 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2865 // region 6-11 is even aligned; it may be padded out more so that
2866 // the region from SP to FP meets the minimum stack alignment.
2867 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2868 // alignment. Region 11, pad1, may be dynamically extended so that
2869 // SP meets the minimum alignment.
2870
2871 frame
2872 %{
2873 // What direction does stack grow in (assumed to be same for C & Java)
2874 stack_direction(TOWARDS_LOW);
2875
2876 // These three registers define part of the calling convention
2877 // between compiled code and the interpreter.
2878 inline_cache_reg(RAX); // Inline Cache Register
2879 interpreter_method_oop_reg(RBX); // Method Oop Register when
2880 // calling interpreter
2881
2882 // Optional: name the operand used by cisc-spilling to access
2883 // [stack_pointer + offset]
2884 cisc_spilling_operand_name(indOffset32);
2885
2886 // Number of stack slots consumed by locking an object
2887 sync_stack_slots(2);
2888
2889 // Compiled code's Frame Pointer
2890 frame_pointer(RSP);
2891
2892 // Interpreter stores its frame pointer in a register which is
2893 // stored to the stack by I2CAdaptors.
2894 // I2CAdaptors convert from interpreted java to compiled java.
2895 interpreter_frame_pointer(RBP);
2896
2897 // Stack alignment requirement
2898 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2899
2900 // Number of stack slots between incoming argument block and the start of
2901 // a new frame. The PROLOG must add this many slots to the stack. The
2902 // EPILOG must remove this many slots. amd64 needs two slots for
2903 // return address.
2904 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2905
2906 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2907 // for calls to C. Supports the var-args backing area for register parms.
2908 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2909
2910 // The after-PROLOG location of the return address. Location of
2911 // return address specifies a type (REG or STACK) and a number
2912 // representing the register number (i.e. - use a register name) or
2913 // stack slot.
2914 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2915 // Otherwise, it is above the locks and verification slot and alignment word
2916 return_addr(STACK - 2 +
2917 align_up((Compile::current()->in_preserve_stack_slots() +
2918 Compile::current()->fixed_slots()),
2919 stack_alignment_in_slots()));
2920
2921 // Body of function which returns an integer array locating
2922 // arguments either in registers or in stack slots. Passed an array
2923 // of ideal registers called "sig" and a "length" count. Stack-slot
2924 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2925 // arguments for a CALLEE. Incoming stack arguments are
2926 // automatically biased by the preserve_stack_slots field above.
2927
2928 calling_convention
2929 %{
2930 // No difference between ingoing/outgoing just pass false
2931 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2932 %}
2933
2934 c_calling_convention
2935 %{
2936 // This is obviously always outgoing
2937 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2938 %}
2939
2940 // Location of compiled Java return values. Same as C for now.
2941 return_value
2942 %{
2943 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2944 "only return normal values");
2945
2946 static const int lo[Op_RegL + 1] = {
2947 0,
2948 0,
2949 RAX_num, // Op_RegN
2950 RAX_num, // Op_RegI
2951 RAX_num, // Op_RegP
2952 XMM0_num, // Op_RegF
2953 XMM0_num, // Op_RegD
2954 RAX_num // Op_RegL
2955 };
2956 static const int hi[Op_RegL + 1] = {
2957 0,
2958 0,
2959 OptoReg::Bad, // Op_RegN
2960 OptoReg::Bad, // Op_RegI
2961 RAX_H_num, // Op_RegP
2962 OptoReg::Bad, // Op_RegF
2963 XMM0b_num, // Op_RegD
2964 RAX_H_num // Op_RegL
2965 };
2966 // Excluded flags and vector registers.
2967 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2968 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2969 %}
2970 %}
2971
2972 //----------ATTRIBUTES---------------------------------------------------------
2973 //----------Operand Attributes-------------------------------------------------
2974 op_attrib op_cost(0); // Required cost attribute
2975
2976 //----------Instruction Attributes---------------------------------------------
2977 ins_attrib ins_cost(100); // Required cost attribute
2978 ins_attrib ins_size(8); // Required size attribute (in bits)
2979 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2980 // a non-matching short branch variant
2981 // of some long branch?
2982 ins_attrib ins_alignment(1); // Required alignment attribute (must
2983 // be a power of 2) specifies the
2984 // alignment that some part of the
2985 // instruction (not necessarily the
2986 // start) requires. If > 1, a
2987 // compute_padding() function must be
2988 // provided for the instruction
2989
2990 //----------OPERANDS-----------------------------------------------------------
2991 // Operand definitions must precede instruction definitions for correct parsing
2992 // in the ADLC because operands constitute user defined types which are used in
2993 // instruction definitions.
2994
2995 //----------Simple Operands----------------------------------------------------
2996 // Immediate Operands
2997 // Integer Immediate
2998 operand immI()
2999 %{
3000 match(ConI);
3001
3002 op_cost(10);
3003 format %{ %}
3004 interface(CONST_INTER);
3005 %}
3006
3007 // Constant for test vs zero
3008 operand immI0()
3009 %{
3010 predicate(n->get_int() == 0);
3011 match(ConI);
3012
3013 op_cost(0);
3014 format %{ %}
3015 interface(CONST_INTER);
3016 %}
3017
3018 // Constant for increment
3019 operand immI1()
3020 %{
3021 predicate(n->get_int() == 1);
3022 match(ConI);
3023
3024 op_cost(0);
3025 format %{ %}
3026 interface(CONST_INTER);
3027 %}
3028
3029 // Constant for decrement
3030 operand immI_M1()
3031 %{
3032 predicate(n->get_int() == -1);
3033 match(ConI);
3034
3035 op_cost(0);
3036 format %{ %}
3037 interface(CONST_INTER);
3038 %}
3039
3040 // Valid scale values for addressing modes
3041 operand immI2()
3042 %{
3043 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3044 match(ConI);
3045
3046 format %{ %}
3047 interface(CONST_INTER);
3048 %}
3049
3050 operand immI8()
3051 %{
3052 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3053 match(ConI);
3054
3055 op_cost(5);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060 operand immU8()
3061 %{
3062 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
3063 match(ConI);
3064
3065 op_cost(5);
3066 format %{ %}
3067 interface(CONST_INTER);
3068 %}
3069
3070 operand immI16()
3071 %{
3072 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3073 match(ConI);
3074
3075 op_cost(10);
3076 format %{ %}
3077 interface(CONST_INTER);
3078 %}
3079
3080 // Int Immediate non-negative
3081 operand immU31()
3082 %{
3083 predicate(n->get_int() >= 0);
3084 match(ConI);
3085
3086 op_cost(0);
3087 format %{ %}
3088 interface(CONST_INTER);
3089 %}
3090
3091 // Constant for long shifts
3092 operand immI_32()
3093 %{
3094 predicate( n->get_int() == 32 );
3095 match(ConI);
3096
3097 op_cost(0);
3098 format %{ %}
3099 interface(CONST_INTER);
3100 %}
3101
3102 // Constant for long shifts
3103 operand immI_64()
3104 %{
3105 predicate( n->get_int() == 64 );
3106 match(ConI);
3107
3108 op_cost(0);
3109 format %{ %}
3110 interface(CONST_INTER);
3111 %}
3112
3113 // Pointer Immediate
3114 operand immP()
3115 %{
3116 match(ConP);
3117
3118 op_cost(10);
3119 format %{ %}
3120 interface(CONST_INTER);
3121 %}
3122
3123 // NULL Pointer Immediate
3124 operand immP0()
3125 %{
3126 predicate(n->get_ptr() == 0);
3127 match(ConP);
3128
3129 op_cost(5);
3130 format %{ %}
3131 interface(CONST_INTER);
3132 %}
3133
3134 // Pointer Immediate
3135 operand immN() %{
3136 match(ConN);
3137
3138 op_cost(10);
3139 format %{ %}
3140 interface(CONST_INTER);
3141 %}
3142
3143 operand immNKlass() %{
3144 match(ConNKlass);
3145
3146 op_cost(10);
3147 format %{ %}
3148 interface(CONST_INTER);
3149 %}
3150
3151 // NULL Pointer Immediate
3152 operand immN0() %{
3153 predicate(n->get_narrowcon() == 0);
3154 match(ConN);
3155
3156 op_cost(5);
3157 format %{ %}
3158 interface(CONST_INTER);
3159 %}
3160
3161 operand immP31()
3162 %{
3163 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3164 && (n->get_ptr() >> 31) == 0);
3165 match(ConP);
3166
3167 op_cost(5);
3168 format %{ %}
3169 interface(CONST_INTER);
3170 %}
3171
3172
3173 // Long Immediate
3174 operand immL()
3175 %{
3176 match(ConL);
3177
3178 op_cost(20);
3179 format %{ %}
3180 interface(CONST_INTER);
3181 %}
3182
3183 // Long Immediate 8-bit
3184 operand immL8()
3185 %{
3186 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3187 match(ConL);
3188
3189 op_cost(5);
3190 format %{ %}
3191 interface(CONST_INTER);
3192 %}
3193
3194 // Long Immediate 32-bit unsigned
3195 operand immUL32()
3196 %{
3197 predicate(n->get_long() == (unsigned int) (n->get_long()));
3198 match(ConL);
3199
3200 op_cost(10);
3201 format %{ %}
3202 interface(CONST_INTER);
3203 %}
3204
3205 // Long Immediate 32-bit signed
3206 operand immL32()
3207 %{
3208 predicate(n->get_long() == (int) (n->get_long()));
3209 match(ConL);
3210
3211 op_cost(15);
3212 format %{ %}
3213 interface(CONST_INTER);
3214 %}
3215
3216 // Long Immediate zero
3217 operand immL0()
3218 %{
3219 predicate(n->get_long() == 0L);
3220 match(ConL);
3221
3222 op_cost(10);
3223 format %{ %}
3224 interface(CONST_INTER);
3225 %}
3226
3227 // Constant for increment
3228 operand immL1()
3229 %{
3230 predicate(n->get_long() == 1);
3231 match(ConL);
3232
3233 format %{ %}
3234 interface(CONST_INTER);
3235 %}
3236
3237 // Constant for decrement
3238 operand immL_M1()
3239 %{
3240 predicate(n->get_long() == -1);
3241 match(ConL);
3242
3243 format %{ %}
3244 interface(CONST_INTER);
3245 %}
3246
3247 // Long Immediate: the value 10
3248 operand immL10()
3249 %{
3250 predicate(n->get_long() == 10);
3251 match(ConL);
3252
3253 format %{ %}
3254 interface(CONST_INTER);
3255 %}
3256
3257 // Long immediate from 0 to 127.
3258 // Used for a shorter form of long mul by 10.
3259 operand immL_127()
3260 %{
3261 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3262 match(ConL);
3263
3264 op_cost(10);
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3268
3269 // Long Immediate: low 32-bit mask
3270 operand immL_32bits()
3271 %{
3272 predicate(n->get_long() == 0xFFFFFFFFL);
3273 match(ConL);
3274 op_cost(20);
3275
3276 format %{ %}
3277 interface(CONST_INTER);
3278 %}
3279
3280 // Float Immediate zero
3281 operand immF0()
3282 %{
3283 predicate(jint_cast(n->getf()) == 0);
3284 match(ConF);
3285
3286 op_cost(5);
3287 format %{ %}
3288 interface(CONST_INTER);
3289 %}
3290
3291 // Float Immediate
3292 operand immF()
3293 %{
3294 match(ConF);
3295
3296 op_cost(15);
3297 format %{ %}
3298 interface(CONST_INTER);
3299 %}
3300
3301 // Double Immediate zero
3302 operand immD0()
3303 %{
3304 predicate(jlong_cast(n->getd()) == 0);
3305 match(ConD);
3306
3307 op_cost(5);
3308 format %{ %}
3309 interface(CONST_INTER);
3310 %}
3311
3312 // Double Immediate
3313 operand immD()
3314 %{
3315 match(ConD);
3316
3317 op_cost(15);
3318 format %{ %}
3319 interface(CONST_INTER);
3320 %}
3321
3322 // Immediates for special shifts (sign extend)
3323
3324 // Constants for increment
3325 operand immI_16()
3326 %{
3327 predicate(n->get_int() == 16);
3328 match(ConI);
3329
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3333
3334 operand immI_24()
3335 %{
3336 predicate(n->get_int() == 24);
3337 match(ConI);
3338
3339 format %{ %}
3340 interface(CONST_INTER);
3341 %}
3342
3343 // Constant for byte-wide masking
3344 operand immI_255()
3345 %{
3346 predicate(n->get_int() == 255);
3347 match(ConI);
3348
3349 format %{ %}
3350 interface(CONST_INTER);
3351 %}
3352
3353 // Constant for short-wide masking
3354 operand immI_65535()
3355 %{
3356 predicate(n->get_int() == 65535);
3357 match(ConI);
3358
3359 format %{ %}
3360 interface(CONST_INTER);
3361 %}
3362
3363 // Constant for byte-wide masking
3364 operand immL_255()
3365 %{
3366 predicate(n->get_long() == 255);
3367 match(ConL);
3368
3369 format %{ %}
3370 interface(CONST_INTER);
3371 %}
3372
3373 // Constant for short-wide masking
3374 operand immL_65535()
3375 %{
3376 predicate(n->get_long() == 65535);
3377 match(ConL);
3378
3379 format %{ %}
3380 interface(CONST_INTER);
3381 %}
3382
3383 // Register Operands
3384 // Integer Register
3385 operand rRegI()
3386 %{
3387 constraint(ALLOC_IN_RC(int_reg));
3388 match(RegI);
3389
3390 match(rax_RegI);
3391 match(rbx_RegI);
3392 match(rcx_RegI);
3393 match(rdx_RegI);
3394 match(rdi_RegI);
3395
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // Special Registers
3401 operand rax_RegI()
3402 %{
3403 constraint(ALLOC_IN_RC(int_rax_reg));
3404 match(RegI);
3405 match(rRegI);
3406
3407 format %{ "RAX" %}
3408 interface(REG_INTER);
3409 %}
3410
3411 // Special Registers
3412 operand rbx_RegI()
3413 %{
3414 constraint(ALLOC_IN_RC(int_rbx_reg));
3415 match(RegI);
3416 match(rRegI);
3417
3418 format %{ "RBX" %}
3419 interface(REG_INTER);
3420 %}
3421
3422 operand rcx_RegI()
3423 %{
3424 constraint(ALLOC_IN_RC(int_rcx_reg));
3425 match(RegI);
3426 match(rRegI);
3427
3428 format %{ "RCX" %}
3429 interface(REG_INTER);
3430 %}
3431
3432 operand rdx_RegI()
3433 %{
3434 constraint(ALLOC_IN_RC(int_rdx_reg));
3435 match(RegI);
3436 match(rRegI);
3437
3438 format %{ "RDX" %}
3439 interface(REG_INTER);
3440 %}
3441
3442 operand rdi_RegI()
3443 %{
3444 constraint(ALLOC_IN_RC(int_rdi_reg));
3445 match(RegI);
3446 match(rRegI);
3447
3448 format %{ "RDI" %}
3449 interface(REG_INTER);
3450 %}
3451
3452 operand no_rcx_RegI()
3453 %{
3454 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3455 match(RegI);
3456 match(rax_RegI);
3457 match(rbx_RegI);
3458 match(rdx_RegI);
3459 match(rdi_RegI);
3460
3461 format %{ %}
3462 interface(REG_INTER);
3463 %}
3464
3465 operand no_rax_rdx_RegI()
3466 %{
3467 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3468 match(RegI);
3469 match(rbx_RegI);
3470 match(rcx_RegI);
3471 match(rdi_RegI);
3472
3473 format %{ %}
3474 interface(REG_INTER);
3475 %}
3476
3477 // Pointer Register
3478 operand any_RegP()
3479 %{
3480 constraint(ALLOC_IN_RC(any_reg));
3481 match(RegP);
3482 match(rax_RegP);
3483 match(rbx_RegP);
3484 match(rdi_RegP);
3485 match(rsi_RegP);
3486 match(rbp_RegP);
3487 match(r15_RegP);
3488 match(rRegP);
3489
3490 format %{ %}
3491 interface(REG_INTER);
3492 %}
3493
3494 operand rRegP()
3495 %{
3496 constraint(ALLOC_IN_RC(ptr_reg));
3497 match(RegP);
3498 match(rax_RegP);
3499 match(rbx_RegP);
3500 match(rdi_RegP);
3501 match(rsi_RegP);
3502 match(rbp_RegP); // See Q&A below about
3503 match(r15_RegP); // r15_RegP and rbp_RegP.
3504
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 operand rRegN() %{
3510 constraint(ALLOC_IN_RC(int_reg));
3511 match(RegN);
3512
3513 format %{ %}
3514 interface(REG_INTER);
3515 %}
3516
3517 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3518 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3519 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3520 // The output of an instruction is controlled by the allocator, which respects
3521 // register class masks, not match rules. Unless an instruction mentions
3522 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3523 // by the allocator as an input.
3524 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3525 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3526 // result, RBP is not included in the output of the instruction either.
3527
3528 operand no_rax_RegP()
3529 %{
3530 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3531 match(RegP);
3532 match(rbx_RegP);
3533 match(rsi_RegP);
3534 match(rdi_RegP);
3535
3536 format %{ %}
3537 interface(REG_INTER);
3538 %}
3539
3540 // This operand is not allowed to use RBP even if
3541 // RBP is not used to hold the frame pointer.
3542 operand no_rbp_RegP()
3543 %{
3544 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3545 match(RegP);
3546 match(rbx_RegP);
3547 match(rsi_RegP);
3548 match(rdi_RegP);
3549
3550 format %{ %}
3551 interface(REG_INTER);
3552 %}
3553
3554 operand no_rax_rbx_RegP()
3555 %{
3556 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3557 match(RegP);
3558 match(rsi_RegP);
3559 match(rdi_RegP);
3560
3561 format %{ %}
3562 interface(REG_INTER);
3563 %}
3564
3565 // Special Registers
3566 // Return a pointer value
3567 operand rax_RegP()
3568 %{
3569 constraint(ALLOC_IN_RC(ptr_rax_reg));
3570 match(RegP);
3571 match(rRegP);
3572
3573 format %{ %}
3574 interface(REG_INTER);
3575 %}
3576
3577 // Special Registers
3578 // Return a compressed pointer value
3579 operand rax_RegN()
3580 %{
3581 constraint(ALLOC_IN_RC(int_rax_reg));
3582 match(RegN);
3583 match(rRegN);
3584
3585 format %{ %}
3586 interface(REG_INTER);
3587 %}
3588
3589 // Used in AtomicAdd
3590 operand rbx_RegP()
3591 %{
3592 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3593 match(RegP);
3594 match(rRegP);
3595
3596 format %{ %}
3597 interface(REG_INTER);
3598 %}
3599
3600 operand rsi_RegP()
3601 %{
3602 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3603 match(RegP);
3604 match(rRegP);
3605
3606 format %{ %}
3607 interface(REG_INTER);
3608 %}
3609
3610 // Used in rep stosq
3611 operand rdi_RegP()
3612 %{
3613 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3614 match(RegP);
3615 match(rRegP);
3616
3617 format %{ %}
3618 interface(REG_INTER);
3619 %}
3620
3621 operand r15_RegP()
3622 %{
3623 constraint(ALLOC_IN_RC(ptr_r15_reg));
3624 match(RegP);
3625 match(rRegP);
3626
3627 format %{ %}
3628 interface(REG_INTER);
3629 %}
3630
3631 operand rRegL()
3632 %{
3633 constraint(ALLOC_IN_RC(long_reg));
3634 match(RegL);
3635 match(rax_RegL);
3636 match(rdx_RegL);
3637
3638 format %{ %}
3639 interface(REG_INTER);
3640 %}
3641
3642 // Special Registers
3643 operand no_rax_rdx_RegL()
3644 %{
3645 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3646 match(RegL);
3647 match(rRegL);
3648
3649 format %{ %}
3650 interface(REG_INTER);
3651 %}
3652
3653 operand no_rax_RegL()
3654 %{
3655 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3656 match(RegL);
3657 match(rRegL);
3658 match(rdx_RegL);
3659
3660 format %{ %}
3661 interface(REG_INTER);
3662 %}
3663
3664 operand no_rcx_RegL()
3665 %{
3666 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3667 match(RegL);
3668 match(rRegL);
3669
3670 format %{ %}
3671 interface(REG_INTER);
3672 %}
3673
3674 operand rax_RegL()
3675 %{
3676 constraint(ALLOC_IN_RC(long_rax_reg));
3677 match(RegL);
3678 match(rRegL);
3679
3680 format %{ "RAX" %}
3681 interface(REG_INTER);
3682 %}
3683
3684 operand rcx_RegL()
3685 %{
3686 constraint(ALLOC_IN_RC(long_rcx_reg));
3687 match(RegL);
3688 match(rRegL);
3689
3690 format %{ %}
3691 interface(REG_INTER);
3692 %}
3693
3694 operand rdx_RegL()
3695 %{
3696 constraint(ALLOC_IN_RC(long_rdx_reg));
3697 match(RegL);
3698 match(rRegL);
3699
3700 format %{ %}
3701 interface(REG_INTER);
3702 %}
3703
3704 // Flags register, used as output of compare instructions
3705 operand rFlagsReg()
3706 %{
3707 constraint(ALLOC_IN_RC(int_flags));
3708 match(RegFlags);
3709
3710 format %{ "RFLAGS" %}
3711 interface(REG_INTER);
3712 %}
3713
3714 // Flags register, used as output of FLOATING POINT compare instructions
3715 operand rFlagsRegU()
3716 %{
3717 constraint(ALLOC_IN_RC(int_flags));
3718 match(RegFlags);
3719
3720 format %{ "RFLAGS_U" %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand rFlagsRegUCF() %{
3725 constraint(ALLOC_IN_RC(int_flags));
3726 match(RegFlags);
3727 predicate(false);
3728
3729 format %{ "RFLAGS_U_CF" %}
3730 interface(REG_INTER);
3731 %}
3732
3733 // Float register operands
3734 operand regF() %{
3735 constraint(ALLOC_IN_RC(float_reg));
3736 match(RegF);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 // Float register operands
3743 operand vlRegF() %{
3744 constraint(ALLOC_IN_RC(float_reg_vl));
3745 match(RegF);
3746
3747 format %{ %}
3748 interface(REG_INTER);
3749 %}
3750
3751 // Double register operands
3752 operand regD() %{
3753 constraint(ALLOC_IN_RC(double_reg));
3754 match(RegD);
3755
3756 format %{ %}
3757 interface(REG_INTER);
3758 %}
3759
3760 // Double register operands
3761 operand vlRegD() %{
3762 constraint(ALLOC_IN_RC(double_reg_vl));
3763 match(RegD);
3764
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3768
3769 // Vectors
3770 operand vecS() %{
3771 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3772 match(VecS);
3773
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 // Vectors
3779 operand legVecS() %{
3780 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3781 match(VecS);
3782
3783 format %{ %}
3784 interface(REG_INTER);
3785 %}
3786
3787 operand vecD() %{
3788 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3789 match(VecD);
3790
3791 format %{ %}
3792 interface(REG_INTER);
3793 %}
3794
3795 operand legVecD() %{
3796 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3797 match(VecD);
3798
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 operand vecX() %{
3804 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3805 match(VecX);
3806
3807 format %{ %}
3808 interface(REG_INTER);
3809 %}
3810
3811 operand legVecX() %{
3812 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3813 match(VecX);
3814
3815 format %{ %}
3816 interface(REG_INTER);
3817 %}
3818
3819 operand vecY() %{
3820 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3821 match(VecY);
3822
3823 format %{ %}
3824 interface(REG_INTER);
3825 %}
3826
3827 operand legVecY() %{
3828 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3829 match(VecY);
3830
3831 format %{ %}
3832 interface(REG_INTER);
3833 %}
3834
3835 //----------Memory Operands----------------------------------------------------
3836 // Direct Memory Operand
3837 // operand direct(immP addr)
3838 // %{
3839 // match(addr);
3840
3841 // format %{ "[$addr]" %}
3842 // interface(MEMORY_INTER) %{
3843 // base(0xFFFFFFFF);
3844 // index(0x4);
3845 // scale(0x0);
3846 // disp($addr);
3847 // %}
3848 // %}
3849
3850 // Indirect Memory Operand
3851 operand indirect(any_RegP reg)
3852 %{
3853 constraint(ALLOC_IN_RC(ptr_reg));
3854 match(reg);
3855
3856 format %{ "[$reg]" %}
3857 interface(MEMORY_INTER) %{
3858 base($reg);
3859 index(0x4);
3860 scale(0x0);
3861 disp(0x0);
3862 %}
3863 %}
3864
3865 // Indirect Memory Plus Short Offset Operand
3866 operand indOffset8(any_RegP reg, immL8 off)
3867 %{
3868 constraint(ALLOC_IN_RC(ptr_reg));
3869 match(AddP reg off);
3870
3871 format %{ "[$reg + $off (8-bit)]" %}
3872 interface(MEMORY_INTER) %{
3873 base($reg);
3874 index(0x4);
3875 scale(0x0);
3876 disp($off);
3877 %}
3878 %}
3879
3880 // Indirect Memory Plus Long Offset Operand
3881 operand indOffset32(any_RegP reg, immL32 off)
3882 %{
3883 constraint(ALLOC_IN_RC(ptr_reg));
3884 match(AddP reg off);
3885
3886 format %{ "[$reg + $off (32-bit)]" %}
3887 interface(MEMORY_INTER) %{
3888 base($reg);
3889 index(0x4);
3890 scale(0x0);
3891 disp($off);
3892 %}
3893 %}
3894
3895 // Indirect Memory Plus Index Register Plus Offset Operand
3896 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3897 %{
3898 constraint(ALLOC_IN_RC(ptr_reg));
3899 match(AddP (AddP reg lreg) off);
3900
3901 op_cost(10);
3902 format %{"[$reg + $off + $lreg]" %}
3903 interface(MEMORY_INTER) %{
3904 base($reg);
3905 index($lreg);
3906 scale(0x0);
3907 disp($off);
3908 %}
3909 %}
3910
3911 // Indirect Memory Plus Index Register Plus Offset Operand
3912 operand indIndex(any_RegP reg, rRegL lreg)
3913 %{
3914 constraint(ALLOC_IN_RC(ptr_reg));
3915 match(AddP reg lreg);
3916
3917 op_cost(10);
3918 format %{"[$reg + $lreg]" %}
3919 interface(MEMORY_INTER) %{
3920 base($reg);
3921 index($lreg);
3922 scale(0x0);
3923 disp(0x0);
3924 %}
3925 %}
3926
3927 // Indirect Memory Times Scale Plus Index Register
3928 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3929 %{
3930 constraint(ALLOC_IN_RC(ptr_reg));
3931 match(AddP reg (LShiftL lreg scale));
3932
3933 op_cost(10);
3934 format %{"[$reg + $lreg << $scale]" %}
3935 interface(MEMORY_INTER) %{
3936 base($reg);
3937 index($lreg);
3938 scale($scale);
3939 disp(0x0);
3940 %}
3941 %}
3942
3943 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3944 %{
3945 constraint(ALLOC_IN_RC(ptr_reg));
3946 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3947 match(AddP reg (LShiftL (ConvI2L idx) scale));
3948
3949 op_cost(10);
3950 format %{"[$reg + pos $idx << $scale]" %}
3951 interface(MEMORY_INTER) %{
3952 base($reg);
3953 index($idx);
3954 scale($scale);
3955 disp(0x0);
3956 %}
3957 %}
3958
3959 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3960 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3961 %{
3962 constraint(ALLOC_IN_RC(ptr_reg));
3963 match(AddP (AddP reg (LShiftL lreg scale)) off);
3964
3965 op_cost(10);
3966 format %{"[$reg + $off + $lreg << $scale]" %}
3967 interface(MEMORY_INTER) %{
3968 base($reg);
3969 index($lreg);
3970 scale($scale);
3971 disp($off);
3972 %}
3973 %}
3974
3975 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3976 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3977 %{
3978 constraint(ALLOC_IN_RC(ptr_reg));
3979 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3980 match(AddP (AddP reg (ConvI2L idx)) off);
3981
3982 op_cost(10);
3983 format %{"[$reg + $off + $idx]" %}
3984 interface(MEMORY_INTER) %{
3985 base($reg);
3986 index($idx);
3987 scale(0x0);
3988 disp($off);
3989 %}
3990 %}
3991
3992 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3993 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3994 %{
3995 constraint(ALLOC_IN_RC(ptr_reg));
3996 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3997 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3998
3999 op_cost(10);
4000 format %{"[$reg + $off + $idx << $scale]" %}
4001 interface(MEMORY_INTER) %{
4002 base($reg);
4003 index($idx);
4004 scale($scale);
4005 disp($off);
4006 %}
4007 %}
4008
4009 // Indirect Narrow Oop Plus Offset Operand
4010 // Note: x86 architecture doesn't support "scale * index + offset" without a base
4011 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
4012 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
4013 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
4014 constraint(ALLOC_IN_RC(ptr_reg));
4015 match(AddP (DecodeN reg) off);
4016
4017 op_cost(10);
4018 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
4019 interface(MEMORY_INTER) %{
4020 base(0xc); // R12
4021 index($reg);
4022 scale(0x3);
4023 disp($off);
4024 %}
4025 %}
4026
4027 // Indirect Memory Operand
4028 operand indirectNarrow(rRegN reg)
4029 %{
4030 predicate(Universe::narrow_oop_shift() == 0);
4031 constraint(ALLOC_IN_RC(ptr_reg));
4032 match(DecodeN reg);
4033
4034 format %{ "[$reg]" %}
4035 interface(MEMORY_INTER) %{
4036 base($reg);
4037 index(0x4);
4038 scale(0x0);
4039 disp(0x0);
4040 %}
4041 %}
4042
4043 // Indirect Memory Plus Short Offset Operand
4044 operand indOffset8Narrow(rRegN reg, immL8 off)
4045 %{
4046 predicate(Universe::narrow_oop_shift() == 0);
4047 constraint(ALLOC_IN_RC(ptr_reg));
4048 match(AddP (DecodeN reg) off);
4049
4050 format %{ "[$reg + $off (8-bit)]" %}
4051 interface(MEMORY_INTER) %{
4052 base($reg);
4053 index(0x4);
4054 scale(0x0);
4055 disp($off);
4056 %}
4057 %}
4058
4059 // Indirect Memory Plus Long Offset Operand
4060 operand indOffset32Narrow(rRegN reg, immL32 off)
4061 %{
4062 predicate(Universe::narrow_oop_shift() == 0);
4063 constraint(ALLOC_IN_RC(ptr_reg));
4064 match(AddP (DecodeN reg) off);
4065
4066 format %{ "[$reg + $off (32-bit)]" %}
4067 interface(MEMORY_INTER) %{
4068 base($reg);
4069 index(0x4);
4070 scale(0x0);
4071 disp($off);
4072 %}
4073 %}
4074
4075 // Indirect Memory Plus Index Register Plus Offset Operand
4076 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4077 %{
4078 predicate(Universe::narrow_oop_shift() == 0);
4079 constraint(ALLOC_IN_RC(ptr_reg));
4080 match(AddP (AddP (DecodeN reg) lreg) off);
4081
4082 op_cost(10);
4083 format %{"[$reg + $off + $lreg]" %}
4084 interface(MEMORY_INTER) %{
4085 base($reg);
4086 index($lreg);
4087 scale(0x0);
4088 disp($off);
4089 %}
4090 %}
4091
4092 // Indirect Memory Plus Index Register Plus Offset Operand
4093 operand indIndexNarrow(rRegN reg, rRegL lreg)
4094 %{
4095 predicate(Universe::narrow_oop_shift() == 0);
4096 constraint(ALLOC_IN_RC(ptr_reg));
4097 match(AddP (DecodeN reg) lreg);
4098
4099 op_cost(10);
4100 format %{"[$reg + $lreg]" %}
4101 interface(MEMORY_INTER) %{
4102 base($reg);
4103 index($lreg);
4104 scale(0x0);
4105 disp(0x0);
4106 %}
4107 %}
4108
4109 // Indirect Memory Times Scale Plus Index Register
4110 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4111 %{
4112 predicate(Universe::narrow_oop_shift() == 0);
4113 constraint(ALLOC_IN_RC(ptr_reg));
4114 match(AddP (DecodeN reg) (LShiftL lreg scale));
4115
4116 op_cost(10);
4117 format %{"[$reg + $lreg << $scale]" %}
4118 interface(MEMORY_INTER) %{
4119 base($reg);
4120 index($lreg);
4121 scale($scale);
4122 disp(0x0);
4123 %}
4124 %}
4125
4126 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4127 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4128 %{
4129 predicate(Universe::narrow_oop_shift() == 0);
4130 constraint(ALLOC_IN_RC(ptr_reg));
4131 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4132
4133 op_cost(10);
4134 format %{"[$reg + $off + $lreg << $scale]" %}
4135 interface(MEMORY_INTER) %{
4136 base($reg);
4137 index($lreg);
4138 scale($scale);
4139 disp($off);
4140 %}
4141 %}
4142
4143 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4144 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4145 %{
4146 constraint(ALLOC_IN_RC(ptr_reg));
4147 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4148 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4149
4150 op_cost(10);
4151 format %{"[$reg + $off + $idx]" %}
4152 interface(MEMORY_INTER) %{
4153 base($reg);
4154 index($idx);
4155 scale(0x0);
4156 disp($off);
4157 %}
4158 %}
4159
4160 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4161 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4162 %{
4163 constraint(ALLOC_IN_RC(ptr_reg));
4164 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4165 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4166
4167 op_cost(10);
4168 format %{"[$reg + $off + $idx << $scale]" %}
4169 interface(MEMORY_INTER) %{
4170 base($reg);
4171 index($idx);
4172 scale($scale);
4173 disp($off);
4174 %}
4175 %}
4176
4177 //----------Special Memory Operands--------------------------------------------
4178 // Stack Slot Operand - This operand is used for loading and storing temporary
4179 // values on the stack where a match requires a value to
4180 // flow through memory.
4181 operand stackSlotP(sRegP reg)
4182 %{
4183 constraint(ALLOC_IN_RC(stack_slots));
4184 // No match rule because this operand is only generated in matching
4185
4186 format %{ "[$reg]" %}
4187 interface(MEMORY_INTER) %{
4188 base(0x4); // RSP
4189 index(0x4); // No Index
4190 scale(0x0); // No Scale
4191 disp($reg); // Stack Offset
4192 %}
4193 %}
4194
4195 operand stackSlotI(sRegI reg)
4196 %{
4197 constraint(ALLOC_IN_RC(stack_slots));
4198 // No match rule because this operand is only generated in matching
4199
4200 format %{ "[$reg]" %}
4201 interface(MEMORY_INTER) %{
4202 base(0x4); // RSP
4203 index(0x4); // No Index
4204 scale(0x0); // No Scale
4205 disp($reg); // Stack Offset
4206 %}
4207 %}
4208
4209 operand stackSlotF(sRegF reg)
4210 %{
4211 constraint(ALLOC_IN_RC(stack_slots));
4212 // No match rule because this operand is only generated in matching
4213
4214 format %{ "[$reg]" %}
4215 interface(MEMORY_INTER) %{
4216 base(0x4); // RSP
4217 index(0x4); // No Index
4218 scale(0x0); // No Scale
4219 disp($reg); // Stack Offset
4220 %}
4221 %}
4222
4223 operand stackSlotD(sRegD reg)
4224 %{
4225 constraint(ALLOC_IN_RC(stack_slots));
4226 // No match rule because this operand is only generated in matching
4227
4228 format %{ "[$reg]" %}
4229 interface(MEMORY_INTER) %{
4230 base(0x4); // RSP
4231 index(0x4); // No Index
4232 scale(0x0); // No Scale
4233 disp($reg); // Stack Offset
4234 %}
4235 %}
4236 operand stackSlotL(sRegL reg)
4237 %{
4238 constraint(ALLOC_IN_RC(stack_slots));
4239 // No match rule because this operand is only generated in matching
4240
4241 format %{ "[$reg]" %}
4242 interface(MEMORY_INTER) %{
4243 base(0x4); // RSP
4244 index(0x4); // No Index
4245 scale(0x0); // No Scale
4246 disp($reg); // Stack Offset
4247 %}
4248 %}
4249
4250 //----------Conditional Branch Operands----------------------------------------
4251 // Comparison Op - This is the operation of the comparison, and is limited to
4252 // the following set of codes:
4253 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4254 //
4255 // Other attributes of the comparison, such as unsignedness, are specified
4256 // by the comparison instruction that sets a condition code flags register.
4257 // That result is represented by a flags operand whose subtype is appropriate
4258 // to the unsignedness (etc.) of the comparison.
4259 //
4260 // Later, the instruction which matches both the Comparison Op (a Bool) and
4261 // the flags (produced by the Cmp) specifies the coding of the comparison op
4262 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4263
4264 // Comparision Code
4265 operand cmpOp()
4266 %{
4267 match(Bool);
4268
4269 format %{ "" %}
4270 interface(COND_INTER) %{
4271 equal(0x4, "e");
4272 not_equal(0x5, "ne");
4273 less(0xC, "l");
4274 greater_equal(0xD, "ge");
4275 less_equal(0xE, "le");
4276 greater(0xF, "g");
4277 overflow(0x0, "o");
4278 no_overflow(0x1, "no");
4279 %}
4280 %}
4281
4282 // Comparison Code, unsigned compare. Used by FP also, with
4283 // C2 (unordered) turned into GT or LT already. The other bits
4284 // C0 and C3 are turned into Carry & Zero flags.
4285 operand cmpOpU()
4286 %{
4287 match(Bool);
4288
4289 format %{ "" %}
4290 interface(COND_INTER) %{
4291 equal(0x4, "e");
4292 not_equal(0x5, "ne");
4293 less(0x2, "b");
4294 greater_equal(0x3, "nb");
4295 less_equal(0x6, "be");
4296 greater(0x7, "nbe");
4297 overflow(0x0, "o");
4298 no_overflow(0x1, "no");
4299 %}
4300 %}
4301
4302
4303 // Floating comparisons that don't require any fixup for the unordered case
4304 operand cmpOpUCF() %{
4305 match(Bool);
4306 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4307 n->as_Bool()->_test._test == BoolTest::ge ||
4308 n->as_Bool()->_test._test == BoolTest::le ||
4309 n->as_Bool()->_test._test == BoolTest::gt);
4310 format %{ "" %}
4311 interface(COND_INTER) %{
4312 equal(0x4, "e");
4313 not_equal(0x5, "ne");
4314 less(0x2, "b");
4315 greater_equal(0x3, "nb");
4316 less_equal(0x6, "be");
4317 greater(0x7, "nbe");
4318 overflow(0x0, "o");
4319 no_overflow(0x1, "no");
4320 %}
4321 %}
4322
4323
4324 // Floating comparisons that can be fixed up with extra conditional jumps
4325 operand cmpOpUCF2() %{
4326 match(Bool);
4327 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4328 n->as_Bool()->_test._test == BoolTest::eq);
4329 format %{ "" %}
4330 interface(COND_INTER) %{
4331 equal(0x4, "e");
4332 not_equal(0x5, "ne");
4333 less(0x2, "b");
4334 greater_equal(0x3, "nb");
4335 less_equal(0x6, "be");
4336 greater(0x7, "nbe");
4337 overflow(0x0, "o");
4338 no_overflow(0x1, "no");
4339 %}
4340 %}
4341
4342 // Operands for bound floating pointer register arguments
4343 operand rxmm0() %{
4344 constraint(ALLOC_IN_RC(xmm0_reg));
4345 match(VecX);
4346 format%{%}
4347 interface(REG_INTER);
4348 %}
4349 operand rxmm1() %{
4350 constraint(ALLOC_IN_RC(xmm1_reg));
4351 match(VecX);
4352 format%{%}
4353 interface(REG_INTER);
4354 %}
4355 operand rxmm2() %{
4356 constraint(ALLOC_IN_RC(xmm2_reg));
4357 match(VecX);
4358 format%{%}
4359 interface(REG_INTER);
4360 %}
4361 operand rxmm3() %{
4362 constraint(ALLOC_IN_RC(xmm3_reg));
4363 match(VecX);
4364 format%{%}
4365 interface(REG_INTER);
4366 %}
4367 operand rxmm4() %{
4368 constraint(ALLOC_IN_RC(xmm4_reg));
4369 match(VecX);
4370 format%{%}
4371 interface(REG_INTER);
4372 %}
4373 operand rxmm5() %{
4374 constraint(ALLOC_IN_RC(xmm5_reg));
4375 match(VecX);
4376 format%{%}
4377 interface(REG_INTER);
4378 %}
4379 operand rxmm6() %{
4380 constraint(ALLOC_IN_RC(xmm6_reg));
4381 match(VecX);
4382 format%{%}
4383 interface(REG_INTER);
4384 %}
4385 operand rxmm7() %{
4386 constraint(ALLOC_IN_RC(xmm7_reg));
4387 match(VecX);
4388 format%{%}
4389 interface(REG_INTER);
4390 %}
4391 operand rxmm8() %{
4392 constraint(ALLOC_IN_RC(xmm8_reg));
4393 match(VecX);
4394 format%{%}
4395 interface(REG_INTER);
4396 %}
4397 operand rxmm9() %{
4398 constraint(ALLOC_IN_RC(xmm9_reg));
4399 match(VecX);
4400 format%{%}
4401 interface(REG_INTER);
4402 %}
4403 operand rxmm10() %{
4404 constraint(ALLOC_IN_RC(xmm10_reg));
4405 match(VecX);
4406 format%{%}
4407 interface(REG_INTER);
4408 %}
4409 operand rxmm11() %{
4410 constraint(ALLOC_IN_RC(xmm11_reg));
4411 match(VecX);
4412 format%{%}
4413 interface(REG_INTER);
4414 %}
4415 operand rxmm12() %{
4416 constraint(ALLOC_IN_RC(xmm12_reg));
4417 match(VecX);
4418 format%{%}
4419 interface(REG_INTER);
4420 %}
4421 operand rxmm13() %{
4422 constraint(ALLOC_IN_RC(xmm13_reg));
4423 match(VecX);
4424 format%{%}
4425 interface(REG_INTER);
4426 %}
4427 operand rxmm14() %{
4428 constraint(ALLOC_IN_RC(xmm14_reg));
4429 match(VecX);
4430 format%{%}
4431 interface(REG_INTER);
4432 %}
4433 operand rxmm15() %{
4434 constraint(ALLOC_IN_RC(xmm15_reg));
4435 match(VecX);
4436 format%{%}
4437 interface(REG_INTER);
4438 %}
4439 operand rxmm16() %{
4440 constraint(ALLOC_IN_RC(xmm16_reg));
4441 match(VecX);
4442 format%{%}
4443 interface(REG_INTER);
4444 %}
4445 operand rxmm17() %{
4446 constraint(ALLOC_IN_RC(xmm17_reg));
4447 match(VecX);
4448 format%{%}
4449 interface(REG_INTER);
4450 %}
4451 operand rxmm18() %{
4452 constraint(ALLOC_IN_RC(xmm18_reg));
4453 match(VecX);
4454 format%{%}
4455 interface(REG_INTER);
4456 %}
4457 operand rxmm19() %{
4458 constraint(ALLOC_IN_RC(xmm19_reg));
4459 match(VecX);
4460 format%{%}
4461 interface(REG_INTER);
4462 %}
4463 operand rxmm20() %{
4464 constraint(ALLOC_IN_RC(xmm20_reg));
4465 match(VecX);
4466 format%{%}
4467 interface(REG_INTER);
4468 %}
4469 operand rxmm21() %{
4470 constraint(ALLOC_IN_RC(xmm21_reg));
4471 match(VecX);
4472 format%{%}
4473 interface(REG_INTER);
4474 %}
4475 operand rxmm22() %{
4476 constraint(ALLOC_IN_RC(xmm22_reg));
4477 match(VecX);
4478 format%{%}
4479 interface(REG_INTER);
4480 %}
4481 operand rxmm23() %{
4482 constraint(ALLOC_IN_RC(xmm23_reg));
4483 match(VecX);
4484 format%{%}
4485 interface(REG_INTER);
4486 %}
4487 operand rxmm24() %{
4488 constraint(ALLOC_IN_RC(xmm24_reg));
4489 match(VecX);
4490 format%{%}
4491 interface(REG_INTER);
4492 %}
4493 operand rxmm25() %{
4494 constraint(ALLOC_IN_RC(xmm25_reg));
4495 match(VecX);
4496 format%{%}
4497 interface(REG_INTER);
4498 %}
4499 operand rxmm26() %{
4500 constraint(ALLOC_IN_RC(xmm26_reg));
4501 match(VecX);
4502 format%{%}
4503 interface(REG_INTER);
4504 %}
4505 operand rxmm27() %{
4506 constraint(ALLOC_IN_RC(xmm27_reg));
4507 match(VecX);
4508 format%{%}
4509 interface(REG_INTER);
4510 %}
4511 operand rxmm28() %{
4512 constraint(ALLOC_IN_RC(xmm28_reg));
4513 match(VecX);
4514 format%{%}
4515 interface(REG_INTER);
4516 %}
4517 operand rxmm29() %{
4518 constraint(ALLOC_IN_RC(xmm29_reg));
4519 match(VecX);
4520 format%{%}
4521 interface(REG_INTER);
4522 %}
4523 operand rxmm30() %{
4524 constraint(ALLOC_IN_RC(xmm30_reg));
4525 match(VecX);
4526 format%{%}
4527 interface(REG_INTER);
4528 %}
4529 operand rxmm31() %{
4530 constraint(ALLOC_IN_RC(xmm31_reg));
4531 match(VecX);
4532 format%{%}
4533 interface(REG_INTER);
4534 %}
4535
4536 //----------OPERAND CLASSES----------------------------------------------------
4537 // Operand Classes are groups of operands that are used as to simplify
4538 // instruction definitions by not requiring the AD writer to specify separate
4539 // instructions for every form of operand when the instruction accepts
4540 // multiple operand types with the same basic encoding and format. The classic
4541 // case of this is memory operands.
4542
4543 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4544 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4545 indCompressedOopOffset,
4546 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4547 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4548 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4549
4550 //----------PIPELINE-----------------------------------------------------------
4551 // Rules which define the behavior of the target architectures pipeline.
4552 pipeline %{
4553
4554 //----------ATTRIBUTES---------------------------------------------------------
4555 attributes %{
4556 variable_size_instructions; // Fixed size instructions
4557 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4558 instruction_unit_size = 1; // An instruction is 1 bytes long
4559 instruction_fetch_unit_size = 16; // The processor fetches one line
4560 instruction_fetch_units = 1; // of 16 bytes
4561
4562 // List of nop instructions
4563 nops( MachNop );
4564 %}
4565
4566 //----------RESOURCES----------------------------------------------------------
4567 // Resources are the functional units available to the machine
4568
4569 // Generic P2/P3 pipeline
4570 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4571 // 3 instructions decoded per cycle.
4572 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4573 // 3 ALU op, only ALU0 handles mul instructions.
4574 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4575 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4576 BR, FPU,
4577 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4578
4579 //----------PIPELINE DESCRIPTION-----------------------------------------------
4580 // Pipeline Description specifies the stages in the machine's pipeline
4581
4582 // Generic P2/P3 pipeline
4583 pipe_desc(S0, S1, S2, S3, S4, S5);
4584
4585 //----------PIPELINE CLASSES---------------------------------------------------
4586 // Pipeline Classes describe the stages in which input and output are
4587 // referenced by the hardware pipeline.
4588
4589 // Naming convention: ialu or fpu
4590 // Then: _reg
4591 // Then: _reg if there is a 2nd register
4592 // Then: _long if it's a pair of instructions implementing a long
4593 // Then: _fat if it requires the big decoder
4594 // Or: _mem if it requires the big decoder and a memory unit.
4595
4596 // Integer ALU reg operation
4597 pipe_class ialu_reg(rRegI dst)
4598 %{
4599 single_instruction;
4600 dst : S4(write);
4601 dst : S3(read);
4602 DECODE : S0; // any decoder
4603 ALU : S3; // any alu
4604 %}
4605
4606 // Long ALU reg operation
4607 pipe_class ialu_reg_long(rRegL dst)
4608 %{
4609 instruction_count(2);
4610 dst : S4(write);
4611 dst : S3(read);
4612 DECODE : S0(2); // any 2 decoders
4613 ALU : S3(2); // both alus
4614 %}
4615
4616 // Integer ALU reg operation using big decoder
4617 pipe_class ialu_reg_fat(rRegI dst)
4618 %{
4619 single_instruction;
4620 dst : S4(write);
4621 dst : S3(read);
4622 D0 : S0; // big decoder only
4623 ALU : S3; // any alu
4624 %}
4625
4626 // Long ALU reg operation using big decoder
4627 pipe_class ialu_reg_long_fat(rRegL dst)
4628 %{
4629 instruction_count(2);
4630 dst : S4(write);
4631 dst : S3(read);
4632 D0 : S0(2); // big decoder only; twice
4633 ALU : S3(2); // any 2 alus
4634 %}
4635
4636 // Integer ALU reg-reg operation
4637 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4638 %{
4639 single_instruction;
4640 dst : S4(write);
4641 src : S3(read);
4642 DECODE : S0; // any decoder
4643 ALU : S3; // any alu
4644 %}
4645
4646 // Long ALU reg-reg operation
4647 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4648 %{
4649 instruction_count(2);
4650 dst : S4(write);
4651 src : S3(read);
4652 DECODE : S0(2); // any 2 decoders
4653 ALU : S3(2); // both alus
4654 %}
4655
4656 // Integer ALU reg-reg operation
4657 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4658 %{
4659 single_instruction;
4660 dst : S4(write);
4661 src : S3(read);
4662 D0 : S0; // big decoder only
4663 ALU : S3; // any alu
4664 %}
4665
4666 // Long ALU reg-reg operation
4667 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4668 %{
4669 instruction_count(2);
4670 dst : S4(write);
4671 src : S3(read);
4672 D0 : S0(2); // big decoder only; twice
4673 ALU : S3(2); // both alus
4674 %}
4675
4676 // Integer ALU reg-mem operation
4677 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4678 %{
4679 single_instruction;
4680 dst : S5(write);
4681 mem : S3(read);
4682 D0 : S0; // big decoder only
4683 ALU : S4; // any alu
4684 MEM : S3; // any mem
4685 %}
4686
4687 // Integer mem operation (prefetch)
4688 pipe_class ialu_mem(memory mem)
4689 %{
4690 single_instruction;
4691 mem : S3(read);
4692 D0 : S0; // big decoder only
4693 MEM : S3; // any mem
4694 %}
4695
4696 // Integer Store to Memory
4697 pipe_class ialu_mem_reg(memory mem, rRegI src)
4698 %{
4699 single_instruction;
4700 mem : S3(read);
4701 src : S5(read);
4702 D0 : S0; // big decoder only
4703 ALU : S4; // any alu
4704 MEM : S3;
4705 %}
4706
4707 // // Long Store to Memory
4708 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4709 // %{
4710 // instruction_count(2);
4711 // mem : S3(read);
4712 // src : S5(read);
4713 // D0 : S0(2); // big decoder only; twice
4714 // ALU : S4(2); // any 2 alus
4715 // MEM : S3(2); // Both mems
4716 // %}
4717
4718 // Integer Store to Memory
4719 pipe_class ialu_mem_imm(memory mem)
4720 %{
4721 single_instruction;
4722 mem : S3(read);
4723 D0 : S0; // big decoder only
4724 ALU : S4; // any alu
4725 MEM : S3;
4726 %}
4727
4728 // Integer ALU0 reg-reg operation
4729 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4730 %{
4731 single_instruction;
4732 dst : S4(write);
4733 src : S3(read);
4734 D0 : S0; // Big decoder only
4735 ALU0 : S3; // only alu0
4736 %}
4737
4738 // Integer ALU0 reg-mem operation
4739 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4740 %{
4741 single_instruction;
4742 dst : S5(write);
4743 mem : S3(read);
4744 D0 : S0; // big decoder only
4745 ALU0 : S4; // ALU0 only
4746 MEM : S3; // any mem
4747 %}
4748
4749 // Integer ALU reg-reg operation
4750 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4751 %{
4752 single_instruction;
4753 cr : S4(write);
4754 src1 : S3(read);
4755 src2 : S3(read);
4756 DECODE : S0; // any decoder
4757 ALU : S3; // any alu
4758 %}
4759
4760 // Integer ALU reg-imm operation
4761 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4762 %{
4763 single_instruction;
4764 cr : S4(write);
4765 src1 : S3(read);
4766 DECODE : S0; // any decoder
4767 ALU : S3; // any alu
4768 %}
4769
4770 // Integer ALU reg-mem operation
4771 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4772 %{
4773 single_instruction;
4774 cr : S4(write);
4775 src1 : S3(read);
4776 src2 : S3(read);
4777 D0 : S0; // big decoder only
4778 ALU : S4; // any alu
4779 MEM : S3;
4780 %}
4781
4782 // Conditional move reg-reg
4783 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4784 %{
4785 instruction_count(4);
4786 y : S4(read);
4787 q : S3(read);
4788 p : S3(read);
4789 DECODE : S0(4); // any decoder
4790 %}
4791
4792 // Conditional move reg-reg
4793 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4794 %{
4795 single_instruction;
4796 dst : S4(write);
4797 src : S3(read);
4798 cr : S3(read);
4799 DECODE : S0; // any decoder
4800 %}
4801
4802 // Conditional move reg-mem
4803 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4804 %{
4805 single_instruction;
4806 dst : S4(write);
4807 src : S3(read);
4808 cr : S3(read);
4809 DECODE : S0; // any decoder
4810 MEM : S3;
4811 %}
4812
4813 // Conditional move reg-reg long
4814 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4815 %{
4816 single_instruction;
4817 dst : S4(write);
4818 src : S3(read);
4819 cr : S3(read);
4820 DECODE : S0(2); // any 2 decoders
4821 %}
4822
4823 // XXX
4824 // // Conditional move double reg-reg
4825 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4826 // %{
4827 // single_instruction;
4828 // dst : S4(write);
4829 // src : S3(read);
4830 // cr : S3(read);
4831 // DECODE : S0; // any decoder
4832 // %}
4833
4834 // Float reg-reg operation
4835 pipe_class fpu_reg(regD dst)
4836 %{
4837 instruction_count(2);
4838 dst : S3(read);
4839 DECODE : S0(2); // any 2 decoders
4840 FPU : S3;
4841 %}
4842
4843 // Float reg-reg operation
4844 pipe_class fpu_reg_reg(regD dst, regD src)
4845 %{
4846 instruction_count(2);
4847 dst : S4(write);
4848 src : S3(read);
4849 DECODE : S0(2); // any 2 decoders
4850 FPU : S3;
4851 %}
4852
4853 // Float reg-reg operation
4854 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4855 %{
4856 instruction_count(3);
4857 dst : S4(write);
4858 src1 : S3(read);
4859 src2 : S3(read);
4860 DECODE : S0(3); // any 3 decoders
4861 FPU : S3(2);
4862 %}
4863
4864 // Float reg-reg operation
4865 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4866 %{
4867 instruction_count(4);
4868 dst : S4(write);
4869 src1 : S3(read);
4870 src2 : S3(read);
4871 src3 : S3(read);
4872 DECODE : S0(4); // any 3 decoders
4873 FPU : S3(2);
4874 %}
4875
4876 // Float reg-reg operation
4877 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4878 %{
4879 instruction_count(4);
4880 dst : S4(write);
4881 src1 : S3(read);
4882 src2 : S3(read);
4883 src3 : S3(read);
4884 DECODE : S1(3); // any 3 decoders
4885 D0 : S0; // Big decoder only
4886 FPU : S3(2);
4887 MEM : S3;
4888 %}
4889
4890 // Float reg-mem operation
4891 pipe_class fpu_reg_mem(regD dst, memory mem)
4892 %{
4893 instruction_count(2);
4894 dst : S5(write);
4895 mem : S3(read);
4896 D0 : S0; // big decoder only
4897 DECODE : S1; // any decoder for FPU POP
4898 FPU : S4;
4899 MEM : S3; // any mem
4900 %}
4901
4902 // Float reg-mem operation
4903 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4904 %{
4905 instruction_count(3);
4906 dst : S5(write);
4907 src1 : S3(read);
4908 mem : S3(read);
4909 D0 : S0; // big decoder only
4910 DECODE : S1(2); // any decoder for FPU POP
4911 FPU : S4;
4912 MEM : S3; // any mem
4913 %}
4914
4915 // Float mem-reg operation
4916 pipe_class fpu_mem_reg(memory mem, regD src)
4917 %{
4918 instruction_count(2);
4919 src : S5(read);
4920 mem : S3(read);
4921 DECODE : S0; // any decoder for FPU PUSH
4922 D0 : S1; // big decoder only
4923 FPU : S4;
4924 MEM : S3; // any mem
4925 %}
4926
4927 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4928 %{
4929 instruction_count(3);
4930 src1 : S3(read);
4931 src2 : S3(read);
4932 mem : S3(read);
4933 DECODE : S0(2); // any decoder for FPU PUSH
4934 D0 : S1; // big decoder only
4935 FPU : S4;
4936 MEM : S3; // any mem
4937 %}
4938
4939 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4940 %{
4941 instruction_count(3);
4942 src1 : S3(read);
4943 src2 : S3(read);
4944 mem : S4(read);
4945 DECODE : S0; // any decoder for FPU PUSH
4946 D0 : S0(2); // big decoder only
4947 FPU : S4;
4948 MEM : S3(2); // any mem
4949 %}
4950
4951 pipe_class fpu_mem_mem(memory dst, memory src1)
4952 %{
4953 instruction_count(2);
4954 src1 : S3(read);
4955 dst : S4(read);
4956 D0 : S0(2); // big decoder only
4957 MEM : S3(2); // any mem
4958 %}
4959
4960 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4961 %{
4962 instruction_count(3);
4963 src1 : S3(read);
4964 src2 : S3(read);
4965 dst : S4(read);
4966 D0 : S0(3); // big decoder only
4967 FPU : S4;
4968 MEM : S3(3); // any mem
4969 %}
4970
4971 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4972 %{
4973 instruction_count(3);
4974 src1 : S4(read);
4975 mem : S4(read);
4976 DECODE : S0; // any decoder for FPU PUSH
4977 D0 : S0(2); // big decoder only
4978 FPU : S4;
4979 MEM : S3(2); // any mem
4980 %}
4981
4982 // Float load constant
4983 pipe_class fpu_reg_con(regD dst)
4984 %{
4985 instruction_count(2);
4986 dst : S5(write);
4987 D0 : S0; // big decoder only for the load
4988 DECODE : S1; // any decoder for FPU POP
4989 FPU : S4;
4990 MEM : S3; // any mem
4991 %}
4992
4993 // Float load constant
4994 pipe_class fpu_reg_reg_con(regD dst, regD src)
4995 %{
4996 instruction_count(3);
4997 dst : S5(write);
4998 src : S3(read);
4999 D0 : S0; // big decoder only for the load
5000 DECODE : S1(2); // any decoder for FPU POP
5001 FPU : S4;
5002 MEM : S3; // any mem
5003 %}
5004
5005 // UnConditional branch
5006 pipe_class pipe_jmp(label labl)
5007 %{
5008 single_instruction;
5009 BR : S3;
5010 %}
5011
5012 // Conditional branch
5013 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
5014 %{
5015 single_instruction;
5016 cr : S1(read);
5017 BR : S3;
5018 %}
5019
5020 // Allocation idiom
5021 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
5022 %{
5023 instruction_count(1); force_serialization;
5024 fixed_latency(6);
5025 heap_ptr : S3(read);
5026 DECODE : S0(3);
5027 D0 : S2;
5028 MEM : S3;
5029 ALU : S3(2);
5030 dst : S5(write);
5031 BR : S5;
5032 %}
5033
5034 // Generic big/slow expanded idiom
5035 pipe_class pipe_slow()
5036 %{
5037 instruction_count(10); multiple_bundles; force_serialization;
5038 fixed_latency(100);
5039 D0 : S0(2);
5040 MEM : S3(2);
5041 %}
5042
5043 // The real do-nothing guy
5044 pipe_class empty()
5045 %{
5046 instruction_count(0);
5047 %}
5048
5049 // Define the class for the Nop node
5050 define
5051 %{
5052 MachNop = empty;
5053 %}
5054
5055 %}
5056
5057 //----------INSTRUCTIONS-------------------------------------------------------
5058 //
5059 // match -- States which machine-independent subtree may be replaced
5060 // by this instruction.
5061 // ins_cost -- The estimated cost of this instruction is used by instruction
5062 // selection to identify a minimum cost tree of machine
5063 // instructions that matches a tree of machine-independent
5064 // instructions.
5065 // format -- A string providing the disassembly for this instruction.
5066 // The value of an instruction's operand may be inserted
5067 // by referring to it with a '$' prefix.
5068 // opcode -- Three instruction opcodes may be provided. These are referred
5069 // to within an encode class as $primary, $secondary, and $tertiary
5070 // rrspectively. The primary opcode is commonly used to
5071 // indicate the type of machine instruction, while secondary
5072 // and tertiary are often used for prefix options or addressing
5073 // modes.
5074 // ins_encode -- A list of encode classes with parameters. The encode class
5075 // name must have been defined in an 'enc_class' specification
5076 // in the encode section of the architecture description.
5077
5078
5079 //----------Load/Store/Move Instructions---------------------------------------
5080 //----------Load Instructions--------------------------------------------------
5081
5082 // Load Byte (8 bit signed)
5083 instruct loadB(rRegI dst, memory mem)
5084 %{
5085 match(Set dst (LoadB mem));
5086
5087 ins_cost(125);
5088 format %{ "movsbl $dst, $mem\t# byte" %}
5089
5090 ins_encode %{
5091 __ movsbl($dst$$Register, $mem$$Address);
5092 %}
5093
5094 ins_pipe(ialu_reg_mem);
5095 %}
5096
5097 // Load Byte (8 bit signed) into Long Register
5098 instruct loadB2L(rRegL dst, memory mem)
5099 %{
5100 match(Set dst (ConvI2L (LoadB mem)));
5101
5102 ins_cost(125);
5103 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5104
5105 ins_encode %{
5106 __ movsbq($dst$$Register, $mem$$Address);
5107 %}
5108
5109 ins_pipe(ialu_reg_mem);
5110 %}
5111
5112 // Load Unsigned Byte (8 bit UNsigned)
5113 instruct loadUB(rRegI dst, memory mem)
5114 %{
5115 match(Set dst (LoadUB mem));
5116
5117 ins_cost(125);
5118 format %{ "movzbl $dst, $mem\t# ubyte" %}
5119
5120 ins_encode %{
5121 __ movzbl($dst$$Register, $mem$$Address);
5122 %}
5123
5124 ins_pipe(ialu_reg_mem);
5125 %}
5126
5127 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5128 instruct loadUB2L(rRegL dst, memory mem)
5129 %{
5130 match(Set dst (ConvI2L (LoadUB mem)));
5131
5132 ins_cost(125);
5133 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5134
5135 ins_encode %{
5136 __ movzbq($dst$$Register, $mem$$Address);
5137 %}
5138
5139 ins_pipe(ialu_reg_mem);
5140 %}
5141
5142 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5143 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5144 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5145 effect(KILL cr);
5146
5147 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5148 "andl $dst, right_n_bits($mask, 8)" %}
5149 ins_encode %{
5150 Register Rdst = $dst$$Register;
5151 __ movzbq(Rdst, $mem$$Address);
5152 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5153 %}
5154 ins_pipe(ialu_reg_mem);
5155 %}
5156
5157 // Load Short (16 bit signed)
5158 instruct loadS(rRegI dst, memory mem)
5159 %{
5160 match(Set dst (LoadS mem));
5161
5162 ins_cost(125);
5163 format %{ "movswl $dst, $mem\t# short" %}
5164
5165 ins_encode %{
5166 __ movswl($dst$$Register, $mem$$Address);
5167 %}
5168
5169 ins_pipe(ialu_reg_mem);
5170 %}
5171
5172 // Load Short (16 bit signed) to Byte (8 bit signed)
5173 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5174 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5175
5176 ins_cost(125);
5177 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5178 ins_encode %{
5179 __ movsbl($dst$$Register, $mem$$Address);
5180 %}
5181 ins_pipe(ialu_reg_mem);
5182 %}
5183
5184 // Load Short (16 bit signed) into Long Register
5185 instruct loadS2L(rRegL dst, memory mem)
5186 %{
5187 match(Set dst (ConvI2L (LoadS mem)));
5188
5189 ins_cost(125);
5190 format %{ "movswq $dst, $mem\t# short -> long" %}
5191
5192 ins_encode %{
5193 __ movswq($dst$$Register, $mem$$Address);
5194 %}
5195
5196 ins_pipe(ialu_reg_mem);
5197 %}
5198
5199 // Load Unsigned Short/Char (16 bit UNsigned)
5200 instruct loadUS(rRegI dst, memory mem)
5201 %{
5202 match(Set dst (LoadUS mem));
5203
5204 ins_cost(125);
5205 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5206
5207 ins_encode %{
5208 __ movzwl($dst$$Register, $mem$$Address);
5209 %}
5210
5211 ins_pipe(ialu_reg_mem);
5212 %}
5213
5214 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5215 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5216 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5217
5218 ins_cost(125);
5219 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5220 ins_encode %{
5221 __ movsbl($dst$$Register, $mem$$Address);
5222 %}
5223 ins_pipe(ialu_reg_mem);
5224 %}
5225
5226 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5227 instruct loadUS2L(rRegL dst, memory mem)
5228 %{
5229 match(Set dst (ConvI2L (LoadUS mem)));
5230
5231 ins_cost(125);
5232 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5233
5234 ins_encode %{
5235 __ movzwq($dst$$Register, $mem$$Address);
5236 %}
5237
5238 ins_pipe(ialu_reg_mem);
5239 %}
5240
5241 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5242 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5243 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5244
5245 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5246 ins_encode %{
5247 __ movzbq($dst$$Register, $mem$$Address);
5248 %}
5249 ins_pipe(ialu_reg_mem);
5250 %}
5251
5252 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5253 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5254 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5255 effect(KILL cr);
5256
5257 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5258 "andl $dst, right_n_bits($mask, 16)" %}
5259 ins_encode %{
5260 Register Rdst = $dst$$Register;
5261 __ movzwq(Rdst, $mem$$Address);
5262 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5263 %}
5264 ins_pipe(ialu_reg_mem);
5265 %}
5266
5267 // Load Integer
5268 instruct loadI(rRegI dst, memory mem)
5269 %{
5270 match(Set dst (LoadI mem));
5271
5272 ins_cost(125);
5273 format %{ "movl $dst, $mem\t# int" %}
5274
5275 ins_encode %{
5276 __ movl($dst$$Register, $mem$$Address);
5277 %}
5278
5279 ins_pipe(ialu_reg_mem);
5280 %}
5281
5282 // Load Integer (32 bit signed) to Byte (8 bit signed)
5283 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5284 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5285
5286 ins_cost(125);
5287 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5288 ins_encode %{
5289 __ movsbl($dst$$Register, $mem$$Address);
5290 %}
5291 ins_pipe(ialu_reg_mem);
5292 %}
5293
5294 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5295 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5296 match(Set dst (AndI (LoadI mem) mask));
5297
5298 ins_cost(125);
5299 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5300 ins_encode %{
5301 __ movzbl($dst$$Register, $mem$$Address);
5302 %}
5303 ins_pipe(ialu_reg_mem);
5304 %}
5305
5306 // Load Integer (32 bit signed) to Short (16 bit signed)
5307 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5308 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5309
5310 ins_cost(125);
5311 format %{ "movswl $dst, $mem\t# int -> short" %}
5312 ins_encode %{
5313 __ movswl($dst$$Register, $mem$$Address);
5314 %}
5315 ins_pipe(ialu_reg_mem);
5316 %}
5317
5318 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5319 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5320 match(Set dst (AndI (LoadI mem) mask));
5321
5322 ins_cost(125);
5323 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5324 ins_encode %{
5325 __ movzwl($dst$$Register, $mem$$Address);
5326 %}
5327 ins_pipe(ialu_reg_mem);
5328 %}
5329
5330 // Load Integer into Long Register
5331 instruct loadI2L(rRegL dst, memory mem)
5332 %{
5333 match(Set dst (ConvI2L (LoadI mem)));
5334
5335 ins_cost(125);
5336 format %{ "movslq $dst, $mem\t# int -> long" %}
5337
5338 ins_encode %{
5339 __ movslq($dst$$Register, $mem$$Address);
5340 %}
5341
5342 ins_pipe(ialu_reg_mem);
5343 %}
5344
5345 // Load Integer with mask 0xFF into Long Register
5346 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5347 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5348
5349 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5350 ins_encode %{
5351 __ movzbq($dst$$Register, $mem$$Address);
5352 %}
5353 ins_pipe(ialu_reg_mem);
5354 %}
5355
5356 // Load Integer with mask 0xFFFF into Long Register
5357 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5358 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5359
5360 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5361 ins_encode %{
5362 __ movzwq($dst$$Register, $mem$$Address);
5363 %}
5364 ins_pipe(ialu_reg_mem);
5365 %}
5366
5367 // Load Integer with a 31-bit mask into Long Register
5368 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5369 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5370 effect(KILL cr);
5371
5372 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5373 "andl $dst, $mask" %}
5374 ins_encode %{
5375 Register Rdst = $dst$$Register;
5376 __ movl(Rdst, $mem$$Address);
5377 __ andl(Rdst, $mask$$constant);
5378 %}
5379 ins_pipe(ialu_reg_mem);
5380 %}
5381
5382 // Load Unsigned Integer into Long Register
5383 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5384 %{
5385 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5386
5387 ins_cost(125);
5388 format %{ "movl $dst, $mem\t# uint -> long" %}
5389
5390 ins_encode %{
5391 __ movl($dst$$Register, $mem$$Address);
5392 %}
5393
5394 ins_pipe(ialu_reg_mem);
5395 %}
5396
5397 // Load Long
5398 instruct loadL(rRegL dst, memory mem)
5399 %{
5400 match(Set dst (LoadL mem));
5401
5402 ins_cost(125);
5403 format %{ "movq $dst, $mem\t# long" %}
5404
5405 ins_encode %{
5406 __ movq($dst$$Register, $mem$$Address);
5407 %}
5408
5409 ins_pipe(ialu_reg_mem); // XXX
5410 %}
5411
5412 // Load Range
5413 instruct loadRange(rRegI dst, memory mem)
5414 %{
5415 match(Set dst (LoadRange mem));
5416
5417 ins_cost(125); // XXX
5418 format %{ "movl $dst, $mem\t# range" %}
5419 opcode(0x8B);
5420 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5421 ins_pipe(ialu_reg_mem);
5422 %}
5423
5424 // Load Pointer
5425 instruct loadP(rRegP dst, memory mem)
5426 %{
5427 match(Set dst (LoadP mem));
5428
5429 ins_cost(125); // XXX
5430 format %{ "movq $dst, $mem\t# ptr" %}
5431 opcode(0x8B);
5432 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5433 ins_pipe(ialu_reg_mem); // XXX
5434 %}
5435
5436 // Load Compressed Pointer
5437 instruct loadN(rRegN dst, memory mem)
5438 %{
5439 match(Set dst (LoadN mem));
5440
5441 ins_cost(125); // XXX
5442 format %{ "movl $dst, $mem\t# compressed ptr" %}
5443 ins_encode %{
5444 __ movl($dst$$Register, $mem$$Address);
5445 %}
5446 ins_pipe(ialu_reg_mem); // XXX
5447 %}
5448
5449
5450 // Load Klass Pointer
5451 instruct loadKlass(rRegP dst, memory mem)
5452 %{
5453 match(Set dst (LoadKlass mem));
5454
5455 ins_cost(125); // XXX
5456 format %{ "movq $dst, $mem\t# class" %}
5457 opcode(0x8B);
5458 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5459 ins_pipe(ialu_reg_mem); // XXX
5460 %}
5461
5462 // Load narrow Klass Pointer
5463 instruct loadNKlass(rRegN dst, memory mem)
5464 %{
5465 match(Set dst (LoadNKlass mem));
5466
5467 ins_cost(125); // XXX
5468 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5469 ins_encode %{
5470 __ movl($dst$$Register, $mem$$Address);
5471 %}
5472 ins_pipe(ialu_reg_mem); // XXX
5473 %}
5474
5475 // Load Float
5476 instruct loadF(regF dst, memory mem)
5477 %{
5478 match(Set dst (LoadF mem));
5479
5480 ins_cost(145); // XXX
5481 format %{ "movss $dst, $mem\t# float" %}
5482 ins_encode %{
5483 __ movflt($dst$$XMMRegister, $mem$$Address);
5484 %}
5485 ins_pipe(pipe_slow); // XXX
5486 %}
5487
5488 // Load Float
5489 instruct MoveF2VL(vlRegF dst, regF src) %{
5490 match(Set dst src);
5491 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5492 ins_encode %{
5493 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5494 %}
5495 ins_pipe( fpu_reg_reg );
5496 %}
5497
5498 // Load Float
5499 instruct MoveVL2F(regF dst, vlRegF src) %{
5500 match(Set dst src);
5501 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5502 ins_encode %{
5503 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5504 %}
5505 ins_pipe( fpu_reg_reg );
5506 %}
5507
5508 // Load Double
5509 instruct loadD_partial(regD dst, memory mem)
5510 %{
5511 predicate(!UseXmmLoadAndClearUpper);
5512 match(Set dst (LoadD mem));
5513
5514 ins_cost(145); // XXX
5515 format %{ "movlpd $dst, $mem\t# double" %}
5516 ins_encode %{
5517 __ movdbl($dst$$XMMRegister, $mem$$Address);
5518 %}
5519 ins_pipe(pipe_slow); // XXX
5520 %}
5521
5522 instruct loadD(regD dst, memory mem)
5523 %{
5524 predicate(UseXmmLoadAndClearUpper);
5525 match(Set dst (LoadD mem));
5526
5527 ins_cost(145); // XXX
5528 format %{ "movsd $dst, $mem\t# double" %}
5529 ins_encode %{
5530 __ movdbl($dst$$XMMRegister, $mem$$Address);
5531 %}
5532 ins_pipe(pipe_slow); // XXX
5533 %}
5534
5535 // Load Double
5536 instruct MoveD2VL(vlRegD dst, regD src) %{
5537 match(Set dst src);
5538 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5539 ins_encode %{
5540 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5541 %}
5542 ins_pipe( fpu_reg_reg );
5543 %}
5544
5545 // Load Double
5546 instruct MoveVL2D(regD dst, vlRegD src) %{
5547 match(Set dst src);
5548 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5549 ins_encode %{
5550 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5551 %}
5552 ins_pipe( fpu_reg_reg );
5553 %}
5554
5555 // Load Effective Address
5556 instruct leaP8(rRegP dst, indOffset8 mem)
5557 %{
5558 match(Set dst mem);
5559
5560 ins_cost(110); // XXX
5561 format %{ "leaq $dst, $mem\t# ptr 8" %}
5562 opcode(0x8D);
5563 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5564 ins_pipe(ialu_reg_reg_fat);
5565 %}
5566
5567 instruct leaP32(rRegP dst, indOffset32 mem)
5568 %{
5569 match(Set dst mem);
5570
5571 ins_cost(110);
5572 format %{ "leaq $dst, $mem\t# ptr 32" %}
5573 opcode(0x8D);
5574 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5575 ins_pipe(ialu_reg_reg_fat);
5576 %}
5577
5578 // instruct leaPIdx(rRegP dst, indIndex mem)
5579 // %{
5580 // match(Set dst mem);
5581
5582 // ins_cost(110);
5583 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5584 // opcode(0x8D);
5585 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5586 // ins_pipe(ialu_reg_reg_fat);
5587 // %}
5588
5589 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5590 %{
5591 match(Set dst mem);
5592
5593 ins_cost(110);
5594 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5595 opcode(0x8D);
5596 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5597 ins_pipe(ialu_reg_reg_fat);
5598 %}
5599
5600 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5601 %{
5602 match(Set dst mem);
5603
5604 ins_cost(110);
5605 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5606 opcode(0x8D);
5607 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5608 ins_pipe(ialu_reg_reg_fat);
5609 %}
5610
5611 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5612 %{
5613 match(Set dst mem);
5614
5615 ins_cost(110);
5616 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5617 opcode(0x8D);
5618 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5619 ins_pipe(ialu_reg_reg_fat);
5620 %}
5621
5622 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5623 %{
5624 match(Set dst mem);
5625
5626 ins_cost(110);
5627 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5628 opcode(0x8D);
5629 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5630 ins_pipe(ialu_reg_reg_fat);
5631 %}
5632
5633 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5634 %{
5635 match(Set dst mem);
5636
5637 ins_cost(110);
5638 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5639 opcode(0x8D);
5640 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5641 ins_pipe(ialu_reg_reg_fat);
5642 %}
5643
5644 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5645 %{
5646 match(Set dst mem);
5647
5648 ins_cost(110);
5649 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5650 opcode(0x8D);
5651 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5652 ins_pipe(ialu_reg_reg_fat);
5653 %}
5654
5655 // Load Effective Address which uses Narrow (32-bits) oop
5656 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5657 %{
5658 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5659 match(Set dst mem);
5660
5661 ins_cost(110);
5662 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5663 opcode(0x8D);
5664 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5665 ins_pipe(ialu_reg_reg_fat);
5666 %}
5667
5668 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5669 %{
5670 predicate(Universe::narrow_oop_shift() == 0);
5671 match(Set dst mem);
5672
5673 ins_cost(110); // XXX
5674 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5675 opcode(0x8D);
5676 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5677 ins_pipe(ialu_reg_reg_fat);
5678 %}
5679
5680 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5681 %{
5682 predicate(Universe::narrow_oop_shift() == 0);
5683 match(Set dst mem);
5684
5685 ins_cost(110);
5686 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5687 opcode(0x8D);
5688 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5689 ins_pipe(ialu_reg_reg_fat);
5690 %}
5691
5692 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5693 %{
5694 predicate(Universe::narrow_oop_shift() == 0);
5695 match(Set dst mem);
5696
5697 ins_cost(110);
5698 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5699 opcode(0x8D);
5700 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5701 ins_pipe(ialu_reg_reg_fat);
5702 %}
5703
5704 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5705 %{
5706 predicate(Universe::narrow_oop_shift() == 0);
5707 match(Set dst mem);
5708
5709 ins_cost(110);
5710 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5711 opcode(0x8D);
5712 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5713 ins_pipe(ialu_reg_reg_fat);
5714 %}
5715
5716 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5717 %{
5718 predicate(Universe::narrow_oop_shift() == 0);
5719 match(Set dst mem);
5720
5721 ins_cost(110);
5722 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5723 opcode(0x8D);
5724 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5725 ins_pipe(ialu_reg_reg_fat);
5726 %}
5727
5728 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5729 %{
5730 predicate(Universe::narrow_oop_shift() == 0);
5731 match(Set dst mem);
5732
5733 ins_cost(110);
5734 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5735 opcode(0x8D);
5736 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5737 ins_pipe(ialu_reg_reg_fat);
5738 %}
5739
5740 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5741 %{
5742 predicate(Universe::narrow_oop_shift() == 0);
5743 match(Set dst mem);
5744
5745 ins_cost(110);
5746 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5747 opcode(0x8D);
5748 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5749 ins_pipe(ialu_reg_reg_fat);
5750 %}
5751
5752 instruct loadConI(rRegI dst, immI src)
5753 %{
5754 match(Set dst src);
5755
5756 format %{ "movl $dst, $src\t# int" %}
5757 ins_encode(load_immI(dst, src));
5758 ins_pipe(ialu_reg_fat); // XXX
5759 %}
5760
5761 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5762 %{
5763 match(Set dst src);
5764 effect(KILL cr);
5765
5766 ins_cost(50);
5767 format %{ "xorl $dst, $dst\t# int" %}
5768 opcode(0x33); /* + rd */
5769 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5770 ins_pipe(ialu_reg);
5771 %}
5772
5773 instruct loadConL(rRegL dst, immL src)
5774 %{
5775 match(Set dst src);
5776
5777 ins_cost(150);
5778 format %{ "movq $dst, $src\t# long" %}
5779 ins_encode(load_immL(dst, src));
5780 ins_pipe(ialu_reg);
5781 %}
5782
5783 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5784 %{
5785 match(Set dst src);
5786 effect(KILL cr);
5787
5788 ins_cost(50);
5789 format %{ "xorl $dst, $dst\t# long" %}
5790 opcode(0x33); /* + rd */
5791 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5792 ins_pipe(ialu_reg); // XXX
5793 %}
5794
5795 instruct loadConUL32(rRegL dst, immUL32 src)
5796 %{
5797 match(Set dst src);
5798
5799 ins_cost(60);
5800 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5801 ins_encode(load_immUL32(dst, src));
5802 ins_pipe(ialu_reg);
5803 %}
5804
5805 instruct loadConL32(rRegL dst, immL32 src)
5806 %{
5807 match(Set dst src);
5808
5809 ins_cost(70);
5810 format %{ "movq $dst, $src\t# long (32-bit)" %}
5811 ins_encode(load_immL32(dst, src));
5812 ins_pipe(ialu_reg);
5813 %}
5814
5815 instruct loadConP(rRegP dst, immP con) %{
5816 match(Set dst con);
5817
5818 format %{ "movq $dst, $con\t# ptr" %}
5819 ins_encode(load_immP(dst, con));
5820 ins_pipe(ialu_reg_fat); // XXX
5821 %}
5822
5823 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5824 %{
5825 match(Set dst src);
5826 effect(KILL cr);
5827
5828 ins_cost(50);
5829 format %{ "xorl $dst, $dst\t# ptr" %}
5830 opcode(0x33); /* + rd */
5831 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5832 ins_pipe(ialu_reg);
5833 %}
5834
5835 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5836 %{
5837 match(Set dst src);
5838 effect(KILL cr);
5839
5840 ins_cost(60);
5841 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5842 ins_encode(load_immP31(dst, src));
5843 ins_pipe(ialu_reg);
5844 %}
5845
5846 instruct loadConF(regF dst, immF con) %{
5847 match(Set dst con);
5848 ins_cost(125);
5849 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5850 ins_encode %{
5851 __ movflt($dst$$XMMRegister, $constantaddress($con));
5852 %}
5853 ins_pipe(pipe_slow);
5854 %}
5855
5856 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5857 match(Set dst src);
5858 effect(KILL cr);
5859 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5860 ins_encode %{
5861 __ xorq($dst$$Register, $dst$$Register);
5862 %}
5863 ins_pipe(ialu_reg);
5864 %}
5865
5866 instruct loadConN(rRegN dst, immN src) %{
5867 match(Set dst src);
5868
5869 ins_cost(125);
5870 format %{ "movl $dst, $src\t# compressed ptr" %}
5871 ins_encode %{
5872 address con = (address)$src$$constant;
5873 if (con == NULL) {
5874 ShouldNotReachHere();
5875 } else {
5876 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5877 }
5878 %}
5879 ins_pipe(ialu_reg_fat); // XXX
5880 %}
5881
5882 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5883 match(Set dst src);
5884
5885 ins_cost(125);
5886 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5887 ins_encode %{
5888 address con = (address)$src$$constant;
5889 if (con == NULL) {
5890 ShouldNotReachHere();
5891 } else {
5892 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5893 }
5894 %}
5895 ins_pipe(ialu_reg_fat); // XXX
5896 %}
5897
5898 instruct loadConF0(regF dst, immF0 src)
5899 %{
5900 match(Set dst src);
5901 ins_cost(100);
5902
5903 format %{ "xorps $dst, $dst\t# float 0.0" %}
5904 ins_encode %{
5905 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5906 %}
5907 ins_pipe(pipe_slow);
5908 %}
5909
5910 // Use the same format since predicate() can not be used here.
5911 instruct loadConD(regD dst, immD con) %{
5912 match(Set dst con);
5913 ins_cost(125);
5914 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5915 ins_encode %{
5916 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5917 %}
5918 ins_pipe(pipe_slow);
5919 %}
5920
5921 instruct loadConD0(regD dst, immD0 src)
5922 %{
5923 match(Set dst src);
5924 ins_cost(100);
5925
5926 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5927 ins_encode %{
5928 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5929 %}
5930 ins_pipe(pipe_slow);
5931 %}
5932
5933 instruct loadSSI(rRegI dst, stackSlotI src)
5934 %{
5935 match(Set dst src);
5936
5937 ins_cost(125);
5938 format %{ "movl $dst, $src\t# int stk" %}
5939 opcode(0x8B);
5940 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5941 ins_pipe(ialu_reg_mem);
5942 %}
5943
5944 instruct loadSSL(rRegL dst, stackSlotL src)
5945 %{
5946 match(Set dst src);
5947
5948 ins_cost(125);
5949 format %{ "movq $dst, $src\t# long stk" %}
5950 opcode(0x8B);
5951 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5952 ins_pipe(ialu_reg_mem);
5953 %}
5954
5955 instruct loadSSP(rRegP dst, stackSlotP src)
5956 %{
5957 match(Set dst src);
5958
5959 ins_cost(125);
5960 format %{ "movq $dst, $src\t# ptr stk" %}
5961 opcode(0x8B);
5962 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5963 ins_pipe(ialu_reg_mem);
5964 %}
5965
5966 instruct loadSSF(regF dst, stackSlotF src)
5967 %{
5968 match(Set dst src);
5969
5970 ins_cost(125);
5971 format %{ "movss $dst, $src\t# float stk" %}
5972 ins_encode %{
5973 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5974 %}
5975 ins_pipe(pipe_slow); // XXX
5976 %}
5977
5978 // Use the same format since predicate() can not be used here.
5979 instruct loadSSD(regD dst, stackSlotD src)
5980 %{
5981 match(Set dst src);
5982
5983 ins_cost(125);
5984 format %{ "movsd $dst, $src\t# double stk" %}
5985 ins_encode %{
5986 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5987 %}
5988 ins_pipe(pipe_slow); // XXX
5989 %}
5990
5991 // Prefetch instructions for allocation.
5992 // Must be safe to execute with invalid address (cannot fault).
5993
5994 instruct prefetchAlloc( memory mem ) %{
5995 predicate(AllocatePrefetchInstr==3);
5996 match(PrefetchAllocation mem);
5997 ins_cost(125);
5998
5999 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6000 ins_encode %{
6001 __ prefetchw($mem$$Address);
6002 %}
6003 ins_pipe(ialu_mem);
6004 %}
6005
6006 instruct prefetchAllocNTA( memory mem ) %{
6007 predicate(AllocatePrefetchInstr==0);
6008 match(PrefetchAllocation mem);
6009 ins_cost(125);
6010
6011 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6012 ins_encode %{
6013 __ prefetchnta($mem$$Address);
6014 %}
6015 ins_pipe(ialu_mem);
6016 %}
6017
6018 instruct prefetchAllocT0( memory mem ) %{
6019 predicate(AllocatePrefetchInstr==1);
6020 match(PrefetchAllocation mem);
6021 ins_cost(125);
6022
6023 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6024 ins_encode %{
6025 __ prefetcht0($mem$$Address);
6026 %}
6027 ins_pipe(ialu_mem);
6028 %}
6029
6030 instruct prefetchAllocT2( memory mem ) %{
6031 predicate(AllocatePrefetchInstr==2);
6032 match(PrefetchAllocation mem);
6033 ins_cost(125);
6034
6035 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6036 ins_encode %{
6037 __ prefetcht2($mem$$Address);
6038 %}
6039 ins_pipe(ialu_mem);
6040 %}
6041
6042 //----------Store Instructions-------------------------------------------------
6043
6044 // Store Byte
6045 instruct storeB(memory mem, rRegI src)
6046 %{
6047 match(Set mem (StoreB mem src));
6048
6049 ins_cost(125); // XXX
6050 format %{ "movb $mem, $src\t# byte" %}
6051 opcode(0x88);
6052 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6053 ins_pipe(ialu_mem_reg);
6054 %}
6055
6056 // Store Char/Short
6057 instruct storeC(memory mem, rRegI src)
6058 %{
6059 match(Set mem (StoreC mem src));
6060
6061 ins_cost(125); // XXX
6062 format %{ "movw $mem, $src\t# char/short" %}
6063 opcode(0x89);
6064 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6065 ins_pipe(ialu_mem_reg);
6066 %}
6067
6068 // Store Integer
6069 instruct storeI(memory mem, rRegI src)
6070 %{
6071 match(Set mem (StoreI mem src));
6072
6073 ins_cost(125); // XXX
6074 format %{ "movl $mem, $src\t# int" %}
6075 opcode(0x89);
6076 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6077 ins_pipe(ialu_mem_reg);
6078 %}
6079
6080 // Store Long
6081 instruct storeL(memory mem, rRegL src)
6082 %{
6083 match(Set mem (StoreL mem src));
6084
6085 ins_cost(125); // XXX
6086 format %{ "movq $mem, $src\t# long" %}
6087 opcode(0x89);
6088 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6089 ins_pipe(ialu_mem_reg); // XXX
6090 %}
6091
6092 // Store Pointer
6093 instruct storeP(memory mem, any_RegP src)
6094 %{
6095 match(Set mem (StoreP mem src));
6096
6097 ins_cost(125); // XXX
6098 format %{ "movq $mem, $src\t# ptr" %}
6099 opcode(0x89);
6100 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6101 ins_pipe(ialu_mem_reg);
6102 %}
6103
6104 instruct storeImmP0(memory mem, immP0 zero)
6105 %{
6106 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6107 match(Set mem (StoreP mem zero));
6108
6109 ins_cost(125); // XXX
6110 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6111 ins_encode %{
6112 __ movq($mem$$Address, r12);
6113 %}
6114 ins_pipe(ialu_mem_reg);
6115 %}
6116
6117 // Store NULL Pointer, mark word, or other simple pointer constant.
6118 instruct storeImmP(memory mem, immP31 src)
6119 %{
6120 match(Set mem (StoreP mem src));
6121
6122 ins_cost(150); // XXX
6123 format %{ "movq $mem, $src\t# ptr" %}
6124 opcode(0xC7); /* C7 /0 */
6125 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6126 ins_pipe(ialu_mem_imm);
6127 %}
6128
6129 // Store Compressed Pointer
6130 instruct storeN(memory mem, rRegN src)
6131 %{
6132 match(Set mem (StoreN mem src));
6133
6134 ins_cost(125); // XXX
6135 format %{ "movl $mem, $src\t# compressed ptr" %}
6136 ins_encode %{
6137 __ movl($mem$$Address, $src$$Register);
6138 %}
6139 ins_pipe(ialu_mem_reg);
6140 %}
6141
6142 instruct storeNKlass(memory mem, rRegN src)
6143 %{
6144 match(Set mem (StoreNKlass mem src));
6145
6146 ins_cost(125); // XXX
6147 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6148 ins_encode %{
6149 __ movl($mem$$Address, $src$$Register);
6150 %}
6151 ins_pipe(ialu_mem_reg);
6152 %}
6153
6154 instruct storeImmN0(memory mem, immN0 zero)
6155 %{
6156 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6157 match(Set mem (StoreN mem zero));
6158
6159 ins_cost(125); // XXX
6160 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6161 ins_encode %{
6162 __ movl($mem$$Address, r12);
6163 %}
6164 ins_pipe(ialu_mem_reg);
6165 %}
6166
6167 instruct storeImmN(memory mem, immN src)
6168 %{
6169 match(Set mem (StoreN mem src));
6170
6171 ins_cost(150); // XXX
6172 format %{ "movl $mem, $src\t# compressed ptr" %}
6173 ins_encode %{
6174 address con = (address)$src$$constant;
6175 if (con == NULL) {
6176 __ movl($mem$$Address, (int32_t)0);
6177 } else {
6178 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6179 }
6180 %}
6181 ins_pipe(ialu_mem_imm);
6182 %}
6183
6184 instruct storeImmNKlass(memory mem, immNKlass src)
6185 %{
6186 match(Set mem (StoreNKlass mem src));
6187
6188 ins_cost(150); // XXX
6189 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6190 ins_encode %{
6191 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6192 %}
6193 ins_pipe(ialu_mem_imm);
6194 %}
6195
6196 // Store Integer Immediate
6197 instruct storeImmI0(memory mem, immI0 zero)
6198 %{
6199 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6200 match(Set mem (StoreI mem zero));
6201
6202 ins_cost(125); // XXX
6203 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6204 ins_encode %{
6205 __ movl($mem$$Address, r12);
6206 %}
6207 ins_pipe(ialu_mem_reg);
6208 %}
6209
6210 instruct storeImmI(memory mem, immI src)
6211 %{
6212 match(Set mem (StoreI mem src));
6213
6214 ins_cost(150);
6215 format %{ "movl $mem, $src\t# int" %}
6216 opcode(0xC7); /* C7 /0 */
6217 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6218 ins_pipe(ialu_mem_imm);
6219 %}
6220
6221 // Store Long Immediate
6222 instruct storeImmL0(memory mem, immL0 zero)
6223 %{
6224 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6225 match(Set mem (StoreL mem zero));
6226
6227 ins_cost(125); // XXX
6228 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6229 ins_encode %{
6230 __ movq($mem$$Address, r12);
6231 %}
6232 ins_pipe(ialu_mem_reg);
6233 %}
6234
6235 instruct storeImmL(memory mem, immL32 src)
6236 %{
6237 match(Set mem (StoreL mem src));
6238
6239 ins_cost(150);
6240 format %{ "movq $mem, $src\t# long" %}
6241 opcode(0xC7); /* C7 /0 */
6242 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6243 ins_pipe(ialu_mem_imm);
6244 %}
6245
6246 // Store Short/Char Immediate
6247 instruct storeImmC0(memory mem, immI0 zero)
6248 %{
6249 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6250 match(Set mem (StoreC mem zero));
6251
6252 ins_cost(125); // XXX
6253 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6254 ins_encode %{
6255 __ movw($mem$$Address, r12);
6256 %}
6257 ins_pipe(ialu_mem_reg);
6258 %}
6259
6260 instruct storeImmI16(memory mem, immI16 src)
6261 %{
6262 predicate(UseStoreImmI16);
6263 match(Set mem (StoreC mem src));
6264
6265 ins_cost(150);
6266 format %{ "movw $mem, $src\t# short/char" %}
6267 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6268 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6269 ins_pipe(ialu_mem_imm);
6270 %}
6271
6272 // Store Byte Immediate
6273 instruct storeImmB0(memory mem, immI0 zero)
6274 %{
6275 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6276 match(Set mem (StoreB mem zero));
6277
6278 ins_cost(125); // XXX
6279 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6280 ins_encode %{
6281 __ movb($mem$$Address, r12);
6282 %}
6283 ins_pipe(ialu_mem_reg);
6284 %}
6285
6286 instruct storeImmB(memory mem, immI8 src)
6287 %{
6288 match(Set mem (StoreB mem src));
6289
6290 ins_cost(150); // XXX
6291 format %{ "movb $mem, $src\t# byte" %}
6292 opcode(0xC6); /* C6 /0 */
6293 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6294 ins_pipe(ialu_mem_imm);
6295 %}
6296
6297 // Store CMS card-mark Immediate
6298 instruct storeImmCM0_reg(memory mem, immI0 zero)
6299 %{
6300 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6301 match(Set mem (StoreCM mem zero));
6302
6303 ins_cost(125); // XXX
6304 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6305 ins_encode %{
6306 __ movb($mem$$Address, r12);
6307 %}
6308 ins_pipe(ialu_mem_reg);
6309 %}
6310
6311 instruct storeImmCM0(memory mem, immI0 src)
6312 %{
6313 match(Set mem (StoreCM mem src));
6314
6315 ins_cost(150); // XXX
6316 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6317 opcode(0xC6); /* C6 /0 */
6318 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6319 ins_pipe(ialu_mem_imm);
6320 %}
6321
6322 // Store Float
6323 instruct storeF(memory mem, regF src)
6324 %{
6325 match(Set mem (StoreF mem src));
6326
6327 ins_cost(95); // XXX
6328 format %{ "movss $mem, $src\t# float" %}
6329 ins_encode %{
6330 __ movflt($mem$$Address, $src$$XMMRegister);
6331 %}
6332 ins_pipe(pipe_slow); // XXX
6333 %}
6334
6335 // Store immediate Float value (it is faster than store from XMM register)
6336 instruct storeF0(memory mem, immF0 zero)
6337 %{
6338 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6339 match(Set mem (StoreF mem zero));
6340
6341 ins_cost(25); // XXX
6342 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6343 ins_encode %{
6344 __ movl($mem$$Address, r12);
6345 %}
6346 ins_pipe(ialu_mem_reg);
6347 %}
6348
6349 instruct storeF_imm(memory mem, immF src)
6350 %{
6351 match(Set mem (StoreF mem src));
6352
6353 ins_cost(50);
6354 format %{ "movl $mem, $src\t# float" %}
6355 opcode(0xC7); /* C7 /0 */
6356 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6357 ins_pipe(ialu_mem_imm);
6358 %}
6359
6360 // Store Double
6361 instruct storeD(memory mem, regD src)
6362 %{
6363 match(Set mem (StoreD mem src));
6364
6365 ins_cost(95); // XXX
6366 format %{ "movsd $mem, $src\t# double" %}
6367 ins_encode %{
6368 __ movdbl($mem$$Address, $src$$XMMRegister);
6369 %}
6370 ins_pipe(pipe_slow); // XXX
6371 %}
6372
6373 // Store immediate double 0.0 (it is faster than store from XMM register)
6374 instruct storeD0_imm(memory mem, immD0 src)
6375 %{
6376 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6377 match(Set mem (StoreD mem src));
6378
6379 ins_cost(50);
6380 format %{ "movq $mem, $src\t# double 0." %}
6381 opcode(0xC7); /* C7 /0 */
6382 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6383 ins_pipe(ialu_mem_imm);
6384 %}
6385
6386 instruct storeD0(memory mem, immD0 zero)
6387 %{
6388 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6389 match(Set mem (StoreD mem zero));
6390
6391 ins_cost(25); // XXX
6392 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6393 ins_encode %{
6394 __ movq($mem$$Address, r12);
6395 %}
6396 ins_pipe(ialu_mem_reg);
6397 %}
6398
6399 instruct storeSSI(stackSlotI dst, rRegI src)
6400 %{
6401 match(Set dst src);
6402
6403 ins_cost(100);
6404 format %{ "movl $dst, $src\t# int stk" %}
6405 opcode(0x89);
6406 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6407 ins_pipe( ialu_mem_reg );
6408 %}
6409
6410 instruct storeSSL(stackSlotL dst, rRegL src)
6411 %{
6412 match(Set dst src);
6413
6414 ins_cost(100);
6415 format %{ "movq $dst, $src\t# long stk" %}
6416 opcode(0x89);
6417 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6418 ins_pipe(ialu_mem_reg);
6419 %}
6420
6421 instruct storeSSP(stackSlotP dst, rRegP src)
6422 %{
6423 match(Set dst src);
6424
6425 ins_cost(100);
6426 format %{ "movq $dst, $src\t# ptr stk" %}
6427 opcode(0x89);
6428 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6429 ins_pipe(ialu_mem_reg);
6430 %}
6431
6432 instruct storeSSF(stackSlotF dst, regF src)
6433 %{
6434 match(Set dst src);
6435
6436 ins_cost(95); // XXX
6437 format %{ "movss $dst, $src\t# float stk" %}
6438 ins_encode %{
6439 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6440 %}
6441 ins_pipe(pipe_slow); // XXX
6442 %}
6443
6444 instruct storeSSD(stackSlotD dst, regD src)
6445 %{
6446 match(Set dst src);
6447
6448 ins_cost(95); // XXX
6449 format %{ "movsd $dst, $src\t# double stk" %}
6450 ins_encode %{
6451 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6452 %}
6453 ins_pipe(pipe_slow); // XXX
6454 %}
6455
6456 //----------BSWAP Instructions-------------------------------------------------
6457 instruct bytes_reverse_int(rRegI dst) %{
6458 match(Set dst (ReverseBytesI dst));
6459
6460 format %{ "bswapl $dst" %}
6461 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6462 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6463 ins_pipe( ialu_reg );
6464 %}
6465
6466 instruct bytes_reverse_long(rRegL dst) %{
6467 match(Set dst (ReverseBytesL dst));
6468
6469 format %{ "bswapq $dst" %}
6470 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6471 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6472 ins_pipe( ialu_reg);
6473 %}
6474
6475 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6476 match(Set dst (ReverseBytesUS dst));
6477 effect(KILL cr);
6478
6479 format %{ "bswapl $dst\n\t"
6480 "shrl $dst,16\n\t" %}
6481 ins_encode %{
6482 __ bswapl($dst$$Register);
6483 __ shrl($dst$$Register, 16);
6484 %}
6485 ins_pipe( ialu_reg );
6486 %}
6487
6488 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6489 match(Set dst (ReverseBytesS dst));
6490 effect(KILL cr);
6491
6492 format %{ "bswapl $dst\n\t"
6493 "sar $dst,16\n\t" %}
6494 ins_encode %{
6495 __ bswapl($dst$$Register);
6496 __ sarl($dst$$Register, 16);
6497 %}
6498 ins_pipe( ialu_reg );
6499 %}
6500
6501 //---------- Zeros Count Instructions ------------------------------------------
6502
6503 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6504 predicate(UseCountLeadingZerosInstruction);
6505 match(Set dst (CountLeadingZerosI src));
6506 effect(KILL cr);
6507
6508 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6509 ins_encode %{
6510 __ lzcntl($dst$$Register, $src$$Register);
6511 %}
6512 ins_pipe(ialu_reg);
6513 %}
6514
6515 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6516 predicate(!UseCountLeadingZerosInstruction);
6517 match(Set dst (CountLeadingZerosI src));
6518 effect(KILL cr);
6519
6520 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6521 "jnz skip\n\t"
6522 "movl $dst, -1\n"
6523 "skip:\n\t"
6524 "negl $dst\n\t"
6525 "addl $dst, 31" %}
6526 ins_encode %{
6527 Register Rdst = $dst$$Register;
6528 Register Rsrc = $src$$Register;
6529 Label skip;
6530 __ bsrl(Rdst, Rsrc);
6531 __ jccb(Assembler::notZero, skip);
6532 __ movl(Rdst, -1);
6533 __ bind(skip);
6534 __ negl(Rdst);
6535 __ addl(Rdst, BitsPerInt - 1);
6536 %}
6537 ins_pipe(ialu_reg);
6538 %}
6539
6540 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6541 predicate(UseCountLeadingZerosInstruction);
6542 match(Set dst (CountLeadingZerosL src));
6543 effect(KILL cr);
6544
6545 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6546 ins_encode %{
6547 __ lzcntq($dst$$Register, $src$$Register);
6548 %}
6549 ins_pipe(ialu_reg);
6550 %}
6551
6552 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6553 predicate(!UseCountLeadingZerosInstruction);
6554 match(Set dst (CountLeadingZerosL src));
6555 effect(KILL cr);
6556
6557 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6558 "jnz skip\n\t"
6559 "movl $dst, -1\n"
6560 "skip:\n\t"
6561 "negl $dst\n\t"
6562 "addl $dst, 63" %}
6563 ins_encode %{
6564 Register Rdst = $dst$$Register;
6565 Register Rsrc = $src$$Register;
6566 Label skip;
6567 __ bsrq(Rdst, Rsrc);
6568 __ jccb(Assembler::notZero, skip);
6569 __ movl(Rdst, -1);
6570 __ bind(skip);
6571 __ negl(Rdst);
6572 __ addl(Rdst, BitsPerLong - 1);
6573 %}
6574 ins_pipe(ialu_reg);
6575 %}
6576
6577 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6578 predicate(UseCountTrailingZerosInstruction);
6579 match(Set dst (CountTrailingZerosI src));
6580 effect(KILL cr);
6581
6582 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6583 ins_encode %{
6584 __ tzcntl($dst$$Register, $src$$Register);
6585 %}
6586 ins_pipe(ialu_reg);
6587 %}
6588
6589 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6590 predicate(!UseCountTrailingZerosInstruction);
6591 match(Set dst (CountTrailingZerosI src));
6592 effect(KILL cr);
6593
6594 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6595 "jnz done\n\t"
6596 "movl $dst, 32\n"
6597 "done:" %}
6598 ins_encode %{
6599 Register Rdst = $dst$$Register;
6600 Label done;
6601 __ bsfl(Rdst, $src$$Register);
6602 __ jccb(Assembler::notZero, done);
6603 __ movl(Rdst, BitsPerInt);
6604 __ bind(done);
6605 %}
6606 ins_pipe(ialu_reg);
6607 %}
6608
6609 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6610 predicate(UseCountTrailingZerosInstruction);
6611 match(Set dst (CountTrailingZerosL src));
6612 effect(KILL cr);
6613
6614 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6615 ins_encode %{
6616 __ tzcntq($dst$$Register, $src$$Register);
6617 %}
6618 ins_pipe(ialu_reg);
6619 %}
6620
6621 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6622 predicate(!UseCountTrailingZerosInstruction);
6623 match(Set dst (CountTrailingZerosL src));
6624 effect(KILL cr);
6625
6626 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6627 "jnz done\n\t"
6628 "movl $dst, 64\n"
6629 "done:" %}
6630 ins_encode %{
6631 Register Rdst = $dst$$Register;
6632 Label done;
6633 __ bsfq(Rdst, $src$$Register);
6634 __ jccb(Assembler::notZero, done);
6635 __ movl(Rdst, BitsPerLong);
6636 __ bind(done);
6637 %}
6638 ins_pipe(ialu_reg);
6639 %}
6640
6641
6642 //---------- Population Count Instructions -------------------------------------
6643
6644 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6645 predicate(UsePopCountInstruction);
6646 match(Set dst (PopCountI src));
6647 effect(KILL cr);
6648
6649 format %{ "popcnt $dst, $src" %}
6650 ins_encode %{
6651 __ popcntl($dst$$Register, $src$$Register);
6652 %}
6653 ins_pipe(ialu_reg);
6654 %}
6655
6656 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6657 predicate(UsePopCountInstruction);
6658 match(Set dst (PopCountI (LoadI mem)));
6659 effect(KILL cr);
6660
6661 format %{ "popcnt $dst, $mem" %}
6662 ins_encode %{
6663 __ popcntl($dst$$Register, $mem$$Address);
6664 %}
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 // Note: Long.bitCount(long) returns an int.
6669 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6670 predicate(UsePopCountInstruction);
6671 match(Set dst (PopCountL src));
6672 effect(KILL cr);
6673
6674 format %{ "popcnt $dst, $src" %}
6675 ins_encode %{
6676 __ popcntq($dst$$Register, $src$$Register);
6677 %}
6678 ins_pipe(ialu_reg);
6679 %}
6680
6681 // Note: Long.bitCount(long) returns an int.
6682 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6683 predicate(UsePopCountInstruction);
6684 match(Set dst (PopCountL (LoadL mem)));
6685 effect(KILL cr);
6686
6687 format %{ "popcnt $dst, $mem" %}
6688 ins_encode %{
6689 __ popcntq($dst$$Register, $mem$$Address);
6690 %}
6691 ins_pipe(ialu_reg);
6692 %}
6693
6694
6695 //----------MemBar Instructions-----------------------------------------------
6696 // Memory barrier flavors
6697
6698 instruct membar_acquire()
6699 %{
6700 match(MemBarAcquire);
6701 match(LoadFence);
6702 ins_cost(0);
6703
6704 size(0);
6705 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6706 ins_encode();
6707 ins_pipe(empty);
6708 %}
6709
6710 instruct membar_acquire_lock()
6711 %{
6712 match(MemBarAcquireLock);
6713 ins_cost(0);
6714
6715 size(0);
6716 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6717 ins_encode();
6718 ins_pipe(empty);
6719 %}
6720
6721 instruct membar_release()
6722 %{
6723 match(MemBarRelease);
6724 match(StoreFence);
6725 ins_cost(0);
6726
6727 size(0);
6728 format %{ "MEMBAR-release ! (empty encoding)" %}
6729 ins_encode();
6730 ins_pipe(empty);
6731 %}
6732
6733 instruct membar_release_lock()
6734 %{
6735 match(MemBarReleaseLock);
6736 ins_cost(0);
6737
6738 size(0);
6739 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6740 ins_encode();
6741 ins_pipe(empty);
6742 %}
6743
6744 instruct membar_volatile(rFlagsReg cr) %{
6745 match(MemBarVolatile);
6746 effect(KILL cr);
6747 ins_cost(400);
6748
6749 format %{
6750 $$template
6751 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6752 %}
6753 ins_encode %{
6754 __ membar(Assembler::StoreLoad);
6755 %}
6756 ins_pipe(pipe_slow);
6757 %}
6758
6759 instruct unnecessary_membar_volatile()
6760 %{
6761 match(MemBarVolatile);
6762 predicate(Matcher::post_store_load_barrier(n));
6763 ins_cost(0);
6764
6765 size(0);
6766 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6767 ins_encode();
6768 ins_pipe(empty);
6769 %}
6770
6771 instruct membar_storestore() %{
6772 match(MemBarStoreStore);
6773 ins_cost(0);
6774
6775 size(0);
6776 format %{ "MEMBAR-storestore (empty encoding)" %}
6777 ins_encode( );
6778 ins_pipe(empty);
6779 %}
6780
6781 //----------Move Instructions--------------------------------------------------
6782
6783 instruct castX2P(rRegP dst, rRegL src)
6784 %{
6785 match(Set dst (CastX2P src));
6786
6787 format %{ "movq $dst, $src\t# long->ptr" %}
6788 ins_encode %{
6789 if ($dst$$reg != $src$$reg) {
6790 __ movptr($dst$$Register, $src$$Register);
6791 }
6792 %}
6793 ins_pipe(ialu_reg_reg); // XXX
6794 %}
6795
6796 instruct castP2X(rRegL dst, rRegP src)
6797 %{
6798 match(Set dst (CastP2X src));
6799
6800 format %{ "movq $dst, $src\t# ptr -> long" %}
6801 ins_encode %{
6802 if ($dst$$reg != $src$$reg) {
6803 __ movptr($dst$$Register, $src$$Register);
6804 }
6805 %}
6806 ins_pipe(ialu_reg_reg); // XXX
6807 %}
6808
6809 // Convert oop into int for vectors alignment masking
6810 instruct convP2I(rRegI dst, rRegP src)
6811 %{
6812 match(Set dst (ConvL2I (CastP2X src)));
6813
6814 format %{ "movl $dst, $src\t# ptr -> int" %}
6815 ins_encode %{
6816 __ movl($dst$$Register, $src$$Register);
6817 %}
6818 ins_pipe(ialu_reg_reg); // XXX
6819 %}
6820
6821 // Convert compressed oop into int for vectors alignment masking
6822 // in case of 32bit oops (heap < 4Gb).
6823 instruct convN2I(rRegI dst, rRegN src)
6824 %{
6825 predicate(Universe::narrow_oop_shift() == 0);
6826 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6827
6828 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6829 ins_encode %{
6830 __ movl($dst$$Register, $src$$Register);
6831 %}
6832 ins_pipe(ialu_reg_reg); // XXX
6833 %}
6834
6835 // Convert oop pointer into compressed form
6836 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6837 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6838 match(Set dst (EncodeP src));
6839 effect(KILL cr);
6840 format %{ "encode_heap_oop $dst,$src" %}
6841 ins_encode %{
6842 Register s = $src$$Register;
6843 Register d = $dst$$Register;
6844 if (s != d) {
6845 __ movq(d, s);
6846 }
6847 __ encode_heap_oop(d);
6848 %}
6849 ins_pipe(ialu_reg_long);
6850 %}
6851
6852 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6853 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6854 match(Set dst (EncodeP src));
6855 effect(KILL cr);
6856 format %{ "encode_heap_oop_not_null $dst,$src" %}
6857 ins_encode %{
6858 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6859 %}
6860 ins_pipe(ialu_reg_long);
6861 %}
6862
6863 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6864 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6865 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6866 match(Set dst (DecodeN src));
6867 effect(KILL cr);
6868 format %{ "decode_heap_oop $dst,$src" %}
6869 ins_encode %{
6870 Register s = $src$$Register;
6871 Register d = $dst$$Register;
6872 if (s != d) {
6873 __ movq(d, s);
6874 }
6875 __ decode_heap_oop(d);
6876 %}
6877 ins_pipe(ialu_reg_long);
6878 %}
6879
6880 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6881 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6882 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6883 match(Set dst (DecodeN src));
6884 effect(KILL cr);
6885 format %{ "decode_heap_oop_not_null $dst,$src" %}
6886 ins_encode %{
6887 Register s = $src$$Register;
6888 Register d = $dst$$Register;
6889 if (s != d) {
6890 __ decode_heap_oop_not_null(d, s);
6891 } else {
6892 __ decode_heap_oop_not_null(d);
6893 }
6894 %}
6895 ins_pipe(ialu_reg_long);
6896 %}
6897
6898 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6899 match(Set dst (EncodePKlass src));
6900 effect(KILL cr);
6901 format %{ "encode_klass_not_null $dst,$src" %}
6902 ins_encode %{
6903 __ encode_klass_not_null($dst$$Register, $src$$Register);
6904 %}
6905 ins_pipe(ialu_reg_long);
6906 %}
6907
6908 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6909 match(Set dst (DecodeNKlass src));
6910 effect(KILL cr);
6911 format %{ "decode_klass_not_null $dst,$src" %}
6912 ins_encode %{
6913 Register s = $src$$Register;
6914 Register d = $dst$$Register;
6915 if (s != d) {
6916 __ decode_klass_not_null(d, s);
6917 } else {
6918 __ decode_klass_not_null(d);
6919 }
6920 %}
6921 ins_pipe(ialu_reg_long);
6922 %}
6923
6924
6925 //----------Conditional Move---------------------------------------------------
6926 // Jump
6927 // dummy instruction for generating temp registers
6928 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6929 match(Jump (LShiftL switch_val shift));
6930 ins_cost(350);
6931 predicate(false);
6932 effect(TEMP dest);
6933
6934 format %{ "leaq $dest, [$constantaddress]\n\t"
6935 "jmp [$dest + $switch_val << $shift]\n\t" %}
6936 ins_encode %{
6937 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6938 // to do that and the compiler is using that register as one it can allocate.
6939 // So we build it all by hand.
6940 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6941 // ArrayAddress dispatch(table, index);
6942 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6943 __ lea($dest$$Register, $constantaddress);
6944 __ jmp(dispatch);
6945 %}
6946 ins_pipe(pipe_jmp);
6947 %}
6948
6949 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6950 match(Jump (AddL (LShiftL switch_val shift) offset));
6951 ins_cost(350);
6952 effect(TEMP dest);
6953
6954 format %{ "leaq $dest, [$constantaddress]\n\t"
6955 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6956 ins_encode %{
6957 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6958 // to do that and the compiler is using that register as one it can allocate.
6959 // So we build it all by hand.
6960 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6961 // ArrayAddress dispatch(table, index);
6962 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6963 __ lea($dest$$Register, $constantaddress);
6964 __ jmp(dispatch);
6965 %}
6966 ins_pipe(pipe_jmp);
6967 %}
6968
6969 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6970 match(Jump switch_val);
6971 ins_cost(350);
6972 effect(TEMP dest);
6973
6974 format %{ "leaq $dest, [$constantaddress]\n\t"
6975 "jmp [$dest + $switch_val]\n\t" %}
6976 ins_encode %{
6977 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6978 // to do that and the compiler is using that register as one it can allocate.
6979 // So we build it all by hand.
6980 // Address index(noreg, switch_reg, Address::times_1);
6981 // ArrayAddress dispatch(table, index);
6982 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6983 __ lea($dest$$Register, $constantaddress);
6984 __ jmp(dispatch);
6985 %}
6986 ins_pipe(pipe_jmp);
6987 %}
6988
6989 // Conditional move
6990 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6991 %{
6992 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6993
6994 ins_cost(200); // XXX
6995 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6996 opcode(0x0F, 0x40);
6997 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6998 ins_pipe(pipe_cmov_reg);
6999 %}
7000
7001 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7002 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7003
7004 ins_cost(200); // XXX
7005 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7006 opcode(0x0F, 0x40);
7007 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7008 ins_pipe(pipe_cmov_reg);
7009 %}
7010
7011 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7012 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7013 ins_cost(200);
7014 expand %{
7015 cmovI_regU(cop, cr, dst, src);
7016 %}
7017 %}
7018
7019 // Conditional move
7020 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7021 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7022
7023 ins_cost(250); // XXX
7024 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7025 opcode(0x0F, 0x40);
7026 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7027 ins_pipe(pipe_cmov_mem);
7028 %}
7029
7030 // Conditional move
7031 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7032 %{
7033 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7034
7035 ins_cost(250); // XXX
7036 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7037 opcode(0x0F, 0x40);
7038 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7039 ins_pipe(pipe_cmov_mem);
7040 %}
7041
7042 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7043 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7044 ins_cost(250);
7045 expand %{
7046 cmovI_memU(cop, cr, dst, src);
7047 %}
7048 %}
7049
7050 // Conditional move
7051 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7052 %{
7053 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7054
7055 ins_cost(200); // XXX
7056 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7057 opcode(0x0F, 0x40);
7058 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7059 ins_pipe(pipe_cmov_reg);
7060 %}
7061
7062 // Conditional move
7063 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7064 %{
7065 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7066
7067 ins_cost(200); // XXX
7068 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7069 opcode(0x0F, 0x40);
7070 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7071 ins_pipe(pipe_cmov_reg);
7072 %}
7073
7074 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7075 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7076 ins_cost(200);
7077 expand %{
7078 cmovN_regU(cop, cr, dst, src);
7079 %}
7080 %}
7081
7082 // Conditional move
7083 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7084 %{
7085 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7086
7087 ins_cost(200); // XXX
7088 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7089 opcode(0x0F, 0x40);
7090 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7091 ins_pipe(pipe_cmov_reg); // XXX
7092 %}
7093
7094 // Conditional move
7095 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7096 %{
7097 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7098
7099 ins_cost(200); // XXX
7100 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7101 opcode(0x0F, 0x40);
7102 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7103 ins_pipe(pipe_cmov_reg); // XXX
7104 %}
7105
7106 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7107 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7108 ins_cost(200);
7109 expand %{
7110 cmovP_regU(cop, cr, dst, src);
7111 %}
7112 %}
7113
7114 // DISABLED: Requires the ADLC to emit a bottom_type call that
7115 // correctly meets the two pointer arguments; one is an incoming
7116 // register but the other is a memory operand. ALSO appears to
7117 // be buggy with implicit null checks.
7118 //
7119 //// Conditional move
7120 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7121 //%{
7122 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7123 // ins_cost(250);
7124 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7125 // opcode(0x0F,0x40);
7126 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7127 // ins_pipe( pipe_cmov_mem );
7128 //%}
7129 //
7130 //// Conditional move
7131 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7132 //%{
7133 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7134 // ins_cost(250);
7135 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7136 // opcode(0x0F,0x40);
7137 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7138 // ins_pipe( pipe_cmov_mem );
7139 //%}
7140
7141 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7142 %{
7143 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7144
7145 ins_cost(200); // XXX
7146 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7147 opcode(0x0F, 0x40);
7148 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7149 ins_pipe(pipe_cmov_reg); // XXX
7150 %}
7151
7152 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7153 %{
7154 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7155
7156 ins_cost(200); // XXX
7157 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7158 opcode(0x0F, 0x40);
7159 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7160 ins_pipe(pipe_cmov_mem); // XXX
7161 %}
7162
7163 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7164 %{
7165 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7166
7167 ins_cost(200); // XXX
7168 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7169 opcode(0x0F, 0x40);
7170 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7171 ins_pipe(pipe_cmov_reg); // XXX
7172 %}
7173
7174 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7175 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7176 ins_cost(200);
7177 expand %{
7178 cmovL_regU(cop, cr, dst, src);
7179 %}
7180 %}
7181
7182 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7183 %{
7184 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7185
7186 ins_cost(200); // XXX
7187 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7188 opcode(0x0F, 0x40);
7189 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7190 ins_pipe(pipe_cmov_mem); // XXX
7191 %}
7192
7193 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7194 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7195 ins_cost(200);
7196 expand %{
7197 cmovL_memU(cop, cr, dst, src);
7198 %}
7199 %}
7200
7201 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7202 %{
7203 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7204
7205 ins_cost(200); // XXX
7206 format %{ "jn$cop skip\t# signed cmove float\n\t"
7207 "movss $dst, $src\n"
7208 "skip:" %}
7209 ins_encode %{
7210 Label Lskip;
7211 // Invert sense of branch from sense of CMOV
7212 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7213 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7214 __ bind(Lskip);
7215 %}
7216 ins_pipe(pipe_slow);
7217 %}
7218
7219 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7220 // %{
7221 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7222
7223 // ins_cost(200); // XXX
7224 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7225 // "movss $dst, $src\n"
7226 // "skip:" %}
7227 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7228 // ins_pipe(pipe_slow);
7229 // %}
7230
7231 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7232 %{
7233 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7234
7235 ins_cost(200); // XXX
7236 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7237 "movss $dst, $src\n"
7238 "skip:" %}
7239 ins_encode %{
7240 Label Lskip;
7241 // Invert sense of branch from sense of CMOV
7242 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7243 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7244 __ bind(Lskip);
7245 %}
7246 ins_pipe(pipe_slow);
7247 %}
7248
7249 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7250 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7251 ins_cost(200);
7252 expand %{
7253 cmovF_regU(cop, cr, dst, src);
7254 %}
7255 %}
7256
7257 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7258 %{
7259 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7260
7261 ins_cost(200); // XXX
7262 format %{ "jn$cop skip\t# signed cmove double\n\t"
7263 "movsd $dst, $src\n"
7264 "skip:" %}
7265 ins_encode %{
7266 Label Lskip;
7267 // Invert sense of branch from sense of CMOV
7268 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7269 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7270 __ bind(Lskip);
7271 %}
7272 ins_pipe(pipe_slow);
7273 %}
7274
7275 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7276 %{
7277 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7278
7279 ins_cost(200); // XXX
7280 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7281 "movsd $dst, $src\n"
7282 "skip:" %}
7283 ins_encode %{
7284 Label Lskip;
7285 // Invert sense of branch from sense of CMOV
7286 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7287 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7288 __ bind(Lskip);
7289 %}
7290 ins_pipe(pipe_slow);
7291 %}
7292
7293 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7294 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7295 ins_cost(200);
7296 expand %{
7297 cmovD_regU(cop, cr, dst, src);
7298 %}
7299 %}
7300
7301 //----------Arithmetic Instructions--------------------------------------------
7302 //----------Addition Instructions----------------------------------------------
7303
7304 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7305 %{
7306 match(Set dst (AddI dst src));
7307 effect(KILL cr);
7308
7309 format %{ "addl $dst, $src\t# int" %}
7310 opcode(0x03);
7311 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7312 ins_pipe(ialu_reg_reg);
7313 %}
7314
7315 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7316 %{
7317 match(Set dst (AddI dst src));
7318 effect(KILL cr);
7319
7320 format %{ "addl $dst, $src\t# int" %}
7321 opcode(0x81, 0x00); /* /0 id */
7322 ins_encode(OpcSErm(dst, src), Con8or32(src));
7323 ins_pipe( ialu_reg );
7324 %}
7325
7326 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7327 %{
7328 match(Set dst (AddI dst (LoadI src)));
7329 effect(KILL cr);
7330
7331 ins_cost(125); // XXX
7332 format %{ "addl $dst, $src\t# int" %}
7333 opcode(0x03);
7334 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7335 ins_pipe(ialu_reg_mem);
7336 %}
7337
7338 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7339 %{
7340 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7341 effect(KILL cr);
7342
7343 ins_cost(150); // XXX
7344 format %{ "addl $dst, $src\t# int" %}
7345 opcode(0x01); /* Opcode 01 /r */
7346 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7347 ins_pipe(ialu_mem_reg);
7348 %}
7349
7350 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7351 %{
7352 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7353 effect(KILL cr);
7354
7355 ins_cost(125); // XXX
7356 format %{ "addl $dst, $src\t# int" %}
7357 opcode(0x81); /* Opcode 81 /0 id */
7358 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7359 ins_pipe(ialu_mem_imm);
7360 %}
7361
7362 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7363 %{
7364 predicate(UseIncDec);
7365 match(Set dst (AddI dst src));
7366 effect(KILL cr);
7367
7368 format %{ "incl $dst\t# int" %}
7369 opcode(0xFF, 0x00); // FF /0
7370 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7371 ins_pipe(ialu_reg);
7372 %}
7373
7374 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7375 %{
7376 predicate(UseIncDec);
7377 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7378 effect(KILL cr);
7379
7380 ins_cost(125); // XXX
7381 format %{ "incl $dst\t# int" %}
7382 opcode(0xFF); /* Opcode FF /0 */
7383 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7384 ins_pipe(ialu_mem_imm);
7385 %}
7386
7387 // XXX why does that use AddI
7388 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7389 %{
7390 predicate(UseIncDec);
7391 match(Set dst (AddI dst src));
7392 effect(KILL cr);
7393
7394 format %{ "decl $dst\t# int" %}
7395 opcode(0xFF, 0x01); // FF /1
7396 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7397 ins_pipe(ialu_reg);
7398 %}
7399
7400 // XXX why does that use AddI
7401 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7402 %{
7403 predicate(UseIncDec);
7404 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7405 effect(KILL cr);
7406
7407 ins_cost(125); // XXX
7408 format %{ "decl $dst\t# int" %}
7409 opcode(0xFF); /* Opcode FF /1 */
7410 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7411 ins_pipe(ialu_mem_imm);
7412 %}
7413
7414 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7415 %{
7416 match(Set dst (AddI src0 src1));
7417
7418 ins_cost(110);
7419 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7420 opcode(0x8D); /* 0x8D /r */
7421 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7422 ins_pipe(ialu_reg_reg);
7423 %}
7424
7425 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7426 %{
7427 match(Set dst (AddL dst src));
7428 effect(KILL cr);
7429
7430 format %{ "addq $dst, $src\t# long" %}
7431 opcode(0x03);
7432 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7433 ins_pipe(ialu_reg_reg);
7434 %}
7435
7436 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7437 %{
7438 match(Set dst (AddL dst src));
7439 effect(KILL cr);
7440
7441 format %{ "addq $dst, $src\t# long" %}
7442 opcode(0x81, 0x00); /* /0 id */
7443 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7444 ins_pipe( ialu_reg );
7445 %}
7446
7447 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7448 %{
7449 match(Set dst (AddL dst (LoadL src)));
7450 effect(KILL cr);
7451
7452 ins_cost(125); // XXX
7453 format %{ "addq $dst, $src\t# long" %}
7454 opcode(0x03);
7455 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7456 ins_pipe(ialu_reg_mem);
7457 %}
7458
7459 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7460 %{
7461 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7462 effect(KILL cr);
7463
7464 ins_cost(150); // XXX
7465 format %{ "addq $dst, $src\t# long" %}
7466 opcode(0x01); /* Opcode 01 /r */
7467 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7468 ins_pipe(ialu_mem_reg);
7469 %}
7470
7471 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7472 %{
7473 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7474 effect(KILL cr);
7475
7476 ins_cost(125); // XXX
7477 format %{ "addq $dst, $src\t# long" %}
7478 opcode(0x81); /* Opcode 81 /0 id */
7479 ins_encode(REX_mem_wide(dst),
7480 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7481 ins_pipe(ialu_mem_imm);
7482 %}
7483
7484 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7485 %{
7486 predicate(UseIncDec);
7487 match(Set dst (AddL dst src));
7488 effect(KILL cr);
7489
7490 format %{ "incq $dst\t# long" %}
7491 opcode(0xFF, 0x00); // FF /0
7492 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7493 ins_pipe(ialu_reg);
7494 %}
7495
7496 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7497 %{
7498 predicate(UseIncDec);
7499 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7500 effect(KILL cr);
7501
7502 ins_cost(125); // XXX
7503 format %{ "incq $dst\t# long" %}
7504 opcode(0xFF); /* Opcode FF /0 */
7505 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7506 ins_pipe(ialu_mem_imm);
7507 %}
7508
7509 // XXX why does that use AddL
7510 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7511 %{
7512 predicate(UseIncDec);
7513 match(Set dst (AddL dst src));
7514 effect(KILL cr);
7515
7516 format %{ "decq $dst\t# long" %}
7517 opcode(0xFF, 0x01); // FF /1
7518 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7519 ins_pipe(ialu_reg);
7520 %}
7521
7522 // XXX why does that use AddL
7523 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7524 %{
7525 predicate(UseIncDec);
7526 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7527 effect(KILL cr);
7528
7529 ins_cost(125); // XXX
7530 format %{ "decq $dst\t# long" %}
7531 opcode(0xFF); /* Opcode FF /1 */
7532 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7533 ins_pipe(ialu_mem_imm);
7534 %}
7535
7536 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7537 %{
7538 match(Set dst (AddL src0 src1));
7539
7540 ins_cost(110);
7541 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7542 opcode(0x8D); /* 0x8D /r */
7543 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7544 ins_pipe(ialu_reg_reg);
7545 %}
7546
7547 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7548 %{
7549 match(Set dst (AddP dst src));
7550 effect(KILL cr);
7551
7552 format %{ "addq $dst, $src\t# ptr" %}
7553 opcode(0x03);
7554 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7555 ins_pipe(ialu_reg_reg);
7556 %}
7557
7558 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7559 %{
7560 match(Set dst (AddP dst src));
7561 effect(KILL cr);
7562
7563 format %{ "addq $dst, $src\t# ptr" %}
7564 opcode(0x81, 0x00); /* /0 id */
7565 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7566 ins_pipe( ialu_reg );
7567 %}
7568
7569 // XXX addP mem ops ????
7570
7571 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7572 %{
7573 match(Set dst (AddP src0 src1));
7574
7575 ins_cost(110);
7576 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7577 opcode(0x8D); /* 0x8D /r */
7578 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7579 ins_pipe(ialu_reg_reg);
7580 %}
7581
7582 instruct checkCastPP(rRegP dst)
7583 %{
7584 match(Set dst (CheckCastPP dst));
7585
7586 size(0);
7587 format %{ "# checkcastPP of $dst" %}
7588 ins_encode(/* empty encoding */);
7589 ins_pipe(empty);
7590 %}
7591
7592 instruct castPP(rRegP dst)
7593 %{
7594 match(Set dst (CastPP dst));
7595
7596 size(0);
7597 format %{ "# castPP of $dst" %}
7598 ins_encode(/* empty encoding */);
7599 ins_pipe(empty);
7600 %}
7601
7602 instruct castII(rRegI dst)
7603 %{
7604 match(Set dst (CastII dst));
7605
7606 size(0);
7607 format %{ "# castII of $dst" %}
7608 ins_encode(/* empty encoding */);
7609 ins_cost(0);
7610 ins_pipe(empty);
7611 %}
7612
7613 // LoadP-locked same as a regular LoadP when used with compare-swap
7614 instruct loadPLocked(rRegP dst, memory mem)
7615 %{
7616 match(Set dst (LoadPLocked mem));
7617
7618 ins_cost(125); // XXX
7619 format %{ "movq $dst, $mem\t# ptr locked" %}
7620 opcode(0x8B);
7621 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7622 ins_pipe(ialu_reg_mem); // XXX
7623 %}
7624
7625 // Conditional-store of the updated heap-top.
7626 // Used during allocation of the shared heap.
7627 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7628
7629 instruct storePConditional(memory heap_top_ptr,
7630 rax_RegP oldval, rRegP newval,
7631 rFlagsReg cr)
7632 %{
7633 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7634
7635 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7636 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7637 opcode(0x0F, 0xB1);
7638 ins_encode(lock_prefix,
7639 REX_reg_mem_wide(newval, heap_top_ptr),
7640 OpcP, OpcS,
7641 reg_mem(newval, heap_top_ptr));
7642 ins_pipe(pipe_cmpxchg);
7643 %}
7644
7645 // Conditional-store of an int value.
7646 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7647 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7648 %{
7649 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7650 effect(KILL oldval);
7651
7652 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7653 opcode(0x0F, 0xB1);
7654 ins_encode(lock_prefix,
7655 REX_reg_mem(newval, mem),
7656 OpcP, OpcS,
7657 reg_mem(newval, mem));
7658 ins_pipe(pipe_cmpxchg);
7659 %}
7660
7661 // Conditional-store of a long value.
7662 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7663 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7664 %{
7665 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7666 effect(KILL oldval);
7667
7668 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7669 opcode(0x0F, 0xB1);
7670 ins_encode(lock_prefix,
7671 REX_reg_mem_wide(newval, mem),
7672 OpcP, OpcS,
7673 reg_mem(newval, mem));
7674 ins_pipe(pipe_cmpxchg);
7675 %}
7676
7677
7678 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7679 instruct compareAndSwapP(rRegI res,
7680 memory mem_ptr,
7681 rax_RegP oldval, rRegP newval,
7682 rFlagsReg cr)
7683 %{
7684 predicate(VM_Version::supports_cx8());
7685 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7686 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7687 effect(KILL cr, KILL oldval);
7688
7689 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7690 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7691 "sete $res\n\t"
7692 "movzbl $res, $res" %}
7693 opcode(0x0F, 0xB1);
7694 ins_encode(lock_prefix,
7695 REX_reg_mem_wide(newval, mem_ptr),
7696 OpcP, OpcS,
7697 reg_mem(newval, mem_ptr),
7698 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7699 REX_reg_breg(res, res), // movzbl
7700 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7701 ins_pipe( pipe_cmpxchg );
7702 %}
7703
7704 instruct compareAndSwapL(rRegI res,
7705 memory mem_ptr,
7706 rax_RegL oldval, rRegL newval,
7707 rFlagsReg cr)
7708 %{
7709 predicate(VM_Version::supports_cx8());
7710 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7711 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7712 effect(KILL cr, KILL oldval);
7713
7714 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7715 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7716 "sete $res\n\t"
7717 "movzbl $res, $res" %}
7718 opcode(0x0F, 0xB1);
7719 ins_encode(lock_prefix,
7720 REX_reg_mem_wide(newval, mem_ptr),
7721 OpcP, OpcS,
7722 reg_mem(newval, mem_ptr),
7723 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7724 REX_reg_breg(res, res), // movzbl
7725 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7726 ins_pipe( pipe_cmpxchg );
7727 %}
7728
7729 instruct compareAndSwapI(rRegI res,
7730 memory mem_ptr,
7731 rax_RegI oldval, rRegI newval,
7732 rFlagsReg cr)
7733 %{
7734 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7735 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7736 effect(KILL cr, KILL oldval);
7737
7738 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7739 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7740 "sete $res\n\t"
7741 "movzbl $res, $res" %}
7742 opcode(0x0F, 0xB1);
7743 ins_encode(lock_prefix,
7744 REX_reg_mem(newval, mem_ptr),
7745 OpcP, OpcS,
7746 reg_mem(newval, mem_ptr),
7747 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7748 REX_reg_breg(res, res), // movzbl
7749 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7750 ins_pipe( pipe_cmpxchg );
7751 %}
7752
7753 instruct compareAndSwapB(rRegI res,
7754 memory mem_ptr,
7755 rax_RegI oldval, rRegI newval,
7756 rFlagsReg cr)
7757 %{
7758 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7759 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7760 effect(KILL cr, KILL oldval);
7761
7762 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7763 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7764 "sete $res\n\t"
7765 "movzbl $res, $res" %}
7766 opcode(0x0F, 0xB0);
7767 ins_encode(lock_prefix,
7768 REX_breg_mem(newval, mem_ptr),
7769 OpcP, OpcS,
7770 reg_mem(newval, mem_ptr),
7771 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7772 REX_reg_breg(res, res), // movzbl
7773 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7774 ins_pipe( pipe_cmpxchg );
7775 %}
7776
7777 instruct compareAndSwapS(rRegI res,
7778 memory mem_ptr,
7779 rax_RegI oldval, rRegI newval,
7780 rFlagsReg cr)
7781 %{
7782 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7783 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7784 effect(KILL cr, KILL oldval);
7785
7786 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7787 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7788 "sete $res\n\t"
7789 "movzbl $res, $res" %}
7790 opcode(0x0F, 0xB1);
7791 ins_encode(lock_prefix,
7792 SizePrefix,
7793 REX_reg_mem(newval, mem_ptr),
7794 OpcP, OpcS,
7795 reg_mem(newval, mem_ptr),
7796 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7797 REX_reg_breg(res, res), // movzbl
7798 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7799 ins_pipe( pipe_cmpxchg );
7800 %}
7801
7802 instruct compareAndSwapN(rRegI res,
7803 memory mem_ptr,
7804 rax_RegN oldval, rRegN newval,
7805 rFlagsReg cr) %{
7806 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7807 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7808 effect(KILL cr, KILL oldval);
7809
7810 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7811 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7812 "sete $res\n\t"
7813 "movzbl $res, $res" %}
7814 opcode(0x0F, 0xB1);
7815 ins_encode(lock_prefix,
7816 REX_reg_mem(newval, mem_ptr),
7817 OpcP, OpcS,
7818 reg_mem(newval, mem_ptr),
7819 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7820 REX_reg_breg(res, res), // movzbl
7821 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7822 ins_pipe( pipe_cmpxchg );
7823 %}
7824
7825 instruct compareAndExchangeB(
7826 memory mem_ptr,
7827 rax_RegI oldval, rRegI newval,
7828 rFlagsReg cr)
7829 %{
7830 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7831 effect(KILL cr);
7832
7833 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7834 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7835 opcode(0x0F, 0xB0);
7836 ins_encode(lock_prefix,
7837 REX_breg_mem(newval, mem_ptr),
7838 OpcP, OpcS,
7839 reg_mem(newval, mem_ptr) // lock cmpxchg
7840 );
7841 ins_pipe( pipe_cmpxchg );
7842 %}
7843
7844 instruct compareAndExchangeS(
7845 memory mem_ptr,
7846 rax_RegI oldval, rRegI newval,
7847 rFlagsReg cr)
7848 %{
7849 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7850 effect(KILL cr);
7851
7852 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7853 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7854 opcode(0x0F, 0xB1);
7855 ins_encode(lock_prefix,
7856 SizePrefix,
7857 REX_reg_mem(newval, mem_ptr),
7858 OpcP, OpcS,
7859 reg_mem(newval, mem_ptr) // lock cmpxchg
7860 );
7861 ins_pipe( pipe_cmpxchg );
7862 %}
7863
7864 instruct compareAndExchangeI(
7865 memory mem_ptr,
7866 rax_RegI oldval, rRegI newval,
7867 rFlagsReg cr)
7868 %{
7869 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7870 effect(KILL cr);
7871
7872 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7873 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7874 opcode(0x0F, 0xB1);
7875 ins_encode(lock_prefix,
7876 REX_reg_mem(newval, mem_ptr),
7877 OpcP, OpcS,
7878 reg_mem(newval, mem_ptr) // lock cmpxchg
7879 );
7880 ins_pipe( pipe_cmpxchg );
7881 %}
7882
7883 instruct compareAndExchangeL(
7884 memory mem_ptr,
7885 rax_RegL oldval, rRegL newval,
7886 rFlagsReg cr)
7887 %{
7888 predicate(VM_Version::supports_cx8());
7889 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7890 effect(KILL cr);
7891
7892 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7893 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7894 opcode(0x0F, 0xB1);
7895 ins_encode(lock_prefix,
7896 REX_reg_mem_wide(newval, mem_ptr),
7897 OpcP, OpcS,
7898 reg_mem(newval, mem_ptr) // lock cmpxchg
7899 );
7900 ins_pipe( pipe_cmpxchg );
7901 %}
7902
7903 instruct compareAndExchangeN(
7904 memory mem_ptr,
7905 rax_RegN oldval, rRegN newval,
7906 rFlagsReg cr) %{
7907 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7908 effect(KILL cr);
7909
7910 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7911 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7912 opcode(0x0F, 0xB1);
7913 ins_encode(lock_prefix,
7914 REX_reg_mem(newval, mem_ptr),
7915 OpcP, OpcS,
7916 reg_mem(newval, mem_ptr) // lock cmpxchg
7917 );
7918 ins_pipe( pipe_cmpxchg );
7919 %}
7920
7921 instruct compareAndExchangeP(
7922 memory mem_ptr,
7923 rax_RegP oldval, rRegP newval,
7924 rFlagsReg cr)
7925 %{
7926 predicate(VM_Version::supports_cx8());
7927 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7928 effect(KILL cr);
7929
7930 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7931 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7932 opcode(0x0F, 0xB1);
7933 ins_encode(lock_prefix,
7934 REX_reg_mem_wide(newval, mem_ptr),
7935 OpcP, OpcS,
7936 reg_mem(newval, mem_ptr) // lock cmpxchg
7937 );
7938 ins_pipe( pipe_cmpxchg );
7939 %}
7940
7941 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7942 predicate(n->as_LoadStore()->result_not_used());
7943 match(Set dummy (GetAndAddB mem add));
7944 effect(KILL cr);
7945 format %{ "ADDB [$mem],$add" %}
7946 ins_encode %{
7947 __ lock();
7948 __ addb($mem$$Address, $add$$constant);
7949 %}
7950 ins_pipe( pipe_cmpxchg );
7951 %}
7952
7953 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7954 match(Set newval (GetAndAddB mem newval));
7955 effect(KILL cr);
7956 format %{ "XADDB [$mem],$newval" %}
7957 ins_encode %{
7958 __ lock();
7959 __ xaddb($mem$$Address, $newval$$Register);
7960 %}
7961 ins_pipe( pipe_cmpxchg );
7962 %}
7963
7964 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7965 predicate(n->as_LoadStore()->result_not_used());
7966 match(Set dummy (GetAndAddS mem add));
7967 effect(KILL cr);
7968 format %{ "ADDW [$mem],$add" %}
7969 ins_encode %{
7970 __ lock();
7971 __ addw($mem$$Address, $add$$constant);
7972 %}
7973 ins_pipe( pipe_cmpxchg );
7974 %}
7975
7976 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7977 match(Set newval (GetAndAddS mem newval));
7978 effect(KILL cr);
7979 format %{ "XADDW [$mem],$newval" %}
7980 ins_encode %{
7981 __ lock();
7982 __ xaddw($mem$$Address, $newval$$Register);
7983 %}
7984 ins_pipe( pipe_cmpxchg );
7985 %}
7986
7987 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7988 predicate(n->as_LoadStore()->result_not_used());
7989 match(Set dummy (GetAndAddI mem add));
7990 effect(KILL cr);
7991 format %{ "ADDL [$mem],$add" %}
7992 ins_encode %{
7993 __ lock();
7994 __ addl($mem$$Address, $add$$constant);
7995 %}
7996 ins_pipe( pipe_cmpxchg );
7997 %}
7998
7999 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8000 match(Set newval (GetAndAddI mem newval));
8001 effect(KILL cr);
8002 format %{ "XADDL [$mem],$newval" %}
8003 ins_encode %{
8004 __ lock();
8005 __ xaddl($mem$$Address, $newval$$Register);
8006 %}
8007 ins_pipe( pipe_cmpxchg );
8008 %}
8009
8010 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8011 predicate(n->as_LoadStore()->result_not_used());
8012 match(Set dummy (GetAndAddL mem add));
8013 effect(KILL cr);
8014 format %{ "ADDQ [$mem],$add" %}
8015 ins_encode %{
8016 __ lock();
8017 __ addq($mem$$Address, $add$$constant);
8018 %}
8019 ins_pipe( pipe_cmpxchg );
8020 %}
8021
8022 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8023 match(Set newval (GetAndAddL mem newval));
8024 effect(KILL cr);
8025 format %{ "XADDQ [$mem],$newval" %}
8026 ins_encode %{
8027 __ lock();
8028 __ xaddq($mem$$Address, $newval$$Register);
8029 %}
8030 ins_pipe( pipe_cmpxchg );
8031 %}
8032
8033 instruct xchgB( memory mem, rRegI newval) %{
8034 match(Set newval (GetAndSetB mem newval));
8035 format %{ "XCHGB $newval,[$mem]" %}
8036 ins_encode %{
8037 __ xchgb($newval$$Register, $mem$$Address);
8038 %}
8039 ins_pipe( pipe_cmpxchg );
8040 %}
8041
8042 instruct xchgS( memory mem, rRegI newval) %{
8043 match(Set newval (GetAndSetS mem newval));
8044 format %{ "XCHGW $newval,[$mem]" %}
8045 ins_encode %{
8046 __ xchgw($newval$$Register, $mem$$Address);
8047 %}
8048 ins_pipe( pipe_cmpxchg );
8049 %}
8050
8051 instruct xchgI( memory mem, rRegI newval) %{
8052 match(Set newval (GetAndSetI mem newval));
8053 format %{ "XCHGL $newval,[$mem]" %}
8054 ins_encode %{
8055 __ xchgl($newval$$Register, $mem$$Address);
8056 %}
8057 ins_pipe( pipe_cmpxchg );
8058 %}
8059
8060 instruct xchgL( memory mem, rRegL newval) %{
8061 match(Set newval (GetAndSetL mem newval));
8062 format %{ "XCHGL $newval,[$mem]" %}
8063 ins_encode %{
8064 __ xchgq($newval$$Register, $mem$$Address);
8065 %}
8066 ins_pipe( pipe_cmpxchg );
8067 %}
8068
8069 instruct xchgP( memory mem, rRegP newval) %{
8070 match(Set newval (GetAndSetP mem newval));
8071 format %{ "XCHGQ $newval,[$mem]" %}
8072 ins_encode %{
8073 __ xchgq($newval$$Register, $mem$$Address);
8074 %}
8075 ins_pipe( pipe_cmpxchg );
8076 %}
8077
8078 instruct xchgN( memory mem, rRegN newval) %{
8079 match(Set newval (GetAndSetN mem newval));
8080 format %{ "XCHGL $newval,$mem]" %}
8081 ins_encode %{
8082 __ xchgl($newval$$Register, $mem$$Address);
8083 %}
8084 ins_pipe( pipe_cmpxchg );
8085 %}
8086
8087 //----------Subtraction Instructions-------------------------------------------
8088
8089 // Integer Subtraction Instructions
8090 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8091 %{
8092 match(Set dst (SubI dst src));
8093 effect(KILL cr);
8094
8095 format %{ "subl $dst, $src\t# int" %}
8096 opcode(0x2B);
8097 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8098 ins_pipe(ialu_reg_reg);
8099 %}
8100
8101 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8102 %{
8103 match(Set dst (SubI dst src));
8104 effect(KILL cr);
8105
8106 format %{ "subl $dst, $src\t# int" %}
8107 opcode(0x81, 0x05); /* Opcode 81 /5 */
8108 ins_encode(OpcSErm(dst, src), Con8or32(src));
8109 ins_pipe(ialu_reg);
8110 %}
8111
8112 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8113 %{
8114 match(Set dst (SubI dst (LoadI src)));
8115 effect(KILL cr);
8116
8117 ins_cost(125);
8118 format %{ "subl $dst, $src\t# int" %}
8119 opcode(0x2B);
8120 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8121 ins_pipe(ialu_reg_mem);
8122 %}
8123
8124 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8125 %{
8126 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8127 effect(KILL cr);
8128
8129 ins_cost(150);
8130 format %{ "subl $dst, $src\t# int" %}
8131 opcode(0x29); /* Opcode 29 /r */
8132 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8133 ins_pipe(ialu_mem_reg);
8134 %}
8135
8136 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8137 %{
8138 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8139 effect(KILL cr);
8140
8141 ins_cost(125); // XXX
8142 format %{ "subl $dst, $src\t# int" %}
8143 opcode(0x81); /* Opcode 81 /5 id */
8144 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8145 ins_pipe(ialu_mem_imm);
8146 %}
8147
8148 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8149 %{
8150 match(Set dst (SubL dst src));
8151 effect(KILL cr);
8152
8153 format %{ "subq $dst, $src\t# long" %}
8154 opcode(0x2B);
8155 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8156 ins_pipe(ialu_reg_reg);
8157 %}
8158
8159 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8160 %{
8161 match(Set dst (SubL dst src));
8162 effect(KILL cr);
8163
8164 format %{ "subq $dst, $src\t# long" %}
8165 opcode(0x81, 0x05); /* Opcode 81 /5 */
8166 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8167 ins_pipe(ialu_reg);
8168 %}
8169
8170 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8171 %{
8172 match(Set dst (SubL dst (LoadL src)));
8173 effect(KILL cr);
8174
8175 ins_cost(125);
8176 format %{ "subq $dst, $src\t# long" %}
8177 opcode(0x2B);
8178 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8179 ins_pipe(ialu_reg_mem);
8180 %}
8181
8182 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8183 %{
8184 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8185 effect(KILL cr);
8186
8187 ins_cost(150);
8188 format %{ "subq $dst, $src\t# long" %}
8189 opcode(0x29); /* Opcode 29 /r */
8190 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8191 ins_pipe(ialu_mem_reg);
8192 %}
8193
8194 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8195 %{
8196 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8197 effect(KILL cr);
8198
8199 ins_cost(125); // XXX
8200 format %{ "subq $dst, $src\t# long" %}
8201 opcode(0x81); /* Opcode 81 /5 id */
8202 ins_encode(REX_mem_wide(dst),
8203 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8204 ins_pipe(ialu_mem_imm);
8205 %}
8206
8207 // Subtract from a pointer
8208 // XXX hmpf???
8209 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8210 %{
8211 match(Set dst (AddP dst (SubI zero src)));
8212 effect(KILL cr);
8213
8214 format %{ "subq $dst, $src\t# ptr - int" %}
8215 opcode(0x2B);
8216 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8217 ins_pipe(ialu_reg_reg);
8218 %}
8219
8220 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8221 %{
8222 match(Set dst (SubI zero dst));
8223 effect(KILL cr);
8224
8225 format %{ "negl $dst\t# int" %}
8226 opcode(0xF7, 0x03); // Opcode F7 /3
8227 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8228 ins_pipe(ialu_reg);
8229 %}
8230
8231 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8232 %{
8233 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8234 effect(KILL cr);
8235
8236 format %{ "negl $dst\t# int" %}
8237 opcode(0xF7, 0x03); // Opcode F7 /3
8238 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8239 ins_pipe(ialu_reg);
8240 %}
8241
8242 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8243 %{
8244 match(Set dst (SubL zero dst));
8245 effect(KILL cr);
8246
8247 format %{ "negq $dst\t# long" %}
8248 opcode(0xF7, 0x03); // Opcode F7 /3
8249 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8250 ins_pipe(ialu_reg);
8251 %}
8252
8253 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8254 %{
8255 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8256 effect(KILL cr);
8257
8258 format %{ "negq $dst\t# long" %}
8259 opcode(0xF7, 0x03); // Opcode F7 /3
8260 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8261 ins_pipe(ialu_reg);
8262 %}
8263
8264 //----------Multiplication/Division Instructions-------------------------------
8265 // Integer Multiplication Instructions
8266 // Multiply Register
8267
8268 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8269 %{
8270 match(Set dst (MulI dst src));
8271 effect(KILL cr);
8272
8273 ins_cost(300);
8274 format %{ "imull $dst, $src\t# int" %}
8275 opcode(0x0F, 0xAF);
8276 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8277 ins_pipe(ialu_reg_reg_alu0);
8278 %}
8279
8280 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8281 %{
8282 match(Set dst (MulI src imm));
8283 effect(KILL cr);
8284
8285 ins_cost(300);
8286 format %{ "imull $dst, $src, $imm\t# int" %}
8287 opcode(0x69); /* 69 /r id */
8288 ins_encode(REX_reg_reg(dst, src),
8289 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8290 ins_pipe(ialu_reg_reg_alu0);
8291 %}
8292
8293 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8294 %{
8295 match(Set dst (MulI dst (LoadI src)));
8296 effect(KILL cr);
8297
8298 ins_cost(350);
8299 format %{ "imull $dst, $src\t# int" %}
8300 opcode(0x0F, 0xAF);
8301 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8302 ins_pipe(ialu_reg_mem_alu0);
8303 %}
8304
8305 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8306 %{
8307 match(Set dst (MulI (LoadI src) imm));
8308 effect(KILL cr);
8309
8310 ins_cost(300);
8311 format %{ "imull $dst, $src, $imm\t# int" %}
8312 opcode(0x69); /* 69 /r id */
8313 ins_encode(REX_reg_mem(dst, src),
8314 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8315 ins_pipe(ialu_reg_mem_alu0);
8316 %}
8317
8318 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8319 %{
8320 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8321 effect(KILL cr, KILL src2);
8322
8323 expand %{ mulI_rReg(dst, src1, cr);
8324 mulI_rReg(src2, src3, cr);
8325 addI_rReg(dst, src2, cr); %}
8326 %}
8327
8328 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8329 %{
8330 match(Set dst (MulL dst src));
8331 effect(KILL cr);
8332
8333 ins_cost(300);
8334 format %{ "imulq $dst, $src\t# long" %}
8335 opcode(0x0F, 0xAF);
8336 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8337 ins_pipe(ialu_reg_reg_alu0);
8338 %}
8339
8340 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8341 %{
8342 match(Set dst (MulL src imm));
8343 effect(KILL cr);
8344
8345 ins_cost(300);
8346 format %{ "imulq $dst, $src, $imm\t# long" %}
8347 opcode(0x69); /* 69 /r id */
8348 ins_encode(REX_reg_reg_wide(dst, src),
8349 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8350 ins_pipe(ialu_reg_reg_alu0);
8351 %}
8352
8353 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8354 %{
8355 match(Set dst (MulL dst (LoadL src)));
8356 effect(KILL cr);
8357
8358 ins_cost(350);
8359 format %{ "imulq $dst, $src\t# long" %}
8360 opcode(0x0F, 0xAF);
8361 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8362 ins_pipe(ialu_reg_mem_alu0);
8363 %}
8364
8365 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8366 %{
8367 match(Set dst (MulL (LoadL src) imm));
8368 effect(KILL cr);
8369
8370 ins_cost(300);
8371 format %{ "imulq $dst, $src, $imm\t# long" %}
8372 opcode(0x69); /* 69 /r id */
8373 ins_encode(REX_reg_mem_wide(dst, src),
8374 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8375 ins_pipe(ialu_reg_mem_alu0);
8376 %}
8377
8378 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8379 %{
8380 match(Set dst (MulHiL src rax));
8381 effect(USE_KILL rax, KILL cr);
8382
8383 ins_cost(300);
8384 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8385 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8386 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8387 ins_pipe(ialu_reg_reg_alu0);
8388 %}
8389
8390 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8391 rFlagsReg cr)
8392 %{
8393 match(Set rax (DivI rax div));
8394 effect(KILL rdx, KILL cr);
8395
8396 ins_cost(30*100+10*100); // XXX
8397 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8398 "jne,s normal\n\t"
8399 "xorl rdx, rdx\n\t"
8400 "cmpl $div, -1\n\t"
8401 "je,s done\n"
8402 "normal: cdql\n\t"
8403 "idivl $div\n"
8404 "done:" %}
8405 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8406 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8407 ins_pipe(ialu_reg_reg_alu0);
8408 %}
8409
8410 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8411 rFlagsReg cr)
8412 %{
8413 match(Set rax (DivL rax div));
8414 effect(KILL rdx, KILL cr);
8415
8416 ins_cost(30*100+10*100); // XXX
8417 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8418 "cmpq rax, rdx\n\t"
8419 "jne,s normal\n\t"
8420 "xorl rdx, rdx\n\t"
8421 "cmpq $div, -1\n\t"
8422 "je,s done\n"
8423 "normal: cdqq\n\t"
8424 "idivq $div\n"
8425 "done:" %}
8426 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8427 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8428 ins_pipe(ialu_reg_reg_alu0);
8429 %}
8430
8431 // Integer DIVMOD with Register, both quotient and mod results
8432 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8433 rFlagsReg cr)
8434 %{
8435 match(DivModI rax div);
8436 effect(KILL cr);
8437
8438 ins_cost(30*100+10*100); // XXX
8439 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8440 "jne,s normal\n\t"
8441 "xorl rdx, rdx\n\t"
8442 "cmpl $div, -1\n\t"
8443 "je,s done\n"
8444 "normal: cdql\n\t"
8445 "idivl $div\n"
8446 "done:" %}
8447 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8448 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8449 ins_pipe(pipe_slow);
8450 %}
8451
8452 // Long DIVMOD with Register, both quotient and mod results
8453 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8454 rFlagsReg cr)
8455 %{
8456 match(DivModL rax div);
8457 effect(KILL cr);
8458
8459 ins_cost(30*100+10*100); // XXX
8460 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8461 "cmpq rax, rdx\n\t"
8462 "jne,s normal\n\t"
8463 "xorl rdx, rdx\n\t"
8464 "cmpq $div, -1\n\t"
8465 "je,s done\n"
8466 "normal: cdqq\n\t"
8467 "idivq $div\n"
8468 "done:" %}
8469 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8470 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8471 ins_pipe(pipe_slow);
8472 %}
8473
8474 //----------- DivL-By-Constant-Expansions--------------------------------------
8475 // DivI cases are handled by the compiler
8476
8477 // Magic constant, reciprocal of 10
8478 instruct loadConL_0x6666666666666667(rRegL dst)
8479 %{
8480 effect(DEF dst);
8481
8482 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8483 ins_encode(load_immL(dst, 0x6666666666666667));
8484 ins_pipe(ialu_reg);
8485 %}
8486
8487 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8488 %{
8489 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8490
8491 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8492 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8493 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8494 ins_pipe(ialu_reg_reg_alu0);
8495 %}
8496
8497 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8498 %{
8499 effect(USE_DEF dst, KILL cr);
8500
8501 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8502 opcode(0xC1, 0x7); /* C1 /7 ib */
8503 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8504 ins_pipe(ialu_reg);
8505 %}
8506
8507 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8508 %{
8509 effect(USE_DEF dst, KILL cr);
8510
8511 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8512 opcode(0xC1, 0x7); /* C1 /7 ib */
8513 ins_encode(reg_opc_imm_wide(dst, 0x2));
8514 ins_pipe(ialu_reg);
8515 %}
8516
8517 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8518 %{
8519 match(Set dst (DivL src div));
8520
8521 ins_cost((5+8)*100);
8522 expand %{
8523 rax_RegL rax; // Killed temp
8524 rFlagsReg cr; // Killed
8525 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8526 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8527 sarL_rReg_63(src, cr); // sarq src, 63
8528 sarL_rReg_2(dst, cr); // sarq rdx, 2
8529 subL_rReg(dst, src, cr); // subl rdx, src
8530 %}
8531 %}
8532
8533 //-----------------------------------------------------------------------------
8534
8535 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8536 rFlagsReg cr)
8537 %{
8538 match(Set rdx (ModI rax div));
8539 effect(KILL rax, KILL cr);
8540
8541 ins_cost(300); // XXX
8542 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8543 "jne,s normal\n\t"
8544 "xorl rdx, rdx\n\t"
8545 "cmpl $div, -1\n\t"
8546 "je,s done\n"
8547 "normal: cdql\n\t"
8548 "idivl $div\n"
8549 "done:" %}
8550 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8551 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8552 ins_pipe(ialu_reg_reg_alu0);
8553 %}
8554
8555 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8556 rFlagsReg cr)
8557 %{
8558 match(Set rdx (ModL rax div));
8559 effect(KILL rax, KILL cr);
8560
8561 ins_cost(300); // XXX
8562 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8563 "cmpq rax, rdx\n\t"
8564 "jne,s normal\n\t"
8565 "xorl rdx, rdx\n\t"
8566 "cmpq $div, -1\n\t"
8567 "je,s done\n"
8568 "normal: cdqq\n\t"
8569 "idivq $div\n"
8570 "done:" %}
8571 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8572 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8573 ins_pipe(ialu_reg_reg_alu0);
8574 %}
8575
8576 // Integer Shift Instructions
8577 // Shift Left by one
8578 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8579 %{
8580 match(Set dst (LShiftI dst shift));
8581 effect(KILL cr);
8582
8583 format %{ "sall $dst, $shift" %}
8584 opcode(0xD1, 0x4); /* D1 /4 */
8585 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8586 ins_pipe(ialu_reg);
8587 %}
8588
8589 // Shift Left by one
8590 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8591 %{
8592 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8593 effect(KILL cr);
8594
8595 format %{ "sall $dst, $shift\t" %}
8596 opcode(0xD1, 0x4); /* D1 /4 */
8597 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8598 ins_pipe(ialu_mem_imm);
8599 %}
8600
8601 // Shift Left by 8-bit immediate
8602 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8603 %{
8604 match(Set dst (LShiftI dst shift));
8605 effect(KILL cr);
8606
8607 format %{ "sall $dst, $shift" %}
8608 opcode(0xC1, 0x4); /* C1 /4 ib */
8609 ins_encode(reg_opc_imm(dst, shift));
8610 ins_pipe(ialu_reg);
8611 %}
8612
8613 // Shift Left by 8-bit immediate
8614 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8615 %{
8616 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8617 effect(KILL cr);
8618
8619 format %{ "sall $dst, $shift" %}
8620 opcode(0xC1, 0x4); /* C1 /4 ib */
8621 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8622 ins_pipe(ialu_mem_imm);
8623 %}
8624
8625 // Shift Left by variable
8626 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8627 %{
8628 match(Set dst (LShiftI dst shift));
8629 effect(KILL cr);
8630
8631 format %{ "sall $dst, $shift" %}
8632 opcode(0xD3, 0x4); /* D3 /4 */
8633 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8634 ins_pipe(ialu_reg_reg);
8635 %}
8636
8637 // Shift Left by variable
8638 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8639 %{
8640 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8641 effect(KILL cr);
8642
8643 format %{ "sall $dst, $shift" %}
8644 opcode(0xD3, 0x4); /* D3 /4 */
8645 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8646 ins_pipe(ialu_mem_reg);
8647 %}
8648
8649 // Arithmetic shift right by one
8650 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8651 %{
8652 match(Set dst (RShiftI dst shift));
8653 effect(KILL cr);
8654
8655 format %{ "sarl $dst, $shift" %}
8656 opcode(0xD1, 0x7); /* D1 /7 */
8657 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8658 ins_pipe(ialu_reg);
8659 %}
8660
8661 // Arithmetic shift right by one
8662 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8663 %{
8664 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8665 effect(KILL cr);
8666
8667 format %{ "sarl $dst, $shift" %}
8668 opcode(0xD1, 0x7); /* D1 /7 */
8669 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8670 ins_pipe(ialu_mem_imm);
8671 %}
8672
8673 // Arithmetic Shift Right by 8-bit immediate
8674 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8675 %{
8676 match(Set dst (RShiftI dst shift));
8677 effect(KILL cr);
8678
8679 format %{ "sarl $dst, $shift" %}
8680 opcode(0xC1, 0x7); /* C1 /7 ib */
8681 ins_encode(reg_opc_imm(dst, shift));
8682 ins_pipe(ialu_mem_imm);
8683 %}
8684
8685 // Arithmetic Shift Right by 8-bit immediate
8686 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8687 %{
8688 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8689 effect(KILL cr);
8690
8691 format %{ "sarl $dst, $shift" %}
8692 opcode(0xC1, 0x7); /* C1 /7 ib */
8693 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8694 ins_pipe(ialu_mem_imm);
8695 %}
8696
8697 // Arithmetic Shift Right by variable
8698 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8699 %{
8700 match(Set dst (RShiftI dst shift));
8701 effect(KILL cr);
8702
8703 format %{ "sarl $dst, $shift" %}
8704 opcode(0xD3, 0x7); /* D3 /7 */
8705 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8706 ins_pipe(ialu_reg_reg);
8707 %}
8708
8709 // Arithmetic Shift Right by variable
8710 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8711 %{
8712 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8713 effect(KILL cr);
8714
8715 format %{ "sarl $dst, $shift" %}
8716 opcode(0xD3, 0x7); /* D3 /7 */
8717 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8718 ins_pipe(ialu_mem_reg);
8719 %}
8720
8721 // Logical shift right by one
8722 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8723 %{
8724 match(Set dst (URShiftI dst shift));
8725 effect(KILL cr);
8726
8727 format %{ "shrl $dst, $shift" %}
8728 opcode(0xD1, 0x5); /* D1 /5 */
8729 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8730 ins_pipe(ialu_reg);
8731 %}
8732
8733 // Logical shift right by one
8734 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8735 %{
8736 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8737 effect(KILL cr);
8738
8739 format %{ "shrl $dst, $shift" %}
8740 opcode(0xD1, 0x5); /* D1 /5 */
8741 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8742 ins_pipe(ialu_mem_imm);
8743 %}
8744
8745 // Logical Shift Right by 8-bit immediate
8746 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8747 %{
8748 match(Set dst (URShiftI dst shift));
8749 effect(KILL cr);
8750
8751 format %{ "shrl $dst, $shift" %}
8752 opcode(0xC1, 0x5); /* C1 /5 ib */
8753 ins_encode(reg_opc_imm(dst, shift));
8754 ins_pipe(ialu_reg);
8755 %}
8756
8757 // Logical Shift Right by 8-bit immediate
8758 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8759 %{
8760 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8761 effect(KILL cr);
8762
8763 format %{ "shrl $dst, $shift" %}
8764 opcode(0xC1, 0x5); /* C1 /5 ib */
8765 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8766 ins_pipe(ialu_mem_imm);
8767 %}
8768
8769 // Logical Shift Right by variable
8770 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8771 %{
8772 match(Set dst (URShiftI dst shift));
8773 effect(KILL cr);
8774
8775 format %{ "shrl $dst, $shift" %}
8776 opcode(0xD3, 0x5); /* D3 /5 */
8777 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8778 ins_pipe(ialu_reg_reg);
8779 %}
8780
8781 // Logical Shift Right by variable
8782 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8783 %{
8784 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8785 effect(KILL cr);
8786
8787 format %{ "shrl $dst, $shift" %}
8788 opcode(0xD3, 0x5); /* D3 /5 */
8789 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8790 ins_pipe(ialu_mem_reg);
8791 %}
8792
8793 // Long Shift Instructions
8794 // Shift Left by one
8795 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8796 %{
8797 match(Set dst (LShiftL dst shift));
8798 effect(KILL cr);
8799
8800 format %{ "salq $dst, $shift" %}
8801 opcode(0xD1, 0x4); /* D1 /4 */
8802 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8803 ins_pipe(ialu_reg);
8804 %}
8805
8806 // Shift Left by one
8807 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8808 %{
8809 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8810 effect(KILL cr);
8811
8812 format %{ "salq $dst, $shift" %}
8813 opcode(0xD1, 0x4); /* D1 /4 */
8814 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8815 ins_pipe(ialu_mem_imm);
8816 %}
8817
8818 // Shift Left by 8-bit immediate
8819 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8820 %{
8821 match(Set dst (LShiftL dst shift));
8822 effect(KILL cr);
8823
8824 format %{ "salq $dst, $shift" %}
8825 opcode(0xC1, 0x4); /* C1 /4 ib */
8826 ins_encode(reg_opc_imm_wide(dst, shift));
8827 ins_pipe(ialu_reg);
8828 %}
8829
8830 // Shift Left by 8-bit immediate
8831 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8832 %{
8833 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8834 effect(KILL cr);
8835
8836 format %{ "salq $dst, $shift" %}
8837 opcode(0xC1, 0x4); /* C1 /4 ib */
8838 ins_encode(REX_mem_wide(dst), OpcP,
8839 RM_opc_mem(secondary, dst), Con8or32(shift));
8840 ins_pipe(ialu_mem_imm);
8841 %}
8842
8843 // Shift Left by variable
8844 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8845 %{
8846 match(Set dst (LShiftL dst shift));
8847 effect(KILL cr);
8848
8849 format %{ "salq $dst, $shift" %}
8850 opcode(0xD3, 0x4); /* D3 /4 */
8851 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8852 ins_pipe(ialu_reg_reg);
8853 %}
8854
8855 // Shift Left by variable
8856 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8857 %{
8858 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8859 effect(KILL cr);
8860
8861 format %{ "salq $dst, $shift" %}
8862 opcode(0xD3, 0x4); /* D3 /4 */
8863 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8864 ins_pipe(ialu_mem_reg);
8865 %}
8866
8867 // Arithmetic shift right by one
8868 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8869 %{
8870 match(Set dst (RShiftL dst shift));
8871 effect(KILL cr);
8872
8873 format %{ "sarq $dst, $shift" %}
8874 opcode(0xD1, 0x7); /* D1 /7 */
8875 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8876 ins_pipe(ialu_reg);
8877 %}
8878
8879 // Arithmetic shift right by one
8880 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8881 %{
8882 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8883 effect(KILL cr);
8884
8885 format %{ "sarq $dst, $shift" %}
8886 opcode(0xD1, 0x7); /* D1 /7 */
8887 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8888 ins_pipe(ialu_mem_imm);
8889 %}
8890
8891 // Arithmetic Shift Right by 8-bit immediate
8892 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8893 %{
8894 match(Set dst (RShiftL dst shift));
8895 effect(KILL cr);
8896
8897 format %{ "sarq $dst, $shift" %}
8898 opcode(0xC1, 0x7); /* C1 /7 ib */
8899 ins_encode(reg_opc_imm_wide(dst, shift));
8900 ins_pipe(ialu_mem_imm);
8901 %}
8902
8903 // Arithmetic Shift Right by 8-bit immediate
8904 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8905 %{
8906 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8907 effect(KILL cr);
8908
8909 format %{ "sarq $dst, $shift" %}
8910 opcode(0xC1, 0x7); /* C1 /7 ib */
8911 ins_encode(REX_mem_wide(dst), OpcP,
8912 RM_opc_mem(secondary, dst), Con8or32(shift));
8913 ins_pipe(ialu_mem_imm);
8914 %}
8915
8916 // Arithmetic Shift Right by variable
8917 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8918 %{
8919 match(Set dst (RShiftL dst shift));
8920 effect(KILL cr);
8921
8922 format %{ "sarq $dst, $shift" %}
8923 opcode(0xD3, 0x7); /* D3 /7 */
8924 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8925 ins_pipe(ialu_reg_reg);
8926 %}
8927
8928 // Arithmetic Shift Right by variable
8929 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8930 %{
8931 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8932 effect(KILL cr);
8933
8934 format %{ "sarq $dst, $shift" %}
8935 opcode(0xD3, 0x7); /* D3 /7 */
8936 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8937 ins_pipe(ialu_mem_reg);
8938 %}
8939
8940 // Logical shift right by one
8941 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8942 %{
8943 match(Set dst (URShiftL dst shift));
8944 effect(KILL cr);
8945
8946 format %{ "shrq $dst, $shift" %}
8947 opcode(0xD1, 0x5); /* D1 /5 */
8948 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8949 ins_pipe(ialu_reg);
8950 %}
8951
8952 // Logical shift right by one
8953 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8954 %{
8955 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8956 effect(KILL cr);
8957
8958 format %{ "shrq $dst, $shift" %}
8959 opcode(0xD1, 0x5); /* D1 /5 */
8960 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8961 ins_pipe(ialu_mem_imm);
8962 %}
8963
8964 // Logical Shift Right by 8-bit immediate
8965 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8966 %{
8967 match(Set dst (URShiftL dst shift));
8968 effect(KILL cr);
8969
8970 format %{ "shrq $dst, $shift" %}
8971 opcode(0xC1, 0x5); /* C1 /5 ib */
8972 ins_encode(reg_opc_imm_wide(dst, shift));
8973 ins_pipe(ialu_reg);
8974 %}
8975
8976
8977 // Logical Shift Right by 8-bit immediate
8978 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8979 %{
8980 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8981 effect(KILL cr);
8982
8983 format %{ "shrq $dst, $shift" %}
8984 opcode(0xC1, 0x5); /* C1 /5 ib */
8985 ins_encode(REX_mem_wide(dst), OpcP,
8986 RM_opc_mem(secondary, dst), Con8or32(shift));
8987 ins_pipe(ialu_mem_imm);
8988 %}
8989
8990 // Logical Shift Right by variable
8991 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8992 %{
8993 match(Set dst (URShiftL dst shift));
8994 effect(KILL cr);
8995
8996 format %{ "shrq $dst, $shift" %}
8997 opcode(0xD3, 0x5); /* D3 /5 */
8998 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8999 ins_pipe(ialu_reg_reg);
9000 %}
9001
9002 // Logical Shift Right by variable
9003 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9004 %{
9005 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9006 effect(KILL cr);
9007
9008 format %{ "shrq $dst, $shift" %}
9009 opcode(0xD3, 0x5); /* D3 /5 */
9010 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9011 ins_pipe(ialu_mem_reg);
9012 %}
9013
9014 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9015 // This idiom is used by the compiler for the i2b bytecode.
9016 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9017 %{
9018 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9019
9020 format %{ "movsbl $dst, $src\t# i2b" %}
9021 opcode(0x0F, 0xBE);
9022 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9023 ins_pipe(ialu_reg_reg);
9024 %}
9025
9026 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9027 // This idiom is used by the compiler the i2s bytecode.
9028 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9029 %{
9030 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9031
9032 format %{ "movswl $dst, $src\t# i2s" %}
9033 opcode(0x0F, 0xBF);
9034 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9035 ins_pipe(ialu_reg_reg);
9036 %}
9037
9038 // ROL/ROR instructions
9039
9040 // ROL expand
9041 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9042 effect(KILL cr, USE_DEF dst);
9043
9044 format %{ "roll $dst" %}
9045 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9046 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9047 ins_pipe(ialu_reg);
9048 %}
9049
9050 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9051 effect(USE_DEF dst, USE shift, KILL cr);
9052
9053 format %{ "roll $dst, $shift" %}
9054 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9055 ins_encode( reg_opc_imm(dst, shift) );
9056 ins_pipe(ialu_reg);
9057 %}
9058
9059 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9060 %{
9061 effect(USE_DEF dst, USE shift, KILL cr);
9062
9063 format %{ "roll $dst, $shift" %}
9064 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9065 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9066 ins_pipe(ialu_reg_reg);
9067 %}
9068 // end of ROL expand
9069
9070 // Rotate Left by one
9071 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9072 %{
9073 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9074
9075 expand %{
9076 rolI_rReg_imm1(dst, cr);
9077 %}
9078 %}
9079
9080 // Rotate Left by 8-bit immediate
9081 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9082 %{
9083 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9084 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9085
9086 expand %{
9087 rolI_rReg_imm8(dst, lshift, cr);
9088 %}
9089 %}
9090
9091 // Rotate Left by variable
9092 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9093 %{
9094 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9095
9096 expand %{
9097 rolI_rReg_CL(dst, shift, cr);
9098 %}
9099 %}
9100
9101 // Rotate Left by variable
9102 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9103 %{
9104 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9105
9106 expand %{
9107 rolI_rReg_CL(dst, shift, cr);
9108 %}
9109 %}
9110
9111 // ROR expand
9112 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9113 %{
9114 effect(USE_DEF dst, KILL cr);
9115
9116 format %{ "rorl $dst" %}
9117 opcode(0xD1, 0x1); /* D1 /1 */
9118 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9119 ins_pipe(ialu_reg);
9120 %}
9121
9122 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9123 %{
9124 effect(USE_DEF dst, USE shift, KILL cr);
9125
9126 format %{ "rorl $dst, $shift" %}
9127 opcode(0xC1, 0x1); /* C1 /1 ib */
9128 ins_encode(reg_opc_imm(dst, shift));
9129 ins_pipe(ialu_reg);
9130 %}
9131
9132 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9133 %{
9134 effect(USE_DEF dst, USE shift, KILL cr);
9135
9136 format %{ "rorl $dst, $shift" %}
9137 opcode(0xD3, 0x1); /* D3 /1 */
9138 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9139 ins_pipe(ialu_reg_reg);
9140 %}
9141 // end of ROR expand
9142
9143 // Rotate Right by one
9144 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9145 %{
9146 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9147
9148 expand %{
9149 rorI_rReg_imm1(dst, cr);
9150 %}
9151 %}
9152
9153 // Rotate Right by 8-bit immediate
9154 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9155 %{
9156 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9157 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9158
9159 expand %{
9160 rorI_rReg_imm8(dst, rshift, cr);
9161 %}
9162 %}
9163
9164 // Rotate Right by variable
9165 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9166 %{
9167 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9168
9169 expand %{
9170 rorI_rReg_CL(dst, shift, cr);
9171 %}
9172 %}
9173
9174 // Rotate Right by variable
9175 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9176 %{
9177 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9178
9179 expand %{
9180 rorI_rReg_CL(dst, shift, cr);
9181 %}
9182 %}
9183
9184 // for long rotate
9185 // ROL expand
9186 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9187 effect(USE_DEF dst, KILL cr);
9188
9189 format %{ "rolq $dst" %}
9190 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9191 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9192 ins_pipe(ialu_reg);
9193 %}
9194
9195 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9196 effect(USE_DEF dst, USE shift, KILL cr);
9197
9198 format %{ "rolq $dst, $shift" %}
9199 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9200 ins_encode( reg_opc_imm_wide(dst, shift) );
9201 ins_pipe(ialu_reg);
9202 %}
9203
9204 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9205 %{
9206 effect(USE_DEF dst, USE shift, KILL cr);
9207
9208 format %{ "rolq $dst, $shift" %}
9209 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9210 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9211 ins_pipe(ialu_reg_reg);
9212 %}
9213 // end of ROL expand
9214
9215 // Rotate Left by one
9216 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9217 %{
9218 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9219
9220 expand %{
9221 rolL_rReg_imm1(dst, cr);
9222 %}
9223 %}
9224
9225 // Rotate Left by 8-bit immediate
9226 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9227 %{
9228 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9229 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9230
9231 expand %{
9232 rolL_rReg_imm8(dst, lshift, cr);
9233 %}
9234 %}
9235
9236 // Rotate Left by variable
9237 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9238 %{
9239 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9240
9241 expand %{
9242 rolL_rReg_CL(dst, shift, cr);
9243 %}
9244 %}
9245
9246 // Rotate Left by variable
9247 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9248 %{
9249 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9250
9251 expand %{
9252 rolL_rReg_CL(dst, shift, cr);
9253 %}
9254 %}
9255
9256 // ROR expand
9257 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9258 %{
9259 effect(USE_DEF dst, KILL cr);
9260
9261 format %{ "rorq $dst" %}
9262 opcode(0xD1, 0x1); /* D1 /1 */
9263 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9264 ins_pipe(ialu_reg);
9265 %}
9266
9267 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9268 %{
9269 effect(USE_DEF dst, USE shift, KILL cr);
9270
9271 format %{ "rorq $dst, $shift" %}
9272 opcode(0xC1, 0x1); /* C1 /1 ib */
9273 ins_encode(reg_opc_imm_wide(dst, shift));
9274 ins_pipe(ialu_reg);
9275 %}
9276
9277 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9278 %{
9279 effect(USE_DEF dst, USE shift, KILL cr);
9280
9281 format %{ "rorq $dst, $shift" %}
9282 opcode(0xD3, 0x1); /* D3 /1 */
9283 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9284 ins_pipe(ialu_reg_reg);
9285 %}
9286 // end of ROR expand
9287
9288 // Rotate Right by one
9289 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9290 %{
9291 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9292
9293 expand %{
9294 rorL_rReg_imm1(dst, cr);
9295 %}
9296 %}
9297
9298 // Rotate Right by 8-bit immediate
9299 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9300 %{
9301 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9302 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9303
9304 expand %{
9305 rorL_rReg_imm8(dst, rshift, cr);
9306 %}
9307 %}
9308
9309 // Rotate Right by variable
9310 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9311 %{
9312 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9313
9314 expand %{
9315 rorL_rReg_CL(dst, shift, cr);
9316 %}
9317 %}
9318
9319 // Rotate Right by variable
9320 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9321 %{
9322 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9323
9324 expand %{
9325 rorL_rReg_CL(dst, shift, cr);
9326 %}
9327 %}
9328
9329 // Logical Instructions
9330
9331 // Integer Logical Instructions
9332
9333 // And Instructions
9334 // And Register with Register
9335 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9336 %{
9337 match(Set dst (AndI dst src));
9338 effect(KILL cr);
9339
9340 format %{ "andl $dst, $src\t# int" %}
9341 opcode(0x23);
9342 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9343 ins_pipe(ialu_reg_reg);
9344 %}
9345
9346 // And Register with Immediate 255
9347 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9348 %{
9349 match(Set dst (AndI dst src));
9350
9351 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9352 opcode(0x0F, 0xB6);
9353 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9354 ins_pipe(ialu_reg);
9355 %}
9356
9357 // And Register with Immediate 255 and promote to long
9358 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9359 %{
9360 match(Set dst (ConvI2L (AndI src mask)));
9361
9362 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9363 opcode(0x0F, 0xB6);
9364 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9365 ins_pipe(ialu_reg);
9366 %}
9367
9368 // And Register with Immediate 65535
9369 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9370 %{
9371 match(Set dst (AndI dst src));
9372
9373 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9374 opcode(0x0F, 0xB7);
9375 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9376 ins_pipe(ialu_reg);
9377 %}
9378
9379 // And Register with Immediate 65535 and promote to long
9380 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9381 %{
9382 match(Set dst (ConvI2L (AndI src mask)));
9383
9384 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9385 opcode(0x0F, 0xB7);
9386 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9387 ins_pipe(ialu_reg);
9388 %}
9389
9390 // And Register with Immediate
9391 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9392 %{
9393 match(Set dst (AndI dst src));
9394 effect(KILL cr);
9395
9396 format %{ "andl $dst, $src\t# int" %}
9397 opcode(0x81, 0x04); /* Opcode 81 /4 */
9398 ins_encode(OpcSErm(dst, src), Con8or32(src));
9399 ins_pipe(ialu_reg);
9400 %}
9401
9402 // And Register with Memory
9403 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9404 %{
9405 match(Set dst (AndI dst (LoadI src)));
9406 effect(KILL cr);
9407
9408 ins_cost(125);
9409 format %{ "andl $dst, $src\t# int" %}
9410 opcode(0x23);
9411 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9412 ins_pipe(ialu_reg_mem);
9413 %}
9414
9415 // And Memory with Register
9416 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9417 %{
9418 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9419 effect(KILL cr);
9420
9421 ins_cost(150);
9422 format %{ "andb $dst, $src\t# byte" %}
9423 opcode(0x20);
9424 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9425 ins_pipe(ialu_mem_reg);
9426 %}
9427
9428 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9429 %{
9430 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9431 effect(KILL cr);
9432
9433 ins_cost(150);
9434 format %{ "andl $dst, $src\t# int" %}
9435 opcode(0x21); /* Opcode 21 /r */
9436 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9437 ins_pipe(ialu_mem_reg);
9438 %}
9439
9440 // And Memory with Immediate
9441 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9442 %{
9443 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9444 effect(KILL cr);
9445
9446 ins_cost(125);
9447 format %{ "andl $dst, $src\t# int" %}
9448 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9449 ins_encode(REX_mem(dst), OpcSE(src),
9450 RM_opc_mem(secondary, dst), Con8or32(src));
9451 ins_pipe(ialu_mem_imm);
9452 %}
9453
9454 // BMI1 instructions
9455 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9456 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9457 predicate(UseBMI1Instructions);
9458 effect(KILL cr);
9459
9460 ins_cost(125);
9461 format %{ "andnl $dst, $src1, $src2" %}
9462
9463 ins_encode %{
9464 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9465 %}
9466 ins_pipe(ialu_reg_mem);
9467 %}
9468
9469 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9470 match(Set dst (AndI (XorI src1 minus_1) src2));
9471 predicate(UseBMI1Instructions);
9472 effect(KILL cr);
9473
9474 format %{ "andnl $dst, $src1, $src2" %}
9475
9476 ins_encode %{
9477 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9478 %}
9479 ins_pipe(ialu_reg);
9480 %}
9481
9482 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9483 match(Set dst (AndI (SubI imm_zero src) src));
9484 predicate(UseBMI1Instructions);
9485 effect(KILL cr);
9486
9487 format %{ "blsil $dst, $src" %}
9488
9489 ins_encode %{
9490 __ blsil($dst$$Register, $src$$Register);
9491 %}
9492 ins_pipe(ialu_reg);
9493 %}
9494
9495 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9496 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9497 predicate(UseBMI1Instructions);
9498 effect(KILL cr);
9499
9500 ins_cost(125);
9501 format %{ "blsil $dst, $src" %}
9502
9503 ins_encode %{
9504 __ blsil($dst$$Register, $src$$Address);
9505 %}
9506 ins_pipe(ialu_reg_mem);
9507 %}
9508
9509 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9510 %{
9511 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9512 predicate(UseBMI1Instructions);
9513 effect(KILL cr);
9514
9515 ins_cost(125);
9516 format %{ "blsmskl $dst, $src" %}
9517
9518 ins_encode %{
9519 __ blsmskl($dst$$Register, $src$$Address);
9520 %}
9521 ins_pipe(ialu_reg_mem);
9522 %}
9523
9524 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9525 %{
9526 match(Set dst (XorI (AddI src minus_1) src));
9527 predicate(UseBMI1Instructions);
9528 effect(KILL cr);
9529
9530 format %{ "blsmskl $dst, $src" %}
9531
9532 ins_encode %{
9533 __ blsmskl($dst$$Register, $src$$Register);
9534 %}
9535
9536 ins_pipe(ialu_reg);
9537 %}
9538
9539 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9540 %{
9541 match(Set dst (AndI (AddI src minus_1) src) );
9542 predicate(UseBMI1Instructions);
9543 effect(KILL cr);
9544
9545 format %{ "blsrl $dst, $src" %}
9546
9547 ins_encode %{
9548 __ blsrl($dst$$Register, $src$$Register);
9549 %}
9550
9551 ins_pipe(ialu_reg_mem);
9552 %}
9553
9554 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9555 %{
9556 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9557 predicate(UseBMI1Instructions);
9558 effect(KILL cr);
9559
9560 ins_cost(125);
9561 format %{ "blsrl $dst, $src" %}
9562
9563 ins_encode %{
9564 __ blsrl($dst$$Register, $src$$Address);
9565 %}
9566
9567 ins_pipe(ialu_reg);
9568 %}
9569
9570 // Or Instructions
9571 // Or Register with Register
9572 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9573 %{
9574 match(Set dst (OrI dst src));
9575 effect(KILL cr);
9576
9577 format %{ "orl $dst, $src\t# int" %}
9578 opcode(0x0B);
9579 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9580 ins_pipe(ialu_reg_reg);
9581 %}
9582
9583 // Or Register with Immediate
9584 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9585 %{
9586 match(Set dst (OrI dst src));
9587 effect(KILL cr);
9588
9589 format %{ "orl $dst, $src\t# int" %}
9590 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9591 ins_encode(OpcSErm(dst, src), Con8or32(src));
9592 ins_pipe(ialu_reg);
9593 %}
9594
9595 // Or Register with Memory
9596 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9597 %{
9598 match(Set dst (OrI dst (LoadI src)));
9599 effect(KILL cr);
9600
9601 ins_cost(125);
9602 format %{ "orl $dst, $src\t# int" %}
9603 opcode(0x0B);
9604 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9605 ins_pipe(ialu_reg_mem);
9606 %}
9607
9608 // Or Memory with Register
9609 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9610 %{
9611 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9612 effect(KILL cr);
9613
9614 ins_cost(150);
9615 format %{ "orb $dst, $src\t# byte" %}
9616 opcode(0x08);
9617 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9618 ins_pipe(ialu_mem_reg);
9619 %}
9620
9621 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9622 %{
9623 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9624 effect(KILL cr);
9625
9626 ins_cost(150);
9627 format %{ "orl $dst, $src\t# int" %}
9628 opcode(0x09); /* Opcode 09 /r */
9629 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9630 ins_pipe(ialu_mem_reg);
9631 %}
9632
9633 // Or Memory with Immediate
9634 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9635 %{
9636 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9637 effect(KILL cr);
9638
9639 ins_cost(125);
9640 format %{ "orl $dst, $src\t# int" %}
9641 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9642 ins_encode(REX_mem(dst), OpcSE(src),
9643 RM_opc_mem(secondary, dst), Con8or32(src));
9644 ins_pipe(ialu_mem_imm);
9645 %}
9646
9647 // Xor Instructions
9648 // Xor Register with Register
9649 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9650 %{
9651 match(Set dst (XorI dst src));
9652 effect(KILL cr);
9653
9654 format %{ "xorl $dst, $src\t# int" %}
9655 opcode(0x33);
9656 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9657 ins_pipe(ialu_reg_reg);
9658 %}
9659
9660 // Xor Register with Immediate -1
9661 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9662 match(Set dst (XorI dst imm));
9663
9664 format %{ "not $dst" %}
9665 ins_encode %{
9666 __ notl($dst$$Register);
9667 %}
9668 ins_pipe(ialu_reg);
9669 %}
9670
9671 // Xor Register with Immediate
9672 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9673 %{
9674 match(Set dst (XorI dst src));
9675 effect(KILL cr);
9676
9677 format %{ "xorl $dst, $src\t# int" %}
9678 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9679 ins_encode(OpcSErm(dst, src), Con8or32(src));
9680 ins_pipe(ialu_reg);
9681 %}
9682
9683 // Xor Register with Memory
9684 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9685 %{
9686 match(Set dst (XorI dst (LoadI src)));
9687 effect(KILL cr);
9688
9689 ins_cost(125);
9690 format %{ "xorl $dst, $src\t# int" %}
9691 opcode(0x33);
9692 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9693 ins_pipe(ialu_reg_mem);
9694 %}
9695
9696 // Xor Memory with Register
9697 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9698 %{
9699 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9700 effect(KILL cr);
9701
9702 ins_cost(150);
9703 format %{ "xorb $dst, $src\t# byte" %}
9704 opcode(0x30);
9705 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9706 ins_pipe(ialu_mem_reg);
9707 %}
9708
9709 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9710 %{
9711 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9712 effect(KILL cr);
9713
9714 ins_cost(150);
9715 format %{ "xorl $dst, $src\t# int" %}
9716 opcode(0x31); /* Opcode 31 /r */
9717 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9718 ins_pipe(ialu_mem_reg);
9719 %}
9720
9721 // Xor Memory with Immediate
9722 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9723 %{
9724 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9725 effect(KILL cr);
9726
9727 ins_cost(125);
9728 format %{ "xorl $dst, $src\t# int" %}
9729 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9730 ins_encode(REX_mem(dst), OpcSE(src),
9731 RM_opc_mem(secondary, dst), Con8or32(src));
9732 ins_pipe(ialu_mem_imm);
9733 %}
9734
9735
9736 // Long Logical Instructions
9737
9738 // And Instructions
9739 // And Register with Register
9740 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9741 %{
9742 match(Set dst (AndL dst src));
9743 effect(KILL cr);
9744
9745 format %{ "andq $dst, $src\t# long" %}
9746 opcode(0x23);
9747 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9748 ins_pipe(ialu_reg_reg);
9749 %}
9750
9751 // And Register with Immediate 255
9752 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9753 %{
9754 match(Set dst (AndL dst src));
9755
9756 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9757 opcode(0x0F, 0xB6);
9758 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9759 ins_pipe(ialu_reg);
9760 %}
9761
9762 // And Register with Immediate 65535
9763 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9764 %{
9765 match(Set dst (AndL dst src));
9766
9767 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9768 opcode(0x0F, 0xB7);
9769 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9770 ins_pipe(ialu_reg);
9771 %}
9772
9773 // And Register with Immediate
9774 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9775 %{
9776 match(Set dst (AndL dst src));
9777 effect(KILL cr);
9778
9779 format %{ "andq $dst, $src\t# long" %}
9780 opcode(0x81, 0x04); /* Opcode 81 /4 */
9781 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9782 ins_pipe(ialu_reg);
9783 %}
9784
9785 // And Register with Memory
9786 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9787 %{
9788 match(Set dst (AndL dst (LoadL src)));
9789 effect(KILL cr);
9790
9791 ins_cost(125);
9792 format %{ "andq $dst, $src\t# long" %}
9793 opcode(0x23);
9794 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9795 ins_pipe(ialu_reg_mem);
9796 %}
9797
9798 // And Memory with Register
9799 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9800 %{
9801 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9802 effect(KILL cr);
9803
9804 ins_cost(150);
9805 format %{ "andq $dst, $src\t# long" %}
9806 opcode(0x21); /* Opcode 21 /r */
9807 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9808 ins_pipe(ialu_mem_reg);
9809 %}
9810
9811 // And Memory with Immediate
9812 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9813 %{
9814 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9815 effect(KILL cr);
9816
9817 ins_cost(125);
9818 format %{ "andq $dst, $src\t# long" %}
9819 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9820 ins_encode(REX_mem_wide(dst), OpcSE(src),
9821 RM_opc_mem(secondary, dst), Con8or32(src));
9822 ins_pipe(ialu_mem_imm);
9823 %}
9824
9825 // BMI1 instructions
9826 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9827 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9828 predicate(UseBMI1Instructions);
9829 effect(KILL cr);
9830
9831 ins_cost(125);
9832 format %{ "andnq $dst, $src1, $src2" %}
9833
9834 ins_encode %{
9835 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9836 %}
9837 ins_pipe(ialu_reg_mem);
9838 %}
9839
9840 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9841 match(Set dst (AndL (XorL src1 minus_1) src2));
9842 predicate(UseBMI1Instructions);
9843 effect(KILL cr);
9844
9845 format %{ "andnq $dst, $src1, $src2" %}
9846
9847 ins_encode %{
9848 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9849 %}
9850 ins_pipe(ialu_reg_mem);
9851 %}
9852
9853 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9854 match(Set dst (AndL (SubL imm_zero src) src));
9855 predicate(UseBMI1Instructions);
9856 effect(KILL cr);
9857
9858 format %{ "blsiq $dst, $src" %}
9859
9860 ins_encode %{
9861 __ blsiq($dst$$Register, $src$$Register);
9862 %}
9863 ins_pipe(ialu_reg);
9864 %}
9865
9866 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9867 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9868 predicate(UseBMI1Instructions);
9869 effect(KILL cr);
9870
9871 ins_cost(125);
9872 format %{ "blsiq $dst, $src" %}
9873
9874 ins_encode %{
9875 __ blsiq($dst$$Register, $src$$Address);
9876 %}
9877 ins_pipe(ialu_reg_mem);
9878 %}
9879
9880 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9881 %{
9882 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9883 predicate(UseBMI1Instructions);
9884 effect(KILL cr);
9885
9886 ins_cost(125);
9887 format %{ "blsmskq $dst, $src" %}
9888
9889 ins_encode %{
9890 __ blsmskq($dst$$Register, $src$$Address);
9891 %}
9892 ins_pipe(ialu_reg_mem);
9893 %}
9894
9895 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9896 %{
9897 match(Set dst (XorL (AddL src minus_1) src));
9898 predicate(UseBMI1Instructions);
9899 effect(KILL cr);
9900
9901 format %{ "blsmskq $dst, $src" %}
9902
9903 ins_encode %{
9904 __ blsmskq($dst$$Register, $src$$Register);
9905 %}
9906
9907 ins_pipe(ialu_reg);
9908 %}
9909
9910 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9911 %{
9912 match(Set dst (AndL (AddL src minus_1) src) );
9913 predicate(UseBMI1Instructions);
9914 effect(KILL cr);
9915
9916 format %{ "blsrq $dst, $src" %}
9917
9918 ins_encode %{
9919 __ blsrq($dst$$Register, $src$$Register);
9920 %}
9921
9922 ins_pipe(ialu_reg);
9923 %}
9924
9925 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9926 %{
9927 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9928 predicate(UseBMI1Instructions);
9929 effect(KILL cr);
9930
9931 ins_cost(125);
9932 format %{ "blsrq $dst, $src" %}
9933
9934 ins_encode %{
9935 __ blsrq($dst$$Register, $src$$Address);
9936 %}
9937
9938 ins_pipe(ialu_reg);
9939 %}
9940
9941 // Or Instructions
9942 // Or Register with Register
9943 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9944 %{
9945 match(Set dst (OrL dst src));
9946 effect(KILL cr);
9947
9948 format %{ "orq $dst, $src\t# long" %}
9949 opcode(0x0B);
9950 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9951 ins_pipe(ialu_reg_reg);
9952 %}
9953
9954 // Use any_RegP to match R15 (TLS register) without spilling.
9955 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9956 match(Set dst (OrL dst (CastP2X src)));
9957 effect(KILL cr);
9958
9959 format %{ "orq $dst, $src\t# long" %}
9960 opcode(0x0B);
9961 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9962 ins_pipe(ialu_reg_reg);
9963 %}
9964
9965
9966 // Or Register with Immediate
9967 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9968 %{
9969 match(Set dst (OrL dst src));
9970 effect(KILL cr);
9971
9972 format %{ "orq $dst, $src\t# long" %}
9973 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9974 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9975 ins_pipe(ialu_reg);
9976 %}
9977
9978 // Or Register with Memory
9979 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9980 %{
9981 match(Set dst (OrL dst (LoadL src)));
9982 effect(KILL cr);
9983
9984 ins_cost(125);
9985 format %{ "orq $dst, $src\t# long" %}
9986 opcode(0x0B);
9987 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9988 ins_pipe(ialu_reg_mem);
9989 %}
9990
9991 // Or Memory with Register
9992 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9993 %{
9994 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9995 effect(KILL cr);
9996
9997 ins_cost(150);
9998 format %{ "orq $dst, $src\t# long" %}
9999 opcode(0x09); /* Opcode 09 /r */
10000 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10001 ins_pipe(ialu_mem_reg);
10002 %}
10003
10004 // Or Memory with Immediate
10005 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10006 %{
10007 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10008 effect(KILL cr);
10009
10010 ins_cost(125);
10011 format %{ "orq $dst, $src\t# long" %}
10012 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10013 ins_encode(REX_mem_wide(dst), OpcSE(src),
10014 RM_opc_mem(secondary, dst), Con8or32(src));
10015 ins_pipe(ialu_mem_imm);
10016 %}
10017
10018 // Xor Instructions
10019 // Xor Register with Register
10020 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10021 %{
10022 match(Set dst (XorL dst src));
10023 effect(KILL cr);
10024
10025 format %{ "xorq $dst, $src\t# long" %}
10026 opcode(0x33);
10027 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10028 ins_pipe(ialu_reg_reg);
10029 %}
10030
10031 // Xor Register with Immediate -1
10032 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10033 match(Set dst (XorL dst imm));
10034
10035 format %{ "notq $dst" %}
10036 ins_encode %{
10037 __ notq($dst$$Register);
10038 %}
10039 ins_pipe(ialu_reg);
10040 %}
10041
10042 // Xor Register with Immediate
10043 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10044 %{
10045 match(Set dst (XorL dst src));
10046 effect(KILL cr);
10047
10048 format %{ "xorq $dst, $src\t# long" %}
10049 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10050 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10051 ins_pipe(ialu_reg);
10052 %}
10053
10054 // Xor Register with Memory
10055 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10056 %{
10057 match(Set dst (XorL dst (LoadL src)));
10058 effect(KILL cr);
10059
10060 ins_cost(125);
10061 format %{ "xorq $dst, $src\t# long" %}
10062 opcode(0x33);
10063 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10064 ins_pipe(ialu_reg_mem);
10065 %}
10066
10067 // Xor Memory with Register
10068 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10069 %{
10070 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10071 effect(KILL cr);
10072
10073 ins_cost(150);
10074 format %{ "xorq $dst, $src\t# long" %}
10075 opcode(0x31); /* Opcode 31 /r */
10076 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10077 ins_pipe(ialu_mem_reg);
10078 %}
10079
10080 // Xor Memory with Immediate
10081 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10082 %{
10083 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10084 effect(KILL cr);
10085
10086 ins_cost(125);
10087 format %{ "xorq $dst, $src\t# long" %}
10088 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10089 ins_encode(REX_mem_wide(dst), OpcSE(src),
10090 RM_opc_mem(secondary, dst), Con8or32(src));
10091 ins_pipe(ialu_mem_imm);
10092 %}
10093
10094 // Convert Int to Boolean
10095 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10096 %{
10097 match(Set dst (Conv2B src));
10098 effect(KILL cr);
10099
10100 format %{ "testl $src, $src\t# ci2b\n\t"
10101 "setnz $dst\n\t"
10102 "movzbl $dst, $dst" %}
10103 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10104 setNZ_reg(dst),
10105 REX_reg_breg(dst, dst), // movzbl
10106 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10107 ins_pipe(pipe_slow); // XXX
10108 %}
10109
10110 // Convert Pointer to Boolean
10111 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10112 %{
10113 match(Set dst (Conv2B src));
10114 effect(KILL cr);
10115
10116 format %{ "testq $src, $src\t# cp2b\n\t"
10117 "setnz $dst\n\t"
10118 "movzbl $dst, $dst" %}
10119 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10120 setNZ_reg(dst),
10121 REX_reg_breg(dst, dst), // movzbl
10122 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10123 ins_pipe(pipe_slow); // XXX
10124 %}
10125
10126 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10127 %{
10128 match(Set dst (CmpLTMask p q));
10129 effect(KILL cr);
10130
10131 ins_cost(400);
10132 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10133 "setlt $dst\n\t"
10134 "movzbl $dst, $dst\n\t"
10135 "negl $dst" %}
10136 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10137 setLT_reg(dst),
10138 REX_reg_breg(dst, dst), // movzbl
10139 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10140 neg_reg(dst));
10141 ins_pipe(pipe_slow);
10142 %}
10143
10144 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10145 %{
10146 match(Set dst (CmpLTMask dst zero));
10147 effect(KILL cr);
10148
10149 ins_cost(100);
10150 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10151 ins_encode %{
10152 __ sarl($dst$$Register, 31);
10153 %}
10154 ins_pipe(ialu_reg);
10155 %}
10156
10157 /* Better to save a register than avoid a branch */
10158 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10159 %{
10160 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10161 effect(KILL cr);
10162 ins_cost(300);
10163 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10164 "jge done\n\t"
10165 "addl $p,$y\n"
10166 "done: " %}
10167 ins_encode %{
10168 Register Rp = $p$$Register;
10169 Register Rq = $q$$Register;
10170 Register Ry = $y$$Register;
10171 Label done;
10172 __ subl(Rp, Rq);
10173 __ jccb(Assembler::greaterEqual, done);
10174 __ addl(Rp, Ry);
10175 __ bind(done);
10176 %}
10177 ins_pipe(pipe_cmplt);
10178 %}
10179
10180 /* Better to save a register than avoid a branch */
10181 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10182 %{
10183 match(Set y (AndI (CmpLTMask p q) y));
10184 effect(KILL cr);
10185
10186 ins_cost(300);
10187
10188 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10189 "jlt done\n\t"
10190 "xorl $y, $y\n"
10191 "done: " %}
10192 ins_encode %{
10193 Register Rp = $p$$Register;
10194 Register Rq = $q$$Register;
10195 Register Ry = $y$$Register;
10196 Label done;
10197 __ cmpl(Rp, Rq);
10198 __ jccb(Assembler::less, done);
10199 __ xorl(Ry, Ry);
10200 __ bind(done);
10201 %}
10202 ins_pipe(pipe_cmplt);
10203 %}
10204
10205
10206 //---------- FP Instructions------------------------------------------------
10207
10208 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10209 %{
10210 match(Set cr (CmpF src1 src2));
10211
10212 ins_cost(145);
10213 format %{ "ucomiss $src1, $src2\n\t"
10214 "jnp,s exit\n\t"
10215 "pushfq\t# saw NaN, set CF\n\t"
10216 "andq [rsp], #0xffffff2b\n\t"
10217 "popfq\n"
10218 "exit:" %}
10219 ins_encode %{
10220 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10221 emit_cmpfp_fixup(_masm);
10222 %}
10223 ins_pipe(pipe_slow);
10224 %}
10225
10226 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10227 match(Set cr (CmpF src1 src2));
10228
10229 ins_cost(100);
10230 format %{ "ucomiss $src1, $src2" %}
10231 ins_encode %{
10232 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10233 %}
10234 ins_pipe(pipe_slow);
10235 %}
10236
10237 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10238 %{
10239 match(Set cr (CmpF src1 (LoadF src2)));
10240
10241 ins_cost(145);
10242 format %{ "ucomiss $src1, $src2\n\t"
10243 "jnp,s exit\n\t"
10244 "pushfq\t# saw NaN, set CF\n\t"
10245 "andq [rsp], #0xffffff2b\n\t"
10246 "popfq\n"
10247 "exit:" %}
10248 ins_encode %{
10249 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10250 emit_cmpfp_fixup(_masm);
10251 %}
10252 ins_pipe(pipe_slow);
10253 %}
10254
10255 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10256 match(Set cr (CmpF src1 (LoadF src2)));
10257
10258 ins_cost(100);
10259 format %{ "ucomiss $src1, $src2" %}
10260 ins_encode %{
10261 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10262 %}
10263 ins_pipe(pipe_slow);
10264 %}
10265
10266 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10267 match(Set cr (CmpF src con));
10268
10269 ins_cost(145);
10270 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10271 "jnp,s exit\n\t"
10272 "pushfq\t# saw NaN, set CF\n\t"
10273 "andq [rsp], #0xffffff2b\n\t"
10274 "popfq\n"
10275 "exit:" %}
10276 ins_encode %{
10277 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10278 emit_cmpfp_fixup(_masm);
10279 %}
10280 ins_pipe(pipe_slow);
10281 %}
10282
10283 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10284 match(Set cr (CmpF src con));
10285 ins_cost(100);
10286 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10287 ins_encode %{
10288 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10289 %}
10290 ins_pipe(pipe_slow);
10291 %}
10292
10293 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10294 %{
10295 match(Set cr (CmpD src1 src2));
10296
10297 ins_cost(145);
10298 format %{ "ucomisd $src1, $src2\n\t"
10299 "jnp,s exit\n\t"
10300 "pushfq\t# saw NaN, set CF\n\t"
10301 "andq [rsp], #0xffffff2b\n\t"
10302 "popfq\n"
10303 "exit:" %}
10304 ins_encode %{
10305 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10306 emit_cmpfp_fixup(_masm);
10307 %}
10308 ins_pipe(pipe_slow);
10309 %}
10310
10311 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10312 match(Set cr (CmpD src1 src2));
10313
10314 ins_cost(100);
10315 format %{ "ucomisd $src1, $src2 test" %}
10316 ins_encode %{
10317 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10318 %}
10319 ins_pipe(pipe_slow);
10320 %}
10321
10322 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10323 %{
10324 match(Set cr (CmpD src1 (LoadD src2)));
10325
10326 ins_cost(145);
10327 format %{ "ucomisd $src1, $src2\n\t"
10328 "jnp,s exit\n\t"
10329 "pushfq\t# saw NaN, set CF\n\t"
10330 "andq [rsp], #0xffffff2b\n\t"
10331 "popfq\n"
10332 "exit:" %}
10333 ins_encode %{
10334 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10335 emit_cmpfp_fixup(_masm);
10336 %}
10337 ins_pipe(pipe_slow);
10338 %}
10339
10340 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10341 match(Set cr (CmpD src1 (LoadD src2)));
10342
10343 ins_cost(100);
10344 format %{ "ucomisd $src1, $src2" %}
10345 ins_encode %{
10346 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10347 %}
10348 ins_pipe(pipe_slow);
10349 %}
10350
10351 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10352 match(Set cr (CmpD src con));
10353
10354 ins_cost(145);
10355 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10356 "jnp,s exit\n\t"
10357 "pushfq\t# saw NaN, set CF\n\t"
10358 "andq [rsp], #0xffffff2b\n\t"
10359 "popfq\n"
10360 "exit:" %}
10361 ins_encode %{
10362 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10363 emit_cmpfp_fixup(_masm);
10364 %}
10365 ins_pipe(pipe_slow);
10366 %}
10367
10368 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10369 match(Set cr (CmpD src con));
10370 ins_cost(100);
10371 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10372 ins_encode %{
10373 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10374 %}
10375 ins_pipe(pipe_slow);
10376 %}
10377
10378 // Compare into -1,0,1
10379 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10380 %{
10381 match(Set dst (CmpF3 src1 src2));
10382 effect(KILL cr);
10383
10384 ins_cost(275);
10385 format %{ "ucomiss $src1, $src2\n\t"
10386 "movl $dst, #-1\n\t"
10387 "jp,s done\n\t"
10388 "jb,s done\n\t"
10389 "setne $dst\n\t"
10390 "movzbl $dst, $dst\n"
10391 "done:" %}
10392 ins_encode %{
10393 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10394 emit_cmpfp3(_masm, $dst$$Register);
10395 %}
10396 ins_pipe(pipe_slow);
10397 %}
10398
10399 // Compare into -1,0,1
10400 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10401 %{
10402 match(Set dst (CmpF3 src1 (LoadF src2)));
10403 effect(KILL cr);
10404
10405 ins_cost(275);
10406 format %{ "ucomiss $src1, $src2\n\t"
10407 "movl $dst, #-1\n\t"
10408 "jp,s done\n\t"
10409 "jb,s done\n\t"
10410 "setne $dst\n\t"
10411 "movzbl $dst, $dst\n"
10412 "done:" %}
10413 ins_encode %{
10414 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10415 emit_cmpfp3(_masm, $dst$$Register);
10416 %}
10417 ins_pipe(pipe_slow);
10418 %}
10419
10420 // Compare into -1,0,1
10421 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10422 match(Set dst (CmpF3 src con));
10423 effect(KILL cr);
10424
10425 ins_cost(275);
10426 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10427 "movl $dst, #-1\n\t"
10428 "jp,s done\n\t"
10429 "jb,s done\n\t"
10430 "setne $dst\n\t"
10431 "movzbl $dst, $dst\n"
10432 "done:" %}
10433 ins_encode %{
10434 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10435 emit_cmpfp3(_masm, $dst$$Register);
10436 %}
10437 ins_pipe(pipe_slow);
10438 %}
10439
10440 // Compare into -1,0,1
10441 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10442 %{
10443 match(Set dst (CmpD3 src1 src2));
10444 effect(KILL cr);
10445
10446 ins_cost(275);
10447 format %{ "ucomisd $src1, $src2\n\t"
10448 "movl $dst, #-1\n\t"
10449 "jp,s done\n\t"
10450 "jb,s done\n\t"
10451 "setne $dst\n\t"
10452 "movzbl $dst, $dst\n"
10453 "done:" %}
10454 ins_encode %{
10455 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10456 emit_cmpfp3(_masm, $dst$$Register);
10457 %}
10458 ins_pipe(pipe_slow);
10459 %}
10460
10461 // Compare into -1,0,1
10462 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10463 %{
10464 match(Set dst (CmpD3 src1 (LoadD src2)));
10465 effect(KILL cr);
10466
10467 ins_cost(275);
10468 format %{ "ucomisd $src1, $src2\n\t"
10469 "movl $dst, #-1\n\t"
10470 "jp,s done\n\t"
10471 "jb,s done\n\t"
10472 "setne $dst\n\t"
10473 "movzbl $dst, $dst\n"
10474 "done:" %}
10475 ins_encode %{
10476 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10477 emit_cmpfp3(_masm, $dst$$Register);
10478 %}
10479 ins_pipe(pipe_slow);
10480 %}
10481
10482 // Compare into -1,0,1
10483 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10484 match(Set dst (CmpD3 src con));
10485 effect(KILL cr);
10486
10487 ins_cost(275);
10488 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10489 "movl $dst, #-1\n\t"
10490 "jp,s done\n\t"
10491 "jb,s done\n\t"
10492 "setne $dst\n\t"
10493 "movzbl $dst, $dst\n"
10494 "done:" %}
10495 ins_encode %{
10496 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10497 emit_cmpfp3(_masm, $dst$$Register);
10498 %}
10499 ins_pipe(pipe_slow);
10500 %}
10501
10502 //----------Arithmetic Conversion Instructions---------------------------------
10503
10504 instruct roundFloat_nop(regF dst)
10505 %{
10506 match(Set dst (RoundFloat dst));
10507
10508 ins_cost(0);
10509 ins_encode();
10510 ins_pipe(empty);
10511 %}
10512
10513 instruct roundDouble_nop(regD dst)
10514 %{
10515 match(Set dst (RoundDouble dst));
10516
10517 ins_cost(0);
10518 ins_encode();
10519 ins_pipe(empty);
10520 %}
10521
10522 instruct convF2D_reg_reg(regD dst, regF src)
10523 %{
10524 match(Set dst (ConvF2D src));
10525
10526 format %{ "cvtss2sd $dst, $src" %}
10527 ins_encode %{
10528 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10529 %}
10530 ins_pipe(pipe_slow); // XXX
10531 %}
10532
10533 instruct convF2D_reg_mem(regD dst, memory src)
10534 %{
10535 match(Set dst (ConvF2D (LoadF src)));
10536
10537 format %{ "cvtss2sd $dst, $src" %}
10538 ins_encode %{
10539 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10540 %}
10541 ins_pipe(pipe_slow); // XXX
10542 %}
10543
10544 instruct convD2F_reg_reg(regF dst, regD src)
10545 %{
10546 match(Set dst (ConvD2F src));
10547
10548 format %{ "cvtsd2ss $dst, $src" %}
10549 ins_encode %{
10550 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10551 %}
10552 ins_pipe(pipe_slow); // XXX
10553 %}
10554
10555 instruct convD2F_reg_mem(regF dst, memory src)
10556 %{
10557 match(Set dst (ConvD2F (LoadD src)));
10558
10559 format %{ "cvtsd2ss $dst, $src" %}
10560 ins_encode %{
10561 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10562 %}
10563 ins_pipe(pipe_slow); // XXX
10564 %}
10565
10566 // XXX do mem variants
10567 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10568 %{
10569 match(Set dst (ConvF2I src));
10570 effect(KILL cr);
10571
10572 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10573 "cmpl $dst, #0x80000000\n\t"
10574 "jne,s done\n\t"
10575 "subq rsp, #8\n\t"
10576 "movss [rsp], $src\n\t"
10577 "call f2i_fixup\n\t"
10578 "popq $dst\n"
10579 "done: "%}
10580 ins_encode %{
10581 Label done;
10582 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10583 __ cmpl($dst$$Register, 0x80000000);
10584 __ jccb(Assembler::notEqual, done);
10585 __ subptr(rsp, 8);
10586 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10587 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10588 __ pop($dst$$Register);
10589 __ bind(done);
10590 %}
10591 ins_pipe(pipe_slow);
10592 %}
10593
10594 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10595 %{
10596 match(Set dst (ConvF2L src));
10597 effect(KILL cr);
10598
10599 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10600 "cmpq $dst, [0x8000000000000000]\n\t"
10601 "jne,s done\n\t"
10602 "subq rsp, #8\n\t"
10603 "movss [rsp], $src\n\t"
10604 "call f2l_fixup\n\t"
10605 "popq $dst\n"
10606 "done: "%}
10607 ins_encode %{
10608 Label done;
10609 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10610 __ cmp64($dst$$Register,
10611 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10612 __ jccb(Assembler::notEqual, done);
10613 __ subptr(rsp, 8);
10614 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10615 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10616 __ pop($dst$$Register);
10617 __ bind(done);
10618 %}
10619 ins_pipe(pipe_slow);
10620 %}
10621
10622 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10623 %{
10624 match(Set dst (ConvD2I src));
10625 effect(KILL cr);
10626
10627 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10628 "cmpl $dst, #0x80000000\n\t"
10629 "jne,s done\n\t"
10630 "subq rsp, #8\n\t"
10631 "movsd [rsp], $src\n\t"
10632 "call d2i_fixup\n\t"
10633 "popq $dst\n"
10634 "done: "%}
10635 ins_encode %{
10636 Label done;
10637 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10638 __ cmpl($dst$$Register, 0x80000000);
10639 __ jccb(Assembler::notEqual, done);
10640 __ subptr(rsp, 8);
10641 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10642 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10643 __ pop($dst$$Register);
10644 __ bind(done);
10645 %}
10646 ins_pipe(pipe_slow);
10647 %}
10648
10649 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10650 %{
10651 match(Set dst (ConvD2L src));
10652 effect(KILL cr);
10653
10654 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10655 "cmpq $dst, [0x8000000000000000]\n\t"
10656 "jne,s done\n\t"
10657 "subq rsp, #8\n\t"
10658 "movsd [rsp], $src\n\t"
10659 "call d2l_fixup\n\t"
10660 "popq $dst\n"
10661 "done: "%}
10662 ins_encode %{
10663 Label done;
10664 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10665 __ cmp64($dst$$Register,
10666 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10667 __ jccb(Assembler::notEqual, done);
10668 __ subptr(rsp, 8);
10669 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10670 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10671 __ pop($dst$$Register);
10672 __ bind(done);
10673 %}
10674 ins_pipe(pipe_slow);
10675 %}
10676
10677 instruct convI2F_reg_reg(regF dst, rRegI src)
10678 %{
10679 predicate(!UseXmmI2F);
10680 match(Set dst (ConvI2F src));
10681
10682 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10683 ins_encode %{
10684 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10685 %}
10686 ins_pipe(pipe_slow); // XXX
10687 %}
10688
10689 instruct convI2F_reg_mem(regF dst, memory src)
10690 %{
10691 match(Set dst (ConvI2F (LoadI src)));
10692
10693 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10694 ins_encode %{
10695 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10696 %}
10697 ins_pipe(pipe_slow); // XXX
10698 %}
10699
10700 instruct convI2D_reg_reg(regD dst, rRegI src)
10701 %{
10702 predicate(!UseXmmI2D);
10703 match(Set dst (ConvI2D src));
10704
10705 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10706 ins_encode %{
10707 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10708 %}
10709 ins_pipe(pipe_slow); // XXX
10710 %}
10711
10712 instruct convI2D_reg_mem(regD dst, memory src)
10713 %{
10714 match(Set dst (ConvI2D (LoadI src)));
10715
10716 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10717 ins_encode %{
10718 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10719 %}
10720 ins_pipe(pipe_slow); // XXX
10721 %}
10722
10723 instruct convXI2F_reg(regF dst, rRegI src)
10724 %{
10725 predicate(UseXmmI2F);
10726 match(Set dst (ConvI2F src));
10727
10728 format %{ "movdl $dst, $src\n\t"
10729 "cvtdq2psl $dst, $dst\t# i2f" %}
10730 ins_encode %{
10731 __ movdl($dst$$XMMRegister, $src$$Register);
10732 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10733 %}
10734 ins_pipe(pipe_slow); // XXX
10735 %}
10736
10737 instruct convXI2D_reg(regD dst, rRegI src)
10738 %{
10739 predicate(UseXmmI2D);
10740 match(Set dst (ConvI2D src));
10741
10742 format %{ "movdl $dst, $src\n\t"
10743 "cvtdq2pdl $dst, $dst\t# i2d" %}
10744 ins_encode %{
10745 __ movdl($dst$$XMMRegister, $src$$Register);
10746 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10747 %}
10748 ins_pipe(pipe_slow); // XXX
10749 %}
10750
10751 instruct convL2F_reg_reg(regF dst, rRegL src)
10752 %{
10753 match(Set dst (ConvL2F src));
10754
10755 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10756 ins_encode %{
10757 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10758 %}
10759 ins_pipe(pipe_slow); // XXX
10760 %}
10761
10762 instruct convL2F_reg_mem(regF dst, memory src)
10763 %{
10764 match(Set dst (ConvL2F (LoadL src)));
10765
10766 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10767 ins_encode %{
10768 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10769 %}
10770 ins_pipe(pipe_slow); // XXX
10771 %}
10772
10773 instruct convL2D_reg_reg(regD dst, rRegL src)
10774 %{
10775 match(Set dst (ConvL2D src));
10776
10777 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10778 ins_encode %{
10779 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10780 %}
10781 ins_pipe(pipe_slow); // XXX
10782 %}
10783
10784 instruct convL2D_reg_mem(regD dst, memory src)
10785 %{
10786 match(Set dst (ConvL2D (LoadL src)));
10787
10788 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10789 ins_encode %{
10790 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10791 %}
10792 ins_pipe(pipe_slow); // XXX
10793 %}
10794
10795 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10796 %{
10797 match(Set dst (ConvI2L src));
10798
10799 ins_cost(125);
10800 format %{ "movslq $dst, $src\t# i2l" %}
10801 ins_encode %{
10802 __ movslq($dst$$Register, $src$$Register);
10803 %}
10804 ins_pipe(ialu_reg_reg);
10805 %}
10806
10807 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10808 // %{
10809 // match(Set dst (ConvI2L src));
10810 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10811 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10812 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10813 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10814 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10815 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10816
10817 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10818 // ins_encode(enc_copy(dst, src));
10819 // // opcode(0x63); // needs REX.W
10820 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10821 // ins_pipe(ialu_reg_reg);
10822 // %}
10823
10824 // Zero-extend convert int to long
10825 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10826 %{
10827 match(Set dst (AndL (ConvI2L src) mask));
10828
10829 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10830 ins_encode %{
10831 if ($dst$$reg != $src$$reg) {
10832 __ movl($dst$$Register, $src$$Register);
10833 }
10834 %}
10835 ins_pipe(ialu_reg_reg);
10836 %}
10837
10838 // Zero-extend convert int to long
10839 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10840 %{
10841 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10842
10843 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10844 ins_encode %{
10845 __ movl($dst$$Register, $src$$Address);
10846 %}
10847 ins_pipe(ialu_reg_mem);
10848 %}
10849
10850 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10851 %{
10852 match(Set dst (AndL src mask));
10853
10854 format %{ "movl $dst, $src\t# zero-extend long" %}
10855 ins_encode %{
10856 __ movl($dst$$Register, $src$$Register);
10857 %}
10858 ins_pipe(ialu_reg_reg);
10859 %}
10860
10861 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10862 %{
10863 match(Set dst (ConvL2I src));
10864
10865 format %{ "movl $dst, $src\t# l2i" %}
10866 ins_encode %{
10867 __ movl($dst$$Register, $src$$Register);
10868 %}
10869 ins_pipe(ialu_reg_reg);
10870 %}
10871
10872
10873 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10874 match(Set dst (MoveF2I src));
10875 effect(DEF dst, USE src);
10876
10877 ins_cost(125);
10878 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10879 ins_encode %{
10880 __ movl($dst$$Register, Address(rsp, $src$$disp));
10881 %}
10882 ins_pipe(ialu_reg_mem);
10883 %}
10884
10885 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10886 match(Set dst (MoveI2F src));
10887 effect(DEF dst, USE src);
10888
10889 ins_cost(125);
10890 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10891 ins_encode %{
10892 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10893 %}
10894 ins_pipe(pipe_slow);
10895 %}
10896
10897 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10898 match(Set dst (MoveD2L src));
10899 effect(DEF dst, USE src);
10900
10901 ins_cost(125);
10902 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10903 ins_encode %{
10904 __ movq($dst$$Register, Address(rsp, $src$$disp));
10905 %}
10906 ins_pipe(ialu_reg_mem);
10907 %}
10908
10909 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10910 predicate(!UseXmmLoadAndClearUpper);
10911 match(Set dst (MoveL2D src));
10912 effect(DEF dst, USE src);
10913
10914 ins_cost(125);
10915 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10916 ins_encode %{
10917 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10918 %}
10919 ins_pipe(pipe_slow);
10920 %}
10921
10922 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10923 predicate(UseXmmLoadAndClearUpper);
10924 match(Set dst (MoveL2D src));
10925 effect(DEF dst, USE src);
10926
10927 ins_cost(125);
10928 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10929 ins_encode %{
10930 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10931 %}
10932 ins_pipe(pipe_slow);
10933 %}
10934
10935
10936 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10937 match(Set dst (MoveF2I src));
10938 effect(DEF dst, USE src);
10939
10940 ins_cost(95); // XXX
10941 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10942 ins_encode %{
10943 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10944 %}
10945 ins_pipe(pipe_slow);
10946 %}
10947
10948 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10949 match(Set dst (MoveI2F src));
10950 effect(DEF dst, USE src);
10951
10952 ins_cost(100);
10953 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10954 ins_encode %{
10955 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10956 %}
10957 ins_pipe( ialu_mem_reg );
10958 %}
10959
10960 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10961 match(Set dst (MoveD2L src));
10962 effect(DEF dst, USE src);
10963
10964 ins_cost(95); // XXX
10965 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10966 ins_encode %{
10967 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10968 %}
10969 ins_pipe(pipe_slow);
10970 %}
10971
10972 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10973 match(Set dst (MoveL2D src));
10974 effect(DEF dst, USE src);
10975
10976 ins_cost(100);
10977 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10978 ins_encode %{
10979 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10980 %}
10981 ins_pipe(ialu_mem_reg);
10982 %}
10983
10984 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10985 match(Set dst (MoveF2I src));
10986 effect(DEF dst, USE src);
10987 ins_cost(85);
10988 format %{ "movd $dst,$src\t# MoveF2I" %}
10989 ins_encode %{
10990 __ movdl($dst$$Register, $src$$XMMRegister);
10991 %}
10992 ins_pipe( pipe_slow );
10993 %}
10994
10995 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10996 match(Set dst (MoveD2L src));
10997 effect(DEF dst, USE src);
10998 ins_cost(85);
10999 format %{ "movd $dst,$src\t# MoveD2L" %}
11000 ins_encode %{
11001 __ movdq($dst$$Register, $src$$XMMRegister);
11002 %}
11003 ins_pipe( pipe_slow );
11004 %}
11005
11006 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11007 match(Set dst (MoveI2F src));
11008 effect(DEF dst, USE src);
11009 ins_cost(100);
11010 format %{ "movd $dst,$src\t# MoveI2F" %}
11011 ins_encode %{
11012 __ movdl($dst$$XMMRegister, $src$$Register);
11013 %}
11014 ins_pipe( pipe_slow );
11015 %}
11016
11017 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11018 match(Set dst (MoveL2D src));
11019 effect(DEF dst, USE src);
11020 ins_cost(100);
11021 format %{ "movd $dst,$src\t# MoveL2D" %}
11022 ins_encode %{
11023 __ movdq($dst$$XMMRegister, $src$$Register);
11024 %}
11025 ins_pipe( pipe_slow );
11026 %}
11027
11028
11029 // =======================================================================
11030 // fast clearing of an array
11031 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11032 Universe dummy, rFlagsReg cr)
11033 %{
11034 predicate(!((ClearArrayNode*)n)->is_large());
11035 match(Set dummy (ClearArray cnt base));
11036 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11037
11038 format %{ $$template
11039 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11040 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11041 $$emit$$"jg LARGE\n\t"
11042 $$emit$$"dec rcx\n\t"
11043 $$emit$$"js DONE\t# Zero length\n\t"
11044 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11045 $$emit$$"dec rcx\n\t"
11046 $$emit$$"jge LOOP\n\t"
11047 $$emit$$"jmp DONE\n\t"
11048 $$emit$$"# LARGE:\n\t"
11049 if (UseFastStosb) {
11050 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11051 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11052 } else if (UseXMMForObjInit) {
11053 $$emit$$"mov rdi,rax\n\t"
11054 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11055 $$emit$$"jmpq L_zero_64_bytes\n\t"
11056 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11057 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11058 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11059 $$emit$$"add 0x40,rax\n\t"
11060 $$emit$$"# L_zero_64_bytes:\n\t"
11061 $$emit$$"sub 0x8,rcx\n\t"
11062 $$emit$$"jge L_loop\n\t"
11063 $$emit$$"add 0x4,rcx\n\t"
11064 $$emit$$"jl L_tail\n\t"
11065 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11066 $$emit$$"add 0x20,rax\n\t"
11067 $$emit$$"sub 0x4,rcx\n\t"
11068 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11069 $$emit$$"add 0x4,rcx\n\t"
11070 $$emit$$"jle L_end\n\t"
11071 $$emit$$"dec rcx\n\t"
11072 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11073 $$emit$$"vmovq xmm0,(rax)\n\t"
11074 $$emit$$"add 0x8,rax\n\t"
11075 $$emit$$"dec rcx\n\t"
11076 $$emit$$"jge L_sloop\n\t"
11077 $$emit$$"# L_end:\n\t"
11078 } else {
11079 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11080 }
11081 $$emit$$"# DONE"
11082 %}
11083 ins_encode %{
11084 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11085 $tmp$$XMMRegister, false);
11086 %}
11087 ins_pipe(pipe_slow);
11088 %}
11089
11090 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11091 Universe dummy, rFlagsReg cr)
11092 %{
11093 predicate(((ClearArrayNode*)n)->is_large());
11094 match(Set dummy (ClearArray cnt base));
11095 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11096
11097 format %{ $$template
11098 if (UseFastStosb) {
11099 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11100 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11101 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11102 } else if (UseXMMForObjInit) {
11103 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11104 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11105 $$emit$$"jmpq L_zero_64_bytes\n\t"
11106 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11107 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11108 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11109 $$emit$$"add 0x40,rax\n\t"
11110 $$emit$$"# L_zero_64_bytes:\n\t"
11111 $$emit$$"sub 0x8,rcx\n\t"
11112 $$emit$$"jge L_loop\n\t"
11113 $$emit$$"add 0x4,rcx\n\t"
11114 $$emit$$"jl L_tail\n\t"
11115 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11116 $$emit$$"add 0x20,rax\n\t"
11117 $$emit$$"sub 0x4,rcx\n\t"
11118 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11119 $$emit$$"add 0x4,rcx\n\t"
11120 $$emit$$"jle L_end\n\t"
11121 $$emit$$"dec rcx\n\t"
11122 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11123 $$emit$$"vmovq xmm0,(rax)\n\t"
11124 $$emit$$"add 0x8,rax\n\t"
11125 $$emit$$"dec rcx\n\t"
11126 $$emit$$"jge L_sloop\n\t"
11127 $$emit$$"# L_end:\n\t"
11128 } else {
11129 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11130 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11131 }
11132 %}
11133 ins_encode %{
11134 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11135 $tmp$$XMMRegister, true);
11136 %}
11137 ins_pipe(pipe_slow);
11138 %}
11139
11140 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11141 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11142 %{
11143 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11144 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11145 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11146
11147 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11148 ins_encode %{
11149 __ string_compare($str1$$Register, $str2$$Register,
11150 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11151 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11152 %}
11153 ins_pipe( pipe_slow );
11154 %}
11155
11156 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11157 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11158 %{
11159 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11160 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11161 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11162
11163 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11164 ins_encode %{
11165 __ string_compare($str1$$Register, $str2$$Register,
11166 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11167 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11168 %}
11169 ins_pipe( pipe_slow );
11170 %}
11171
11172 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11173 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11174 %{
11175 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11176 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11177 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11178
11179 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11180 ins_encode %{
11181 __ string_compare($str1$$Register, $str2$$Register,
11182 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11183 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11184 %}
11185 ins_pipe( pipe_slow );
11186 %}
11187
11188 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11189 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11190 %{
11191 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11192 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11193 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11194
11195 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11196 ins_encode %{
11197 __ string_compare($str2$$Register, $str1$$Register,
11198 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11199 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11200 %}
11201 ins_pipe( pipe_slow );
11202 %}
11203
11204 // fast search of substring with known size.
11205 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11206 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11207 %{
11208 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11209 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11210 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11211
11212 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11213 ins_encode %{
11214 int icnt2 = (int)$int_cnt2$$constant;
11215 if (icnt2 >= 16) {
11216 // IndexOf for constant substrings with size >= 16 elements
11217 // which don't need to be loaded through stack.
11218 __ string_indexofC8($str1$$Register, $str2$$Register,
11219 $cnt1$$Register, $cnt2$$Register,
11220 icnt2, $result$$Register,
11221 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11222 } else {
11223 // Small strings are loaded through stack if they cross page boundary.
11224 __ string_indexof($str1$$Register, $str2$$Register,
11225 $cnt1$$Register, $cnt2$$Register,
11226 icnt2, $result$$Register,
11227 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11228 }
11229 %}
11230 ins_pipe( pipe_slow );
11231 %}
11232
11233 // fast search of substring with known size.
11234 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11235 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11236 %{
11237 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11238 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11239 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11240
11241 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11242 ins_encode %{
11243 int icnt2 = (int)$int_cnt2$$constant;
11244 if (icnt2 >= 8) {
11245 // IndexOf for constant substrings with size >= 8 elements
11246 // which don't need to be loaded through stack.
11247 __ string_indexofC8($str1$$Register, $str2$$Register,
11248 $cnt1$$Register, $cnt2$$Register,
11249 icnt2, $result$$Register,
11250 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11251 } else {
11252 // Small strings are loaded through stack if they cross page boundary.
11253 __ string_indexof($str1$$Register, $str2$$Register,
11254 $cnt1$$Register, $cnt2$$Register,
11255 icnt2, $result$$Register,
11256 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11257 }
11258 %}
11259 ins_pipe( pipe_slow );
11260 %}
11261
11262 // fast search of substring with known size.
11263 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11264 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11265 %{
11266 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11267 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11268 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11269
11270 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11271 ins_encode %{
11272 int icnt2 = (int)$int_cnt2$$constant;
11273 if (icnt2 >= 8) {
11274 // IndexOf for constant substrings with size >= 8 elements
11275 // which don't need to be loaded through stack.
11276 __ string_indexofC8($str1$$Register, $str2$$Register,
11277 $cnt1$$Register, $cnt2$$Register,
11278 icnt2, $result$$Register,
11279 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11280 } else {
11281 // Small strings are loaded through stack if they cross page boundary.
11282 __ string_indexof($str1$$Register, $str2$$Register,
11283 $cnt1$$Register, $cnt2$$Register,
11284 icnt2, $result$$Register,
11285 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11286 }
11287 %}
11288 ins_pipe( pipe_slow );
11289 %}
11290
11291 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11292 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11293 %{
11294 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11295 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11296 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11297
11298 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11299 ins_encode %{
11300 __ string_indexof($str1$$Register, $str2$$Register,
11301 $cnt1$$Register, $cnt2$$Register,
11302 (-1), $result$$Register,
11303 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11304 %}
11305 ins_pipe( pipe_slow );
11306 %}
11307
11308 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11309 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11310 %{
11311 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11312 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11313 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11314
11315 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11316 ins_encode %{
11317 __ string_indexof($str1$$Register, $str2$$Register,
11318 $cnt1$$Register, $cnt2$$Register,
11319 (-1), $result$$Register,
11320 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11321 %}
11322 ins_pipe( pipe_slow );
11323 %}
11324
11325 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11326 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11327 %{
11328 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11329 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11330 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11331
11332 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11333 ins_encode %{
11334 __ string_indexof($str1$$Register, $str2$$Register,
11335 $cnt1$$Register, $cnt2$$Register,
11336 (-1), $result$$Register,
11337 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11338 %}
11339 ins_pipe( pipe_slow );
11340 %}
11341
11342 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11343 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11344 %{
11345 predicate(UseSSE42Intrinsics);
11346 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11347 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11348 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11349 ins_encode %{
11350 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11351 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11352 %}
11353 ins_pipe( pipe_slow );
11354 %}
11355
11356 // fast string equals
11357 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11358 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11359 %{
11360 match(Set result (StrEquals (Binary str1 str2) cnt));
11361 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11362
11363 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11364 ins_encode %{
11365 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11366 $cnt$$Register, $result$$Register, $tmp3$$Register,
11367 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11368 %}
11369 ins_pipe( pipe_slow );
11370 %}
11371
11372 // fast array equals
11373 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11374 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11375 %{
11376 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11377 match(Set result (AryEq ary1 ary2));
11378 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11379
11380 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11381 ins_encode %{
11382 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11383 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11384 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11385 %}
11386 ins_pipe( pipe_slow );
11387 %}
11388
11389 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11390 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11391 %{
11392 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11393 match(Set result (AryEq ary1 ary2));
11394 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11395
11396 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11397 ins_encode %{
11398 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11399 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11400 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11401 %}
11402 ins_pipe( pipe_slow );
11403 %}
11404
11405 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11406 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11407 %{
11408 match(Set result (HasNegatives ary1 len));
11409 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11410
11411 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11412 ins_encode %{
11413 __ has_negatives($ary1$$Register, $len$$Register,
11414 $result$$Register, $tmp3$$Register,
11415 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11416 %}
11417 ins_pipe( pipe_slow );
11418 %}
11419
11420 // fast char[] to byte[] compression
11421 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11422 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11423 match(Set result (StrCompressedCopy src (Binary dst len)));
11424 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11425
11426 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11427 ins_encode %{
11428 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11429 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11430 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11431 %}
11432 ins_pipe( pipe_slow );
11433 %}
11434
11435 // fast byte[] to char[] inflation
11436 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11437 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11438 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11439 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11440
11441 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11442 ins_encode %{
11443 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11444 $tmp1$$XMMRegister, $tmp2$$Register);
11445 %}
11446 ins_pipe( pipe_slow );
11447 %}
11448
11449 // encode char[] to byte[] in ISO_8859_1
11450 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11451 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11452 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11453 match(Set result (EncodeISOArray src (Binary dst len)));
11454 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11455
11456 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11457 ins_encode %{
11458 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11459 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11460 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11461 %}
11462 ins_pipe( pipe_slow );
11463 %}
11464
11465 //----------Overflow Math Instructions-----------------------------------------
11466
11467 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11468 %{
11469 match(Set cr (OverflowAddI op1 op2));
11470 effect(DEF cr, USE_KILL op1, USE op2);
11471
11472 format %{ "addl $op1, $op2\t# overflow check int" %}
11473
11474 ins_encode %{
11475 __ addl($op1$$Register, $op2$$Register);
11476 %}
11477 ins_pipe(ialu_reg_reg);
11478 %}
11479
11480 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11481 %{
11482 match(Set cr (OverflowAddI op1 op2));
11483 effect(DEF cr, USE_KILL op1, USE op2);
11484
11485 format %{ "addl $op1, $op2\t# overflow check int" %}
11486
11487 ins_encode %{
11488 __ addl($op1$$Register, $op2$$constant);
11489 %}
11490 ins_pipe(ialu_reg_reg);
11491 %}
11492
11493 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11494 %{
11495 match(Set cr (OverflowAddL op1 op2));
11496 effect(DEF cr, USE_KILL op1, USE op2);
11497
11498 format %{ "addq $op1, $op2\t# overflow check long" %}
11499 ins_encode %{
11500 __ addq($op1$$Register, $op2$$Register);
11501 %}
11502 ins_pipe(ialu_reg_reg);
11503 %}
11504
11505 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11506 %{
11507 match(Set cr (OverflowAddL op1 op2));
11508 effect(DEF cr, USE_KILL op1, USE op2);
11509
11510 format %{ "addq $op1, $op2\t# overflow check long" %}
11511 ins_encode %{
11512 __ addq($op1$$Register, $op2$$constant);
11513 %}
11514 ins_pipe(ialu_reg_reg);
11515 %}
11516
11517 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11518 %{
11519 match(Set cr (OverflowSubI op1 op2));
11520
11521 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11522 ins_encode %{
11523 __ cmpl($op1$$Register, $op2$$Register);
11524 %}
11525 ins_pipe(ialu_reg_reg);
11526 %}
11527
11528 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11529 %{
11530 match(Set cr (OverflowSubI op1 op2));
11531
11532 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11533 ins_encode %{
11534 __ cmpl($op1$$Register, $op2$$constant);
11535 %}
11536 ins_pipe(ialu_reg_reg);
11537 %}
11538
11539 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11540 %{
11541 match(Set cr (OverflowSubL op1 op2));
11542
11543 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11544 ins_encode %{
11545 __ cmpq($op1$$Register, $op2$$Register);
11546 %}
11547 ins_pipe(ialu_reg_reg);
11548 %}
11549
11550 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11551 %{
11552 match(Set cr (OverflowSubL op1 op2));
11553
11554 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11555 ins_encode %{
11556 __ cmpq($op1$$Register, $op2$$constant);
11557 %}
11558 ins_pipe(ialu_reg_reg);
11559 %}
11560
11561 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11562 %{
11563 match(Set cr (OverflowSubI zero op2));
11564 effect(DEF cr, USE_KILL op2);
11565
11566 format %{ "negl $op2\t# overflow check int" %}
11567 ins_encode %{
11568 __ negl($op2$$Register);
11569 %}
11570 ins_pipe(ialu_reg_reg);
11571 %}
11572
11573 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11574 %{
11575 match(Set cr (OverflowSubL zero op2));
11576 effect(DEF cr, USE_KILL op2);
11577
11578 format %{ "negq $op2\t# overflow check long" %}
11579 ins_encode %{
11580 __ negq($op2$$Register);
11581 %}
11582 ins_pipe(ialu_reg_reg);
11583 %}
11584
11585 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11586 %{
11587 match(Set cr (OverflowMulI op1 op2));
11588 effect(DEF cr, USE_KILL op1, USE op2);
11589
11590 format %{ "imull $op1, $op2\t# overflow check int" %}
11591 ins_encode %{
11592 __ imull($op1$$Register, $op2$$Register);
11593 %}
11594 ins_pipe(ialu_reg_reg_alu0);
11595 %}
11596
11597 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11598 %{
11599 match(Set cr (OverflowMulI op1 op2));
11600 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11601
11602 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11603 ins_encode %{
11604 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11605 %}
11606 ins_pipe(ialu_reg_reg_alu0);
11607 %}
11608
11609 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11610 %{
11611 match(Set cr (OverflowMulL op1 op2));
11612 effect(DEF cr, USE_KILL op1, USE op2);
11613
11614 format %{ "imulq $op1, $op2\t# overflow check long" %}
11615 ins_encode %{
11616 __ imulq($op1$$Register, $op2$$Register);
11617 %}
11618 ins_pipe(ialu_reg_reg_alu0);
11619 %}
11620
11621 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11622 %{
11623 match(Set cr (OverflowMulL op1 op2));
11624 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11625
11626 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11627 ins_encode %{
11628 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11629 %}
11630 ins_pipe(ialu_reg_reg_alu0);
11631 %}
11632
11633
11634 //----------Control Flow Instructions------------------------------------------
11635 // Signed compare Instructions
11636
11637 // XXX more variants!!
11638 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11639 %{
11640 match(Set cr (CmpI op1 op2));
11641 effect(DEF cr, USE op1, USE op2);
11642
11643 format %{ "cmpl $op1, $op2" %}
11644 opcode(0x3B); /* Opcode 3B /r */
11645 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11646 ins_pipe(ialu_cr_reg_reg);
11647 %}
11648
11649 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11650 %{
11651 match(Set cr (CmpI op1 op2));
11652
11653 format %{ "cmpl $op1, $op2" %}
11654 opcode(0x81, 0x07); /* Opcode 81 /7 */
11655 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11656 ins_pipe(ialu_cr_reg_imm);
11657 %}
11658
11659 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11660 %{
11661 match(Set cr (CmpI op1 (LoadI op2)));
11662
11663 ins_cost(500); // XXX
11664 format %{ "cmpl $op1, $op2" %}
11665 opcode(0x3B); /* Opcode 3B /r */
11666 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11667 ins_pipe(ialu_cr_reg_mem);
11668 %}
11669
11670 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11671 %{
11672 match(Set cr (CmpI src zero));
11673
11674 format %{ "testl $src, $src" %}
11675 opcode(0x85);
11676 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11677 ins_pipe(ialu_cr_reg_imm);
11678 %}
11679
11680 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11681 %{
11682 match(Set cr (CmpI (AndI src con) zero));
11683
11684 format %{ "testl $src, $con" %}
11685 opcode(0xF7, 0x00);
11686 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11687 ins_pipe(ialu_cr_reg_imm);
11688 %}
11689
11690 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11691 %{
11692 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11693
11694 format %{ "testl $src, $mem" %}
11695 opcode(0x85);
11696 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11697 ins_pipe(ialu_cr_reg_mem);
11698 %}
11699
11700 // Unsigned compare Instructions; really, same as signed except they
11701 // produce an rFlagsRegU instead of rFlagsReg.
11702 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11703 %{
11704 match(Set cr (CmpU op1 op2));
11705
11706 format %{ "cmpl $op1, $op2\t# unsigned" %}
11707 opcode(0x3B); /* Opcode 3B /r */
11708 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11709 ins_pipe(ialu_cr_reg_reg);
11710 %}
11711
11712 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11713 %{
11714 match(Set cr (CmpU op1 op2));
11715
11716 format %{ "cmpl $op1, $op2\t# unsigned" %}
11717 opcode(0x81,0x07); /* Opcode 81 /7 */
11718 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11719 ins_pipe(ialu_cr_reg_imm);
11720 %}
11721
11722 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11723 %{
11724 match(Set cr (CmpU op1 (LoadI op2)));
11725
11726 ins_cost(500); // XXX
11727 format %{ "cmpl $op1, $op2\t# unsigned" %}
11728 opcode(0x3B); /* Opcode 3B /r */
11729 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11730 ins_pipe(ialu_cr_reg_mem);
11731 %}
11732
11733 // // // Cisc-spilled version of cmpU_rReg
11734 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11735 // //%{
11736 // // match(Set cr (CmpU (LoadI op1) op2));
11737 // //
11738 // // format %{ "CMPu $op1,$op2" %}
11739 // // ins_cost(500);
11740 // // opcode(0x39); /* Opcode 39 /r */
11741 // // ins_encode( OpcP, reg_mem( op1, op2) );
11742 // //%}
11743
11744 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11745 %{
11746 match(Set cr (CmpU src zero));
11747
11748 format %{ "testl $src, $src\t# unsigned" %}
11749 opcode(0x85);
11750 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11751 ins_pipe(ialu_cr_reg_imm);
11752 %}
11753
11754 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11755 %{
11756 match(Set cr (CmpP op1 op2));
11757
11758 format %{ "cmpq $op1, $op2\t# ptr" %}
11759 opcode(0x3B); /* Opcode 3B /r */
11760 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11761 ins_pipe(ialu_cr_reg_reg);
11762 %}
11763
11764 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11765 %{
11766 match(Set cr (CmpP op1 (LoadP op2)));
11767
11768 ins_cost(500); // XXX
11769 format %{ "cmpq $op1, $op2\t# ptr" %}
11770 opcode(0x3B); /* Opcode 3B /r */
11771 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11772 ins_pipe(ialu_cr_reg_mem);
11773 %}
11774
11775 // // // Cisc-spilled version of cmpP_rReg
11776 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11777 // //%{
11778 // // match(Set cr (CmpP (LoadP op1) op2));
11779 // //
11780 // // format %{ "CMPu $op1,$op2" %}
11781 // // ins_cost(500);
11782 // // opcode(0x39); /* Opcode 39 /r */
11783 // // ins_encode( OpcP, reg_mem( op1, op2) );
11784 // //%}
11785
11786 // XXX this is generalized by compP_rReg_mem???
11787 // Compare raw pointer (used in out-of-heap check).
11788 // Only works because non-oop pointers must be raw pointers
11789 // and raw pointers have no anti-dependencies.
11790 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11791 %{
11792 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11793 match(Set cr (CmpP op1 (LoadP op2)));
11794
11795 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11796 opcode(0x3B); /* Opcode 3B /r */
11797 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11798 ins_pipe(ialu_cr_reg_mem);
11799 %}
11800
11801 // This will generate a signed flags result. This should be OK since
11802 // any compare to a zero should be eq/neq.
11803 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11804 %{
11805 match(Set cr (CmpP src zero));
11806
11807 format %{ "testq $src, $src\t# ptr" %}
11808 opcode(0x85);
11809 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11810 ins_pipe(ialu_cr_reg_imm);
11811 %}
11812
11813 // This will generate a signed flags result. This should be OK since
11814 // any compare to a zero should be eq/neq.
11815 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11816 %{
11817 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11818 match(Set cr (CmpP (LoadP op) zero));
11819
11820 ins_cost(500); // XXX
11821 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11822 opcode(0xF7); /* Opcode F7 /0 */
11823 ins_encode(REX_mem_wide(op),
11824 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11825 ins_pipe(ialu_cr_reg_imm);
11826 %}
11827
11828 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11829 %{
11830 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11831 match(Set cr (CmpP (LoadP mem) zero));
11832
11833 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11834 ins_encode %{
11835 __ cmpq(r12, $mem$$Address);
11836 %}
11837 ins_pipe(ialu_cr_reg_mem);
11838 %}
11839
11840 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11841 %{
11842 match(Set cr (CmpN op1 op2));
11843
11844 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11845 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11846 ins_pipe(ialu_cr_reg_reg);
11847 %}
11848
11849 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11850 %{
11851 match(Set cr (CmpN src (LoadN mem)));
11852
11853 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11854 ins_encode %{
11855 __ cmpl($src$$Register, $mem$$Address);
11856 %}
11857 ins_pipe(ialu_cr_reg_mem);
11858 %}
11859
11860 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11861 match(Set cr (CmpN op1 op2));
11862
11863 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11864 ins_encode %{
11865 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11866 %}
11867 ins_pipe(ialu_cr_reg_imm);
11868 %}
11869
11870 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11871 %{
11872 match(Set cr (CmpN src (LoadN mem)));
11873
11874 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11875 ins_encode %{
11876 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11877 %}
11878 ins_pipe(ialu_cr_reg_mem);
11879 %}
11880
11881 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11882 match(Set cr (CmpN op1 op2));
11883
11884 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11885 ins_encode %{
11886 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11887 %}
11888 ins_pipe(ialu_cr_reg_imm);
11889 %}
11890
11891 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11892 %{
11893 match(Set cr (CmpN src (LoadNKlass mem)));
11894
11895 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11896 ins_encode %{
11897 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11898 %}
11899 ins_pipe(ialu_cr_reg_mem);
11900 %}
11901
11902 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11903 match(Set cr (CmpN src zero));
11904
11905 format %{ "testl $src, $src\t# compressed ptr" %}
11906 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11907 ins_pipe(ialu_cr_reg_imm);
11908 %}
11909
11910 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11911 %{
11912 predicate(Universe::narrow_oop_base() != NULL);
11913 match(Set cr (CmpN (LoadN mem) zero));
11914
11915 ins_cost(500); // XXX
11916 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11917 ins_encode %{
11918 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11919 %}
11920 ins_pipe(ialu_cr_reg_mem);
11921 %}
11922
11923 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11924 %{
11925 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11926 match(Set cr (CmpN (LoadN mem) zero));
11927
11928 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11929 ins_encode %{
11930 __ cmpl(r12, $mem$$Address);
11931 %}
11932 ins_pipe(ialu_cr_reg_mem);
11933 %}
11934
11935 // Yanked all unsigned pointer compare operations.
11936 // Pointer compares are done with CmpP which is already unsigned.
11937
11938 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11939 %{
11940 match(Set cr (CmpL op1 op2));
11941
11942 format %{ "cmpq $op1, $op2" %}
11943 opcode(0x3B); /* Opcode 3B /r */
11944 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11945 ins_pipe(ialu_cr_reg_reg);
11946 %}
11947
11948 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11949 %{
11950 match(Set cr (CmpL op1 op2));
11951
11952 format %{ "cmpq $op1, $op2" %}
11953 opcode(0x81, 0x07); /* Opcode 81 /7 */
11954 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11955 ins_pipe(ialu_cr_reg_imm);
11956 %}
11957
11958 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11959 %{
11960 match(Set cr (CmpL op1 (LoadL op2)));
11961
11962 format %{ "cmpq $op1, $op2" %}
11963 opcode(0x3B); /* Opcode 3B /r */
11964 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11965 ins_pipe(ialu_cr_reg_mem);
11966 %}
11967
11968 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11969 %{
11970 match(Set cr (CmpL src zero));
11971
11972 format %{ "testq $src, $src" %}
11973 opcode(0x85);
11974 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11975 ins_pipe(ialu_cr_reg_imm);
11976 %}
11977
11978 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11979 %{
11980 match(Set cr (CmpL (AndL src con) zero));
11981
11982 format %{ "testq $src, $con\t# long" %}
11983 opcode(0xF7, 0x00);
11984 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11985 ins_pipe(ialu_cr_reg_imm);
11986 %}
11987
11988 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11989 %{
11990 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11991
11992 format %{ "testq $src, $mem" %}
11993 opcode(0x85);
11994 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11995 ins_pipe(ialu_cr_reg_mem);
11996 %}
11997
11998 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11999 %{
12000 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12001
12002 format %{ "testq $src, $mem" %}
12003 opcode(0x85);
12004 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12005 ins_pipe(ialu_cr_reg_mem);
12006 %}
12007
12008 // Manifest a CmpL result in an integer register. Very painful.
12009 // This is the test to avoid.
12010 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12011 %{
12012 match(Set dst (CmpL3 src1 src2));
12013 effect(KILL flags);
12014
12015 ins_cost(275); // XXX
12016 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12017 "movl $dst, -1\n\t"
12018 "jl,s done\n\t"
12019 "setne $dst\n\t"
12020 "movzbl $dst, $dst\n\t"
12021 "done:" %}
12022 ins_encode(cmpl3_flag(src1, src2, dst));
12023 ins_pipe(pipe_slow);
12024 %}
12025
12026 // Unsigned long compare Instructions; really, same as signed long except they
12027 // produce an rFlagsRegU instead of rFlagsReg.
12028 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12029 %{
12030 match(Set cr (CmpUL op1 op2));
12031
12032 format %{ "cmpq $op1, $op2\t# unsigned" %}
12033 opcode(0x3B); /* Opcode 3B /r */
12034 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12035 ins_pipe(ialu_cr_reg_reg);
12036 %}
12037
12038 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12039 %{
12040 match(Set cr (CmpUL op1 op2));
12041
12042 format %{ "cmpq $op1, $op2\t# unsigned" %}
12043 opcode(0x81, 0x07); /* Opcode 81 /7 */
12044 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12045 ins_pipe(ialu_cr_reg_imm);
12046 %}
12047
12048 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12049 %{
12050 match(Set cr (CmpUL op1 (LoadL op2)));
12051
12052 format %{ "cmpq $op1, $op2\t# unsigned" %}
12053 opcode(0x3B); /* Opcode 3B /r */
12054 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12055 ins_pipe(ialu_cr_reg_mem);
12056 %}
12057
12058 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12059 %{
12060 match(Set cr (CmpUL src zero));
12061
12062 format %{ "testq $src, $src\t# unsigned" %}
12063 opcode(0x85);
12064 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12065 ins_pipe(ialu_cr_reg_imm);
12066 %}
12067
12068 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12069 %{
12070 match(Set cr (CmpI (LoadB mem) imm));
12071
12072 ins_cost(125);
12073 format %{ "cmpb $mem, $imm" %}
12074 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12075 ins_pipe(ialu_cr_reg_mem);
12076 %}
12077
12078 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12079 %{
12080 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12081
12082 ins_cost(125);
12083 format %{ "testb $mem, $imm\t# ubyte" %}
12084 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12085 ins_pipe(ialu_cr_reg_mem);
12086 %}
12087
12088 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12089 %{
12090 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12091
12092 ins_cost(125);
12093 format %{ "testb $mem, $imm\t# byte" %}
12094 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12095 ins_pipe(ialu_cr_reg_mem);
12096 %}
12097
12098 //----------Max and Min--------------------------------------------------------
12099 // Min Instructions
12100
12101 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12102 %{
12103 effect(USE_DEF dst, USE src, USE cr);
12104
12105 format %{ "cmovlgt $dst, $src\t# min" %}
12106 opcode(0x0F, 0x4F);
12107 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12108 ins_pipe(pipe_cmov_reg);
12109 %}
12110
12111
12112 instruct minI_rReg(rRegI dst, rRegI src)
12113 %{
12114 match(Set dst (MinI dst src));
12115
12116 ins_cost(200);
12117 expand %{
12118 rFlagsReg cr;
12119 compI_rReg(cr, dst, src);
12120 cmovI_reg_g(dst, src, cr);
12121 %}
12122 %}
12123
12124 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12125 %{
12126 effect(USE_DEF dst, USE src, USE cr);
12127
12128 format %{ "cmovllt $dst, $src\t# max" %}
12129 opcode(0x0F, 0x4C);
12130 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12131 ins_pipe(pipe_cmov_reg);
12132 %}
12133
12134
12135 instruct maxI_rReg(rRegI dst, rRegI src)
12136 %{
12137 match(Set dst (MaxI dst src));
12138
12139 ins_cost(200);
12140 expand %{
12141 rFlagsReg cr;
12142 compI_rReg(cr, dst, src);
12143 cmovI_reg_l(dst, src, cr);
12144 %}
12145 %}
12146
12147 // ============================================================================
12148 // Branch Instructions
12149
12150 // Jump Direct - Label defines a relative address from JMP+1
12151 instruct jmpDir(label labl)
12152 %{
12153 match(Goto);
12154 effect(USE labl);
12155
12156 ins_cost(300);
12157 format %{ "jmp $labl" %}
12158 size(5);
12159 ins_encode %{
12160 Label* L = $labl$$label;
12161 __ jmp(*L, false); // Always long jump
12162 %}
12163 ins_pipe(pipe_jmp);
12164 %}
12165
12166 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12167 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12168 %{
12169 match(If cop cr);
12170 effect(USE labl);
12171
12172 ins_cost(300);
12173 format %{ "j$cop $labl" %}
12174 size(6);
12175 ins_encode %{
12176 Label* L = $labl$$label;
12177 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12178 %}
12179 ins_pipe(pipe_jcc);
12180 %}
12181
12182 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12183 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12184 %{
12185 predicate(!n->has_vector_mask_set());
12186 match(CountedLoopEnd cop cr);
12187 effect(USE labl);
12188
12189 ins_cost(300);
12190 format %{ "j$cop $labl\t# loop end" %}
12191 size(6);
12192 ins_encode %{
12193 Label* L = $labl$$label;
12194 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12195 %}
12196 ins_pipe(pipe_jcc);
12197 %}
12198
12199 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12200 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12201 predicate(!n->has_vector_mask_set());
12202 match(CountedLoopEnd cop cmp);
12203 effect(USE labl);
12204
12205 ins_cost(300);
12206 format %{ "j$cop,u $labl\t# loop end" %}
12207 size(6);
12208 ins_encode %{
12209 Label* L = $labl$$label;
12210 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12211 %}
12212 ins_pipe(pipe_jcc);
12213 %}
12214
12215 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12216 predicate(!n->has_vector_mask_set());
12217 match(CountedLoopEnd cop cmp);
12218 effect(USE labl);
12219
12220 ins_cost(200);
12221 format %{ "j$cop,u $labl\t# loop end" %}
12222 size(6);
12223 ins_encode %{
12224 Label* L = $labl$$label;
12225 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12226 %}
12227 ins_pipe(pipe_jcc);
12228 %}
12229
12230 // mask version
12231 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12232 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12233 %{
12234 predicate(n->has_vector_mask_set());
12235 match(CountedLoopEnd cop cr);
12236 effect(USE labl);
12237
12238 ins_cost(400);
12239 format %{ "j$cop $labl\t# loop end\n\t"
12240 "restorevectmask \t# vector mask restore for loops" %}
12241 size(10);
12242 ins_encode %{
12243 Label* L = $labl$$label;
12244 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12245 __ restorevectmask();
12246 %}
12247 ins_pipe(pipe_jcc);
12248 %}
12249
12250 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12251 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12252 predicate(n->has_vector_mask_set());
12253 match(CountedLoopEnd cop cmp);
12254 effect(USE labl);
12255
12256 ins_cost(400);
12257 format %{ "j$cop,u $labl\t# loop end\n\t"
12258 "restorevectmask \t# vector mask restore for loops" %}
12259 size(10);
12260 ins_encode %{
12261 Label* L = $labl$$label;
12262 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12263 __ restorevectmask();
12264 %}
12265 ins_pipe(pipe_jcc);
12266 %}
12267
12268 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12269 predicate(n->has_vector_mask_set());
12270 match(CountedLoopEnd cop cmp);
12271 effect(USE labl);
12272
12273 ins_cost(300);
12274 format %{ "j$cop,u $labl\t# loop end\n\t"
12275 "restorevectmask \t# vector mask restore for loops" %}
12276 size(10);
12277 ins_encode %{
12278 Label* L = $labl$$label;
12279 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12280 __ restorevectmask();
12281 %}
12282 ins_pipe(pipe_jcc);
12283 %}
12284
12285 // Jump Direct Conditional - using unsigned comparison
12286 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12287 match(If cop cmp);
12288 effect(USE labl);
12289
12290 ins_cost(300);
12291 format %{ "j$cop,u $labl" %}
12292 size(6);
12293 ins_encode %{
12294 Label* L = $labl$$label;
12295 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12296 %}
12297 ins_pipe(pipe_jcc);
12298 %}
12299
12300 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12301 match(If cop cmp);
12302 effect(USE labl);
12303
12304 ins_cost(200);
12305 format %{ "j$cop,u $labl" %}
12306 size(6);
12307 ins_encode %{
12308 Label* L = $labl$$label;
12309 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12310 %}
12311 ins_pipe(pipe_jcc);
12312 %}
12313
12314 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12315 match(If cop cmp);
12316 effect(USE labl);
12317
12318 ins_cost(200);
12319 format %{ $$template
12320 if ($cop$$cmpcode == Assembler::notEqual) {
12321 $$emit$$"jp,u $labl\n\t"
12322 $$emit$$"j$cop,u $labl"
12323 } else {
12324 $$emit$$"jp,u done\n\t"
12325 $$emit$$"j$cop,u $labl\n\t"
12326 $$emit$$"done:"
12327 }
12328 %}
12329 ins_encode %{
12330 Label* l = $labl$$label;
12331 if ($cop$$cmpcode == Assembler::notEqual) {
12332 __ jcc(Assembler::parity, *l, false);
12333 __ jcc(Assembler::notEqual, *l, false);
12334 } else if ($cop$$cmpcode == Assembler::equal) {
12335 Label done;
12336 __ jccb(Assembler::parity, done);
12337 __ jcc(Assembler::equal, *l, false);
12338 __ bind(done);
12339 } else {
12340 ShouldNotReachHere();
12341 }
12342 %}
12343 ins_pipe(pipe_jcc);
12344 %}
12345
12346 // ============================================================================
12347 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12348 // superklass array for an instance of the superklass. Set a hidden
12349 // internal cache on a hit (cache is checked with exposed code in
12350 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12351 // encoding ALSO sets flags.
12352
12353 instruct partialSubtypeCheck(rdi_RegP result,
12354 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12355 rFlagsReg cr)
12356 %{
12357 match(Set result (PartialSubtypeCheck sub super));
12358 effect(KILL rcx, KILL cr);
12359
12360 ins_cost(1100); // slightly larger than the next version
12361 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12362 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12363 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12364 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12365 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12366 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12367 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12368 "miss:\t" %}
12369
12370 opcode(0x1); // Force a XOR of RDI
12371 ins_encode(enc_PartialSubtypeCheck());
12372 ins_pipe(pipe_slow);
12373 %}
12374
12375 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12376 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12377 immP0 zero,
12378 rdi_RegP result)
12379 %{
12380 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12381 effect(KILL rcx, KILL result);
12382
12383 ins_cost(1000);
12384 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12385 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12386 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12387 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12388 "jne,s miss\t\t# Missed: flags nz\n\t"
12389 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12390 "miss:\t" %}
12391
12392 opcode(0x0); // No need to XOR RDI
12393 ins_encode(enc_PartialSubtypeCheck());
12394 ins_pipe(pipe_slow);
12395 %}
12396
12397 // ============================================================================
12398 // Branch Instructions -- short offset versions
12399 //
12400 // These instructions are used to replace jumps of a long offset (the default
12401 // match) with jumps of a shorter offset. These instructions are all tagged
12402 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12403 // match rules in general matching. Instead, the ADLC generates a conversion
12404 // method in the MachNode which can be used to do in-place replacement of the
12405 // long variant with the shorter variant. The compiler will determine if a
12406 // branch can be taken by the is_short_branch_offset() predicate in the machine
12407 // specific code section of the file.
12408
12409 // Jump Direct - Label defines a relative address from JMP+1
12410 instruct jmpDir_short(label labl) %{
12411 match(Goto);
12412 effect(USE labl);
12413
12414 ins_cost(300);
12415 format %{ "jmp,s $labl" %}
12416 size(2);
12417 ins_encode %{
12418 Label* L = $labl$$label;
12419 __ jmpb(*L);
12420 %}
12421 ins_pipe(pipe_jmp);
12422 ins_short_branch(1);
12423 %}
12424
12425 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12426 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12427 match(If cop cr);
12428 effect(USE labl);
12429
12430 ins_cost(300);
12431 format %{ "j$cop,s $labl" %}
12432 size(2);
12433 ins_encode %{
12434 Label* L = $labl$$label;
12435 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12436 %}
12437 ins_pipe(pipe_jcc);
12438 ins_short_branch(1);
12439 %}
12440
12441 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12442 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12443 match(CountedLoopEnd cop cr);
12444 effect(USE labl);
12445
12446 ins_cost(300);
12447 format %{ "j$cop,s $labl\t# loop end" %}
12448 size(2);
12449 ins_encode %{
12450 Label* L = $labl$$label;
12451 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12452 %}
12453 ins_pipe(pipe_jcc);
12454 ins_short_branch(1);
12455 %}
12456
12457 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12458 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12459 match(CountedLoopEnd cop cmp);
12460 effect(USE labl);
12461
12462 ins_cost(300);
12463 format %{ "j$cop,us $labl\t# loop end" %}
12464 size(2);
12465 ins_encode %{
12466 Label* L = $labl$$label;
12467 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12468 %}
12469 ins_pipe(pipe_jcc);
12470 ins_short_branch(1);
12471 %}
12472
12473 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12474 match(CountedLoopEnd cop cmp);
12475 effect(USE labl);
12476
12477 ins_cost(300);
12478 format %{ "j$cop,us $labl\t# loop end" %}
12479 size(2);
12480 ins_encode %{
12481 Label* L = $labl$$label;
12482 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12483 %}
12484 ins_pipe(pipe_jcc);
12485 ins_short_branch(1);
12486 %}
12487
12488 // Jump Direct Conditional - using unsigned comparison
12489 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12490 match(If cop cmp);
12491 effect(USE labl);
12492
12493 ins_cost(300);
12494 format %{ "j$cop,us $labl" %}
12495 size(2);
12496 ins_encode %{
12497 Label* L = $labl$$label;
12498 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12499 %}
12500 ins_pipe(pipe_jcc);
12501 ins_short_branch(1);
12502 %}
12503
12504 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12505 match(If cop cmp);
12506 effect(USE labl);
12507
12508 ins_cost(300);
12509 format %{ "j$cop,us $labl" %}
12510 size(2);
12511 ins_encode %{
12512 Label* L = $labl$$label;
12513 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12514 %}
12515 ins_pipe(pipe_jcc);
12516 ins_short_branch(1);
12517 %}
12518
12519 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12520 match(If cop cmp);
12521 effect(USE labl);
12522
12523 ins_cost(300);
12524 format %{ $$template
12525 if ($cop$$cmpcode == Assembler::notEqual) {
12526 $$emit$$"jp,u,s $labl\n\t"
12527 $$emit$$"j$cop,u,s $labl"
12528 } else {
12529 $$emit$$"jp,u,s done\n\t"
12530 $$emit$$"j$cop,u,s $labl\n\t"
12531 $$emit$$"done:"
12532 }
12533 %}
12534 size(4);
12535 ins_encode %{
12536 Label* l = $labl$$label;
12537 if ($cop$$cmpcode == Assembler::notEqual) {
12538 __ jccb(Assembler::parity, *l);
12539 __ jccb(Assembler::notEqual, *l);
12540 } else if ($cop$$cmpcode == Assembler::equal) {
12541 Label done;
12542 __ jccb(Assembler::parity, done);
12543 __ jccb(Assembler::equal, *l);
12544 __ bind(done);
12545 } else {
12546 ShouldNotReachHere();
12547 }
12548 %}
12549 ins_pipe(pipe_jcc);
12550 ins_short_branch(1);
12551 %}
12552
12553 // ============================================================================
12554 // inlined locking and unlocking
12555
12556 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12557 predicate(Compile::current()->use_rtm());
12558 match(Set cr (FastLock object box));
12559 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12560 ins_cost(300);
12561 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12562 ins_encode %{
12563 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12564 $scr$$Register, $cx1$$Register, $cx2$$Register,
12565 _counters, _rtm_counters, _stack_rtm_counters,
12566 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12567 true, ra_->C->profile_rtm());
12568 %}
12569 ins_pipe(pipe_slow);
12570 %}
12571
12572 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12573 predicate(!Compile::current()->use_rtm());
12574 match(Set cr (FastLock object box));
12575 effect(TEMP tmp, TEMP scr, USE_KILL box);
12576 ins_cost(300);
12577 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12578 ins_encode %{
12579 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12580 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12581 %}
12582 ins_pipe(pipe_slow);
12583 %}
12584
12585 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12586 match(Set cr (FastUnlock object box));
12587 effect(TEMP tmp, USE_KILL box);
12588 ins_cost(300);
12589 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12590 ins_encode %{
12591 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12592 %}
12593 ins_pipe(pipe_slow);
12594 %}
12595
12596
12597 // ============================================================================
12598 // Safepoint Instructions
12599 instruct safePoint_poll(rFlagsReg cr)
12600 %{
12601 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12602 match(SafePoint);
12603 effect(KILL cr);
12604
12605 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12606 "# Safepoint: poll for GC" %}
12607 ins_cost(125);
12608 ins_encode %{
12609 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12610 __ testl(rax, addr);
12611 %}
12612 ins_pipe(ialu_reg_mem);
12613 %}
12614
12615 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12616 %{
12617 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12618 match(SafePoint poll);
12619 effect(KILL cr, USE poll);
12620
12621 format %{ "testl rax, [$poll]\t"
12622 "# Safepoint: poll for GC" %}
12623 ins_cost(125);
12624 ins_encode %{
12625 __ relocate(relocInfo::poll_type);
12626 __ testl(rax, Address($poll$$Register, 0));
12627 %}
12628 ins_pipe(ialu_reg_mem);
12629 %}
12630
12631 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12632 %{
12633 predicate(SafepointMechanism::uses_thread_local_poll());
12634 match(SafePoint poll);
12635 effect(KILL cr, USE poll);
12636
12637 format %{ "testl rax, [$poll]\t"
12638 "# Safepoint: poll for GC" %}
12639 ins_cost(125);
12640 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12641 ins_encode %{
12642 __ relocate(relocInfo::poll_type);
12643 address pre_pc = __ pc();
12644 __ testl(rax, Address($poll$$Register, 0));
12645 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12646 %}
12647 ins_pipe(ialu_reg_mem);
12648 %}
12649
12650 // ============================================================================
12651 // Procedure Call/Return Instructions
12652 // Call Java Static Instruction
12653 // Note: If this code changes, the corresponding ret_addr_offset() and
12654 // compute_padding() functions will have to be adjusted.
12655 instruct CallStaticJavaDirect(method meth) %{
12656 match(CallStaticJava);
12657 effect(USE meth);
12658
12659 ins_cost(300);
12660 format %{ "call,static " %}
12661 opcode(0xE8); /* E8 cd */
12662 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12663 ins_pipe(pipe_slow);
12664 ins_alignment(4);
12665 %}
12666
12667 // Call Java Dynamic Instruction
12668 // Note: If this code changes, the corresponding ret_addr_offset() and
12669 // compute_padding() functions will have to be adjusted.
12670 instruct CallDynamicJavaDirect(method meth)
12671 %{
12672 match(CallDynamicJava);
12673 effect(USE meth);
12674
12675 ins_cost(300);
12676 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12677 "call,dynamic " %}
12678 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12679 ins_pipe(pipe_slow);
12680 ins_alignment(4);
12681 %}
12682
12683 // Call Runtime Instruction
12684 instruct CallRuntimeDirect(method meth)
12685 %{
12686 match(CallRuntime);
12687 effect(USE meth);
12688
12689 ins_cost(300);
12690 format %{ "call,runtime " %}
12691 ins_encode(clear_avx, Java_To_Runtime(meth));
12692 ins_pipe(pipe_slow);
12693 %}
12694
12695 // Call runtime without safepoint
12696 instruct CallLeafDirect(method meth)
12697 %{
12698 match(CallLeaf);
12699 effect(USE meth);
12700
12701 ins_cost(300);
12702 format %{ "call_leaf,runtime " %}
12703 ins_encode(clear_avx, Java_To_Runtime(meth));
12704 ins_pipe(pipe_slow);
12705 %}
12706
12707 // Call runtime without safepoint
12708 instruct CallLeafNoFPDirect(method meth)
12709 %{
12710 match(CallLeafNoFP);
12711 effect(USE meth);
12712
12713 ins_cost(300);
12714 format %{ "call_leaf_nofp,runtime " %}
12715 ins_encode(clear_avx, Java_To_Runtime(meth));
12716 ins_pipe(pipe_slow);
12717 %}
12718
12719 // Return Instruction
12720 // Remove the return address & jump to it.
12721 // Notice: We always emit a nop after a ret to make sure there is room
12722 // for safepoint patching
12723 instruct Ret()
12724 %{
12725 match(Return);
12726
12727 format %{ "ret" %}
12728 opcode(0xC3);
12729 ins_encode(OpcP);
12730 ins_pipe(pipe_jmp);
12731 %}
12732
12733 // Tail Call; Jump from runtime stub to Java code.
12734 // Also known as an 'interprocedural jump'.
12735 // Target of jump will eventually return to caller.
12736 // TailJump below removes the return address.
12737 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12738 %{
12739 match(TailCall jump_target method_oop);
12740
12741 ins_cost(300);
12742 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12743 opcode(0xFF, 0x4); /* Opcode FF /4 */
12744 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12745 ins_pipe(pipe_jmp);
12746 %}
12747
12748 // Tail Jump; remove the return address; jump to target.
12749 // TailCall above leaves the return address around.
12750 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12751 %{
12752 match(TailJump jump_target ex_oop);
12753
12754 ins_cost(300);
12755 format %{ "popq rdx\t# pop return address\n\t"
12756 "jmp $jump_target" %}
12757 opcode(0xFF, 0x4); /* Opcode FF /4 */
12758 ins_encode(Opcode(0x5a), // popq rdx
12759 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12760 ins_pipe(pipe_jmp);
12761 %}
12762
12763 // Create exception oop: created by stack-crawling runtime code.
12764 // Created exception is now available to this handler, and is setup
12765 // just prior to jumping to this handler. No code emitted.
12766 instruct CreateException(rax_RegP ex_oop)
12767 %{
12768 match(Set ex_oop (CreateEx));
12769
12770 size(0);
12771 // use the following format syntax
12772 format %{ "# exception oop is in rax; no code emitted" %}
12773 ins_encode();
12774 ins_pipe(empty);
12775 %}
12776
12777 // Rethrow exception:
12778 // The exception oop will come in the first argument position.
12779 // Then JUMP (not call) to the rethrow stub code.
12780 instruct RethrowException()
12781 %{
12782 match(Rethrow);
12783
12784 // use the following format syntax
12785 format %{ "jmp rethrow_stub" %}
12786 ins_encode(enc_rethrow);
12787 ins_pipe(pipe_jmp);
12788 %}
12789
12790 // ============================================================================
12791 // This name is KNOWN by the ADLC and cannot be changed.
12792 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12793 // for this guy.
12794 instruct tlsLoadP(r15_RegP dst) %{
12795 match(Set dst (ThreadLocal));
12796 effect(DEF dst);
12797
12798 size(0);
12799 format %{ "# TLS is in R15" %}
12800 ins_encode( /*empty encoding*/ );
12801 ins_pipe(ialu_reg_reg);
12802 %}
12803
12804
12805 //----------PEEPHOLE RULES-----------------------------------------------------
12806 // These must follow all instruction definitions as they use the names
12807 // defined in the instructions definitions.
12808 //
12809 // peepmatch ( root_instr_name [preceding_instruction]* );
12810 //
12811 // peepconstraint %{
12812 // (instruction_number.operand_name relational_op instruction_number.operand_name
12813 // [, ...] );
12814 // // instruction numbers are zero-based using left to right order in peepmatch
12815 //
12816 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12817 // // provide an instruction_number.operand_name for each operand that appears
12818 // // in the replacement instruction's match rule
12819 //
12820 // ---------VM FLAGS---------------------------------------------------------
12821 //
12822 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12823 //
12824 // Each peephole rule is given an identifying number starting with zero and
12825 // increasing by one in the order seen by the parser. An individual peephole
12826 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12827 // on the command-line.
12828 //
12829 // ---------CURRENT LIMITATIONS----------------------------------------------
12830 //
12831 // Only match adjacent instructions in same basic block
12832 // Only equality constraints
12833 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12834 // Only one replacement instruction
12835 //
12836 // ---------EXAMPLE----------------------------------------------------------
12837 //
12838 // // pertinent parts of existing instructions in architecture description
12839 // instruct movI(rRegI dst, rRegI src)
12840 // %{
12841 // match(Set dst (CopyI src));
12842 // %}
12843 //
12844 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12845 // %{
12846 // match(Set dst (AddI dst src));
12847 // effect(KILL cr);
12848 // %}
12849 //
12850 // // Change (inc mov) to lea
12851 // peephole %{
12852 // // increment preceeded by register-register move
12853 // peepmatch ( incI_rReg movI );
12854 // // require that the destination register of the increment
12855 // // match the destination register of the move
12856 // peepconstraint ( 0.dst == 1.dst );
12857 // // construct a replacement instruction that sets
12858 // // the destination to ( move's source register + one )
12859 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12860 // %}
12861 //
12862
12863 // Implementation no longer uses movX instructions since
12864 // machine-independent system no longer uses CopyX nodes.
12865 //
12866 // peephole
12867 // %{
12868 // peepmatch (incI_rReg movI);
12869 // peepconstraint (0.dst == 1.dst);
12870 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12871 // %}
12872
12873 // peephole
12874 // %{
12875 // peepmatch (decI_rReg movI);
12876 // peepconstraint (0.dst == 1.dst);
12877 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12878 // %}
12879
12880 // peephole
12881 // %{
12882 // peepmatch (addI_rReg_imm movI);
12883 // peepconstraint (0.dst == 1.dst);
12884 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12885 // %}
12886
12887 // peephole
12888 // %{
12889 // peepmatch (incL_rReg movL);
12890 // peepconstraint (0.dst == 1.dst);
12891 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12892 // %}
12893
12894 // peephole
12895 // %{
12896 // peepmatch (decL_rReg movL);
12897 // peepconstraint (0.dst == 1.dst);
12898 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12899 // %}
12900
12901 // peephole
12902 // %{
12903 // peepmatch (addL_rReg_imm movL);
12904 // peepconstraint (0.dst == 1.dst);
12905 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12906 // %}
12907
12908 // peephole
12909 // %{
12910 // peepmatch (addP_rReg_imm movP);
12911 // peepconstraint (0.dst == 1.dst);
12912 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12913 // %}
12914
12915 // // Change load of spilled value to only a spill
12916 // instruct storeI(memory mem, rRegI src)
12917 // %{
12918 // match(Set mem (StoreI mem src));
12919 // %}
12920 //
12921 // instruct loadI(rRegI dst, memory mem)
12922 // %{
12923 // match(Set dst (LoadI mem));
12924 // %}
12925 //
12926
12927 peephole
12928 %{
12929 peepmatch (loadI storeI);
12930 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12931 peepreplace (storeI(1.mem 1.mem 1.src));
12932 %}
12933
12934 peephole
12935 %{
12936 peepmatch (loadL storeL);
12937 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12938 peepreplace (storeL(1.mem 1.mem 1.src));
12939 %}
12940
12941 //----------SMARTSPILL RULES---------------------------------------------------
12942 // These must follow all instruction definitions as they use the names
12943 // defined in the instructions definitions.