src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64Assembler.java

rev 56282 : [mq]: graal

*** 52,61 ****
--- 52,62 ----
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLZ;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CNT;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSEL;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSINC;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSNEG;
+ import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DC;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DMB;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EON;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EOR;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EXTR;
  import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FABS;
*** 671,680 ****
--- 672,682 ----
          HINT(0xD503201F),
          DMB(0x000000A0),
  
          MRS(0xD5300000),
          MSR(0xD5100000),
+         DC(0xD5087000),
  
          BLR_NATIVE(0xc0000000),
  
          ADDV(0x0e31b800);
  
*** 707,716 ****
--- 709,736 ----
          private final int crn;
          private final int crm;
          private final int op2;
      }
  
+     public enum DataCacheOperationType {
+         ZVA(0b011, 0b0100, 0b001);
+ 
+         DataCacheOperationType(int op1, int crm, int op2) {
+             this.op1 = op1;
+             this.crm = crm;
+             this.op2 = op2;
+         }
+ 
+         public int encoding() {
+             return op1 << 16 | crm << 8 | op2 << 5;
+         }
+ 
+         private final int op1;
+         private final int crm;
+         private final int op2;
+     }
+ 
      public enum ShiftType {
          LSL(0),
          LSR(1),
          ASR(2),
          ROR(3);
*** 1013,1023 ****
              emitInt(type.encoding | instrEncoding | getConditionalBranchImm(imm21) | rd(reg), pos);
          }
      }
  
      private static int getConditionalBranchImm(int imm21) {
!         assert NumUtil.isSignedNbit(21, imm21) && (imm21 & 0x3) == 0 : "Immediate has to be 21bit signed number and word aligned";
          int imm = (imm21 & NumUtil.getNbitNumberInt(21)) >> 2;
          return imm << ConditionalBranchImmOffset;
      }
  
      /* Unconditional Branch (immediate) (5.2.2) */
--- 1033,1043 ----
              emitInt(type.encoding | instrEncoding | getConditionalBranchImm(imm21) | rd(reg), pos);
          }
      }
  
      private static int getConditionalBranchImm(int imm21) {
!         assert NumUtil.isSignedNbit(21, imm21) && (imm21 & 0x3) == 0 : String.format("Immediate has to be 21bit signed number and word aligned got value 0x%x", imm21);
          int imm = (imm21 & NumUtil.getNbitNumberInt(21)) >> 2;
          return imm << ConditionalBranchImmOffset;
      }
  
      /* Unconditional Branch (immediate) (5.2.2) */
*** 1229,1239 ****
       * @param destSize number of bits written to memory. Must be 8, 16, 32 or 64.
       * @param rt general purpose register. May not be null or stackpointer.
       * @param address all addressing modes allowed. May not be null.
       */
      public void str(int destSize, Register rt, AArch64Address address) {
!         assert rt.getRegisterCategory().equals(CPU);
          assert destSize == 8 || destSize == 16 || destSize == 32 || destSize == 64;
          int transferSize = NumUtil.log2Ceil(destSize / 8);
          loadStoreInstruction(STR, rt, address, General64, transferSize);
      }
  
--- 1249,1259 ----
       * @param destSize number of bits written to memory. Must be 8, 16, 32 or 64.
       * @param rt general purpose register. May not be null or stackpointer.
       * @param address all addressing modes allowed. May not be null.
       */
      public void str(int destSize, Register rt, AArch64Address address) {
!         assert rt.getRegisterCategory().equals(CPU) : rt;
          assert destSize == 8 || destSize == 16 || destSize == 32 || destSize == 64;
          int transferSize = NumUtil.log2Ceil(destSize / 8);
          loadStoreInstruction(STR, rt, address, General64, transferSize);
      }
  
*** 2959,2968 ****
--- 2979,2992 ----
  
      public void msr(SystemRegister systemRegister, Register src) {
          emitInt(MRS.encoding | systemRegister.encoding() | rt(src));
      }
  
+     public void dc(DataCacheOperationType type, Register src) {
+         emitInt(DC.encoding | type.encoding() | rt(src));
+     }
+ 
      public void annotatePatchingImmediate(int pos, Instruction instruction, int operandSizeBits, int offsetBits, int shift) {
          if (codePatchingAnnotationConsumer != null) {
              codePatchingAnnotationConsumer.accept(new SingleInstructionAnnotation(pos, instruction, operandSizeBits, offsetBits, shift));
          }
      }