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src/cpu/aarch64/vm/globals_aarch64.hpp

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 137   product(bool, NearCpool, true,                                        \
 138          "constant pool is close to instructions")                      \
 139                                                                         \
 140   product(bool, UseBarriersForVolatile, false,                          \
 141           "Use memory barriers to implement volatile accesses")         \
 142   product(bool, UseNeon, false,                                         \
 143           "Use Neon for CRC32 computation")                             \
 144   product(bool, UseCRC32, false,                                        \
 145           "Use CRC32 instructions for CRC32 computation")               \
 146   product(bool, UseSIMDForMemoryOps, false,                             \
 147           "Use SIMD instructions in generated memory move code")        \
 148   product(bool, AvoidUnalignedAccesses, false,                          \
 149           "Avoid generating unaligned memory accesses")                 \
 150   product(bool, UseLSE, false,                                          \
 151           "Use LSE instructions")                                       \
 152   product(bool, UseBlockZeroing, true,                                  \
 153           "Use DC ZVA for block zeroing")                               \
 154   product(intx, BlockZeroingLowLimit, 256,                              \
 155           "Minimum size in bytes when block zeroing will be used")      \
 156           range(1, max_jint)                                            \
 157   product(bool, TraceTraps, false, "Trace all traps the signal handler")
 158 



 159 #endif
 160 
 161 
 162 #endif // CPU_AARCH64_VM_GLOBALS_AARCH64_HPP


 137   product(bool, NearCpool, true,                                        \
 138          "constant pool is close to instructions")                      \
 139                                                                         \
 140   product(bool, UseBarriersForVolatile, false,                          \
 141           "Use memory barriers to implement volatile accesses")         \
 142   product(bool, UseNeon, false,                                         \
 143           "Use Neon for CRC32 computation")                             \
 144   product(bool, UseCRC32, false,                                        \
 145           "Use CRC32 instructions for CRC32 computation")               \
 146   product(bool, UseSIMDForMemoryOps, false,                             \
 147           "Use SIMD instructions in generated memory move code")        \
 148   product(bool, AvoidUnalignedAccesses, false,                          \
 149           "Avoid generating unaligned memory accesses")                 \
 150   product(bool, UseLSE, false,                                          \
 151           "Use LSE instructions")                                       \
 152   product(bool, UseBlockZeroing, true,                                  \
 153           "Use DC ZVA for block zeroing")                               \
 154   product(intx, BlockZeroingLowLimit, 256,                              \
 155           "Minimum size in bytes when block zeroing will be used")      \
 156           range(1, max_jint)                                            \
 157   product(bool, TraceTraps, false, "Trace all traps the signal handler")\
 158   product(int, SoftwarePrefetchHintDistance, -1,                        \
 159           "Use prfm hint with specified distance in compiled code."     \
 160           "Value -1 means off.")                                        \
 161           range(-1, 32760)
 162 #endif
 163 
 164 
 165 #endif // CPU_AARCH64_VM_GLOBALS_AARCH64_HPP
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